1a1b63119SJosé Roberto de Souza // SPDX-License-Identifier: MIT 2a1b63119SJosé Roberto de Souza /* 3a1b63119SJosé Roberto de Souza * Copyright © 2021 Intel Corporation 4a1b63119SJosé Roberto de Souza */ 5a1b63119SJosé Roberto de Souza 6a1b63119SJosé Roberto de Souza #include "i915_drv.h" 7a1b63119SJosé Roberto de Souza #include "intel_atomic.h" 8a1b63119SJosé Roberto de Souza #include "intel_de.h" 9a1b63119SJosé Roberto de Souza #include "intel_display_types.h" 10a1b63119SJosé Roberto de Souza #include "intel_drrs.h" 11a1b63119SJosé Roberto de Souza #include "intel_panel.h" 12a1b63119SJosé Roberto de Souza 13a1b63119SJosé Roberto de Souza /** 14a1b63119SJosé Roberto de Souza * DOC: Display Refresh Rate Switching (DRRS) 15a1b63119SJosé Roberto de Souza * 16a1b63119SJosé Roberto de Souza * Display Refresh Rate Switching (DRRS) is a power conservation feature 17a1b63119SJosé Roberto de Souza * which enables swtching between low and high refresh rates, 18a1b63119SJosé Roberto de Souza * dynamically, based on the usage scenario. This feature is applicable 19a1b63119SJosé Roberto de Souza * for internal panels. 20a1b63119SJosé Roberto de Souza * 21a1b63119SJosé Roberto de Souza * Indication that the panel supports DRRS is given by the panel EDID, which 22a1b63119SJosé Roberto de Souza * would list multiple refresh rates for one resolution. 23a1b63119SJosé Roberto de Souza * 24a1b63119SJosé Roberto de Souza * DRRS is of 2 types - static and seamless. 25a1b63119SJosé Roberto de Souza * Static DRRS involves changing refresh rate (RR) by doing a full modeset 26a1b63119SJosé Roberto de Souza * (may appear as a blink on screen) and is used in dock-undock scenario. 27a1b63119SJosé Roberto de Souza * Seamless DRRS involves changing RR without any visual effect to the user 28a1b63119SJosé Roberto de Souza * and can be used during normal system usage. This is done by programming 29a1b63119SJosé Roberto de Souza * certain registers. 30a1b63119SJosé Roberto de Souza * 31a1b63119SJosé Roberto de Souza * Support for static/seamless DRRS may be indicated in the VBT based on 32a1b63119SJosé Roberto de Souza * inputs from the panel spec. 33a1b63119SJosé Roberto de Souza * 34a1b63119SJosé Roberto de Souza * DRRS saves power by switching to low RR based on usage scenarios. 35a1b63119SJosé Roberto de Souza * 36a1b63119SJosé Roberto de Souza * The implementation is based on frontbuffer tracking implementation. When 37a1b63119SJosé Roberto de Souza * there is a disturbance on the screen triggered by user activity or a periodic 38a1b63119SJosé Roberto de Souza * system activity, DRRS is disabled (RR is changed to high RR). When there is 39a1b63119SJosé Roberto de Souza * no movement on screen, after a timeout of 1 second, a switch to low RR is 40a1b63119SJosé Roberto de Souza * made. 41a1b63119SJosé Roberto de Souza * 423a3dd534SJosé Roberto de Souza * For integration with frontbuffer tracking code, intel_drrs_invalidate() 433a3dd534SJosé Roberto de Souza * and intel_drrs_flush() are called. 44a1b63119SJosé Roberto de Souza * 45a1b63119SJosé Roberto de Souza * DRRS can be further extended to support other internal panels and also 46a1b63119SJosé Roberto de Souza * the scenario of video playback wherein RR is set based on the rate 47a1b63119SJosé Roberto de Souza * requested by userspace. 48a1b63119SJosé Roberto de Souza */ 49a1b63119SJosé Roberto de Souza 50c3e27f43SVille Syrjälä static bool can_enable_drrs(struct intel_connector *connector, 51c3e27f43SVille Syrjälä const struct intel_crtc_state *pipe_config) 52a1b63119SJosé Roberto de Souza { 53c3e27f43SVille Syrjälä const struct drm_i915_private *i915 = to_i915(connector->base.dev); 54a1b63119SJosé Roberto de Souza 55a1b63119SJosé Roberto de Souza if (pipe_config->vrr.enable) 56c3e27f43SVille Syrjälä return false; 57a1b63119SJosé Roberto de Souza 58a1b63119SJosé Roberto de Souza /* 59a1b63119SJosé Roberto de Souza * DRRS and PSR can't be enable together, so giving preference to PSR 60a1b63119SJosé Roberto de Souza * as it allows more power-savings by complete shutting down display, 613a3dd534SJosé Roberto de Souza * so to guarantee this, intel_drrs_compute_config() must be called 62a1b63119SJosé Roberto de Souza * after intel_psr_compute_config(). 63a1b63119SJosé Roberto de Souza */ 64a1b63119SJosé Roberto de Souza if (pipe_config->has_psr) 65c3e27f43SVille Syrjälä return false; 66a1b63119SJosé Roberto de Souza 67c3e27f43SVille Syrjälä return connector->panel.downclock_mode && 68*c25300f0SVille Syrjälä i915->vbt.drrs_type == DRRS_TYPE_SEAMLESS; 69c3e27f43SVille Syrjälä } 70c3e27f43SVille Syrjälä 71c3e27f43SVille Syrjälä void 72c3e27f43SVille Syrjälä intel_drrs_compute_config(struct intel_dp *intel_dp, 73c3e27f43SVille Syrjälä struct intel_crtc_state *pipe_config, 74c3e27f43SVille Syrjälä int output_bpp, bool constant_n) 75c3e27f43SVille Syrjälä { 76c3e27f43SVille Syrjälä struct intel_connector *connector = intel_dp->attached_connector; 771d06c820SVille Syrjälä struct drm_i915_private *i915 = to_i915(connector->base.dev); 78c3e27f43SVille Syrjälä int pixel_clock; 79c3e27f43SVille Syrjälä 801d06c820SVille Syrjälä if (!can_enable_drrs(connector, pipe_config)) { 811d06c820SVille Syrjälä if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder)) 821d06c820SVille Syrjälä intel_zero_m_n(&pipe_config->dp_m2_n2); 83a1b63119SJosé Roberto de Souza return; 841d06c820SVille Syrjälä } 85a1b63119SJosé Roberto de Souza 861fa7bb12SVille Syrjälä if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) 871fa7bb12SVille Syrjälä pipe_config->msa_timing_delay = i915->vbt.edp.drrs_msa_timing_delay; 881fa7bb12SVille Syrjälä 89a1b63119SJosé Roberto de Souza pipe_config->has_drrs = true; 90a1b63119SJosé Roberto de Souza 91c3e27f43SVille Syrjälä pixel_clock = connector->panel.downclock_mode->clock; 92a1b63119SJosé Roberto de Souza if (pipe_config->splitter.enable) 93a1b63119SJosé Roberto de Souza pixel_clock /= pipe_config->splitter.link_count; 94a1b63119SJosé Roberto de Souza 95a1b63119SJosé Roberto de Souza intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock, 96a1b63119SJosé Roberto de Souza pipe_config->port_clock, &pipe_config->dp_m2_n2, 97a1b63119SJosé Roberto de Souza constant_n, pipe_config->fec_enable); 98a1b63119SJosé Roberto de Souza 99a1b63119SJosé Roberto de Souza /* FIXME: abstract this better */ 100a1b63119SJosé Roberto de Souza if (pipe_config->splitter.enable) 1015f721a5dSVille Syrjälä pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; 102a1b63119SJosé Roberto de Souza } 103a1b63119SJosé Roberto de Souza 10414683babSVille Syrjälä static void 10514683babSVille Syrjälä intel_drrs_set_refresh_rate_pipeconf(const struct intel_crtc_state *crtc_state, 1065a220c53SVille Syrjälä enum drrs_refresh_rate refresh_rate) 10714683babSVille Syrjälä { 10814683babSVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 10914683babSVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 11014683babSVille Syrjälä enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 11114683babSVille Syrjälä u32 val, bit; 11214683babSVille Syrjälä 11314683babSVille Syrjälä if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 114dd7ae6b3SVille Syrjälä bit = PIPECONF_REFRESH_RATE_ALT_VLV; 11514683babSVille Syrjälä else 116dd7ae6b3SVille Syrjälä bit = PIPECONF_REFRESH_RATE_ALT_ILK; 11714683babSVille Syrjälä 11814683babSVille Syrjälä val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 11914683babSVille Syrjälä 1205a220c53SVille Syrjälä if (refresh_rate == DRRS_REFRESH_RATE_LOW) 12114683babSVille Syrjälä val |= bit; 12214683babSVille Syrjälä else 12314683babSVille Syrjälä val &= ~bit; 12414683babSVille Syrjälä 12514683babSVille Syrjälä intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 12614683babSVille Syrjälä } 12714683babSVille Syrjälä 12814683babSVille Syrjälä static void 12914683babSVille Syrjälä intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state, 1305a220c53SVille Syrjälä enum drrs_refresh_rate refresh_rate) 13114683babSVille Syrjälä { 1320adc41deSVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1330adc41deSVille Syrjälä 1340adc41deSVille Syrjälä intel_cpu_transcoder_set_m1_n1(crtc, crtc_state->cpu_transcoder, 1355a220c53SVille Syrjälä refresh_rate == DRRS_REFRESH_RATE_LOW ? 136be0c94eeSVille Syrjälä &crtc_state->dp_m2_n2 : &crtc_state->dp_m_n); 13714683babSVille Syrjälä } 13814683babSVille Syrjälä 1393a3dd534SJosé Roberto de Souza static void intel_drrs_set_state(struct drm_i915_private *dev_priv, 140a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state, 1415a220c53SVille Syrjälä enum drrs_refresh_rate refresh_rate) 142a1b63119SJosé Roberto de Souza { 143a1b63119SJosé Roberto de Souza struct intel_dp *intel_dp = dev_priv->drrs.dp; 144a1b63119SJosé Roberto de Souza struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 145a1b63119SJosé Roberto de Souza 146c7c4dfb6SJosé Roberto de Souza if (!intel_dp) { 147a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n"); 148a1b63119SJosé Roberto de Souza return; 149a1b63119SJosé Roberto de Souza } 150a1b63119SJosé Roberto de Souza 151a1b63119SJosé Roberto de Souza if (!crtc) { 152a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 153a1b63119SJosé Roberto de Souza "DRRS: intel_crtc not initialized\n"); 154a1b63119SJosé Roberto de Souza return; 155a1b63119SJosé Roberto de Souza } 156a1b63119SJosé Roberto de Souza 157*c25300f0SVille Syrjälä if (dev_priv->vbt.drrs_type != DRRS_TYPE_SEAMLESS) { 158a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n"); 159a1b63119SJosé Roberto de Souza return; 160a1b63119SJosé Roberto de Souza } 161a1b63119SJosé Roberto de Souza 1625a220c53SVille Syrjälä if (refresh_rate == dev_priv->drrs.refresh_rate) 163a1b63119SJosé Roberto de Souza return; 164a1b63119SJosé Roberto de Souza 165a1b63119SJosé Roberto de Souza if (!crtc_state->hw.active) { 166a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 167a1b63119SJosé Roberto de Souza "eDP encoder disabled. CRTC not Active\n"); 168a1b63119SJosé Roberto de Souza return; 169a1b63119SJosé Roberto de Souza } 170a1b63119SJosé Roberto de Souza 17114683babSVille Syrjälä if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) 1725a220c53SVille Syrjälä intel_drrs_set_refresh_rate_m_n(crtc_state, refresh_rate); 17314683babSVille Syrjälä else if (DISPLAY_VER(dev_priv) > 6) 1745a220c53SVille Syrjälä intel_drrs_set_refresh_rate_pipeconf(crtc_state, refresh_rate); 175a1b63119SJosé Roberto de Souza 1765a220c53SVille Syrjälä dev_priv->drrs.refresh_rate = refresh_rate; 177a1b63119SJosé Roberto de Souza 1785a220c53SVille Syrjälä drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %s\n", 1795a220c53SVille Syrjälä refresh_rate == DRRS_REFRESH_RATE_LOW ? "low" : "high"); 180a1b63119SJosé Roberto de Souza } 181a1b63119SJosé Roberto de Souza 182a1b63119SJosé Roberto de Souza static void 1833a3dd534SJosé Roberto de Souza intel_drrs_enable_locked(struct intel_dp *intel_dp) 184a1b63119SJosé Roberto de Souza { 185a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 186a1b63119SJosé Roberto de Souza 187a1b63119SJosé Roberto de Souza dev_priv->drrs.busy_frontbuffer_bits = 0; 188a1b63119SJosé Roberto de Souza dev_priv->drrs.dp = intel_dp; 189a1b63119SJosé Roberto de Souza } 190a1b63119SJosé Roberto de Souza 191a1b63119SJosé Roberto de Souza /** 1923a3dd534SJosé Roberto de Souza * intel_drrs_enable - init drrs struct if supported 193a1b63119SJosé Roberto de Souza * @intel_dp: DP struct 194a1b63119SJosé Roberto de Souza * @crtc_state: A pointer to the active crtc state. 195a1b63119SJosé Roberto de Souza * 196a1b63119SJosé Roberto de Souza * Initializes frontbuffer_bits and drrs.dp 197a1b63119SJosé Roberto de Souza */ 1983a3dd534SJosé Roberto de Souza void intel_drrs_enable(struct intel_dp *intel_dp, 199a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state) 200a1b63119SJosé Roberto de Souza { 201a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 202a1b63119SJosé Roberto de Souza 203a1b63119SJosé Roberto de Souza if (!crtc_state->has_drrs) 204a1b63119SJosé Roberto de Souza return; 205a1b63119SJosé Roberto de Souza 206a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n"); 207a1b63119SJosé Roberto de Souza 208a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 209a1b63119SJosé Roberto de Souza 210a1b63119SJosé Roberto de Souza if (dev_priv->drrs.dp) { 211a1b63119SJosé Roberto de Souza drm_warn(&dev_priv->drm, "DRRS already enabled\n"); 212a1b63119SJosé Roberto de Souza goto unlock; 213a1b63119SJosé Roberto de Souza } 214a1b63119SJosé Roberto de Souza 2153a3dd534SJosé Roberto de Souza intel_drrs_enable_locked(intel_dp); 216a1b63119SJosé Roberto de Souza 217a1b63119SJosé Roberto de Souza unlock: 218a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 219a1b63119SJosé Roberto de Souza } 220a1b63119SJosé Roberto de Souza 221a1b63119SJosé Roberto de Souza static void 2223a3dd534SJosé Roberto de Souza intel_drrs_disable_locked(struct intel_dp *intel_dp, 223a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state) 224a1b63119SJosé Roberto de Souza { 225a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 226a1b63119SJosé Roberto de Souza 2275a220c53SVille Syrjälä intel_drrs_set_state(dev_priv, crtc_state, DRRS_REFRESH_RATE_HIGH); 228a1b63119SJosé Roberto de Souza dev_priv->drrs.dp = NULL; 229a1b63119SJosé Roberto de Souza } 230a1b63119SJosé Roberto de Souza 231a1b63119SJosé Roberto de Souza /** 2323a3dd534SJosé Roberto de Souza * intel_drrs_disable - Disable DRRS 233a1b63119SJosé Roberto de Souza * @intel_dp: DP struct 234a1b63119SJosé Roberto de Souza * @old_crtc_state: Pointer to old crtc_state. 235a1b63119SJosé Roberto de Souza * 236a1b63119SJosé Roberto de Souza */ 2373a3dd534SJosé Roberto de Souza void intel_drrs_disable(struct intel_dp *intel_dp, 238a1b63119SJosé Roberto de Souza const struct intel_crtc_state *old_crtc_state) 239a1b63119SJosé Roberto de Souza { 240a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 241a1b63119SJosé Roberto de Souza 242a1b63119SJosé Roberto de Souza if (!old_crtc_state->has_drrs) 243a1b63119SJosé Roberto de Souza return; 244a1b63119SJosé Roberto de Souza 245a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 246a1b63119SJosé Roberto de Souza if (!dev_priv->drrs.dp) { 247a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 248a1b63119SJosé Roberto de Souza return; 249a1b63119SJosé Roberto de Souza } 250a1b63119SJosé Roberto de Souza 2513a3dd534SJosé Roberto de Souza intel_drrs_disable_locked(intel_dp, old_crtc_state); 252a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 253a1b63119SJosé Roberto de Souza 254a1b63119SJosé Roberto de Souza cancel_delayed_work_sync(&dev_priv->drrs.work); 255a1b63119SJosé Roberto de Souza } 256a1b63119SJosé Roberto de Souza 257a1b63119SJosé Roberto de Souza /** 2583a3dd534SJosé Roberto de Souza * intel_drrs_update - Update DRRS state 259a1b63119SJosé Roberto de Souza * @intel_dp: Intel DP 260a1b63119SJosé Roberto de Souza * @crtc_state: new CRTC state 261a1b63119SJosé Roberto de Souza * 262a1b63119SJosé Roberto de Souza * This function will update DRRS states, disabling or enabling DRRS when 2633a3dd534SJosé Roberto de Souza * executing fastsets. For full modeset, intel_drrs_disable() and 2643a3dd534SJosé Roberto de Souza * intel_drrs_enable() should be called instead. 265a1b63119SJosé Roberto de Souza */ 266a1b63119SJosé Roberto de Souza void 2673a3dd534SJosé Roberto de Souza intel_drrs_update(struct intel_dp *intel_dp, 268a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state) 269a1b63119SJosé Roberto de Souza { 270a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 271a1b63119SJosé Roberto de Souza 272*c25300f0SVille Syrjälä if (dev_priv->vbt.drrs_type != DRRS_TYPE_SEAMLESS) 273a1b63119SJosé Roberto de Souza return; 274a1b63119SJosé Roberto de Souza 275a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 276a1b63119SJosé Roberto de Souza 277a1b63119SJosé Roberto de Souza /* New state matches current one? */ 278a1b63119SJosé Roberto de Souza if (crtc_state->has_drrs == !!dev_priv->drrs.dp) 279a1b63119SJosé Roberto de Souza goto unlock; 280a1b63119SJosé Roberto de Souza 281a1b63119SJosé Roberto de Souza if (crtc_state->has_drrs) 2823a3dd534SJosé Roberto de Souza intel_drrs_enable_locked(intel_dp); 283a1b63119SJosé Roberto de Souza else 2843a3dd534SJosé Roberto de Souza intel_drrs_disable_locked(intel_dp, crtc_state); 285a1b63119SJosé Roberto de Souza 286a1b63119SJosé Roberto de Souza unlock: 287a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 288a1b63119SJosé Roberto de Souza } 289a1b63119SJosé Roberto de Souza 2903a3dd534SJosé Roberto de Souza static void intel_drrs_downclock_work(struct work_struct *work) 291a1b63119SJosé Roberto de Souza { 292a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = 293a1b63119SJosé Roberto de Souza container_of(work, typeof(*dev_priv), drrs.work.work); 294a1b63119SJosé Roberto de Souza struct intel_dp *intel_dp; 295a1b63119SJosé Roberto de Souza 296a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 297a1b63119SJosé Roberto de Souza 298a1b63119SJosé Roberto de Souza intel_dp = dev_priv->drrs.dp; 299a1b63119SJosé Roberto de Souza 300a1b63119SJosé Roberto de Souza if (!intel_dp) 301a1b63119SJosé Roberto de Souza goto unlock; 302a1b63119SJosé Roberto de Souza 303a1b63119SJosé Roberto de Souza /* 304a1b63119SJosé Roberto de Souza * The delayed work can race with an invalidate hence we need to 305a1b63119SJosé Roberto de Souza * recheck. 306a1b63119SJosé Roberto de Souza */ 307a1b63119SJosé Roberto de Souza 3085a220c53SVille Syrjälä if (!dev_priv->drrs.busy_frontbuffer_bits) { 3095a220c53SVille Syrjälä struct intel_crtc *crtc = 3105a220c53SVille Syrjälä to_intel_crtc(dp_to_dig_port(intel_dp)->base.base.crtc); 311a1b63119SJosé Roberto de Souza 3125a220c53SVille Syrjälä intel_drrs_set_state(dev_priv, crtc->config, 3135a220c53SVille Syrjälä DRRS_REFRESH_RATE_LOW); 3145a220c53SVille Syrjälä } 315a1b63119SJosé Roberto de Souza 316a1b63119SJosé Roberto de Souza unlock: 317a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 318a1b63119SJosé Roberto de Souza } 319a1b63119SJosé Roberto de Souza 3206bd58b70SJosé Roberto de Souza static void intel_drrs_frontbuffer_update(struct drm_i915_private *dev_priv, 3216bd58b70SJosé Roberto de Souza unsigned int frontbuffer_bits, 3226bd58b70SJosé Roberto de Souza bool invalidate) 323a1b63119SJosé Roberto de Souza { 324a1b63119SJosé Roberto de Souza struct intel_dp *intel_dp; 325a1b63119SJosé Roberto de Souza struct drm_crtc *crtc; 326a1b63119SJosé Roberto de Souza enum pipe pipe; 327a1b63119SJosé Roberto de Souza 328*c25300f0SVille Syrjälä if (dev_priv->vbt.drrs_type != DRRS_TYPE_SEAMLESS) 329a1b63119SJosé Roberto de Souza return; 330a1b63119SJosé Roberto de Souza 331a1b63119SJosé Roberto de Souza cancel_delayed_work(&dev_priv->drrs.work); 332a1b63119SJosé Roberto de Souza 333a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 334a1b63119SJosé Roberto de Souza 335a1b63119SJosé Roberto de Souza intel_dp = dev_priv->drrs.dp; 336a1b63119SJosé Roberto de Souza if (!intel_dp) { 337a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 338a1b63119SJosé Roberto de Souza return; 339a1b63119SJosé Roberto de Souza } 340a1b63119SJosé Roberto de Souza 341a1b63119SJosé Roberto de Souza crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 342a1b63119SJosé Roberto de Souza pipe = to_intel_crtc(crtc)->pipe; 343a1b63119SJosé Roberto de Souza 344a1b63119SJosé Roberto de Souza frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 3456bd58b70SJosé Roberto de Souza if (invalidate) 346a1b63119SJosé Roberto de Souza dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; 3476bd58b70SJosé Roberto de Souza else 3486bd58b70SJosé Roberto de Souza dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; 349a1b63119SJosé Roberto de Souza 3506bd58b70SJosé Roberto de Souza /* flush/invalidate means busy screen hence upclock */ 351c7c4dfb6SJosé Roberto de Souza if (frontbuffer_bits) 3523a3dd534SJosé Roberto de Souza intel_drrs_set_state(dev_priv, to_intel_crtc(crtc)->config, 3535a220c53SVille Syrjälä DRRS_REFRESH_RATE_HIGH); 354a1b63119SJosé Roberto de Souza 3556bd58b70SJosé Roberto de Souza /* 3566bd58b70SJosé Roberto de Souza * flush also means no more activity hence schedule downclock, if all 3576bd58b70SJosé Roberto de Souza * other fbs are quiescent too 3586bd58b70SJosé Roberto de Souza */ 3596bd58b70SJosé Roberto de Souza if (!invalidate && !dev_priv->drrs.busy_frontbuffer_bits) 3606bd58b70SJosé Roberto de Souza schedule_delayed_work(&dev_priv->drrs.work, 3616bd58b70SJosé Roberto de Souza msecs_to_jiffies(1000)); 362a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 363a1b63119SJosé Roberto de Souza } 364a1b63119SJosé Roberto de Souza 365a1b63119SJosé Roberto de Souza /** 3666bd58b70SJosé Roberto de Souza * intel_drrs_invalidate - Disable Idleness DRRS 3676bd58b70SJosé Roberto de Souza * @dev_priv: i915 device 3686bd58b70SJosé Roberto de Souza * @frontbuffer_bits: frontbuffer plane tracking bits 3696bd58b70SJosé Roberto de Souza * 3706bd58b70SJosé Roberto de Souza * This function gets called everytime rendering on the given planes start. 3716bd58b70SJosé Roberto de Souza * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). 3726bd58b70SJosé Roberto de Souza * 3736bd58b70SJosé Roberto de Souza * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 3746bd58b70SJosé Roberto de Souza */ 3756bd58b70SJosé Roberto de Souza void intel_drrs_invalidate(struct drm_i915_private *dev_priv, 3766bd58b70SJosé Roberto de Souza unsigned int frontbuffer_bits) 3776bd58b70SJosé Roberto de Souza { 3786bd58b70SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, true); 3796bd58b70SJosé Roberto de Souza } 3806bd58b70SJosé Roberto de Souza 3816bd58b70SJosé Roberto de Souza /** 3823a3dd534SJosé Roberto de Souza * intel_drrs_flush - Restart Idleness DRRS 383a1b63119SJosé Roberto de Souza * @dev_priv: i915 device 384a1b63119SJosé Roberto de Souza * @frontbuffer_bits: frontbuffer plane tracking bits 385a1b63119SJosé Roberto de Souza * 386a1b63119SJosé Roberto de Souza * This function gets called every time rendering on the given planes has 387a1b63119SJosé Roberto de Souza * completed or flip on a crtc is completed. So DRRS should be upclocked 388a1b63119SJosé Roberto de Souza * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, 389a1b63119SJosé Roberto de Souza * if no other planes are dirty. 390a1b63119SJosé Roberto de Souza * 391a1b63119SJosé Roberto de Souza * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 392a1b63119SJosé Roberto de Souza */ 3933a3dd534SJosé Roberto de Souza void intel_drrs_flush(struct drm_i915_private *dev_priv, 394a1b63119SJosé Roberto de Souza unsigned int frontbuffer_bits) 395a1b63119SJosé Roberto de Souza { 3966bd58b70SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false); 397a1b63119SJosé Roberto de Souza } 398a1b63119SJosé Roberto de Souza 3990f3692b5SJosé Roberto de Souza void intel_drrs_page_flip(struct intel_atomic_state *state, 4000f3692b5SJosé Roberto de Souza struct intel_crtc *crtc) 4010f3692b5SJosé Roberto de Souza { 4020f3692b5SJosé Roberto de Souza struct drm_i915_private *dev_priv = to_i915(state->base.dev); 4030f3692b5SJosé Roberto de Souza unsigned int frontbuffer_bits = INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe); 4040f3692b5SJosé Roberto de Souza 4050f3692b5SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false); 4060f3692b5SJosé Roberto de Souza } 4070f3692b5SJosé Roberto de Souza 408a1b63119SJosé Roberto de Souza /** 4093a3dd534SJosé Roberto de Souza * intel_drrs_init - Init basic DRRS work and mutex. 410a1b63119SJosé Roberto de Souza * @connector: eDP connector 411a1b63119SJosé Roberto de Souza * @fixed_mode: preferred mode of panel 412a1b63119SJosé Roberto de Souza * 413a1b63119SJosé Roberto de Souza * This function is called only once at driver load to initialize basic 414a1b63119SJosé Roberto de Souza * DRRS stuff. 415a1b63119SJosé Roberto de Souza * 416a1b63119SJosé Roberto de Souza * Returns: 417a1b63119SJosé Roberto de Souza * Downclock mode if panel supports it, else return NULL. 418a1b63119SJosé Roberto de Souza * DRRS support is determined by the presence of downclock mode (apart 419a1b63119SJosé Roberto de Souza * from VBT setting). 420a1b63119SJosé Roberto de Souza */ 421a1b63119SJosé Roberto de Souza struct drm_display_mode * 4223a3dd534SJosé Roberto de Souza intel_drrs_init(struct intel_connector *connector, 423faf6e8fcSVille Syrjälä const struct drm_display_mode *fixed_mode) 424a1b63119SJosé Roberto de Souza { 425a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 426f0d4ce59SVille Syrjälä struct intel_encoder *encoder = connector->encoder; 427a1b63119SJosé Roberto de Souza struct drm_display_mode *downclock_mode = NULL; 428a1b63119SJosé Roberto de Souza 4293a3dd534SJosé Roberto de Souza INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_drrs_downclock_work); 430a1b63119SJosé Roberto de Souza mutex_init(&dev_priv->drrs.mutex); 431a1b63119SJosé Roberto de Souza 432a1b63119SJosé Roberto de Souza if (DISPLAY_VER(dev_priv) <= 6) { 433a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 4345f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported on platform\n", 4355f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 436a1b63119SJosé Roberto de Souza return NULL; 437a1b63119SJosé Roberto de Souza } 438a1b63119SJosé Roberto de Souza 439f0d4ce59SVille Syrjälä if ((DISPLAY_VER(dev_priv) < 8 && !HAS_GMCH(dev_priv)) && 440f0d4ce59SVille Syrjälä encoder->port != PORT_A) { 441f0d4ce59SVille Syrjälä drm_dbg_kms(&dev_priv->drm, 4425f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported on [ENCODER:%d:%s]\n", 4435f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name, 4445f6a9beaSVille Syrjälä encoder->base.base.id, encoder->base.name); 445f0d4ce59SVille Syrjälä return NULL; 446f0d4ce59SVille Syrjälä } 447f0d4ce59SVille Syrjälä 4488e9c9848SVille Syrjälä if (dev_priv->vbt.drrs_type != DRRS_TYPE_SEAMLESS) { 4495f6a9beaSVille Syrjälä drm_dbg_kms(&dev_priv->drm, 4505f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported according to VBT\n", 4515f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 452a1b63119SJosé Roberto de Souza return NULL; 453a1b63119SJosé Roberto de Souza } 454a1b63119SJosé Roberto de Souza 455a1b63119SJosé Roberto de Souza downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode); 456a1b63119SJosé Roberto de Souza if (!downclock_mode) { 457a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 4585f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported due to lack of downclock mode\n", 4595f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 460a1b63119SJosé Roberto de Souza return NULL; 461a1b63119SJosé Roberto de Souza } 462a1b63119SJosé Roberto de Souza 4635a220c53SVille Syrjälä dev_priv->drrs.refresh_rate = DRRS_REFRESH_RATE_HIGH; 464a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 4655f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] seamless DRRS supported\n", 4665f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 4675f6a9beaSVille Syrjälä 468a1b63119SJosé Roberto de Souza return downclock_mode; 469a1b63119SJosé Roberto de Souza } 470