1a1b63119SJosé Roberto de Souza // SPDX-License-Identifier: MIT 2a1b63119SJosé Roberto de Souza /* 3a1b63119SJosé Roberto de Souza * Copyright © 2021 Intel Corporation 4a1b63119SJosé Roberto de Souza */ 5a1b63119SJosé Roberto de Souza 6a1b63119SJosé Roberto de Souza #include "i915_drv.h" 7a1b63119SJosé Roberto de Souza #include "intel_atomic.h" 8a1b63119SJosé Roberto de Souza #include "intel_de.h" 9a1b63119SJosé Roberto de Souza #include "intel_display_types.h" 10a1b63119SJosé Roberto de Souza #include "intel_drrs.h" 11a1b63119SJosé Roberto de Souza #include "intel_panel.h" 12a1b63119SJosé Roberto de Souza 13a1b63119SJosé Roberto de Souza /** 14a1b63119SJosé Roberto de Souza * DOC: Display Refresh Rate Switching (DRRS) 15a1b63119SJosé Roberto de Souza * 16a1b63119SJosé Roberto de Souza * Display Refresh Rate Switching (DRRS) is a power conservation feature 17a1b63119SJosé Roberto de Souza * which enables swtching between low and high refresh rates, 18a1b63119SJosé Roberto de Souza * dynamically, based on the usage scenario. This feature is applicable 19a1b63119SJosé Roberto de Souza * for internal panels. 20a1b63119SJosé Roberto de Souza * 21a1b63119SJosé Roberto de Souza * Indication that the panel supports DRRS is given by the panel EDID, which 22a1b63119SJosé Roberto de Souza * would list multiple refresh rates for one resolution. 23a1b63119SJosé Roberto de Souza * 24a1b63119SJosé Roberto de Souza * DRRS is of 2 types - static and seamless. 25a1b63119SJosé Roberto de Souza * Static DRRS involves changing refresh rate (RR) by doing a full modeset 26a1b63119SJosé Roberto de Souza * (may appear as a blink on screen) and is used in dock-undock scenario. 27a1b63119SJosé Roberto de Souza * Seamless DRRS involves changing RR without any visual effect to the user 28a1b63119SJosé Roberto de Souza * and can be used during normal system usage. This is done by programming 29a1b63119SJosé Roberto de Souza * certain registers. 30a1b63119SJosé Roberto de Souza * 31a1b63119SJosé Roberto de Souza * Support for static/seamless DRRS may be indicated in the VBT based on 32a1b63119SJosé Roberto de Souza * inputs from the panel spec. 33a1b63119SJosé Roberto de Souza * 34a1b63119SJosé Roberto de Souza * DRRS saves power by switching to low RR based on usage scenarios. 35a1b63119SJosé Roberto de Souza * 36a1b63119SJosé Roberto de Souza * The implementation is based on frontbuffer tracking implementation. When 37a1b63119SJosé Roberto de Souza * there is a disturbance on the screen triggered by user activity or a periodic 38a1b63119SJosé Roberto de Souza * system activity, DRRS is disabled (RR is changed to high RR). When there is 39a1b63119SJosé Roberto de Souza * no movement on screen, after a timeout of 1 second, a switch to low RR is 40a1b63119SJosé Roberto de Souza * made. 41a1b63119SJosé Roberto de Souza * 423a3dd534SJosé Roberto de Souza * For integration with frontbuffer tracking code, intel_drrs_invalidate() 433a3dd534SJosé Roberto de Souza * and intel_drrs_flush() are called. 44a1b63119SJosé Roberto de Souza * 45a1b63119SJosé Roberto de Souza * DRRS can be further extended to support other internal panels and also 46a1b63119SJosé Roberto de Souza * the scenario of video playback wherein RR is set based on the rate 47a1b63119SJosé Roberto de Souza * requested by userspace. 48a1b63119SJosé Roberto de Souza */ 49a1b63119SJosé Roberto de Souza 50a1b63119SJosé Roberto de Souza void 513a3dd534SJosé Roberto de Souza intel_drrs_compute_config(struct intel_dp *intel_dp, 52a1b63119SJosé Roberto de Souza struct intel_crtc_state *pipe_config, 53a1b63119SJosé Roberto de Souza int output_bpp, bool constant_n) 54a1b63119SJosé Roberto de Souza { 55a1b63119SJosé Roberto de Souza struct intel_connector *intel_connector = intel_dp->attached_connector; 56a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 57a1b63119SJosé Roberto de Souza int pixel_clock; 58a1b63119SJosé Roberto de Souza 59a1b63119SJosé Roberto de Souza if (pipe_config->vrr.enable) 60a1b63119SJosé Roberto de Souza return; 61a1b63119SJosé Roberto de Souza 62a1b63119SJosé Roberto de Souza /* 63a1b63119SJosé Roberto de Souza * DRRS and PSR can't be enable together, so giving preference to PSR 64a1b63119SJosé Roberto de Souza * as it allows more power-savings by complete shutting down display, 653a3dd534SJosé Roberto de Souza * so to guarantee this, intel_drrs_compute_config() must be called 66a1b63119SJosé Roberto de Souza * after intel_psr_compute_config(). 67a1b63119SJosé Roberto de Souza */ 68a1b63119SJosé Roberto de Souza if (pipe_config->has_psr) 69a1b63119SJosé Roberto de Souza return; 70a1b63119SJosé Roberto de Souza 71a1b63119SJosé Roberto de Souza if (!intel_connector->panel.downclock_mode || 72a1b63119SJosé Roberto de Souza dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT) 73a1b63119SJosé Roberto de Souza return; 74a1b63119SJosé Roberto de Souza 75a1b63119SJosé Roberto de Souza pipe_config->has_drrs = true; 76a1b63119SJosé Roberto de Souza 77a1b63119SJosé Roberto de Souza pixel_clock = intel_connector->panel.downclock_mode->clock; 78a1b63119SJosé Roberto de Souza if (pipe_config->splitter.enable) 79a1b63119SJosé Roberto de Souza pixel_clock /= pipe_config->splitter.link_count; 80a1b63119SJosé Roberto de Souza 81a1b63119SJosé Roberto de Souza intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock, 82a1b63119SJosé Roberto de Souza pipe_config->port_clock, &pipe_config->dp_m2_n2, 83a1b63119SJosé Roberto de Souza constant_n, pipe_config->fec_enable); 84a1b63119SJosé Roberto de Souza 85a1b63119SJosé Roberto de Souza /* FIXME: abstract this better */ 86a1b63119SJosé Roberto de Souza if (pipe_config->splitter.enable) 875f721a5dSVille Syrjälä pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; 88a1b63119SJosé Roberto de Souza } 89a1b63119SJosé Roberto de Souza 9014683babSVille Syrjälä static void 9114683babSVille Syrjälä intel_drrs_set_refresh_rate_pipeconf(const struct intel_crtc_state *crtc_state, 9214683babSVille Syrjälä enum drrs_refresh_rate_type refresh_type) 9314683babSVille Syrjälä { 9414683babSVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 9514683babSVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 9614683babSVille Syrjälä enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 9714683babSVille Syrjälä u32 val, bit; 9814683babSVille Syrjälä 9914683babSVille Syrjälä if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 10014683babSVille Syrjälä bit = PIPECONF_EDP_RR_MODE_SWITCH_VLV; 10114683babSVille Syrjälä else 10214683babSVille Syrjälä bit = PIPECONF_EDP_RR_MODE_SWITCH; 10314683babSVille Syrjälä 10414683babSVille Syrjälä val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 10514683babSVille Syrjälä 10614683babSVille Syrjälä if (refresh_type == DRRS_LOW_RR) 10714683babSVille Syrjälä val |= bit; 10814683babSVille Syrjälä else 10914683babSVille Syrjälä val &= ~bit; 11014683babSVille Syrjälä 11114683babSVille Syrjälä intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 11214683babSVille Syrjälä } 11314683babSVille Syrjälä 11414683babSVille Syrjälä static void 11514683babSVille Syrjälä intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state, 11614683babSVille Syrjälä enum drrs_refresh_rate_type refresh_type) 11714683babSVille Syrjälä { 118*be0c94eeSVille Syrjälä intel_cpu_transcoder_set_m1_n1(crtc_state, refresh_type == DRRS_LOW_RR ? 119*be0c94eeSVille Syrjälä &crtc_state->dp_m2_n2 : &crtc_state->dp_m_n); 12014683babSVille Syrjälä } 12114683babSVille Syrjälä 1223a3dd534SJosé Roberto de Souza static void intel_drrs_set_state(struct drm_i915_private *dev_priv, 123a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state, 124c7c4dfb6SJosé Roberto de Souza enum drrs_refresh_rate_type refresh_type) 125a1b63119SJosé Roberto de Souza { 126a1b63119SJosé Roberto de Souza struct intel_dp *intel_dp = dev_priv->drrs.dp; 127a1b63119SJosé Roberto de Souza struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 128c7c4dfb6SJosé Roberto de Souza struct drm_display_mode *mode; 129a1b63119SJosé Roberto de Souza 130c7c4dfb6SJosé Roberto de Souza if (!intel_dp) { 131a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n"); 132a1b63119SJosé Roberto de Souza return; 133a1b63119SJosé Roberto de Souza } 134a1b63119SJosé Roberto de Souza 135a1b63119SJosé Roberto de Souza if (!crtc) { 136a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 137a1b63119SJosé Roberto de Souza "DRRS: intel_crtc not initialized\n"); 138a1b63119SJosé Roberto de Souza return; 139a1b63119SJosé Roberto de Souza } 140a1b63119SJosé Roberto de Souza 141a1b63119SJosé Roberto de Souza if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { 142a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n"); 143a1b63119SJosé Roberto de Souza return; 144a1b63119SJosé Roberto de Souza } 145a1b63119SJosé Roberto de Souza 146c7c4dfb6SJosé Roberto de Souza if (refresh_type == dev_priv->drrs.refresh_rate_type) 147a1b63119SJosé Roberto de Souza return; 148a1b63119SJosé Roberto de Souza 149a1b63119SJosé Roberto de Souza if (!crtc_state->hw.active) { 150a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 151a1b63119SJosé Roberto de Souza "eDP encoder disabled. CRTC not Active\n"); 152a1b63119SJosé Roberto de Souza return; 153a1b63119SJosé Roberto de Souza } 154a1b63119SJosé Roberto de Souza 15514683babSVille Syrjälä if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) 15614683babSVille Syrjälä intel_drrs_set_refresh_rate_m_n(crtc_state, refresh_type); 15714683babSVille Syrjälä else if (DISPLAY_VER(dev_priv) > 6) 15814683babSVille Syrjälä intel_drrs_set_refresh_rate_pipeconf(crtc_state, refresh_type); 159a1b63119SJosé Roberto de Souza 160c7c4dfb6SJosé Roberto de Souza dev_priv->drrs.refresh_rate_type = refresh_type; 161a1b63119SJosé Roberto de Souza 162c7c4dfb6SJosé Roberto de Souza if (refresh_type == DRRS_LOW_RR) 163c7c4dfb6SJosé Roberto de Souza mode = intel_dp->attached_connector->panel.downclock_mode; 164c7c4dfb6SJosé Roberto de Souza else 165c7c4dfb6SJosé Roberto de Souza mode = intel_dp->attached_connector->panel.fixed_mode; 166a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n", 167c7c4dfb6SJosé Roberto de Souza drm_mode_vrefresh(mode)); 168a1b63119SJosé Roberto de Souza } 169a1b63119SJosé Roberto de Souza 170a1b63119SJosé Roberto de Souza static void 1713a3dd534SJosé Roberto de Souza intel_drrs_enable_locked(struct intel_dp *intel_dp) 172a1b63119SJosé Roberto de Souza { 173a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 174a1b63119SJosé Roberto de Souza 175a1b63119SJosé Roberto de Souza dev_priv->drrs.busy_frontbuffer_bits = 0; 176a1b63119SJosé Roberto de Souza dev_priv->drrs.dp = intel_dp; 177a1b63119SJosé Roberto de Souza } 178a1b63119SJosé Roberto de Souza 179a1b63119SJosé Roberto de Souza /** 1803a3dd534SJosé Roberto de Souza * intel_drrs_enable - init drrs struct if supported 181a1b63119SJosé Roberto de Souza * @intel_dp: DP struct 182a1b63119SJosé Roberto de Souza * @crtc_state: A pointer to the active crtc state. 183a1b63119SJosé Roberto de Souza * 184a1b63119SJosé Roberto de Souza * Initializes frontbuffer_bits and drrs.dp 185a1b63119SJosé Roberto de Souza */ 1863a3dd534SJosé Roberto de Souza void intel_drrs_enable(struct intel_dp *intel_dp, 187a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state) 188a1b63119SJosé Roberto de Souza { 189a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 190a1b63119SJosé Roberto de Souza 191a1b63119SJosé Roberto de Souza if (!crtc_state->has_drrs) 192a1b63119SJosé Roberto de Souza return; 193a1b63119SJosé Roberto de Souza 194a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n"); 195a1b63119SJosé Roberto de Souza 196a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 197a1b63119SJosé Roberto de Souza 198a1b63119SJosé Roberto de Souza if (dev_priv->drrs.dp) { 199a1b63119SJosé Roberto de Souza drm_warn(&dev_priv->drm, "DRRS already enabled\n"); 200a1b63119SJosé Roberto de Souza goto unlock; 201a1b63119SJosé Roberto de Souza } 202a1b63119SJosé Roberto de Souza 2033a3dd534SJosé Roberto de Souza intel_drrs_enable_locked(intel_dp); 204a1b63119SJosé Roberto de Souza 205a1b63119SJosé Roberto de Souza unlock: 206a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 207a1b63119SJosé Roberto de Souza } 208a1b63119SJosé Roberto de Souza 209a1b63119SJosé Roberto de Souza static void 2103a3dd534SJosé Roberto de Souza intel_drrs_disable_locked(struct intel_dp *intel_dp, 211a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state) 212a1b63119SJosé Roberto de Souza { 213a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 214a1b63119SJosé Roberto de Souza 215c7c4dfb6SJosé Roberto de Souza intel_drrs_set_state(dev_priv, crtc_state, DRRS_HIGH_RR); 216a1b63119SJosé Roberto de Souza dev_priv->drrs.dp = NULL; 217a1b63119SJosé Roberto de Souza } 218a1b63119SJosé Roberto de Souza 219a1b63119SJosé Roberto de Souza /** 2203a3dd534SJosé Roberto de Souza * intel_drrs_disable - Disable DRRS 221a1b63119SJosé Roberto de Souza * @intel_dp: DP struct 222a1b63119SJosé Roberto de Souza * @old_crtc_state: Pointer to old crtc_state. 223a1b63119SJosé Roberto de Souza * 224a1b63119SJosé Roberto de Souza */ 2253a3dd534SJosé Roberto de Souza void intel_drrs_disable(struct intel_dp *intel_dp, 226a1b63119SJosé Roberto de Souza const struct intel_crtc_state *old_crtc_state) 227a1b63119SJosé Roberto de Souza { 228a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 229a1b63119SJosé Roberto de Souza 230a1b63119SJosé Roberto de Souza if (!old_crtc_state->has_drrs) 231a1b63119SJosé Roberto de Souza return; 232a1b63119SJosé Roberto de Souza 233a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 234a1b63119SJosé Roberto de Souza if (!dev_priv->drrs.dp) { 235a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 236a1b63119SJosé Roberto de Souza return; 237a1b63119SJosé Roberto de Souza } 238a1b63119SJosé Roberto de Souza 2393a3dd534SJosé Roberto de Souza intel_drrs_disable_locked(intel_dp, old_crtc_state); 240a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 241a1b63119SJosé Roberto de Souza 242a1b63119SJosé Roberto de Souza cancel_delayed_work_sync(&dev_priv->drrs.work); 243a1b63119SJosé Roberto de Souza } 244a1b63119SJosé Roberto de Souza 245a1b63119SJosé Roberto de Souza /** 2463a3dd534SJosé Roberto de Souza * intel_drrs_update - Update DRRS state 247a1b63119SJosé Roberto de Souza * @intel_dp: Intel DP 248a1b63119SJosé Roberto de Souza * @crtc_state: new CRTC state 249a1b63119SJosé Roberto de Souza * 250a1b63119SJosé Roberto de Souza * This function will update DRRS states, disabling or enabling DRRS when 2513a3dd534SJosé Roberto de Souza * executing fastsets. For full modeset, intel_drrs_disable() and 2523a3dd534SJosé Roberto de Souza * intel_drrs_enable() should be called instead. 253a1b63119SJosé Roberto de Souza */ 254a1b63119SJosé Roberto de Souza void 2553a3dd534SJosé Roberto de Souza intel_drrs_update(struct intel_dp *intel_dp, 256a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state) 257a1b63119SJosé Roberto de Souza { 258a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 259a1b63119SJosé Roberto de Souza 260a1b63119SJosé Roberto de Souza if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT) 261a1b63119SJosé Roberto de Souza return; 262a1b63119SJosé Roberto de Souza 263a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 264a1b63119SJosé Roberto de Souza 265a1b63119SJosé Roberto de Souza /* New state matches current one? */ 266a1b63119SJosé Roberto de Souza if (crtc_state->has_drrs == !!dev_priv->drrs.dp) 267a1b63119SJosé Roberto de Souza goto unlock; 268a1b63119SJosé Roberto de Souza 269a1b63119SJosé Roberto de Souza if (crtc_state->has_drrs) 2703a3dd534SJosé Roberto de Souza intel_drrs_enable_locked(intel_dp); 271a1b63119SJosé Roberto de Souza else 2723a3dd534SJosé Roberto de Souza intel_drrs_disable_locked(intel_dp, crtc_state); 273a1b63119SJosé Roberto de Souza 274a1b63119SJosé Roberto de Souza unlock: 275a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 276a1b63119SJosé Roberto de Souza } 277a1b63119SJosé Roberto de Souza 2783a3dd534SJosé Roberto de Souza static void intel_drrs_downclock_work(struct work_struct *work) 279a1b63119SJosé Roberto de Souza { 280a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = 281a1b63119SJosé Roberto de Souza container_of(work, typeof(*dev_priv), drrs.work.work); 282a1b63119SJosé Roberto de Souza struct intel_dp *intel_dp; 283c7c4dfb6SJosé Roberto de Souza struct drm_crtc *crtc; 284a1b63119SJosé Roberto de Souza 285a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 286a1b63119SJosé Roberto de Souza 287a1b63119SJosé Roberto de Souza intel_dp = dev_priv->drrs.dp; 288a1b63119SJosé Roberto de Souza 289a1b63119SJosé Roberto de Souza if (!intel_dp) 290a1b63119SJosé Roberto de Souza goto unlock; 291a1b63119SJosé Roberto de Souza 292a1b63119SJosé Roberto de Souza /* 293a1b63119SJosé Roberto de Souza * The delayed work can race with an invalidate hence we need to 294a1b63119SJosé Roberto de Souza * recheck. 295a1b63119SJosé Roberto de Souza */ 296a1b63119SJosé Roberto de Souza 297a1b63119SJosé Roberto de Souza if (dev_priv->drrs.busy_frontbuffer_bits) 298a1b63119SJosé Roberto de Souza goto unlock; 299a1b63119SJosé Roberto de Souza 300c7c4dfb6SJosé Roberto de Souza crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 301c7c4dfb6SJosé Roberto de Souza intel_drrs_set_state(dev_priv, to_intel_crtc(crtc)->config, DRRS_LOW_RR); 302a1b63119SJosé Roberto de Souza 303a1b63119SJosé Roberto de Souza unlock: 304a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 305a1b63119SJosé Roberto de Souza } 306a1b63119SJosé Roberto de Souza 3076bd58b70SJosé Roberto de Souza static void intel_drrs_frontbuffer_update(struct drm_i915_private *dev_priv, 3086bd58b70SJosé Roberto de Souza unsigned int frontbuffer_bits, 3096bd58b70SJosé Roberto de Souza bool invalidate) 310a1b63119SJosé Roberto de Souza { 311a1b63119SJosé Roberto de Souza struct intel_dp *intel_dp; 312a1b63119SJosé Roberto de Souza struct drm_crtc *crtc; 313a1b63119SJosé Roberto de Souza enum pipe pipe; 314a1b63119SJosé Roberto de Souza 315a1b63119SJosé Roberto de Souza if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) 316a1b63119SJosé Roberto de Souza return; 317a1b63119SJosé Roberto de Souza 318a1b63119SJosé Roberto de Souza cancel_delayed_work(&dev_priv->drrs.work); 319a1b63119SJosé Roberto de Souza 320a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 321a1b63119SJosé Roberto de Souza 322a1b63119SJosé Roberto de Souza intel_dp = dev_priv->drrs.dp; 323a1b63119SJosé Roberto de Souza if (!intel_dp) { 324a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 325a1b63119SJosé Roberto de Souza return; 326a1b63119SJosé Roberto de Souza } 327a1b63119SJosé Roberto de Souza 328a1b63119SJosé Roberto de Souza crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 329a1b63119SJosé Roberto de Souza pipe = to_intel_crtc(crtc)->pipe; 330a1b63119SJosé Roberto de Souza 331a1b63119SJosé Roberto de Souza frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 3326bd58b70SJosé Roberto de Souza if (invalidate) 333a1b63119SJosé Roberto de Souza dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; 3346bd58b70SJosé Roberto de Souza else 3356bd58b70SJosé Roberto de Souza dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; 336a1b63119SJosé Roberto de Souza 3376bd58b70SJosé Roberto de Souza /* flush/invalidate means busy screen hence upclock */ 338c7c4dfb6SJosé Roberto de Souza if (frontbuffer_bits) 3393a3dd534SJosé Roberto de Souza intel_drrs_set_state(dev_priv, to_intel_crtc(crtc)->config, 340c7c4dfb6SJosé Roberto de Souza DRRS_HIGH_RR); 341a1b63119SJosé Roberto de Souza 3426bd58b70SJosé Roberto de Souza /* 3436bd58b70SJosé Roberto de Souza * flush also means no more activity hence schedule downclock, if all 3446bd58b70SJosé Roberto de Souza * other fbs are quiescent too 3456bd58b70SJosé Roberto de Souza */ 3466bd58b70SJosé Roberto de Souza if (!invalidate && !dev_priv->drrs.busy_frontbuffer_bits) 3476bd58b70SJosé Roberto de Souza schedule_delayed_work(&dev_priv->drrs.work, 3486bd58b70SJosé Roberto de Souza msecs_to_jiffies(1000)); 349a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 350a1b63119SJosé Roberto de Souza } 351a1b63119SJosé Roberto de Souza 352a1b63119SJosé Roberto de Souza /** 3536bd58b70SJosé Roberto de Souza * intel_drrs_invalidate - Disable Idleness DRRS 3546bd58b70SJosé Roberto de Souza * @dev_priv: i915 device 3556bd58b70SJosé Roberto de Souza * @frontbuffer_bits: frontbuffer plane tracking bits 3566bd58b70SJosé Roberto de Souza * 3576bd58b70SJosé Roberto de Souza * This function gets called everytime rendering on the given planes start. 3586bd58b70SJosé Roberto de Souza * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). 3596bd58b70SJosé Roberto de Souza * 3606bd58b70SJosé Roberto de Souza * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 3616bd58b70SJosé Roberto de Souza */ 3626bd58b70SJosé Roberto de Souza void intel_drrs_invalidate(struct drm_i915_private *dev_priv, 3636bd58b70SJosé Roberto de Souza unsigned int frontbuffer_bits) 3646bd58b70SJosé Roberto de Souza { 3656bd58b70SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, true); 3666bd58b70SJosé Roberto de Souza } 3676bd58b70SJosé Roberto de Souza 3686bd58b70SJosé Roberto de Souza /** 3693a3dd534SJosé Roberto de Souza * intel_drrs_flush - Restart Idleness DRRS 370a1b63119SJosé Roberto de Souza * @dev_priv: i915 device 371a1b63119SJosé Roberto de Souza * @frontbuffer_bits: frontbuffer plane tracking bits 372a1b63119SJosé Roberto de Souza * 373a1b63119SJosé Roberto de Souza * This function gets called every time rendering on the given planes has 374a1b63119SJosé Roberto de Souza * completed or flip on a crtc is completed. So DRRS should be upclocked 375a1b63119SJosé Roberto de Souza * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, 376a1b63119SJosé Roberto de Souza * if no other planes are dirty. 377a1b63119SJosé Roberto de Souza * 378a1b63119SJosé Roberto de Souza * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 379a1b63119SJosé Roberto de Souza */ 3803a3dd534SJosé Roberto de Souza void intel_drrs_flush(struct drm_i915_private *dev_priv, 381a1b63119SJosé Roberto de Souza unsigned int frontbuffer_bits) 382a1b63119SJosé Roberto de Souza { 3836bd58b70SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false); 384a1b63119SJosé Roberto de Souza } 385a1b63119SJosé Roberto de Souza 3860f3692b5SJosé Roberto de Souza void intel_drrs_page_flip(struct intel_atomic_state *state, 3870f3692b5SJosé Roberto de Souza struct intel_crtc *crtc) 3880f3692b5SJosé Roberto de Souza { 3890f3692b5SJosé Roberto de Souza struct drm_i915_private *dev_priv = to_i915(state->base.dev); 3900f3692b5SJosé Roberto de Souza unsigned int frontbuffer_bits = INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe); 3910f3692b5SJosé Roberto de Souza 3920f3692b5SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false); 3930f3692b5SJosé Roberto de Souza } 3940f3692b5SJosé Roberto de Souza 395a1b63119SJosé Roberto de Souza /** 3963a3dd534SJosé Roberto de Souza * intel_drrs_init - Init basic DRRS work and mutex. 397a1b63119SJosé Roberto de Souza * @connector: eDP connector 398a1b63119SJosé Roberto de Souza * @fixed_mode: preferred mode of panel 399a1b63119SJosé Roberto de Souza * 400a1b63119SJosé Roberto de Souza * This function is called only once at driver load to initialize basic 401a1b63119SJosé Roberto de Souza * DRRS stuff. 402a1b63119SJosé Roberto de Souza * 403a1b63119SJosé Roberto de Souza * Returns: 404a1b63119SJosé Roberto de Souza * Downclock mode if panel supports it, else return NULL. 405a1b63119SJosé Roberto de Souza * DRRS support is determined by the presence of downclock mode (apart 406a1b63119SJosé Roberto de Souza * from VBT setting). 407a1b63119SJosé Roberto de Souza */ 408a1b63119SJosé Roberto de Souza struct drm_display_mode * 4093a3dd534SJosé Roberto de Souza intel_drrs_init(struct intel_connector *connector, 410a1b63119SJosé Roberto de Souza struct drm_display_mode *fixed_mode) 411a1b63119SJosé Roberto de Souza { 412a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 413a1b63119SJosé Roberto de Souza struct drm_display_mode *downclock_mode = NULL; 414a1b63119SJosé Roberto de Souza 4153a3dd534SJosé Roberto de Souza INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_drrs_downclock_work); 416a1b63119SJosé Roberto de Souza mutex_init(&dev_priv->drrs.mutex); 417a1b63119SJosé Roberto de Souza 418a1b63119SJosé Roberto de Souza if (DISPLAY_VER(dev_priv) <= 6) { 419a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 420a1b63119SJosé Roberto de Souza "DRRS supported for Gen7 and above\n"); 421a1b63119SJosé Roberto de Souza return NULL; 422a1b63119SJosé Roberto de Souza } 423a1b63119SJosé Roberto de Souza 424a1b63119SJosé Roberto de Souza if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { 425a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n"); 426a1b63119SJosé Roberto de Souza return NULL; 427a1b63119SJosé Roberto de Souza } 428a1b63119SJosé Roberto de Souza 429a1b63119SJosé Roberto de Souza downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode); 430a1b63119SJosé Roberto de Souza if (!downclock_mode) { 431a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 432a1b63119SJosé Roberto de Souza "Downclock mode is not found. DRRS not supported\n"); 433a1b63119SJosé Roberto de Souza return NULL; 434a1b63119SJosé Roberto de Souza } 435a1b63119SJosé Roberto de Souza 436a1b63119SJosé Roberto de Souza dev_priv->drrs.type = dev_priv->vbt.drrs_type; 437a1b63119SJosé Roberto de Souza 438a1b63119SJosé Roberto de Souza dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; 439a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 440a1b63119SJosé Roberto de Souza "seamless DRRS supported for eDP panel.\n"); 441a1b63119SJosé Roberto de Souza return downclock_mode; 442a1b63119SJosé Roberto de Souza } 443