1a1b63119SJosé Roberto de Souza // SPDX-License-Identifier: MIT 2a1b63119SJosé Roberto de Souza /* 3a1b63119SJosé Roberto de Souza * Copyright © 2021 Intel Corporation 4a1b63119SJosé Roberto de Souza */ 5a1b63119SJosé Roberto de Souza 6a1b63119SJosé Roberto de Souza #include "i915_drv.h" 7a1b63119SJosé Roberto de Souza #include "intel_atomic.h" 8a1b63119SJosé Roberto de Souza #include "intel_de.h" 9a1b63119SJosé Roberto de Souza #include "intel_display_types.h" 10a1b63119SJosé Roberto de Souza #include "intel_drrs.h" 11a1b63119SJosé Roberto de Souza #include "intel_panel.h" 12a1b63119SJosé Roberto de Souza 13a1b63119SJosé Roberto de Souza /** 14a1b63119SJosé Roberto de Souza * DOC: Display Refresh Rate Switching (DRRS) 15a1b63119SJosé Roberto de Souza * 16a1b63119SJosé Roberto de Souza * Display Refresh Rate Switching (DRRS) is a power conservation feature 17a1b63119SJosé Roberto de Souza * which enables swtching between low and high refresh rates, 18a1b63119SJosé Roberto de Souza * dynamically, based on the usage scenario. This feature is applicable 19a1b63119SJosé Roberto de Souza * for internal panels. 20a1b63119SJosé Roberto de Souza * 21a1b63119SJosé Roberto de Souza * Indication that the panel supports DRRS is given by the panel EDID, which 22a1b63119SJosé Roberto de Souza * would list multiple refresh rates for one resolution. 23a1b63119SJosé Roberto de Souza * 24a1b63119SJosé Roberto de Souza * DRRS is of 2 types - static and seamless. 25a1b63119SJosé Roberto de Souza * Static DRRS involves changing refresh rate (RR) by doing a full modeset 26a1b63119SJosé Roberto de Souza * (may appear as a blink on screen) and is used in dock-undock scenario. 27a1b63119SJosé Roberto de Souza * Seamless DRRS involves changing RR without any visual effect to the user 28a1b63119SJosé Roberto de Souza * and can be used during normal system usage. This is done by programming 29a1b63119SJosé Roberto de Souza * certain registers. 30a1b63119SJosé Roberto de Souza * 31a1b63119SJosé Roberto de Souza * Support for static/seamless DRRS may be indicated in the VBT based on 32a1b63119SJosé Roberto de Souza * inputs from the panel spec. 33a1b63119SJosé Roberto de Souza * 34a1b63119SJosé Roberto de Souza * DRRS saves power by switching to low RR based on usage scenarios. 35a1b63119SJosé Roberto de Souza * 36a1b63119SJosé Roberto de Souza * The implementation is based on frontbuffer tracking implementation. When 37a1b63119SJosé Roberto de Souza * there is a disturbance on the screen triggered by user activity or a periodic 38a1b63119SJosé Roberto de Souza * system activity, DRRS is disabled (RR is changed to high RR). When there is 39a1b63119SJosé Roberto de Souza * no movement on screen, after a timeout of 1 second, a switch to low RR is 40a1b63119SJosé Roberto de Souza * made. 41a1b63119SJosé Roberto de Souza * 423a3dd534SJosé Roberto de Souza * For integration with frontbuffer tracking code, intel_drrs_invalidate() 433a3dd534SJosé Roberto de Souza * and intel_drrs_flush() are called. 44a1b63119SJosé Roberto de Souza * 45a1b63119SJosé Roberto de Souza * DRRS can be further extended to support other internal panels and also 46a1b63119SJosé Roberto de Souza * the scenario of video playback wherein RR is set based on the rate 47a1b63119SJosé Roberto de Souza * requested by userspace. 48a1b63119SJosé Roberto de Souza */ 49a1b63119SJosé Roberto de Souza 50a1b952d4SVille Syrjälä const char *intel_drrs_type_str(enum drrs_type drrs_type) 51a1b952d4SVille Syrjälä { 52a1b952d4SVille Syrjälä static const char * const str[] = { 53a1b952d4SVille Syrjälä [DRRS_TYPE_NONE] = "none", 54a1b952d4SVille Syrjälä [DRRS_TYPE_STATIC] = "static", 55a1b952d4SVille Syrjälä [DRRS_TYPE_SEAMLESS] = "seamless", 56a1b952d4SVille Syrjälä }; 57a1b952d4SVille Syrjälä 58a1b952d4SVille Syrjälä if (drrs_type >= ARRAY_SIZE(str)) 59a1b952d4SVille Syrjälä return "<invalid>"; 60a1b952d4SVille Syrjälä 61a1b952d4SVille Syrjälä return str[drrs_type]; 62a1b952d4SVille Syrjälä } 63a1b952d4SVille Syrjälä 64c3e27f43SVille Syrjälä static bool can_enable_drrs(struct intel_connector *connector, 65f0a57798SVille Syrjälä const struct intel_crtc_state *pipe_config) 66a1b63119SJosé Roberto de Souza { 67a1b63119SJosé Roberto de Souza if (pipe_config->vrr.enable) 68c3e27f43SVille Syrjälä return false; 69a1b63119SJosé Roberto de Souza 70a1b63119SJosé Roberto de Souza /* 71a1b63119SJosé Roberto de Souza * DRRS and PSR can't be enable together, so giving preference to PSR 72a1b63119SJosé Roberto de Souza * as it allows more power-savings by complete shutting down display, 733a3dd534SJosé Roberto de Souza * so to guarantee this, intel_drrs_compute_config() must be called 74a1b63119SJosé Roberto de Souza * after intel_psr_compute_config(). 75a1b63119SJosé Roberto de Souza */ 76a1b63119SJosé Roberto de Souza if (pipe_config->has_psr) 77c3e27f43SVille Syrjälä return false; 78a1b63119SJosé Roberto de Souza 79f0a57798SVille Syrjälä return intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 80c3e27f43SVille Syrjälä } 81c3e27f43SVille Syrjälä 82c3e27f43SVille Syrjälä void 83*ba770ce3SVille Syrjälä intel_drrs_compute_config(struct intel_connector *connector, 84c3e27f43SVille Syrjälä struct intel_crtc_state *pipe_config, 85c3e27f43SVille Syrjälä int output_bpp, bool constant_n) 86c3e27f43SVille Syrjälä { 871d06c820SVille Syrjälä struct drm_i915_private *i915 = to_i915(connector->base.dev); 8809270678SVille Syrjälä const struct drm_display_mode *downclock_mode = 8909270678SVille Syrjälä intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); 90c3e27f43SVille Syrjälä int pixel_clock; 91c3e27f43SVille Syrjälä 92f0a57798SVille Syrjälä if (!can_enable_drrs(connector, pipe_config)) { 931d06c820SVille Syrjälä if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder)) 941d06c820SVille Syrjälä intel_zero_m_n(&pipe_config->dp_m2_n2); 95a1b63119SJosé Roberto de Souza return; 961d06c820SVille Syrjälä } 97a1b63119SJosé Roberto de Souza 981fa7bb12SVille Syrjälä if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) 991fa7bb12SVille Syrjälä pipe_config->msa_timing_delay = i915->vbt.edp.drrs_msa_timing_delay; 1001fa7bb12SVille Syrjälä 101a1b63119SJosé Roberto de Souza pipe_config->has_drrs = true; 102a1b63119SJosé Roberto de Souza 10309270678SVille Syrjälä pixel_clock = downclock_mode->clock; 104a1b63119SJosé Roberto de Souza if (pipe_config->splitter.enable) 105a1b63119SJosé Roberto de Souza pixel_clock /= pipe_config->splitter.link_count; 106a1b63119SJosé Roberto de Souza 107a1b63119SJosé Roberto de Souza intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock, 108a1b63119SJosé Roberto de Souza pipe_config->port_clock, &pipe_config->dp_m2_n2, 109a1b63119SJosé Roberto de Souza constant_n, pipe_config->fec_enable); 110a1b63119SJosé Roberto de Souza 111a1b63119SJosé Roberto de Souza /* FIXME: abstract this better */ 112a1b63119SJosé Roberto de Souza if (pipe_config->splitter.enable) 1135f721a5dSVille Syrjälä pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; 114a1b63119SJosé Roberto de Souza } 115a1b63119SJosé Roberto de Souza 11614683babSVille Syrjälä static void 11714683babSVille Syrjälä intel_drrs_set_refresh_rate_pipeconf(const struct intel_crtc_state *crtc_state, 1185a220c53SVille Syrjälä enum drrs_refresh_rate refresh_rate) 11914683babSVille Syrjälä { 12014683babSVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 12114683babSVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 12214683babSVille Syrjälä enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 12314683babSVille Syrjälä u32 val, bit; 12414683babSVille Syrjälä 12514683babSVille Syrjälä if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 126dd7ae6b3SVille Syrjälä bit = PIPECONF_REFRESH_RATE_ALT_VLV; 12714683babSVille Syrjälä else 128dd7ae6b3SVille Syrjälä bit = PIPECONF_REFRESH_RATE_ALT_ILK; 12914683babSVille Syrjälä 13014683babSVille Syrjälä val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 13114683babSVille Syrjälä 1325a220c53SVille Syrjälä if (refresh_rate == DRRS_REFRESH_RATE_LOW) 13314683babSVille Syrjälä val |= bit; 13414683babSVille Syrjälä else 13514683babSVille Syrjälä val &= ~bit; 13614683babSVille Syrjälä 13714683babSVille Syrjälä intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 13814683babSVille Syrjälä } 13914683babSVille Syrjälä 14014683babSVille Syrjälä static void 14114683babSVille Syrjälä intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state, 1425a220c53SVille Syrjälä enum drrs_refresh_rate refresh_rate) 14314683babSVille Syrjälä { 1440adc41deSVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1450adc41deSVille Syrjälä 1460adc41deSVille Syrjälä intel_cpu_transcoder_set_m1_n1(crtc, crtc_state->cpu_transcoder, 1475a220c53SVille Syrjälä refresh_rate == DRRS_REFRESH_RATE_LOW ? 148be0c94eeSVille Syrjälä &crtc_state->dp_m2_n2 : &crtc_state->dp_m_n); 14914683babSVille Syrjälä } 15014683babSVille Syrjälä 1513a3dd534SJosé Roberto de Souza static void intel_drrs_set_state(struct drm_i915_private *dev_priv, 152a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state, 1535a220c53SVille Syrjälä enum drrs_refresh_rate refresh_rate) 154a1b63119SJosé Roberto de Souza { 155a1b63119SJosé Roberto de Souza struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 156a1b63119SJosé Roberto de Souza 157*ba770ce3SVille Syrjälä if (!dev_priv->drrs.crtc) { 158a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n"); 159a1b63119SJosé Roberto de Souza return; 160a1b63119SJosé Roberto de Souza } 161a1b63119SJosé Roberto de Souza 162a1b63119SJosé Roberto de Souza if (!crtc) { 163a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 164a1b63119SJosé Roberto de Souza "DRRS: intel_crtc not initialized\n"); 165a1b63119SJosé Roberto de Souza return; 166a1b63119SJosé Roberto de Souza } 167a1b63119SJosé Roberto de Souza 168c25300f0SVille Syrjälä if (dev_priv->vbt.drrs_type != DRRS_TYPE_SEAMLESS) { 169a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n"); 170a1b63119SJosé Roberto de Souza return; 171a1b63119SJosé Roberto de Souza } 172a1b63119SJosé Roberto de Souza 1735a220c53SVille Syrjälä if (refresh_rate == dev_priv->drrs.refresh_rate) 174a1b63119SJosé Roberto de Souza return; 175a1b63119SJosé Roberto de Souza 176a1b63119SJosé Roberto de Souza if (!crtc_state->hw.active) { 177a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 178a1b63119SJosé Roberto de Souza "eDP encoder disabled. CRTC not Active\n"); 179a1b63119SJosé Roberto de Souza return; 180a1b63119SJosé Roberto de Souza } 181a1b63119SJosé Roberto de Souza 18214683babSVille Syrjälä if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) 1835a220c53SVille Syrjälä intel_drrs_set_refresh_rate_m_n(crtc_state, refresh_rate); 18414683babSVille Syrjälä else if (DISPLAY_VER(dev_priv) > 6) 1855a220c53SVille Syrjälä intel_drrs_set_refresh_rate_pipeconf(crtc_state, refresh_rate); 186a1b63119SJosé Roberto de Souza 1875a220c53SVille Syrjälä dev_priv->drrs.refresh_rate = refresh_rate; 188a1b63119SJosé Roberto de Souza 1895a220c53SVille Syrjälä drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %s\n", 1905a220c53SVille Syrjälä refresh_rate == DRRS_REFRESH_RATE_LOW ? "low" : "high"); 191a1b63119SJosé Roberto de Souza } 192a1b63119SJosé Roberto de Souza 193a1b63119SJosé Roberto de Souza static void 194*ba770ce3SVille Syrjälä intel_drrs_enable_locked(struct intel_crtc *crtc) 195a1b63119SJosé Roberto de Souza { 196*ba770ce3SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 197a1b63119SJosé Roberto de Souza 198a1b63119SJosé Roberto de Souza dev_priv->drrs.busy_frontbuffer_bits = 0; 199*ba770ce3SVille Syrjälä dev_priv->drrs.crtc = crtc; 200a1b63119SJosé Roberto de Souza } 201a1b63119SJosé Roberto de Souza 202a1b63119SJosé Roberto de Souza /** 2033a3dd534SJosé Roberto de Souza * intel_drrs_enable - init drrs struct if supported 204a1b63119SJosé Roberto de Souza * @crtc_state: A pointer to the active crtc state. 205a1b63119SJosé Roberto de Souza * 206a1b63119SJosé Roberto de Souza * Initializes frontbuffer_bits and drrs.dp 207a1b63119SJosé Roberto de Souza */ 208*ba770ce3SVille Syrjälä void intel_drrs_enable(const struct intel_crtc_state *crtc_state) 209a1b63119SJosé Roberto de Souza { 210*ba770ce3SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 211*ba770ce3SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 212a1b63119SJosé Roberto de Souza 213a1b63119SJosé Roberto de Souza if (!crtc_state->has_drrs) 214a1b63119SJosé Roberto de Souza return; 215a1b63119SJosé Roberto de Souza 216a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n"); 217a1b63119SJosé Roberto de Souza 218a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 219a1b63119SJosé Roberto de Souza 220*ba770ce3SVille Syrjälä if (dev_priv->drrs.crtc) { 221a1b63119SJosé Roberto de Souza drm_warn(&dev_priv->drm, "DRRS already enabled\n"); 222a1b63119SJosé Roberto de Souza goto unlock; 223a1b63119SJosé Roberto de Souza } 224a1b63119SJosé Roberto de Souza 225*ba770ce3SVille Syrjälä intel_drrs_enable_locked(crtc); 226a1b63119SJosé Roberto de Souza 227a1b63119SJosé Roberto de Souza unlock: 228a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 229a1b63119SJosé Roberto de Souza } 230a1b63119SJosé Roberto de Souza 231a1b63119SJosé Roberto de Souza static void 232*ba770ce3SVille Syrjälä intel_drrs_disable_locked(const struct intel_crtc_state *crtc_state) 233a1b63119SJosé Roberto de Souza { 234*ba770ce3SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 235a1b63119SJosé Roberto de Souza 2365a220c53SVille Syrjälä intel_drrs_set_state(dev_priv, crtc_state, DRRS_REFRESH_RATE_HIGH); 237*ba770ce3SVille Syrjälä dev_priv->drrs.crtc = NULL; 238a1b63119SJosé Roberto de Souza } 239a1b63119SJosé Roberto de Souza 240a1b63119SJosé Roberto de Souza /** 2413a3dd534SJosé Roberto de Souza * intel_drrs_disable - Disable DRRS 242a1b63119SJosé Roberto de Souza * @old_crtc_state: Pointer to old crtc_state. 243a1b63119SJosé Roberto de Souza */ 244*ba770ce3SVille Syrjälä void intel_drrs_disable(const struct intel_crtc_state *old_crtc_state) 245a1b63119SJosé Roberto de Souza { 246*ba770ce3SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 247*ba770ce3SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 248a1b63119SJosé Roberto de Souza 249a1b63119SJosé Roberto de Souza if (!old_crtc_state->has_drrs) 250a1b63119SJosé Roberto de Souza return; 251a1b63119SJosé Roberto de Souza 252a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 253*ba770ce3SVille Syrjälä if (dev_priv->drrs.crtc != crtc) { 254a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 255a1b63119SJosé Roberto de Souza return; 256a1b63119SJosé Roberto de Souza } 257a1b63119SJosé Roberto de Souza 258*ba770ce3SVille Syrjälä intel_drrs_disable_locked(old_crtc_state); 259a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 260a1b63119SJosé Roberto de Souza 261a1b63119SJosé Roberto de Souza cancel_delayed_work_sync(&dev_priv->drrs.work); 262a1b63119SJosé Roberto de Souza } 263a1b63119SJosé Roberto de Souza 264a1b63119SJosé Roberto de Souza /** 2653a3dd534SJosé Roberto de Souza * intel_drrs_update - Update DRRS state 266a1b63119SJosé Roberto de Souza * @crtc_state: new CRTC state 267a1b63119SJosé Roberto de Souza * 268a1b63119SJosé Roberto de Souza * This function will update DRRS states, disabling or enabling DRRS when 2693a3dd534SJosé Roberto de Souza * executing fastsets. For full modeset, intel_drrs_disable() and 2703a3dd534SJosé Roberto de Souza * intel_drrs_enable() should be called instead. 271a1b63119SJosé Roberto de Souza */ 272a1b63119SJosé Roberto de Souza void 273*ba770ce3SVille Syrjälä intel_drrs_update(const struct intel_crtc_state *crtc_state) 274a1b63119SJosé Roberto de Souza { 275*ba770ce3SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 276*ba770ce3SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 277a1b63119SJosé Roberto de Souza 278c25300f0SVille Syrjälä if (dev_priv->vbt.drrs_type != DRRS_TYPE_SEAMLESS) 279a1b63119SJosé Roberto de Souza return; 280a1b63119SJosé Roberto de Souza 281a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 282a1b63119SJosé Roberto de Souza 283a1b63119SJosé Roberto de Souza /* New state matches current one? */ 284*ba770ce3SVille Syrjälä if (crtc_state->has_drrs == !!dev_priv->drrs.crtc) 285a1b63119SJosé Roberto de Souza goto unlock; 286a1b63119SJosé Roberto de Souza 287a1b63119SJosé Roberto de Souza if (crtc_state->has_drrs) 288*ba770ce3SVille Syrjälä intel_drrs_enable_locked(crtc); 289a1b63119SJosé Roberto de Souza else 290*ba770ce3SVille Syrjälä intel_drrs_disable_locked(crtc_state); 291a1b63119SJosé Roberto de Souza 292a1b63119SJosé Roberto de Souza unlock: 293a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 294a1b63119SJosé Roberto de Souza } 295a1b63119SJosé Roberto de Souza 2963a3dd534SJosé Roberto de Souza static void intel_drrs_downclock_work(struct work_struct *work) 297a1b63119SJosé Roberto de Souza { 298a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = 299a1b63119SJosé Roberto de Souza container_of(work, typeof(*dev_priv), drrs.work.work); 300*ba770ce3SVille Syrjälä struct intel_crtc *crtc; 301a1b63119SJosé Roberto de Souza 302a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 303a1b63119SJosé Roberto de Souza 304*ba770ce3SVille Syrjälä crtc = dev_priv->drrs.crtc; 305*ba770ce3SVille Syrjälä if (!crtc) 306a1b63119SJosé Roberto de Souza goto unlock; 307a1b63119SJosé Roberto de Souza 308a1b63119SJosé Roberto de Souza /* 309a1b63119SJosé Roberto de Souza * The delayed work can race with an invalidate hence we need to 310a1b63119SJosé Roberto de Souza * recheck. 311a1b63119SJosé Roberto de Souza */ 312a1b63119SJosé Roberto de Souza 3135a220c53SVille Syrjälä if (!dev_priv->drrs.busy_frontbuffer_bits) { 3145a220c53SVille Syrjälä intel_drrs_set_state(dev_priv, crtc->config, 3155a220c53SVille Syrjälä DRRS_REFRESH_RATE_LOW); 3165a220c53SVille Syrjälä } 317a1b63119SJosé Roberto de Souza 318a1b63119SJosé Roberto de Souza unlock: 319a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 320a1b63119SJosé Roberto de Souza } 321a1b63119SJosé Roberto de Souza 3226bd58b70SJosé Roberto de Souza static void intel_drrs_frontbuffer_update(struct drm_i915_private *dev_priv, 3236bd58b70SJosé Roberto de Souza unsigned int frontbuffer_bits, 3246bd58b70SJosé Roberto de Souza bool invalidate) 325a1b63119SJosé Roberto de Souza { 326*ba770ce3SVille Syrjälä struct intel_crtc *crtc; 327a1b63119SJosé Roberto de Souza 328c25300f0SVille Syrjälä if (dev_priv->vbt.drrs_type != DRRS_TYPE_SEAMLESS) 329a1b63119SJosé Roberto de Souza return; 330a1b63119SJosé Roberto de Souza 331a1b63119SJosé Roberto de Souza cancel_delayed_work(&dev_priv->drrs.work); 332a1b63119SJosé Roberto de Souza 333a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 334a1b63119SJosé Roberto de Souza 335*ba770ce3SVille Syrjälä crtc = dev_priv->drrs.crtc; 336*ba770ce3SVille Syrjälä if (!crtc) { 337a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 338a1b63119SJosé Roberto de Souza return; 339a1b63119SJosé Roberto de Souza } 340a1b63119SJosé Roberto de Souza 341*ba770ce3SVille Syrjälä frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe); 3426bd58b70SJosé Roberto de Souza if (invalidate) 343a1b63119SJosé Roberto de Souza dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; 3446bd58b70SJosé Roberto de Souza else 3456bd58b70SJosé Roberto de Souza dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; 346a1b63119SJosé Roberto de Souza 3476bd58b70SJosé Roberto de Souza /* flush/invalidate means busy screen hence upclock */ 348c7c4dfb6SJosé Roberto de Souza if (frontbuffer_bits) 349*ba770ce3SVille Syrjälä intel_drrs_set_state(dev_priv, crtc->config, 3505a220c53SVille Syrjälä DRRS_REFRESH_RATE_HIGH); 351a1b63119SJosé Roberto de Souza 3526bd58b70SJosé Roberto de Souza /* 3536bd58b70SJosé Roberto de Souza * flush also means no more activity hence schedule downclock, if all 3546bd58b70SJosé Roberto de Souza * other fbs are quiescent too 3556bd58b70SJosé Roberto de Souza */ 3566bd58b70SJosé Roberto de Souza if (!invalidate && !dev_priv->drrs.busy_frontbuffer_bits) 3576bd58b70SJosé Roberto de Souza schedule_delayed_work(&dev_priv->drrs.work, 3586bd58b70SJosé Roberto de Souza msecs_to_jiffies(1000)); 359a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 360a1b63119SJosé Roberto de Souza } 361a1b63119SJosé Roberto de Souza 362a1b63119SJosé Roberto de Souza /** 3636bd58b70SJosé Roberto de Souza * intel_drrs_invalidate - Disable Idleness DRRS 3646bd58b70SJosé Roberto de Souza * @dev_priv: i915 device 3656bd58b70SJosé Roberto de Souza * @frontbuffer_bits: frontbuffer plane tracking bits 3666bd58b70SJosé Roberto de Souza * 3676bd58b70SJosé Roberto de Souza * This function gets called everytime rendering on the given planes start. 3686bd58b70SJosé Roberto de Souza * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). 3696bd58b70SJosé Roberto de Souza * 3706bd58b70SJosé Roberto de Souza * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 3716bd58b70SJosé Roberto de Souza */ 3726bd58b70SJosé Roberto de Souza void intel_drrs_invalidate(struct drm_i915_private *dev_priv, 3736bd58b70SJosé Roberto de Souza unsigned int frontbuffer_bits) 3746bd58b70SJosé Roberto de Souza { 3756bd58b70SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, true); 3766bd58b70SJosé Roberto de Souza } 3776bd58b70SJosé Roberto de Souza 3786bd58b70SJosé Roberto de Souza /** 3793a3dd534SJosé Roberto de Souza * intel_drrs_flush - Restart Idleness DRRS 380a1b63119SJosé Roberto de Souza * @dev_priv: i915 device 381a1b63119SJosé Roberto de Souza * @frontbuffer_bits: frontbuffer plane tracking bits 382a1b63119SJosé Roberto de Souza * 383a1b63119SJosé Roberto de Souza * This function gets called every time rendering on the given planes has 384a1b63119SJosé Roberto de Souza * completed or flip on a crtc is completed. So DRRS should be upclocked 385a1b63119SJosé Roberto de Souza * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, 386a1b63119SJosé Roberto de Souza * if no other planes are dirty. 387a1b63119SJosé Roberto de Souza * 388a1b63119SJosé Roberto de Souza * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 389a1b63119SJosé Roberto de Souza */ 3903a3dd534SJosé Roberto de Souza void intel_drrs_flush(struct drm_i915_private *dev_priv, 391a1b63119SJosé Roberto de Souza unsigned int frontbuffer_bits) 392a1b63119SJosé Roberto de Souza { 3936bd58b70SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false); 394a1b63119SJosé Roberto de Souza } 395a1b63119SJosé Roberto de Souza 3960f3692b5SJosé Roberto de Souza void intel_drrs_page_flip(struct intel_atomic_state *state, 3970f3692b5SJosé Roberto de Souza struct intel_crtc *crtc) 3980f3692b5SJosé Roberto de Souza { 3990f3692b5SJosé Roberto de Souza struct drm_i915_private *dev_priv = to_i915(state->base.dev); 4000f3692b5SJosé Roberto de Souza unsigned int frontbuffer_bits = INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe); 4010f3692b5SJosé Roberto de Souza 4020f3692b5SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false); 4030f3692b5SJosé Roberto de Souza } 4040f3692b5SJosé Roberto de Souza 405a1b63119SJosé Roberto de Souza /** 4063a3dd534SJosé Roberto de Souza * intel_drrs_init - Init basic DRRS work and mutex. 407a1b63119SJosé Roberto de Souza * @connector: eDP connector 408a1b63119SJosé Roberto de Souza * @fixed_mode: preferred mode of panel 409a1b63119SJosé Roberto de Souza * 410a1b63119SJosé Roberto de Souza * This function is called only once at driver load to initialize basic 411a1b63119SJosé Roberto de Souza * DRRS stuff. 412a1b63119SJosé Roberto de Souza * 413a1b63119SJosé Roberto de Souza * Returns: 414a1b63119SJosé Roberto de Souza * Downclock mode if panel supports it, else return NULL. 415a1b63119SJosé Roberto de Souza * DRRS support is determined by the presence of downclock mode (apart 416a1b63119SJosé Roberto de Souza * from VBT setting). 417a1b63119SJosé Roberto de Souza */ 418a1b63119SJosé Roberto de Souza struct drm_display_mode * 4193a3dd534SJosé Roberto de Souza intel_drrs_init(struct intel_connector *connector, 420faf6e8fcSVille Syrjälä const struct drm_display_mode *fixed_mode) 421a1b63119SJosé Roberto de Souza { 422a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 423f0d4ce59SVille Syrjälä struct intel_encoder *encoder = connector->encoder; 424a1b63119SJosé Roberto de Souza struct drm_display_mode *downclock_mode = NULL; 425a1b63119SJosé Roberto de Souza 4263a3dd534SJosé Roberto de Souza INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_drrs_downclock_work); 427a1b63119SJosé Roberto de Souza mutex_init(&dev_priv->drrs.mutex); 428a1b63119SJosé Roberto de Souza 429a1b63119SJosé Roberto de Souza if (DISPLAY_VER(dev_priv) <= 6) { 430a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 4315f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported on platform\n", 4325f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 433a1b63119SJosé Roberto de Souza return NULL; 434a1b63119SJosé Roberto de Souza } 435a1b63119SJosé Roberto de Souza 436f0d4ce59SVille Syrjälä if ((DISPLAY_VER(dev_priv) < 8 && !HAS_GMCH(dev_priv)) && 437f0d4ce59SVille Syrjälä encoder->port != PORT_A) { 438f0d4ce59SVille Syrjälä drm_dbg_kms(&dev_priv->drm, 4395f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported on [ENCODER:%d:%s]\n", 4405f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name, 4415f6a9beaSVille Syrjälä encoder->base.base.id, encoder->base.name); 442f0d4ce59SVille Syrjälä return NULL; 443f0d4ce59SVille Syrjälä } 444f0d4ce59SVille Syrjälä 4458e9c9848SVille Syrjälä if (dev_priv->vbt.drrs_type != DRRS_TYPE_SEAMLESS) { 4465f6a9beaSVille Syrjälä drm_dbg_kms(&dev_priv->drm, 4475f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported according to VBT\n", 4485f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 449a1b63119SJosé Roberto de Souza return NULL; 450a1b63119SJosé Roberto de Souza } 451a1b63119SJosé Roberto de Souza 452a1b63119SJosé Roberto de Souza downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode); 453a1b63119SJosé Roberto de Souza if (!downclock_mode) { 454a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 4555f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported due to lack of downclock mode\n", 4565f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 457a1b63119SJosé Roberto de Souza return NULL; 458a1b63119SJosé Roberto de Souza } 459a1b63119SJosé Roberto de Souza 4605a220c53SVille Syrjälä dev_priv->drrs.refresh_rate = DRRS_REFRESH_RATE_HIGH; 461a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 462a1b952d4SVille Syrjälä "[CONNECTOR:%d:%s] %s DRRS supported\n", 463a1b952d4SVille Syrjälä connector->base.base.id, connector->base.name, 464a1b952d4SVille Syrjälä intel_drrs_type_str(dev_priv->vbt.drrs_type)); 4655f6a9beaSVille Syrjälä 466a1b63119SJosé Roberto de Souza return downclock_mode; 467a1b63119SJosé Roberto de Souza } 468