1a1b63119SJosé Roberto de Souza // SPDX-License-Identifier: MIT 2a1b63119SJosé Roberto de Souza /* 3a1b63119SJosé Roberto de Souza * Copyright © 2021 Intel Corporation 4a1b63119SJosé Roberto de Souza */ 5a1b63119SJosé Roberto de Souza 6a1b63119SJosé Roberto de Souza #include "i915_drv.h" 7a1b63119SJosé Roberto de Souza #include "intel_atomic.h" 8a1b63119SJosé Roberto de Souza #include "intel_de.h" 9a1b63119SJosé Roberto de Souza #include "intel_display_types.h" 10a1b63119SJosé Roberto de Souza #include "intel_drrs.h" 11a1b63119SJosé Roberto de Souza #include "intel_panel.h" 12a1b63119SJosé Roberto de Souza 13a1b63119SJosé Roberto de Souza /** 14a1b63119SJosé Roberto de Souza * DOC: Display Refresh Rate Switching (DRRS) 15a1b63119SJosé Roberto de Souza * 16a1b63119SJosé Roberto de Souza * Display Refresh Rate Switching (DRRS) is a power conservation feature 17a1b63119SJosé Roberto de Souza * which enables swtching between low and high refresh rates, 18a1b63119SJosé Roberto de Souza * dynamically, based on the usage scenario. This feature is applicable 19a1b63119SJosé Roberto de Souza * for internal panels. 20a1b63119SJosé Roberto de Souza * 21a1b63119SJosé Roberto de Souza * Indication that the panel supports DRRS is given by the panel EDID, which 22a1b63119SJosé Roberto de Souza * would list multiple refresh rates for one resolution. 23a1b63119SJosé Roberto de Souza * 24a1b63119SJosé Roberto de Souza * DRRS is of 2 types - static and seamless. 25a1b63119SJosé Roberto de Souza * Static DRRS involves changing refresh rate (RR) by doing a full modeset 26a1b63119SJosé Roberto de Souza * (may appear as a blink on screen) and is used in dock-undock scenario. 27a1b63119SJosé Roberto de Souza * Seamless DRRS involves changing RR without any visual effect to the user 28a1b63119SJosé Roberto de Souza * and can be used during normal system usage. This is done by programming 29a1b63119SJosé Roberto de Souza * certain registers. 30a1b63119SJosé Roberto de Souza * 31a1b63119SJosé Roberto de Souza * Support for static/seamless DRRS may be indicated in the VBT based on 32a1b63119SJosé Roberto de Souza * inputs from the panel spec. 33a1b63119SJosé Roberto de Souza * 34a1b63119SJosé Roberto de Souza * DRRS saves power by switching to low RR based on usage scenarios. 35a1b63119SJosé Roberto de Souza * 36a1b63119SJosé Roberto de Souza * The implementation is based on frontbuffer tracking implementation. When 37a1b63119SJosé Roberto de Souza * there is a disturbance on the screen triggered by user activity or a periodic 38a1b63119SJosé Roberto de Souza * system activity, DRRS is disabled (RR is changed to high RR). When there is 39a1b63119SJosé Roberto de Souza * no movement on screen, after a timeout of 1 second, a switch to low RR is 40a1b63119SJosé Roberto de Souza * made. 41a1b63119SJosé Roberto de Souza * 423a3dd534SJosé Roberto de Souza * For integration with frontbuffer tracking code, intel_drrs_invalidate() 433a3dd534SJosé Roberto de Souza * and intel_drrs_flush() are called. 44a1b63119SJosé Roberto de Souza * 45a1b63119SJosé Roberto de Souza * DRRS can be further extended to support other internal panels and also 46a1b63119SJosé Roberto de Souza * the scenario of video playback wherein RR is set based on the rate 47a1b63119SJosé Roberto de Souza * requested by userspace. 48a1b63119SJosé Roberto de Souza */ 49a1b63119SJosé Roberto de Souza 50c3e27f43SVille Syrjälä static bool can_enable_drrs(struct intel_connector *connector, 51c3e27f43SVille Syrjälä const struct intel_crtc_state *pipe_config) 52a1b63119SJosé Roberto de Souza { 53c3e27f43SVille Syrjälä const struct drm_i915_private *i915 = to_i915(connector->base.dev); 54a1b63119SJosé Roberto de Souza 55a1b63119SJosé Roberto de Souza if (pipe_config->vrr.enable) 56c3e27f43SVille Syrjälä return false; 57a1b63119SJosé Roberto de Souza 58a1b63119SJosé Roberto de Souza /* 59a1b63119SJosé Roberto de Souza * DRRS and PSR can't be enable together, so giving preference to PSR 60a1b63119SJosé Roberto de Souza * as it allows more power-savings by complete shutting down display, 613a3dd534SJosé Roberto de Souza * so to guarantee this, intel_drrs_compute_config() must be called 62a1b63119SJosé Roberto de Souza * after intel_psr_compute_config(). 63a1b63119SJosé Roberto de Souza */ 64a1b63119SJosé Roberto de Souza if (pipe_config->has_psr) 65c3e27f43SVille Syrjälä return false; 66a1b63119SJosé Roberto de Souza 67c3e27f43SVille Syrjälä return connector->panel.downclock_mode && 68*8e9c9848SVille Syrjälä i915->drrs.type == DRRS_TYPE_SEAMLESS; 69c3e27f43SVille Syrjälä } 70c3e27f43SVille Syrjälä 71c3e27f43SVille Syrjälä void 72c3e27f43SVille Syrjälä intel_drrs_compute_config(struct intel_dp *intel_dp, 73c3e27f43SVille Syrjälä struct intel_crtc_state *pipe_config, 74c3e27f43SVille Syrjälä int output_bpp, bool constant_n) 75c3e27f43SVille Syrjälä { 76c3e27f43SVille Syrjälä struct intel_connector *connector = intel_dp->attached_connector; 771d06c820SVille Syrjälä struct drm_i915_private *i915 = to_i915(connector->base.dev); 78c3e27f43SVille Syrjälä int pixel_clock; 79c3e27f43SVille Syrjälä 801d06c820SVille Syrjälä if (!can_enable_drrs(connector, pipe_config)) { 811d06c820SVille Syrjälä if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder)) 821d06c820SVille Syrjälä intel_zero_m_n(&pipe_config->dp_m2_n2); 83a1b63119SJosé Roberto de Souza return; 841d06c820SVille Syrjälä } 85a1b63119SJosé Roberto de Souza 861fa7bb12SVille Syrjälä if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) 871fa7bb12SVille Syrjälä pipe_config->msa_timing_delay = i915->vbt.edp.drrs_msa_timing_delay; 881fa7bb12SVille Syrjälä 89a1b63119SJosé Roberto de Souza pipe_config->has_drrs = true; 90a1b63119SJosé Roberto de Souza 91c3e27f43SVille Syrjälä pixel_clock = connector->panel.downclock_mode->clock; 92a1b63119SJosé Roberto de Souza if (pipe_config->splitter.enable) 93a1b63119SJosé Roberto de Souza pixel_clock /= pipe_config->splitter.link_count; 94a1b63119SJosé Roberto de Souza 95a1b63119SJosé Roberto de Souza intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock, 96a1b63119SJosé Roberto de Souza pipe_config->port_clock, &pipe_config->dp_m2_n2, 97a1b63119SJosé Roberto de Souza constant_n, pipe_config->fec_enable); 98a1b63119SJosé Roberto de Souza 99a1b63119SJosé Roberto de Souza /* FIXME: abstract this better */ 100a1b63119SJosé Roberto de Souza if (pipe_config->splitter.enable) 1015f721a5dSVille Syrjälä pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; 102a1b63119SJosé Roberto de Souza } 103a1b63119SJosé Roberto de Souza 10414683babSVille Syrjälä static void 10514683babSVille Syrjälä intel_drrs_set_refresh_rate_pipeconf(const struct intel_crtc_state *crtc_state, 10614683babSVille Syrjälä enum drrs_refresh_rate_type refresh_type) 10714683babSVille Syrjälä { 10814683babSVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 10914683babSVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 11014683babSVille Syrjälä enum transcoder cpu_transcoder = crtc_state->cpu_transcoder; 11114683babSVille Syrjälä u32 val, bit; 11214683babSVille Syrjälä 11314683babSVille Syrjälä if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 11414683babSVille Syrjälä bit = PIPECONF_EDP_RR_MODE_SWITCH_VLV; 11514683babSVille Syrjälä else 11614683babSVille Syrjälä bit = PIPECONF_EDP_RR_MODE_SWITCH; 11714683babSVille Syrjälä 11814683babSVille Syrjälä val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 11914683babSVille Syrjälä 12014683babSVille Syrjälä if (refresh_type == DRRS_LOW_RR) 12114683babSVille Syrjälä val |= bit; 12214683babSVille Syrjälä else 12314683babSVille Syrjälä val &= ~bit; 12414683babSVille Syrjälä 12514683babSVille Syrjälä intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 12614683babSVille Syrjälä } 12714683babSVille Syrjälä 12814683babSVille Syrjälä static void 12914683babSVille Syrjälä intel_drrs_set_refresh_rate_m_n(const struct intel_crtc_state *crtc_state, 13014683babSVille Syrjälä enum drrs_refresh_rate_type refresh_type) 13114683babSVille Syrjälä { 1320adc41deSVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1330adc41deSVille Syrjälä 1340adc41deSVille Syrjälä intel_cpu_transcoder_set_m1_n1(crtc, crtc_state->cpu_transcoder, 1350adc41deSVille Syrjälä refresh_type == DRRS_LOW_RR ? 136be0c94eeSVille Syrjälä &crtc_state->dp_m2_n2 : &crtc_state->dp_m_n); 13714683babSVille Syrjälä } 13814683babSVille Syrjälä 1393a3dd534SJosé Roberto de Souza static void intel_drrs_set_state(struct drm_i915_private *dev_priv, 140a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state, 141c7c4dfb6SJosé Roberto de Souza enum drrs_refresh_rate_type refresh_type) 142a1b63119SJosé Roberto de Souza { 143a1b63119SJosé Roberto de Souza struct intel_dp *intel_dp = dev_priv->drrs.dp; 144a1b63119SJosé Roberto de Souza struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 145c7c4dfb6SJosé Roberto de Souza struct drm_display_mode *mode; 146a1b63119SJosé Roberto de Souza 147c7c4dfb6SJosé Roberto de Souza if (!intel_dp) { 148a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n"); 149a1b63119SJosé Roberto de Souza return; 150a1b63119SJosé Roberto de Souza } 151a1b63119SJosé Roberto de Souza 152a1b63119SJosé Roberto de Souza if (!crtc) { 153a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 154a1b63119SJosé Roberto de Souza "DRRS: intel_crtc not initialized\n"); 155a1b63119SJosé Roberto de Souza return; 156a1b63119SJosé Roberto de Souza } 157a1b63119SJosé Roberto de Souza 158*8e9c9848SVille Syrjälä if (dev_priv->drrs.type != DRRS_TYPE_SEAMLESS) { 159a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n"); 160a1b63119SJosé Roberto de Souza return; 161a1b63119SJosé Roberto de Souza } 162a1b63119SJosé Roberto de Souza 163c7c4dfb6SJosé Roberto de Souza if (refresh_type == dev_priv->drrs.refresh_rate_type) 164a1b63119SJosé Roberto de Souza return; 165a1b63119SJosé Roberto de Souza 166a1b63119SJosé Roberto de Souza if (!crtc_state->hw.active) { 167a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 168a1b63119SJosé Roberto de Souza "eDP encoder disabled. CRTC not Active\n"); 169a1b63119SJosé Roberto de Souza return; 170a1b63119SJosé Roberto de Souza } 171a1b63119SJosé Roberto de Souza 17214683babSVille Syrjälä if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) 17314683babSVille Syrjälä intel_drrs_set_refresh_rate_m_n(crtc_state, refresh_type); 17414683babSVille Syrjälä else if (DISPLAY_VER(dev_priv) > 6) 17514683babSVille Syrjälä intel_drrs_set_refresh_rate_pipeconf(crtc_state, refresh_type); 176a1b63119SJosé Roberto de Souza 177c7c4dfb6SJosé Roberto de Souza dev_priv->drrs.refresh_rate_type = refresh_type; 178a1b63119SJosé Roberto de Souza 179c7c4dfb6SJosé Roberto de Souza if (refresh_type == DRRS_LOW_RR) 180c7c4dfb6SJosé Roberto de Souza mode = intel_dp->attached_connector->panel.downclock_mode; 181c7c4dfb6SJosé Roberto de Souza else 182c7c4dfb6SJosé Roberto de Souza mode = intel_dp->attached_connector->panel.fixed_mode; 183a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n", 184c7c4dfb6SJosé Roberto de Souza drm_mode_vrefresh(mode)); 185a1b63119SJosé Roberto de Souza } 186a1b63119SJosé Roberto de Souza 187a1b63119SJosé Roberto de Souza static void 1883a3dd534SJosé Roberto de Souza intel_drrs_enable_locked(struct intel_dp *intel_dp) 189a1b63119SJosé Roberto de Souza { 190a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 191a1b63119SJosé Roberto de Souza 192a1b63119SJosé Roberto de Souza dev_priv->drrs.busy_frontbuffer_bits = 0; 193a1b63119SJosé Roberto de Souza dev_priv->drrs.dp = intel_dp; 194a1b63119SJosé Roberto de Souza } 195a1b63119SJosé Roberto de Souza 196a1b63119SJosé Roberto de Souza /** 1973a3dd534SJosé Roberto de Souza * intel_drrs_enable - init drrs struct if supported 198a1b63119SJosé Roberto de Souza * @intel_dp: DP struct 199a1b63119SJosé Roberto de Souza * @crtc_state: A pointer to the active crtc state. 200a1b63119SJosé Roberto de Souza * 201a1b63119SJosé Roberto de Souza * Initializes frontbuffer_bits and drrs.dp 202a1b63119SJosé Roberto de Souza */ 2033a3dd534SJosé Roberto de Souza void intel_drrs_enable(struct intel_dp *intel_dp, 204a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state) 205a1b63119SJosé Roberto de Souza { 206a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 207a1b63119SJosé Roberto de Souza 208a1b63119SJosé Roberto de Souza if (!crtc_state->has_drrs) 209a1b63119SJosé Roberto de Souza return; 210a1b63119SJosé Roberto de Souza 211a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n"); 212a1b63119SJosé Roberto de Souza 213a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 214a1b63119SJosé Roberto de Souza 215a1b63119SJosé Roberto de Souza if (dev_priv->drrs.dp) { 216a1b63119SJosé Roberto de Souza drm_warn(&dev_priv->drm, "DRRS already enabled\n"); 217a1b63119SJosé Roberto de Souza goto unlock; 218a1b63119SJosé Roberto de Souza } 219a1b63119SJosé Roberto de Souza 2203a3dd534SJosé Roberto de Souza intel_drrs_enable_locked(intel_dp); 221a1b63119SJosé Roberto de Souza 222a1b63119SJosé Roberto de Souza unlock: 223a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 224a1b63119SJosé Roberto de Souza } 225a1b63119SJosé Roberto de Souza 226a1b63119SJosé Roberto de Souza static void 2273a3dd534SJosé Roberto de Souza intel_drrs_disable_locked(struct intel_dp *intel_dp, 228a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state) 229a1b63119SJosé Roberto de Souza { 230a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 231a1b63119SJosé Roberto de Souza 232c7c4dfb6SJosé Roberto de Souza intel_drrs_set_state(dev_priv, crtc_state, DRRS_HIGH_RR); 233a1b63119SJosé Roberto de Souza dev_priv->drrs.dp = NULL; 234a1b63119SJosé Roberto de Souza } 235a1b63119SJosé Roberto de Souza 236a1b63119SJosé Roberto de Souza /** 2373a3dd534SJosé Roberto de Souza * intel_drrs_disable - Disable DRRS 238a1b63119SJosé Roberto de Souza * @intel_dp: DP struct 239a1b63119SJosé Roberto de Souza * @old_crtc_state: Pointer to old crtc_state. 240a1b63119SJosé Roberto de Souza * 241a1b63119SJosé Roberto de Souza */ 2423a3dd534SJosé Roberto de Souza void intel_drrs_disable(struct intel_dp *intel_dp, 243a1b63119SJosé Roberto de Souza const struct intel_crtc_state *old_crtc_state) 244a1b63119SJosé Roberto de Souza { 245a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 246a1b63119SJosé Roberto de Souza 247a1b63119SJosé Roberto de Souza if (!old_crtc_state->has_drrs) 248a1b63119SJosé Roberto de Souza return; 249a1b63119SJosé Roberto de Souza 250a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 251a1b63119SJosé Roberto de Souza if (!dev_priv->drrs.dp) { 252a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 253a1b63119SJosé Roberto de Souza return; 254a1b63119SJosé Roberto de Souza } 255a1b63119SJosé Roberto de Souza 2563a3dd534SJosé Roberto de Souza intel_drrs_disable_locked(intel_dp, old_crtc_state); 257a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 258a1b63119SJosé Roberto de Souza 259a1b63119SJosé Roberto de Souza cancel_delayed_work_sync(&dev_priv->drrs.work); 260a1b63119SJosé Roberto de Souza } 261a1b63119SJosé Roberto de Souza 262a1b63119SJosé Roberto de Souza /** 2633a3dd534SJosé Roberto de Souza * intel_drrs_update - Update DRRS state 264a1b63119SJosé Roberto de Souza * @intel_dp: Intel DP 265a1b63119SJosé Roberto de Souza * @crtc_state: new CRTC state 266a1b63119SJosé Roberto de Souza * 267a1b63119SJosé Roberto de Souza * This function will update DRRS states, disabling or enabling DRRS when 2683a3dd534SJosé Roberto de Souza * executing fastsets. For full modeset, intel_drrs_disable() and 2693a3dd534SJosé Roberto de Souza * intel_drrs_enable() should be called instead. 270a1b63119SJosé Roberto de Souza */ 271a1b63119SJosé Roberto de Souza void 2723a3dd534SJosé Roberto de Souza intel_drrs_update(struct intel_dp *intel_dp, 273a1b63119SJosé Roberto de Souza const struct intel_crtc_state *crtc_state) 274a1b63119SJosé Roberto de Souza { 275a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 276a1b63119SJosé Roberto de Souza 277*8e9c9848SVille Syrjälä if (dev_priv->drrs.type != DRRS_TYPE_SEAMLESS) 278a1b63119SJosé Roberto de Souza return; 279a1b63119SJosé Roberto de Souza 280a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 281a1b63119SJosé Roberto de Souza 282a1b63119SJosé Roberto de Souza /* New state matches current one? */ 283a1b63119SJosé Roberto de Souza if (crtc_state->has_drrs == !!dev_priv->drrs.dp) 284a1b63119SJosé Roberto de Souza goto unlock; 285a1b63119SJosé Roberto de Souza 286a1b63119SJosé Roberto de Souza if (crtc_state->has_drrs) 2873a3dd534SJosé Roberto de Souza intel_drrs_enable_locked(intel_dp); 288a1b63119SJosé Roberto de Souza else 2893a3dd534SJosé Roberto de Souza intel_drrs_disable_locked(intel_dp, crtc_state); 290a1b63119SJosé Roberto de Souza 291a1b63119SJosé Roberto de Souza unlock: 292a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 293a1b63119SJosé Roberto de Souza } 294a1b63119SJosé Roberto de Souza 2953a3dd534SJosé Roberto de Souza static void intel_drrs_downclock_work(struct work_struct *work) 296a1b63119SJosé Roberto de Souza { 297a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = 298a1b63119SJosé Roberto de Souza container_of(work, typeof(*dev_priv), drrs.work.work); 299a1b63119SJosé Roberto de Souza struct intel_dp *intel_dp; 300c7c4dfb6SJosé Roberto de Souza struct drm_crtc *crtc; 301a1b63119SJosé Roberto de Souza 302a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 303a1b63119SJosé Roberto de Souza 304a1b63119SJosé Roberto de Souza intel_dp = dev_priv->drrs.dp; 305a1b63119SJosé Roberto de Souza 306a1b63119SJosé Roberto de Souza if (!intel_dp) 307a1b63119SJosé Roberto de Souza goto unlock; 308a1b63119SJosé Roberto de Souza 309a1b63119SJosé Roberto de Souza /* 310a1b63119SJosé Roberto de Souza * The delayed work can race with an invalidate hence we need to 311a1b63119SJosé Roberto de Souza * recheck. 312a1b63119SJosé Roberto de Souza */ 313a1b63119SJosé Roberto de Souza 314a1b63119SJosé Roberto de Souza if (dev_priv->drrs.busy_frontbuffer_bits) 315a1b63119SJosé Roberto de Souza goto unlock; 316a1b63119SJosé Roberto de Souza 317c7c4dfb6SJosé Roberto de Souza crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 318c7c4dfb6SJosé Roberto de Souza intel_drrs_set_state(dev_priv, to_intel_crtc(crtc)->config, DRRS_LOW_RR); 319a1b63119SJosé Roberto de Souza 320a1b63119SJosé Roberto de Souza unlock: 321a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 322a1b63119SJosé Roberto de Souza } 323a1b63119SJosé Roberto de Souza 3246bd58b70SJosé Roberto de Souza static void intel_drrs_frontbuffer_update(struct drm_i915_private *dev_priv, 3256bd58b70SJosé Roberto de Souza unsigned int frontbuffer_bits, 3266bd58b70SJosé Roberto de Souza bool invalidate) 327a1b63119SJosé Roberto de Souza { 328a1b63119SJosé Roberto de Souza struct intel_dp *intel_dp; 329a1b63119SJosé Roberto de Souza struct drm_crtc *crtc; 330a1b63119SJosé Roberto de Souza enum pipe pipe; 331a1b63119SJosé Roberto de Souza 332*8e9c9848SVille Syrjälä if (dev_priv->drrs.type != DRRS_TYPE_SEAMLESS) 333a1b63119SJosé Roberto de Souza return; 334a1b63119SJosé Roberto de Souza 335a1b63119SJosé Roberto de Souza cancel_delayed_work(&dev_priv->drrs.work); 336a1b63119SJosé Roberto de Souza 337a1b63119SJosé Roberto de Souza mutex_lock(&dev_priv->drrs.mutex); 338a1b63119SJosé Roberto de Souza 339a1b63119SJosé Roberto de Souza intel_dp = dev_priv->drrs.dp; 340a1b63119SJosé Roberto de Souza if (!intel_dp) { 341a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 342a1b63119SJosé Roberto de Souza return; 343a1b63119SJosé Roberto de Souza } 344a1b63119SJosé Roberto de Souza 345a1b63119SJosé Roberto de Souza crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 346a1b63119SJosé Roberto de Souza pipe = to_intel_crtc(crtc)->pipe; 347a1b63119SJosé Roberto de Souza 348a1b63119SJosé Roberto de Souza frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 3496bd58b70SJosé Roberto de Souza if (invalidate) 350a1b63119SJosé Roberto de Souza dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; 3516bd58b70SJosé Roberto de Souza else 3526bd58b70SJosé Roberto de Souza dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; 353a1b63119SJosé Roberto de Souza 3546bd58b70SJosé Roberto de Souza /* flush/invalidate means busy screen hence upclock */ 355c7c4dfb6SJosé Roberto de Souza if (frontbuffer_bits) 3563a3dd534SJosé Roberto de Souza intel_drrs_set_state(dev_priv, to_intel_crtc(crtc)->config, 357c7c4dfb6SJosé Roberto de Souza DRRS_HIGH_RR); 358a1b63119SJosé Roberto de Souza 3596bd58b70SJosé Roberto de Souza /* 3606bd58b70SJosé Roberto de Souza * flush also means no more activity hence schedule downclock, if all 3616bd58b70SJosé Roberto de Souza * other fbs are quiescent too 3626bd58b70SJosé Roberto de Souza */ 3636bd58b70SJosé Roberto de Souza if (!invalidate && !dev_priv->drrs.busy_frontbuffer_bits) 3646bd58b70SJosé Roberto de Souza schedule_delayed_work(&dev_priv->drrs.work, 3656bd58b70SJosé Roberto de Souza msecs_to_jiffies(1000)); 366a1b63119SJosé Roberto de Souza mutex_unlock(&dev_priv->drrs.mutex); 367a1b63119SJosé Roberto de Souza } 368a1b63119SJosé Roberto de Souza 369a1b63119SJosé Roberto de Souza /** 3706bd58b70SJosé Roberto de Souza * intel_drrs_invalidate - Disable Idleness DRRS 3716bd58b70SJosé Roberto de Souza * @dev_priv: i915 device 3726bd58b70SJosé Roberto de Souza * @frontbuffer_bits: frontbuffer plane tracking bits 3736bd58b70SJosé Roberto de Souza * 3746bd58b70SJosé Roberto de Souza * This function gets called everytime rendering on the given planes start. 3756bd58b70SJosé Roberto de Souza * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). 3766bd58b70SJosé Roberto de Souza * 3776bd58b70SJosé Roberto de Souza * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 3786bd58b70SJosé Roberto de Souza */ 3796bd58b70SJosé Roberto de Souza void intel_drrs_invalidate(struct drm_i915_private *dev_priv, 3806bd58b70SJosé Roberto de Souza unsigned int frontbuffer_bits) 3816bd58b70SJosé Roberto de Souza { 3826bd58b70SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, true); 3836bd58b70SJosé Roberto de Souza } 3846bd58b70SJosé Roberto de Souza 3856bd58b70SJosé Roberto de Souza /** 3863a3dd534SJosé Roberto de Souza * intel_drrs_flush - Restart Idleness DRRS 387a1b63119SJosé Roberto de Souza * @dev_priv: i915 device 388a1b63119SJosé Roberto de Souza * @frontbuffer_bits: frontbuffer plane tracking bits 389a1b63119SJosé Roberto de Souza * 390a1b63119SJosé Roberto de Souza * This function gets called every time rendering on the given planes has 391a1b63119SJosé Roberto de Souza * completed or flip on a crtc is completed. So DRRS should be upclocked 392a1b63119SJosé Roberto de Souza * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, 393a1b63119SJosé Roberto de Souza * if no other planes are dirty. 394a1b63119SJosé Roberto de Souza * 395a1b63119SJosé Roberto de Souza * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 396a1b63119SJosé Roberto de Souza */ 3973a3dd534SJosé Roberto de Souza void intel_drrs_flush(struct drm_i915_private *dev_priv, 398a1b63119SJosé Roberto de Souza unsigned int frontbuffer_bits) 399a1b63119SJosé Roberto de Souza { 4006bd58b70SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false); 401a1b63119SJosé Roberto de Souza } 402a1b63119SJosé Roberto de Souza 4030f3692b5SJosé Roberto de Souza void intel_drrs_page_flip(struct intel_atomic_state *state, 4040f3692b5SJosé Roberto de Souza struct intel_crtc *crtc) 4050f3692b5SJosé Roberto de Souza { 4060f3692b5SJosé Roberto de Souza struct drm_i915_private *dev_priv = to_i915(state->base.dev); 4070f3692b5SJosé Roberto de Souza unsigned int frontbuffer_bits = INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe); 4080f3692b5SJosé Roberto de Souza 4090f3692b5SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false); 4100f3692b5SJosé Roberto de Souza } 4110f3692b5SJosé Roberto de Souza 412a1b63119SJosé Roberto de Souza /** 4133a3dd534SJosé Roberto de Souza * intel_drrs_init - Init basic DRRS work and mutex. 414a1b63119SJosé Roberto de Souza * @connector: eDP connector 415a1b63119SJosé Roberto de Souza * @fixed_mode: preferred mode of panel 416a1b63119SJosé Roberto de Souza * 417a1b63119SJosé Roberto de Souza * This function is called only once at driver load to initialize basic 418a1b63119SJosé Roberto de Souza * DRRS stuff. 419a1b63119SJosé Roberto de Souza * 420a1b63119SJosé Roberto de Souza * Returns: 421a1b63119SJosé Roberto de Souza * Downclock mode if panel supports it, else return NULL. 422a1b63119SJosé Roberto de Souza * DRRS support is determined by the presence of downclock mode (apart 423a1b63119SJosé Roberto de Souza * from VBT setting). 424a1b63119SJosé Roberto de Souza */ 425a1b63119SJosé Roberto de Souza struct drm_display_mode * 4263a3dd534SJosé Roberto de Souza intel_drrs_init(struct intel_connector *connector, 427faf6e8fcSVille Syrjälä const struct drm_display_mode *fixed_mode) 428a1b63119SJosé Roberto de Souza { 429a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 430f0d4ce59SVille Syrjälä struct intel_encoder *encoder = connector->encoder; 431a1b63119SJosé Roberto de Souza struct drm_display_mode *downclock_mode = NULL; 432a1b63119SJosé Roberto de Souza 4333a3dd534SJosé Roberto de Souza INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_drrs_downclock_work); 434a1b63119SJosé Roberto de Souza mutex_init(&dev_priv->drrs.mutex); 435a1b63119SJosé Roberto de Souza 436a1b63119SJosé Roberto de Souza if (DISPLAY_VER(dev_priv) <= 6) { 437a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 4385f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported on platform\n", 4395f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 440a1b63119SJosé Roberto de Souza return NULL; 441a1b63119SJosé Roberto de Souza } 442a1b63119SJosé Roberto de Souza 443f0d4ce59SVille Syrjälä if ((DISPLAY_VER(dev_priv) < 8 && !HAS_GMCH(dev_priv)) && 444f0d4ce59SVille Syrjälä encoder->port != PORT_A) { 445f0d4ce59SVille Syrjälä drm_dbg_kms(&dev_priv->drm, 4465f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported on [ENCODER:%d:%s]\n", 4475f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name, 4485f6a9beaSVille Syrjälä encoder->base.base.id, encoder->base.name); 449f0d4ce59SVille Syrjälä return NULL; 450f0d4ce59SVille Syrjälä } 451f0d4ce59SVille Syrjälä 452*8e9c9848SVille Syrjälä if (dev_priv->vbt.drrs_type != DRRS_TYPE_SEAMLESS) { 4535f6a9beaSVille Syrjälä drm_dbg_kms(&dev_priv->drm, 4545f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported according to VBT\n", 4555f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 456a1b63119SJosé Roberto de Souza return NULL; 457a1b63119SJosé Roberto de Souza } 458a1b63119SJosé Roberto de Souza 459a1b63119SJosé Roberto de Souza downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode); 460a1b63119SJosé Roberto de Souza if (!downclock_mode) { 461a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 4625f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported due to lack of downclock mode\n", 4635f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 464a1b63119SJosé Roberto de Souza return NULL; 465a1b63119SJosé Roberto de Souza } 466a1b63119SJosé Roberto de Souza 467a1b63119SJosé Roberto de Souza dev_priv->drrs.type = dev_priv->vbt.drrs_type; 468a1b63119SJosé Roberto de Souza 469a1b63119SJosé Roberto de Souza dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; 470a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 4715f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] seamless DRRS supported\n", 4725f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 4735f6a9beaSVille Syrjälä 474a1b63119SJosé Roberto de Souza return downclock_mode; 475a1b63119SJosé Roberto de Souza } 476