1a1b63119SJosé Roberto de Souza // SPDX-License-Identifier: MIT 2a1b63119SJosé Roberto de Souza /* 3a1b63119SJosé Roberto de Souza * Copyright © 2021 Intel Corporation 4a1b63119SJosé Roberto de Souza */ 5a1b63119SJosé Roberto de Souza 6a1b63119SJosé Roberto de Souza #include "i915_drv.h" 7a1b63119SJosé Roberto de Souza #include "intel_atomic.h" 8a1b63119SJosé Roberto de Souza #include "intel_de.h" 9a1b63119SJosé Roberto de Souza #include "intel_display_types.h" 10a1b63119SJosé Roberto de Souza #include "intel_drrs.h" 11a1b63119SJosé Roberto de Souza #include "intel_panel.h" 12a1b63119SJosé Roberto de Souza 13a1b63119SJosé Roberto de Souza /** 14a1b63119SJosé Roberto de Souza * DOC: Display Refresh Rate Switching (DRRS) 15a1b63119SJosé Roberto de Souza * 16a1b63119SJosé Roberto de Souza * Display Refresh Rate Switching (DRRS) is a power conservation feature 17a1b63119SJosé Roberto de Souza * which enables swtching between low and high refresh rates, 18a1b63119SJosé Roberto de Souza * dynamically, based on the usage scenario. This feature is applicable 19a1b63119SJosé Roberto de Souza * for internal panels. 20a1b63119SJosé Roberto de Souza * 21a1b63119SJosé Roberto de Souza * Indication that the panel supports DRRS is given by the panel EDID, which 22a1b63119SJosé Roberto de Souza * would list multiple refresh rates for one resolution. 23a1b63119SJosé Roberto de Souza * 24a1b63119SJosé Roberto de Souza * DRRS is of 2 types - static and seamless. 25a1b63119SJosé Roberto de Souza * Static DRRS involves changing refresh rate (RR) by doing a full modeset 26a1b63119SJosé Roberto de Souza * (may appear as a blink on screen) and is used in dock-undock scenario. 27a1b63119SJosé Roberto de Souza * Seamless DRRS involves changing RR without any visual effect to the user 28a1b63119SJosé Roberto de Souza * and can be used during normal system usage. This is done by programming 29a1b63119SJosé Roberto de Souza * certain registers. 30a1b63119SJosé Roberto de Souza * 31a1b63119SJosé Roberto de Souza * Support for static/seamless DRRS may be indicated in the VBT based on 32a1b63119SJosé Roberto de Souza * inputs from the panel spec. 33a1b63119SJosé Roberto de Souza * 34a1b63119SJosé Roberto de Souza * DRRS saves power by switching to low RR based on usage scenarios. 35a1b63119SJosé Roberto de Souza * 36a1b63119SJosé Roberto de Souza * The implementation is based on frontbuffer tracking implementation. When 37a1b63119SJosé Roberto de Souza * there is a disturbance on the screen triggered by user activity or a periodic 38a1b63119SJosé Roberto de Souza * system activity, DRRS is disabled (RR is changed to high RR). When there is 39a1b63119SJosé Roberto de Souza * no movement on screen, after a timeout of 1 second, a switch to low RR is 40a1b63119SJosé Roberto de Souza * made. 41a1b63119SJosé Roberto de Souza * 423a3dd534SJosé Roberto de Souza * For integration with frontbuffer tracking code, intel_drrs_invalidate() 433a3dd534SJosé Roberto de Souza * and intel_drrs_flush() are called. 44a1b63119SJosé Roberto de Souza * 45a1b63119SJosé Roberto de Souza * DRRS can be further extended to support other internal panels and also 46a1b63119SJosé Roberto de Souza * the scenario of video playback wherein RR is set based on the rate 47a1b63119SJosé Roberto de Souza * requested by userspace. 48a1b63119SJosé Roberto de Souza */ 49a1b63119SJosé Roberto de Souza 50a1b952d4SVille Syrjälä const char *intel_drrs_type_str(enum drrs_type drrs_type) 51a1b952d4SVille Syrjälä { 52a1b952d4SVille Syrjälä static const char * const str[] = { 53a1b952d4SVille Syrjälä [DRRS_TYPE_NONE] = "none", 54a1b952d4SVille Syrjälä [DRRS_TYPE_STATIC] = "static", 55a1b952d4SVille Syrjälä [DRRS_TYPE_SEAMLESS] = "seamless", 56a1b952d4SVille Syrjälä }; 57a1b952d4SVille Syrjälä 58a1b952d4SVille Syrjälä if (drrs_type >= ARRAY_SIZE(str)) 59a1b952d4SVille Syrjälä return "<invalid>"; 60a1b952d4SVille Syrjälä 61a1b952d4SVille Syrjälä return str[drrs_type]; 62a1b952d4SVille Syrjälä } 63a1b952d4SVille Syrjälä 64c3e27f43SVille Syrjälä static bool can_enable_drrs(struct intel_connector *connector, 65*2260e4d8SVille Syrjälä const struct intel_crtc_state *pipe_config, 66*2260e4d8SVille Syrjälä const struct drm_display_mode *downclock_mode) 67a1b63119SJosé Roberto de Souza { 68a1b63119SJosé Roberto de Souza if (pipe_config->vrr.enable) 69c3e27f43SVille Syrjälä return false; 70a1b63119SJosé Roberto de Souza 71a1b63119SJosé Roberto de Souza /* 72a1b63119SJosé Roberto de Souza * DRRS and PSR can't be enable together, so giving preference to PSR 73a1b63119SJosé Roberto de Souza * as it allows more power-savings by complete shutting down display, 743a3dd534SJosé Roberto de Souza * so to guarantee this, intel_drrs_compute_config() must be called 75a1b63119SJosé Roberto de Souza * after intel_psr_compute_config(). 76a1b63119SJosé Roberto de Souza */ 77a1b63119SJosé Roberto de Souza if (pipe_config->has_psr) 78c3e27f43SVille Syrjälä return false; 79a1b63119SJosé Roberto de Souza 80*2260e4d8SVille Syrjälä return downclock_mode && 81*2260e4d8SVille Syrjälä intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 82c3e27f43SVille Syrjälä } 83c3e27f43SVille Syrjälä 84c3e27f43SVille Syrjälä void 85ba770ce3SVille Syrjälä intel_drrs_compute_config(struct intel_connector *connector, 86c3e27f43SVille Syrjälä struct intel_crtc_state *pipe_config, 87c3e27f43SVille Syrjälä int output_bpp, bool constant_n) 88c3e27f43SVille Syrjälä { 891d06c820SVille Syrjälä struct drm_i915_private *i915 = to_i915(connector->base.dev); 9009270678SVille Syrjälä const struct drm_display_mode *downclock_mode = 9109270678SVille Syrjälä intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); 92c3e27f43SVille Syrjälä int pixel_clock; 93c3e27f43SVille Syrjälä 94*2260e4d8SVille Syrjälä if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { 951d06c820SVille Syrjälä if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder)) 961d06c820SVille Syrjälä intel_zero_m_n(&pipe_config->dp_m2_n2); 97a1b63119SJosé Roberto de Souza return; 981d06c820SVille Syrjälä } 99a1b63119SJosé Roberto de Souza 1001fa7bb12SVille Syrjälä if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) 1011fa7bb12SVille Syrjälä pipe_config->msa_timing_delay = i915->vbt.edp.drrs_msa_timing_delay; 1021fa7bb12SVille Syrjälä 103a1b63119SJosé Roberto de Souza pipe_config->has_drrs = true; 104a1b63119SJosé Roberto de Souza 10509270678SVille Syrjälä pixel_clock = downclock_mode->clock; 106a1b63119SJosé Roberto de Souza if (pipe_config->splitter.enable) 107a1b63119SJosé Roberto de Souza pixel_clock /= pipe_config->splitter.link_count; 108a1b63119SJosé Roberto de Souza 109a1b63119SJosé Roberto de Souza intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock, 110a1b63119SJosé Roberto de Souza pipe_config->port_clock, &pipe_config->dp_m2_n2, 111a1b63119SJosé Roberto de Souza constant_n, pipe_config->fec_enable); 112a1b63119SJosé Roberto de Souza 113a1b63119SJosé Roberto de Souza /* FIXME: abstract this better */ 114a1b63119SJosé Roberto de Souza if (pipe_config->splitter.enable) 1155f721a5dSVille Syrjälä pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; 116a1b63119SJosé Roberto de Souza } 117a1b63119SJosé Roberto de Souza 11814683babSVille Syrjälä static void 119851f15feSVille Syrjälä intel_drrs_set_refresh_rate_pipeconf(struct intel_crtc *crtc, 1205a220c53SVille Syrjälä enum drrs_refresh_rate refresh_rate) 12114683babSVille Syrjälä { 12214683babSVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 123851f15feSVille Syrjälä enum transcoder cpu_transcoder = crtc->drrs.cpu_transcoder; 12414683babSVille Syrjälä u32 val, bit; 12514683babSVille Syrjälä 12614683babSVille Syrjälä if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 127dd7ae6b3SVille Syrjälä bit = PIPECONF_REFRESH_RATE_ALT_VLV; 12814683babSVille Syrjälä else 129dd7ae6b3SVille Syrjälä bit = PIPECONF_REFRESH_RATE_ALT_ILK; 13014683babSVille Syrjälä 13114683babSVille Syrjälä val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 13214683babSVille Syrjälä 1335a220c53SVille Syrjälä if (refresh_rate == DRRS_REFRESH_RATE_LOW) 13414683babSVille Syrjälä val |= bit; 13514683babSVille Syrjälä else 13614683babSVille Syrjälä val &= ~bit; 13714683babSVille Syrjälä 13814683babSVille Syrjälä intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 13914683babSVille Syrjälä } 14014683babSVille Syrjälä 14114683babSVille Syrjälä static void 142851f15feSVille Syrjälä intel_drrs_set_refresh_rate_m_n(struct intel_crtc *crtc, 1435a220c53SVille Syrjälä enum drrs_refresh_rate refresh_rate) 14414683babSVille Syrjälä { 145851f15feSVille Syrjälä intel_cpu_transcoder_set_m1_n1(crtc, crtc->drrs.cpu_transcoder, 1465a220c53SVille Syrjälä refresh_rate == DRRS_REFRESH_RATE_LOW ? 147851f15feSVille Syrjälä &crtc->drrs.m2_n2 : &crtc->drrs.m_n); 14814683babSVille Syrjälä } 14914683babSVille Syrjälä 150851f15feSVille Syrjälä bool intel_drrs_is_enabled(struct intel_crtc *crtc) 151a1b63119SJosé Roberto de Souza { 152851f15feSVille Syrjälä return crtc->drrs.cpu_transcoder != INVALID_TRANSCODER; 153a1b63119SJosé Roberto de Souza } 154a1b63119SJosé Roberto de Souza 155851f15feSVille Syrjälä static void intel_drrs_set_state(struct intel_crtc *crtc, 156851f15feSVille Syrjälä enum drrs_refresh_rate refresh_rate) 157a1b63119SJosé Roberto de Souza { 158ba770ce3SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 159a1b63119SJosé Roberto de Souza 160851f15feSVille Syrjälä if (refresh_rate == crtc->drrs.refresh_rate) 161851f15feSVille Syrjälä return; 162851f15feSVille Syrjälä 163c2f12155SVille Syrjälä if (intel_cpu_transcoder_has_m2_n2(dev_priv, crtc->drrs.cpu_transcoder)) 164851f15feSVille Syrjälä intel_drrs_set_refresh_rate_pipeconf(crtc, refresh_rate); 165c2f12155SVille Syrjälä else 166c2f12155SVille Syrjälä intel_drrs_set_refresh_rate_m_n(crtc, refresh_rate); 167851f15feSVille Syrjälä 168851f15feSVille Syrjälä crtc->drrs.refresh_rate = refresh_rate; 169a1b63119SJosé Roberto de Souza } 170a1b63119SJosé Roberto de Souza 171a1b63119SJosé Roberto de Souza /** 1723a3dd534SJosé Roberto de Souza * intel_drrs_enable - init drrs struct if supported 173a1b63119SJosé Roberto de Souza * @crtc_state: A pointer to the active crtc state. 174a1b63119SJosé Roberto de Souza * 175a1b63119SJosé Roberto de Souza * Initializes frontbuffer_bits and drrs.dp 176a1b63119SJosé Roberto de Souza */ 177ba770ce3SVille Syrjälä void intel_drrs_enable(const struct intel_crtc_state *crtc_state) 178a1b63119SJosé Roberto de Souza { 179ba770ce3SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 180ba770ce3SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 181a1b63119SJosé Roberto de Souza 182a1b63119SJosé Roberto de Souza if (!crtc_state->has_drrs) 183a1b63119SJosé Roberto de Souza return; 184a1b63119SJosé Roberto de Souza 185851f15feSVille Syrjälä drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Enabling DRRS\n", 186851f15feSVille Syrjälä crtc->base.base.id, crtc->base.name); 187a1b63119SJosé Roberto de Souza 188851f15feSVille Syrjälä mutex_lock(&crtc->drrs.mutex); 189a1b63119SJosé Roberto de Souza 190851f15feSVille Syrjälä crtc->drrs.cpu_transcoder = crtc_state->cpu_transcoder; 191851f15feSVille Syrjälä crtc->drrs.m_n = crtc_state->dp_m_n; 192851f15feSVille Syrjälä crtc->drrs.m2_n2 = crtc_state->dp_m2_n2; 193851f15feSVille Syrjälä crtc->drrs.busy_frontbuffer_bits = 0; 194a1b63119SJosé Roberto de Souza 195851f15feSVille Syrjälä mutex_unlock(&crtc->drrs.mutex); 196a1b63119SJosé Roberto de Souza } 197a1b63119SJosé Roberto de Souza 198a1b63119SJosé Roberto de Souza /** 1993a3dd534SJosé Roberto de Souza * intel_drrs_disable - Disable DRRS 200a1b63119SJosé Roberto de Souza * @old_crtc_state: Pointer to old crtc_state. 201a1b63119SJosé Roberto de Souza */ 202ba770ce3SVille Syrjälä void intel_drrs_disable(const struct intel_crtc_state *old_crtc_state) 203a1b63119SJosé Roberto de Souza { 204ba770ce3SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 205ba770ce3SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 206a1b63119SJosé Roberto de Souza 207a1b63119SJosé Roberto de Souza if (!old_crtc_state->has_drrs) 208a1b63119SJosé Roberto de Souza return; 209a1b63119SJosé Roberto de Souza 210851f15feSVille Syrjälä drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] Disabling DRRS\n", 211851f15feSVille Syrjälä crtc->base.base.id, crtc->base.name); 212a1b63119SJosé Roberto de Souza 213851f15feSVille Syrjälä mutex_lock(&crtc->drrs.mutex); 214a1b63119SJosé Roberto de Souza 215851f15feSVille Syrjälä if (intel_drrs_is_enabled(crtc)) 216851f15feSVille Syrjälä intel_drrs_set_state(crtc, DRRS_REFRESH_RATE_HIGH); 217851f15feSVille Syrjälä 218851f15feSVille Syrjälä crtc->drrs.cpu_transcoder = INVALID_TRANSCODER; 219851f15feSVille Syrjälä crtc->drrs.busy_frontbuffer_bits = 0; 220851f15feSVille Syrjälä 221851f15feSVille Syrjälä mutex_unlock(&crtc->drrs.mutex); 222851f15feSVille Syrjälä 223851f15feSVille Syrjälä cancel_delayed_work_sync(&crtc->drrs.work); 224a1b63119SJosé Roberto de Souza } 225a1b63119SJosé Roberto de Souza 226a1b63119SJosé Roberto de Souza /** 227851f15feSVille Syrjälä * intel_drrs_update - Update DRRS during fastset 228851f15feSVille Syrjälä * @state: atomic state 229851f15feSVille Syrjälä * @crtc: crtc 230a1b63119SJosé Roberto de Souza */ 231851f15feSVille Syrjälä void intel_drrs_update(struct intel_atomic_state *state, 232851f15feSVille Syrjälä struct intel_crtc *crtc) 233a1b63119SJosé Roberto de Souza { 234851f15feSVille Syrjälä const struct intel_crtc_state *old_crtc_state = 235851f15feSVille Syrjälä intel_atomic_get_old_crtc_state(state, crtc); 236851f15feSVille Syrjälä const struct intel_crtc_state *new_crtc_state = 237851f15feSVille Syrjälä intel_atomic_get_new_crtc_state(state, crtc); 238a1b63119SJosé Roberto de Souza 239851f15feSVille Syrjälä if (old_crtc_state->has_drrs == new_crtc_state->has_drrs) 240a1b63119SJosé Roberto de Souza return; 241a1b63119SJosé Roberto de Souza 242851f15feSVille Syrjälä if (new_crtc_state->has_drrs) 243851f15feSVille Syrjälä intel_drrs_enable(new_crtc_state); 244a1b63119SJosé Roberto de Souza else 245851f15feSVille Syrjälä intel_drrs_disable(old_crtc_state); 246a1b63119SJosé Roberto de Souza } 247a1b63119SJosé Roberto de Souza 2483a3dd534SJosé Roberto de Souza static void intel_drrs_downclock_work(struct work_struct *work) 249a1b63119SJosé Roberto de Souza { 250851f15feSVille Syrjälä struct intel_crtc *crtc = container_of(work, typeof(*crtc), drrs.work.work); 251a1b63119SJosé Roberto de Souza 252851f15feSVille Syrjälä mutex_lock(&crtc->drrs.mutex); 253a1b63119SJosé Roberto de Souza 254851f15feSVille Syrjälä if (intel_drrs_is_enabled(crtc) && !crtc->drrs.busy_frontbuffer_bits) 255851f15feSVille Syrjälä intel_drrs_set_state(crtc, DRRS_REFRESH_RATE_LOW); 256a1b63119SJosé Roberto de Souza 257851f15feSVille Syrjälä mutex_unlock(&crtc->drrs.mutex); 258a1b63119SJosé Roberto de Souza } 259a1b63119SJosé Roberto de Souza 2606bd58b70SJosé Roberto de Souza static void intel_drrs_frontbuffer_update(struct drm_i915_private *dev_priv, 2616bd58b70SJosé Roberto de Souza unsigned int frontbuffer_bits, 2626bd58b70SJosé Roberto de Souza bool invalidate) 263a1b63119SJosé Roberto de Souza { 264ba770ce3SVille Syrjälä struct intel_crtc *crtc; 265a1b63119SJosé Roberto de Souza 266c25300f0SVille Syrjälä if (dev_priv->vbt.drrs_type != DRRS_TYPE_SEAMLESS) 267a1b63119SJosé Roberto de Souza return; 268a1b63119SJosé Roberto de Souza 269851f15feSVille Syrjälä for_each_intel_crtc(&dev_priv->drm, crtc) { 270851f15feSVille Syrjälä cancel_delayed_work(&crtc->drrs.work); 271a1b63119SJosé Roberto de Souza 272851f15feSVille Syrjälä mutex_lock(&crtc->drrs.mutex); 273a1b63119SJosé Roberto de Souza 274851f15feSVille Syrjälä if (!intel_drrs_is_enabled(crtc)) { 275851f15feSVille Syrjälä mutex_unlock(&crtc->drrs.mutex); 276851f15feSVille Syrjälä continue; 277a1b63119SJosé Roberto de Souza } 278a1b63119SJosé Roberto de Souza 279ba770ce3SVille Syrjälä frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe); 2806bd58b70SJosé Roberto de Souza if (invalidate) 281851f15feSVille Syrjälä crtc->drrs.busy_frontbuffer_bits |= frontbuffer_bits; 2826bd58b70SJosé Roberto de Souza else 283851f15feSVille Syrjälä crtc->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; 284a1b63119SJosé Roberto de Souza 2856bd58b70SJosé Roberto de Souza /* flush/invalidate means busy screen hence upclock */ 286c7c4dfb6SJosé Roberto de Souza if (frontbuffer_bits) 287851f15feSVille Syrjälä intel_drrs_set_state(crtc, DRRS_REFRESH_RATE_HIGH); 288a1b63119SJosé Roberto de Souza 2896bd58b70SJosé Roberto de Souza /* 2906bd58b70SJosé Roberto de Souza * flush also means no more activity hence schedule downclock, if all 2916bd58b70SJosé Roberto de Souza * other fbs are quiescent too 2926bd58b70SJosé Roberto de Souza */ 293851f15feSVille Syrjälä if (!invalidate && !crtc->drrs.busy_frontbuffer_bits) 294851f15feSVille Syrjälä schedule_delayed_work(&crtc->drrs.work, 2956bd58b70SJosé Roberto de Souza msecs_to_jiffies(1000)); 296851f15feSVille Syrjälä 297851f15feSVille Syrjälä mutex_unlock(&crtc->drrs.mutex); 298851f15feSVille Syrjälä } 299a1b63119SJosé Roberto de Souza } 300a1b63119SJosé Roberto de Souza 301a1b63119SJosé Roberto de Souza /** 3026bd58b70SJosé Roberto de Souza * intel_drrs_invalidate - Disable Idleness DRRS 3036bd58b70SJosé Roberto de Souza * @dev_priv: i915 device 3046bd58b70SJosé Roberto de Souza * @frontbuffer_bits: frontbuffer plane tracking bits 3056bd58b70SJosé Roberto de Souza * 3066bd58b70SJosé Roberto de Souza * This function gets called everytime rendering on the given planes start. 3076bd58b70SJosé Roberto de Souza * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). 3086bd58b70SJosé Roberto de Souza * 3096bd58b70SJosé Roberto de Souza * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 3106bd58b70SJosé Roberto de Souza */ 3116bd58b70SJosé Roberto de Souza void intel_drrs_invalidate(struct drm_i915_private *dev_priv, 3126bd58b70SJosé Roberto de Souza unsigned int frontbuffer_bits) 3136bd58b70SJosé Roberto de Souza { 3146bd58b70SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, true); 3156bd58b70SJosé Roberto de Souza } 3166bd58b70SJosé Roberto de Souza 3176bd58b70SJosé Roberto de Souza /** 3183a3dd534SJosé Roberto de Souza * intel_drrs_flush - Restart Idleness DRRS 319a1b63119SJosé Roberto de Souza * @dev_priv: i915 device 320a1b63119SJosé Roberto de Souza * @frontbuffer_bits: frontbuffer plane tracking bits 321a1b63119SJosé Roberto de Souza * 322a1b63119SJosé Roberto de Souza * This function gets called every time rendering on the given planes has 323a1b63119SJosé Roberto de Souza * completed or flip on a crtc is completed. So DRRS should be upclocked 324a1b63119SJosé Roberto de Souza * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, 325a1b63119SJosé Roberto de Souza * if no other planes are dirty. 326a1b63119SJosé Roberto de Souza * 327a1b63119SJosé Roberto de Souza * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 328a1b63119SJosé Roberto de Souza */ 3293a3dd534SJosé Roberto de Souza void intel_drrs_flush(struct drm_i915_private *dev_priv, 330a1b63119SJosé Roberto de Souza unsigned int frontbuffer_bits) 331a1b63119SJosé Roberto de Souza { 3326bd58b70SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false); 333a1b63119SJosé Roberto de Souza } 334a1b63119SJosé Roberto de Souza 335851f15feSVille Syrjälä void intel_drrs_page_flip(struct intel_crtc *crtc) 3360f3692b5SJosé Roberto de Souza { 337851f15feSVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 3380f3692b5SJosé Roberto de Souza unsigned int frontbuffer_bits = INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe); 3390f3692b5SJosé Roberto de Souza 3400f3692b5SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false); 3410f3692b5SJosé Roberto de Souza } 3420f3692b5SJosé Roberto de Souza 343a1b63119SJosé Roberto de Souza /** 344851f15feSVille Syrjälä * intel_crtc_drrs_init - Init DRRS for CRTC 345851f15feSVille Syrjälä * @crtc: crtc 346a1b63119SJosé Roberto de Souza * 347a1b63119SJosé Roberto de Souza * This function is called only once at driver load to initialize basic 348a1b63119SJosé Roberto de Souza * DRRS stuff. 349a1b63119SJosé Roberto de Souza * 350851f15feSVille Syrjälä */ 351851f15feSVille Syrjälä void intel_crtc_drrs_init(struct intel_crtc *crtc) 352851f15feSVille Syrjälä { 353851f15feSVille Syrjälä INIT_DELAYED_WORK(&crtc->drrs.work, intel_drrs_downclock_work); 354851f15feSVille Syrjälä mutex_init(&crtc->drrs.mutex); 355851f15feSVille Syrjälä crtc->drrs.cpu_transcoder = INVALID_TRANSCODER; 356851f15feSVille Syrjälä } 357851f15feSVille Syrjälä 358851f15feSVille Syrjälä /** 359851f15feSVille Syrjälä * intel_drrs_init - Init DRRS for eDP connector 360851f15feSVille Syrjälä * @connector: eDP connector 361851f15feSVille Syrjälä * @fixed_mode: preferred mode of panel 362851f15feSVille Syrjälä * 363851f15feSVille Syrjälä * This function is called only once at driver load to initialize 364851f15feSVille Syrjälä * DRRS support for the connector. 365851f15feSVille Syrjälä * 366a1b63119SJosé Roberto de Souza * Returns: 367a1b63119SJosé Roberto de Souza * Downclock mode if panel supports it, else return NULL. 368a1b63119SJosé Roberto de Souza * DRRS support is determined by the presence of downclock mode (apart 369a1b63119SJosé Roberto de Souza * from VBT setting). 370a1b63119SJosé Roberto de Souza */ 371a1b63119SJosé Roberto de Souza struct drm_display_mode * 3723a3dd534SJosé Roberto de Souza intel_drrs_init(struct intel_connector *connector, 373faf6e8fcSVille Syrjälä const struct drm_display_mode *fixed_mode) 374a1b63119SJosé Roberto de Souza { 375a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 376f0d4ce59SVille Syrjälä struct intel_encoder *encoder = connector->encoder; 377851f15feSVille Syrjälä struct drm_display_mode *downclock_mode; 378a1b63119SJosé Roberto de Souza 379c2f12155SVille Syrjälä if (DISPLAY_VER(dev_priv) < 5) { 380a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 3815f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported on platform\n", 3825f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 383a1b63119SJosé Roberto de Souza return NULL; 384a1b63119SJosé Roberto de Souza } 385a1b63119SJosé Roberto de Souza 386f0d4ce59SVille Syrjälä if ((DISPLAY_VER(dev_priv) < 8 && !HAS_GMCH(dev_priv)) && 387f0d4ce59SVille Syrjälä encoder->port != PORT_A) { 388f0d4ce59SVille Syrjälä drm_dbg_kms(&dev_priv->drm, 3895f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported on [ENCODER:%d:%s]\n", 3905f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name, 3915f6a9beaSVille Syrjälä encoder->base.base.id, encoder->base.name); 392f0d4ce59SVille Syrjälä return NULL; 393f0d4ce59SVille Syrjälä } 394f0d4ce59SVille Syrjälä 395c5ee2343SVille Syrjälä if (dev_priv->vbt.drrs_type == DRRS_TYPE_NONE) { 3965f6a9beaSVille Syrjälä drm_dbg_kms(&dev_priv->drm, 3975f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported according to VBT\n", 3985f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 399a1b63119SJosé Roberto de Souza return NULL; 400a1b63119SJosé Roberto de Souza } 401a1b63119SJosé Roberto de Souza 402a1b63119SJosé Roberto de Souza downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode); 403a1b63119SJosé Roberto de Souza if (!downclock_mode) { 404a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 4055f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported due to lack of downclock mode\n", 4065f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 407a1b63119SJosé Roberto de Souza return NULL; 408a1b63119SJosé Roberto de Souza } 409a1b63119SJosé Roberto de Souza 410a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 411a1b952d4SVille Syrjälä "[CONNECTOR:%d:%s] %s DRRS supported\n", 412a1b952d4SVille Syrjälä connector->base.base.id, connector->base.name, 413a1b952d4SVille Syrjälä intel_drrs_type_str(dev_priv->vbt.drrs_type)); 4145f6a9beaSVille Syrjälä 415a1b63119SJosé Roberto de Souza return downclock_mode; 416a1b63119SJosé Roberto de Souza } 417