1a1b63119SJosé Roberto de Souza // SPDX-License-Identifier: MIT 2a1b63119SJosé Roberto de Souza /* 3a1b63119SJosé Roberto de Souza * Copyright © 2021 Intel Corporation 4a1b63119SJosé Roberto de Souza */ 5a1b63119SJosé Roberto de Souza 6a1b63119SJosé Roberto de Souza #include "i915_drv.h" 7a1b63119SJosé Roberto de Souza #include "intel_atomic.h" 8a1b63119SJosé Roberto de Souza #include "intel_de.h" 9a1b63119SJosé Roberto de Souza #include "intel_display_types.h" 10a1b63119SJosé Roberto de Souza #include "intel_drrs.h" 11a1b63119SJosé Roberto de Souza #include "intel_panel.h" 12a1b63119SJosé Roberto de Souza 13a1b63119SJosé Roberto de Souza /** 14a1b63119SJosé Roberto de Souza * DOC: Display Refresh Rate Switching (DRRS) 15a1b63119SJosé Roberto de Souza * 16a1b63119SJosé Roberto de Souza * Display Refresh Rate Switching (DRRS) is a power conservation feature 17a1b63119SJosé Roberto de Souza * which enables swtching between low and high refresh rates, 18a1b63119SJosé Roberto de Souza * dynamically, based on the usage scenario. This feature is applicable 19a1b63119SJosé Roberto de Souza * for internal panels. 20a1b63119SJosé Roberto de Souza * 21a1b63119SJosé Roberto de Souza * Indication that the panel supports DRRS is given by the panel EDID, which 22a1b63119SJosé Roberto de Souza * would list multiple refresh rates for one resolution. 23a1b63119SJosé Roberto de Souza * 24a1b63119SJosé Roberto de Souza * DRRS is of 2 types - static and seamless. 25a1b63119SJosé Roberto de Souza * Static DRRS involves changing refresh rate (RR) by doing a full modeset 26a1b63119SJosé Roberto de Souza * (may appear as a blink on screen) and is used in dock-undock scenario. 27a1b63119SJosé Roberto de Souza * Seamless DRRS involves changing RR without any visual effect to the user 28a1b63119SJosé Roberto de Souza * and can be used during normal system usage. This is done by programming 29a1b63119SJosé Roberto de Souza * certain registers. 30a1b63119SJosé Roberto de Souza * 31a1b63119SJosé Roberto de Souza * Support for static/seamless DRRS may be indicated in the VBT based on 32a1b63119SJosé Roberto de Souza * inputs from the panel spec. 33a1b63119SJosé Roberto de Souza * 34a1b63119SJosé Roberto de Souza * DRRS saves power by switching to low RR based on usage scenarios. 35a1b63119SJosé Roberto de Souza * 36a1b63119SJosé Roberto de Souza * The implementation is based on frontbuffer tracking implementation. When 37a1b63119SJosé Roberto de Souza * there is a disturbance on the screen triggered by user activity or a periodic 38a1b63119SJosé Roberto de Souza * system activity, DRRS is disabled (RR is changed to high RR). When there is 39a1b63119SJosé Roberto de Souza * no movement on screen, after a timeout of 1 second, a switch to low RR is 40a1b63119SJosé Roberto de Souza * made. 41a1b63119SJosé Roberto de Souza * 423a3dd534SJosé Roberto de Souza * For integration with frontbuffer tracking code, intel_drrs_invalidate() 433a3dd534SJosé Roberto de Souza * and intel_drrs_flush() are called. 44a1b63119SJosé Roberto de Souza * 45a1b63119SJosé Roberto de Souza * DRRS can be further extended to support other internal panels and also 46a1b63119SJosé Roberto de Souza * the scenario of video playback wherein RR is set based on the rate 47a1b63119SJosé Roberto de Souza * requested by userspace. 48a1b63119SJosé Roberto de Souza */ 49a1b63119SJosé Roberto de Souza 50a1b952d4SVille Syrjälä const char *intel_drrs_type_str(enum drrs_type drrs_type) 51a1b952d4SVille Syrjälä { 52a1b952d4SVille Syrjälä static const char * const str[] = { 53a1b952d4SVille Syrjälä [DRRS_TYPE_NONE] = "none", 54a1b952d4SVille Syrjälä [DRRS_TYPE_STATIC] = "static", 55a1b952d4SVille Syrjälä [DRRS_TYPE_SEAMLESS] = "seamless", 56a1b952d4SVille Syrjälä }; 57a1b952d4SVille Syrjälä 58a1b952d4SVille Syrjälä if (drrs_type >= ARRAY_SIZE(str)) 59a1b952d4SVille Syrjälä return "<invalid>"; 60a1b952d4SVille Syrjälä 61a1b952d4SVille Syrjälä return str[drrs_type]; 62a1b952d4SVille Syrjälä } 63a1b952d4SVille Syrjälä 64c3e27f43SVille Syrjälä static bool can_enable_drrs(struct intel_connector *connector, 652260e4d8SVille Syrjälä const struct intel_crtc_state *pipe_config, 662260e4d8SVille Syrjälä const struct drm_display_mode *downclock_mode) 67a1b63119SJosé Roberto de Souza { 68a1b63119SJosé Roberto de Souza if (pipe_config->vrr.enable) 69c3e27f43SVille Syrjälä return false; 70a1b63119SJosé Roberto de Souza 71a1b63119SJosé Roberto de Souza /* 72a1b63119SJosé Roberto de Souza * DRRS and PSR can't be enable together, so giving preference to PSR 73a1b63119SJosé Roberto de Souza * as it allows more power-savings by complete shutting down display, 743a3dd534SJosé Roberto de Souza * so to guarantee this, intel_drrs_compute_config() must be called 75a1b63119SJosé Roberto de Souza * after intel_psr_compute_config(). 76a1b63119SJosé Roberto de Souza */ 77a1b63119SJosé Roberto de Souza if (pipe_config->has_psr) 78c3e27f43SVille Syrjälä return false; 79a1b63119SJosé Roberto de Souza 802260e4d8SVille Syrjälä return downclock_mode && 812260e4d8SVille Syrjälä intel_panel_drrs_type(connector) == DRRS_TYPE_SEAMLESS; 82c3e27f43SVille Syrjälä } 83c3e27f43SVille Syrjälä 84c3e27f43SVille Syrjälä void 85ba770ce3SVille Syrjälä intel_drrs_compute_config(struct intel_connector *connector, 86c3e27f43SVille Syrjälä struct intel_crtc_state *pipe_config, 87c3e27f43SVille Syrjälä int output_bpp, bool constant_n) 88c3e27f43SVille Syrjälä { 891d06c820SVille Syrjälä struct drm_i915_private *i915 = to_i915(connector->base.dev); 9009270678SVille Syrjälä const struct drm_display_mode *downclock_mode = 9109270678SVille Syrjälä intel_panel_downclock_mode(connector, &pipe_config->hw.adjusted_mode); 92c3e27f43SVille Syrjälä int pixel_clock; 93c3e27f43SVille Syrjälä 942260e4d8SVille Syrjälä if (!can_enable_drrs(connector, pipe_config, downclock_mode)) { 951d06c820SVille Syrjälä if (intel_cpu_transcoder_has_m2_n2(i915, pipe_config->cpu_transcoder)) 961d06c820SVille Syrjälä intel_zero_m_n(&pipe_config->dp_m2_n2); 97a1b63119SJosé Roberto de Souza return; 981d06c820SVille Syrjälä } 99a1b63119SJosé Roberto de Souza 1001fa7bb12SVille Syrjälä if (IS_IRONLAKE(i915) || IS_SANDYBRIDGE(i915) || IS_IVYBRIDGE(i915)) 1011fa7bb12SVille Syrjälä pipe_config->msa_timing_delay = i915->vbt.edp.drrs_msa_timing_delay; 1021fa7bb12SVille Syrjälä 103a1b63119SJosé Roberto de Souza pipe_config->has_drrs = true; 104a1b63119SJosé Roberto de Souza 10509270678SVille Syrjälä pixel_clock = downclock_mode->clock; 106a1b63119SJosé Roberto de Souza if (pipe_config->splitter.enable) 107a1b63119SJosé Roberto de Souza pixel_clock /= pipe_config->splitter.link_count; 108a1b63119SJosé Roberto de Souza 109a1b63119SJosé Roberto de Souza intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock, 110a1b63119SJosé Roberto de Souza pipe_config->port_clock, &pipe_config->dp_m2_n2, 111a1b63119SJosé Roberto de Souza constant_n, pipe_config->fec_enable); 112a1b63119SJosé Roberto de Souza 113a1b63119SJosé Roberto de Souza /* FIXME: abstract this better */ 114a1b63119SJosé Roberto de Souza if (pipe_config->splitter.enable) 1155f721a5dSVille Syrjälä pipe_config->dp_m2_n2.data_m *= pipe_config->splitter.link_count; 116a1b63119SJosé Roberto de Souza } 117a1b63119SJosé Roberto de Souza 11814683babSVille Syrjälä static void 119851f15feSVille Syrjälä intel_drrs_set_refresh_rate_pipeconf(struct intel_crtc *crtc, 1205a220c53SVille Syrjälä enum drrs_refresh_rate refresh_rate) 12114683babSVille Syrjälä { 12214683babSVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 123851f15feSVille Syrjälä enum transcoder cpu_transcoder = crtc->drrs.cpu_transcoder; 12414683babSVille Syrjälä u32 val, bit; 12514683babSVille Syrjälä 12614683babSVille Syrjälä if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 127dd7ae6b3SVille Syrjälä bit = PIPECONF_REFRESH_RATE_ALT_VLV; 12814683babSVille Syrjälä else 129dd7ae6b3SVille Syrjälä bit = PIPECONF_REFRESH_RATE_ALT_ILK; 13014683babSVille Syrjälä 13114683babSVille Syrjälä val = intel_de_read(dev_priv, PIPECONF(cpu_transcoder)); 13214683babSVille Syrjälä 1335a220c53SVille Syrjälä if (refresh_rate == DRRS_REFRESH_RATE_LOW) 13414683babSVille Syrjälä val |= bit; 13514683babSVille Syrjälä else 13614683babSVille Syrjälä val &= ~bit; 13714683babSVille Syrjälä 13814683babSVille Syrjälä intel_de_write(dev_priv, PIPECONF(cpu_transcoder), val); 13914683babSVille Syrjälä } 14014683babSVille Syrjälä 14114683babSVille Syrjälä static void 142851f15feSVille Syrjälä intel_drrs_set_refresh_rate_m_n(struct intel_crtc *crtc, 1435a220c53SVille Syrjälä enum drrs_refresh_rate refresh_rate) 14414683babSVille Syrjälä { 145851f15feSVille Syrjälä intel_cpu_transcoder_set_m1_n1(crtc, crtc->drrs.cpu_transcoder, 1465a220c53SVille Syrjälä refresh_rate == DRRS_REFRESH_RATE_LOW ? 147851f15feSVille Syrjälä &crtc->drrs.m2_n2 : &crtc->drrs.m_n); 14814683babSVille Syrjälä } 14914683babSVille Syrjälä 150851f15feSVille Syrjälä bool intel_drrs_is_enabled(struct intel_crtc *crtc) 151a1b63119SJosé Roberto de Souza { 152851f15feSVille Syrjälä return crtc->drrs.cpu_transcoder != INVALID_TRANSCODER; 153a1b63119SJosé Roberto de Souza } 154a1b63119SJosé Roberto de Souza 155851f15feSVille Syrjälä static void intel_drrs_set_state(struct intel_crtc *crtc, 156851f15feSVille Syrjälä enum drrs_refresh_rate refresh_rate) 157a1b63119SJosé Roberto de Souza { 158ba770ce3SVille Syrjälä struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 159a1b63119SJosé Roberto de Souza 160851f15feSVille Syrjälä if (refresh_rate == crtc->drrs.refresh_rate) 161851f15feSVille Syrjälä return; 162851f15feSVille Syrjälä 163c2f12155SVille Syrjälä if (intel_cpu_transcoder_has_m2_n2(dev_priv, crtc->drrs.cpu_transcoder)) 164851f15feSVille Syrjälä intel_drrs_set_refresh_rate_pipeconf(crtc, refresh_rate); 165c2f12155SVille Syrjälä else 166c2f12155SVille Syrjälä intel_drrs_set_refresh_rate_m_n(crtc, refresh_rate); 167851f15feSVille Syrjälä 168851f15feSVille Syrjälä crtc->drrs.refresh_rate = refresh_rate; 169a1b63119SJosé Roberto de Souza } 170a1b63119SJosé Roberto de Souza 1711c004047SVille Syrjälä static void intel_drrs_schedule_work(struct intel_crtc *crtc) 1721c004047SVille Syrjälä { 1731c004047SVille Syrjälä mod_delayed_work(system_wq, &crtc->drrs.work, msecs_to_jiffies(1000)); 1741c004047SVille Syrjälä } 1751c004047SVille Syrjälä 17670e10a2bSVille Syrjälä static unsigned int intel_drrs_frontbuffer_bits(const struct intel_crtc_state *crtc_state) 17770e10a2bSVille Syrjälä { 17870e10a2bSVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 17970e10a2bSVille Syrjälä 18070e10a2bSVille Syrjälä return INTEL_FRONTBUFFER_ALL_MASK(crtc->pipe); 18170e10a2bSVille Syrjälä } 18270e10a2bSVille Syrjälä 183a1b63119SJosé Roberto de Souza /** 1843a3dd534SJosé Roberto de Souza * intel_drrs_enable - init drrs struct if supported 185a1b63119SJosé Roberto de Souza * @crtc_state: A pointer to the active crtc state. 186a1b63119SJosé Roberto de Souza * 187a1b63119SJosé Roberto de Souza * Initializes frontbuffer_bits and drrs.dp 188a1b63119SJosé Roberto de Souza */ 189ba770ce3SVille Syrjälä void intel_drrs_enable(const struct intel_crtc_state *crtc_state) 190a1b63119SJosé Roberto de Souza { 191ba770ce3SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 192a1b63119SJosé Roberto de Souza 193a1b63119SJosé Roberto de Souza if (!crtc_state->has_drrs) 194a1b63119SJosé Roberto de Souza return; 195a1b63119SJosé Roberto de Souza 196*1b333c67SVille Syrjälä if (!crtc_state->hw.active) 197*1b333c67SVille Syrjälä return; 198a1b63119SJosé Roberto de Souza 199851f15feSVille Syrjälä mutex_lock(&crtc->drrs.mutex); 200a1b63119SJosé Roberto de Souza 201851f15feSVille Syrjälä crtc->drrs.cpu_transcoder = crtc_state->cpu_transcoder; 202851f15feSVille Syrjälä crtc->drrs.m_n = crtc_state->dp_m_n; 203851f15feSVille Syrjälä crtc->drrs.m2_n2 = crtc_state->dp_m2_n2; 20470e10a2bSVille Syrjälä crtc->drrs.frontbuffer_bits = intel_drrs_frontbuffer_bits(crtc_state); 205851f15feSVille Syrjälä crtc->drrs.busy_frontbuffer_bits = 0; 206a1b63119SJosé Roberto de Souza 2071c004047SVille Syrjälä intel_drrs_schedule_work(crtc); 2081c004047SVille Syrjälä 209851f15feSVille Syrjälä mutex_unlock(&crtc->drrs.mutex); 210a1b63119SJosé Roberto de Souza } 211a1b63119SJosé Roberto de Souza 212a1b63119SJosé Roberto de Souza /** 2133a3dd534SJosé Roberto de Souza * intel_drrs_disable - Disable DRRS 214a1b63119SJosé Roberto de Souza * @old_crtc_state: Pointer to old crtc_state. 215a1b63119SJosé Roberto de Souza */ 216ba770ce3SVille Syrjälä void intel_drrs_disable(const struct intel_crtc_state *old_crtc_state) 217a1b63119SJosé Roberto de Souza { 218ba770ce3SVille Syrjälä struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 219a1b63119SJosé Roberto de Souza 220a1b63119SJosé Roberto de Souza if (!old_crtc_state->has_drrs) 221a1b63119SJosé Roberto de Souza return; 222a1b63119SJosé Roberto de Souza 223*1b333c67SVille Syrjälä if (!old_crtc_state->hw.active) 224*1b333c67SVille Syrjälä return; 225a1b63119SJosé Roberto de Souza 226851f15feSVille Syrjälä mutex_lock(&crtc->drrs.mutex); 227a1b63119SJosé Roberto de Souza 228851f15feSVille Syrjälä if (intel_drrs_is_enabled(crtc)) 229851f15feSVille Syrjälä intel_drrs_set_state(crtc, DRRS_REFRESH_RATE_HIGH); 230851f15feSVille Syrjälä 231851f15feSVille Syrjälä crtc->drrs.cpu_transcoder = INVALID_TRANSCODER; 23270e10a2bSVille Syrjälä crtc->drrs.frontbuffer_bits = 0; 233851f15feSVille Syrjälä crtc->drrs.busy_frontbuffer_bits = 0; 234851f15feSVille Syrjälä 235851f15feSVille Syrjälä mutex_unlock(&crtc->drrs.mutex); 236851f15feSVille Syrjälä 237851f15feSVille Syrjälä cancel_delayed_work_sync(&crtc->drrs.work); 238a1b63119SJosé Roberto de Souza } 239a1b63119SJosé Roberto de Souza 2403a3dd534SJosé Roberto de Souza static void intel_drrs_downclock_work(struct work_struct *work) 241a1b63119SJosé Roberto de Souza { 242851f15feSVille Syrjälä struct intel_crtc *crtc = container_of(work, typeof(*crtc), drrs.work.work); 243a1b63119SJosé Roberto de Souza 244851f15feSVille Syrjälä mutex_lock(&crtc->drrs.mutex); 245a1b63119SJosé Roberto de Souza 246851f15feSVille Syrjälä if (intel_drrs_is_enabled(crtc) && !crtc->drrs.busy_frontbuffer_bits) 247851f15feSVille Syrjälä intel_drrs_set_state(crtc, DRRS_REFRESH_RATE_LOW); 248a1b63119SJosé Roberto de Souza 249851f15feSVille Syrjälä mutex_unlock(&crtc->drrs.mutex); 250a1b63119SJosé Roberto de Souza } 251a1b63119SJosé Roberto de Souza 2526bd58b70SJosé Roberto de Souza static void intel_drrs_frontbuffer_update(struct drm_i915_private *dev_priv, 25318f23b92SVille Syrjälä unsigned int all_frontbuffer_bits, 2546bd58b70SJosé Roberto de Souza bool invalidate) 255a1b63119SJosé Roberto de Souza { 256ba770ce3SVille Syrjälä struct intel_crtc *crtc; 257a1b63119SJosé Roberto de Souza 258c25300f0SVille Syrjälä if (dev_priv->vbt.drrs_type != DRRS_TYPE_SEAMLESS) 259a1b63119SJosé Roberto de Souza return; 260a1b63119SJosé Roberto de Souza 261851f15feSVille Syrjälä for_each_intel_crtc(&dev_priv->drm, crtc) { 26218f23b92SVille Syrjälä unsigned int frontbuffer_bits; 26318f23b92SVille Syrjälä 264851f15feSVille Syrjälä mutex_lock(&crtc->drrs.mutex); 265a1b63119SJosé Roberto de Souza 266fb4ae6e6SVille Syrjälä frontbuffer_bits = all_frontbuffer_bits & crtc->drrs.frontbuffer_bits; 267fb4ae6e6SVille Syrjälä if (!frontbuffer_bits) { 268851f15feSVille Syrjälä mutex_unlock(&crtc->drrs.mutex); 269851f15feSVille Syrjälä continue; 270a1b63119SJosé Roberto de Souza } 271a1b63119SJosé Roberto de Souza 2726bd58b70SJosé Roberto de Souza if (invalidate) 273851f15feSVille Syrjälä crtc->drrs.busy_frontbuffer_bits |= frontbuffer_bits; 2746bd58b70SJosé Roberto de Souza else 275851f15feSVille Syrjälä crtc->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; 276a1b63119SJosé Roberto de Souza 2776bd58b70SJosé Roberto de Souza /* flush/invalidate means busy screen hence upclock */ 278851f15feSVille Syrjälä intel_drrs_set_state(crtc, DRRS_REFRESH_RATE_HIGH); 279a1b63119SJosé Roberto de Souza 2806bd58b70SJosé Roberto de Souza /* 2816bd58b70SJosé Roberto de Souza * flush also means no more activity hence schedule downclock, if all 2826bd58b70SJosé Roberto de Souza * other fbs are quiescent too 2836bd58b70SJosé Roberto de Souza */ 284fb4ae6e6SVille Syrjälä if (!crtc->drrs.busy_frontbuffer_bits) 2851c004047SVille Syrjälä intel_drrs_schedule_work(crtc); 286fb4ae6e6SVille Syrjälä else 287fb4ae6e6SVille Syrjälä cancel_delayed_work(&crtc->drrs.work); 288851f15feSVille Syrjälä 289851f15feSVille Syrjälä mutex_unlock(&crtc->drrs.mutex); 290851f15feSVille Syrjälä } 291a1b63119SJosé Roberto de Souza } 292a1b63119SJosé Roberto de Souza 293a1b63119SJosé Roberto de Souza /** 2946bd58b70SJosé Roberto de Souza * intel_drrs_invalidate - Disable Idleness DRRS 2956bd58b70SJosé Roberto de Souza * @dev_priv: i915 device 2966bd58b70SJosé Roberto de Souza * @frontbuffer_bits: frontbuffer plane tracking bits 2976bd58b70SJosé Roberto de Souza * 2986bd58b70SJosé Roberto de Souza * This function gets called everytime rendering on the given planes start. 2996bd58b70SJosé Roberto de Souza * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). 3006bd58b70SJosé Roberto de Souza * 3016bd58b70SJosé Roberto de Souza * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 3026bd58b70SJosé Roberto de Souza */ 3036bd58b70SJosé Roberto de Souza void intel_drrs_invalidate(struct drm_i915_private *dev_priv, 3046bd58b70SJosé Roberto de Souza unsigned int frontbuffer_bits) 3056bd58b70SJosé Roberto de Souza { 3066bd58b70SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, true); 3076bd58b70SJosé Roberto de Souza } 3086bd58b70SJosé Roberto de Souza 3096bd58b70SJosé Roberto de Souza /** 3103a3dd534SJosé Roberto de Souza * intel_drrs_flush - Restart Idleness DRRS 311a1b63119SJosé Roberto de Souza * @dev_priv: i915 device 312a1b63119SJosé Roberto de Souza * @frontbuffer_bits: frontbuffer plane tracking bits 313a1b63119SJosé Roberto de Souza * 314a1b63119SJosé Roberto de Souza * This function gets called every time rendering on the given planes has 315a1b63119SJosé Roberto de Souza * completed or flip on a crtc is completed. So DRRS should be upclocked 316a1b63119SJosé Roberto de Souza * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, 317a1b63119SJosé Roberto de Souza * if no other planes are dirty. 318a1b63119SJosé Roberto de Souza * 319a1b63119SJosé Roberto de Souza * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 320a1b63119SJosé Roberto de Souza */ 3213a3dd534SJosé Roberto de Souza void intel_drrs_flush(struct drm_i915_private *dev_priv, 322a1b63119SJosé Roberto de Souza unsigned int frontbuffer_bits) 323a1b63119SJosé Roberto de Souza { 3246bd58b70SJosé Roberto de Souza intel_drrs_frontbuffer_update(dev_priv, frontbuffer_bits, false); 325a1b63119SJosé Roberto de Souza } 326a1b63119SJosé Roberto de Souza 327a1b63119SJosé Roberto de Souza /** 328851f15feSVille Syrjälä * intel_crtc_drrs_init - Init DRRS for CRTC 329851f15feSVille Syrjälä * @crtc: crtc 330a1b63119SJosé Roberto de Souza * 331a1b63119SJosé Roberto de Souza * This function is called only once at driver load to initialize basic 332a1b63119SJosé Roberto de Souza * DRRS stuff. 333a1b63119SJosé Roberto de Souza * 334851f15feSVille Syrjälä */ 335851f15feSVille Syrjälä void intel_crtc_drrs_init(struct intel_crtc *crtc) 336851f15feSVille Syrjälä { 337851f15feSVille Syrjälä INIT_DELAYED_WORK(&crtc->drrs.work, intel_drrs_downclock_work); 338851f15feSVille Syrjälä mutex_init(&crtc->drrs.mutex); 339851f15feSVille Syrjälä crtc->drrs.cpu_transcoder = INVALID_TRANSCODER; 340851f15feSVille Syrjälä } 341851f15feSVille Syrjälä 342851f15feSVille Syrjälä /** 343851f15feSVille Syrjälä * intel_drrs_init - Init DRRS for eDP connector 344851f15feSVille Syrjälä * @connector: eDP connector 345851f15feSVille Syrjälä * @fixed_mode: preferred mode of panel 346851f15feSVille Syrjälä * 347851f15feSVille Syrjälä * This function is called only once at driver load to initialize 348851f15feSVille Syrjälä * DRRS support for the connector. 349851f15feSVille Syrjälä * 350a1b63119SJosé Roberto de Souza * Returns: 351a1b63119SJosé Roberto de Souza * Downclock mode if panel supports it, else return NULL. 352a1b63119SJosé Roberto de Souza * DRRS support is determined by the presence of downclock mode (apart 353a1b63119SJosé Roberto de Souza * from VBT setting). 354a1b63119SJosé Roberto de Souza */ 355a1b63119SJosé Roberto de Souza struct drm_display_mode * 3563a3dd534SJosé Roberto de Souza intel_drrs_init(struct intel_connector *connector, 357faf6e8fcSVille Syrjälä const struct drm_display_mode *fixed_mode) 358a1b63119SJosé Roberto de Souza { 359a1b63119SJosé Roberto de Souza struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 360f0d4ce59SVille Syrjälä struct intel_encoder *encoder = connector->encoder; 361851f15feSVille Syrjälä struct drm_display_mode *downclock_mode; 362a1b63119SJosé Roberto de Souza 363c2f12155SVille Syrjälä if (DISPLAY_VER(dev_priv) < 5) { 364a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 3655f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported on platform\n", 3665f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 367a1b63119SJosé Roberto de Souza return NULL; 368a1b63119SJosé Roberto de Souza } 369a1b63119SJosé Roberto de Souza 370f0d4ce59SVille Syrjälä if ((DISPLAY_VER(dev_priv) < 8 && !HAS_GMCH(dev_priv)) && 371f0d4ce59SVille Syrjälä encoder->port != PORT_A) { 372f0d4ce59SVille Syrjälä drm_dbg_kms(&dev_priv->drm, 3735f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported on [ENCODER:%d:%s]\n", 3745f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name, 3755f6a9beaSVille Syrjälä encoder->base.base.id, encoder->base.name); 376f0d4ce59SVille Syrjälä return NULL; 377f0d4ce59SVille Syrjälä } 378f0d4ce59SVille Syrjälä 379c5ee2343SVille Syrjälä if (dev_priv->vbt.drrs_type == DRRS_TYPE_NONE) { 3805f6a9beaSVille Syrjälä drm_dbg_kms(&dev_priv->drm, 3815f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported according to VBT\n", 3825f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 383a1b63119SJosé Roberto de Souza return NULL; 384a1b63119SJosé Roberto de Souza } 385a1b63119SJosé Roberto de Souza 386a1b63119SJosé Roberto de Souza downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode); 387a1b63119SJosé Roberto de Souza if (!downclock_mode) { 388a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 3895f6a9beaSVille Syrjälä "[CONNECTOR:%d:%s] DRRS not supported due to lack of downclock mode\n", 3905f6a9beaSVille Syrjälä connector->base.base.id, connector->base.name); 391a1b63119SJosé Roberto de Souza return NULL; 392a1b63119SJosé Roberto de Souza } 393a1b63119SJosé Roberto de Souza 394a1b63119SJosé Roberto de Souza drm_dbg_kms(&dev_priv->drm, 395a1b952d4SVille Syrjälä "[CONNECTOR:%d:%s] %s DRRS supported\n", 396a1b952d4SVille Syrjälä connector->base.base.id, connector->base.name, 397a1b952d4SVille Syrjälä intel_drrs_type_str(dev_priv->vbt.drrs_type)); 3985f6a9beaSVille Syrjälä 399a1b63119SJosé Roberto de Souza return downclock_mode; 400a1b63119SJosé Roberto de Souza } 401