1 // SPDX-License-Identifier: MIT
2 /*
3  * Copyright © 2021 Intel Corporation
4  */
5 
6 #include "gem/i915_gem_domain.h"
7 #include "gem/i915_gem_internal.h"
8 #include "gt/gen8_ppgtt.h"
9 
10 #include "i915_drv.h"
11 #include "intel_display_types.h"
12 #include "intel_dpt.h"
13 #include "intel_fb.h"
14 
15 struct i915_dpt {
16 	struct i915_address_space vm;
17 
18 	struct drm_i915_gem_object *obj;
19 	struct i915_vma *vma;
20 	void __iomem *iomem;
21 };
22 
23 #define i915_is_dpt(vm) ((vm)->is_dpt)
24 
25 static inline struct i915_dpt *
26 i915_vm_to_dpt(struct i915_address_space *vm)
27 {
28 	BUILD_BUG_ON(offsetof(struct i915_dpt, vm));
29 	GEM_BUG_ON(!i915_is_dpt(vm));
30 	return container_of(vm, struct i915_dpt, vm);
31 }
32 
33 #define dpt_total_entries(dpt) ((dpt)->vm.total >> PAGE_SHIFT)
34 
35 static void gen8_set_pte(void __iomem *addr, gen8_pte_t pte)
36 {
37 	writeq(pte, addr);
38 }
39 
40 static void dpt_insert_page(struct i915_address_space *vm,
41 			    dma_addr_t addr,
42 			    u64 offset,
43 			    enum i915_cache_level level,
44 			    u32 flags)
45 {
46 	struct i915_dpt *dpt = i915_vm_to_dpt(vm);
47 	gen8_pte_t __iomem *base = dpt->iomem;
48 
49 	gen8_set_pte(base + offset / I915_GTT_PAGE_SIZE,
50 		     vm->pte_encode(addr, level, flags));
51 }
52 
53 static void dpt_insert_entries(struct i915_address_space *vm,
54 			       struct i915_vma_resource *vma_res,
55 			       enum i915_cache_level level,
56 			       u32 flags)
57 {
58 	struct i915_dpt *dpt = i915_vm_to_dpt(vm);
59 	gen8_pte_t __iomem *base = dpt->iomem;
60 	const gen8_pte_t pte_encode = vm->pte_encode(0, level, flags);
61 	struct sgt_iter sgt_iter;
62 	dma_addr_t addr;
63 	int i;
64 
65 	/*
66 	 * Note that we ignore PTE_READ_ONLY here. The caller must be careful
67 	 * not to allow the user to override access to a read only page.
68 	 */
69 
70 	i = vma_res->start / I915_GTT_PAGE_SIZE;
71 	for_each_sgt_daddr(addr, sgt_iter, vma_res->bi.pages)
72 		gen8_set_pte(&base[i++], pte_encode | addr);
73 }
74 
75 static void dpt_clear_range(struct i915_address_space *vm,
76 			    u64 start, u64 length)
77 {
78 }
79 
80 static void dpt_bind_vma(struct i915_address_space *vm,
81 			 struct i915_vm_pt_stash *stash,
82 			 struct i915_vma_resource *vma_res,
83 			 enum i915_cache_level cache_level,
84 			 u32 flags)
85 {
86 	u32 pte_flags;
87 
88 	if (vma_res->bound_flags)
89 		return;
90 
91 	/* Applicable to VLV (gen8+ do not support RO in the GGTT) */
92 	pte_flags = 0;
93 	if (vm->has_read_only && vma_res->bi.readonly)
94 		pte_flags |= PTE_READ_ONLY;
95 	if (vma_res->bi.lmem)
96 		pte_flags |= PTE_LM;
97 
98 	vm->insert_entries(vm, vma_res, cache_level, pte_flags);
99 
100 	vma_res->page_sizes_gtt = I915_GTT_PAGE_SIZE;
101 
102 	/*
103 	 * Without aliasing PPGTT there's no difference between
104 	 * GLOBAL/LOCAL_BIND, it's all the same ptes. Hence unconditionally
105 	 * upgrade to both bound if we bind either to avoid double-binding.
106 	 */
107 	vma_res->bound_flags = I915_VMA_GLOBAL_BIND | I915_VMA_LOCAL_BIND;
108 }
109 
110 static void dpt_unbind_vma(struct i915_address_space *vm,
111 			   struct i915_vma_resource *vma_res)
112 {
113 	vm->clear_range(vm, vma_res->start, vma_res->vma_size);
114 }
115 
116 static void dpt_cleanup(struct i915_address_space *vm)
117 {
118 	struct i915_dpt *dpt = i915_vm_to_dpt(vm);
119 
120 	i915_gem_object_put(dpt->obj);
121 }
122 
123 struct i915_vma *intel_dpt_pin(struct i915_address_space *vm)
124 {
125 	struct drm_i915_private *i915 = vm->i915;
126 	struct i915_dpt *dpt = i915_vm_to_dpt(vm);
127 	intel_wakeref_t wakeref;
128 	struct i915_vma *vma;
129 	void __iomem *iomem;
130 	struct i915_gem_ww_ctx ww;
131 	u64 pin_flags = 0;
132 	int err;
133 
134 	if (i915_gem_object_is_stolen(dpt->obj))
135 		pin_flags |= PIN_MAPPABLE;
136 
137 	wakeref = intel_runtime_pm_get(&i915->runtime_pm);
138 	atomic_inc(&i915->gpu_error.pending_fb_pin);
139 
140 	for_i915_gem_ww(&ww, err, true) {
141 		err = i915_gem_object_lock(dpt->obj, &ww);
142 		if (err)
143 			continue;
144 
145 		vma = i915_gem_object_ggtt_pin_ww(dpt->obj, &ww, NULL, 0, 4096,
146 						  pin_flags);
147 		if (IS_ERR(vma)) {
148 			err = PTR_ERR(vma);
149 			continue;
150 		}
151 
152 		iomem = i915_vma_pin_iomap(vma);
153 		i915_vma_unpin(vma);
154 
155 		if (IS_ERR(iomem)) {
156 			err = PTR_ERR(iomem);
157 			continue;
158 		}
159 
160 		dpt->vma = vma;
161 		dpt->iomem = iomem;
162 
163 		i915_vma_get(vma);
164 	}
165 
166 	atomic_dec(&i915->gpu_error.pending_fb_pin);
167 	intel_runtime_pm_put(&i915->runtime_pm, wakeref);
168 
169 	return err ? ERR_PTR(err) : vma;
170 }
171 
172 void intel_dpt_unpin(struct i915_address_space *vm)
173 {
174 	struct i915_dpt *dpt = i915_vm_to_dpt(vm);
175 
176 	i915_vma_unpin_iomap(dpt->vma);
177 	i915_vma_put(dpt->vma);
178 }
179 
180 /**
181  * intel_dpt_resume - restore the memory mapping for all DPT FBs during system resume
182  * @i915: device instance
183  *
184  * Restore the memory mapping during system resume for all framebuffers which
185  * are mapped to HW via a GGTT->DPT page table. The content of these page
186  * tables are not stored in the hibernation image during S4 and S3RST->S4
187  * transitions, so here we reprogram the PTE entries in those tables.
188  *
189  * This function must be called after the mappings in GGTT have been restored calling
190  * i915_ggtt_resume().
191  */
192 void intel_dpt_resume(struct drm_i915_private *i915)
193 {
194 	struct drm_framebuffer *drm_fb;
195 
196 	if (!HAS_DISPLAY(i915))
197 		return;
198 
199 	mutex_lock(&i915->drm.mode_config.fb_lock);
200 	drm_for_each_fb(drm_fb, &i915->drm) {
201 		struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
202 
203 		if (fb->dpt_vm)
204 			i915_ggtt_resume_vm(fb->dpt_vm);
205 	}
206 	mutex_unlock(&i915->drm.mode_config.fb_lock);
207 }
208 
209 /**
210  * intel_dpt_suspend - suspend the memory mapping for all DPT FBs during system suspend
211  * @i915: device instance
212  *
213  * Suspend the memory mapping during system suspend for all framebuffers which
214  * are mapped to HW via a GGTT->DPT page table.
215  *
216  * This function must be called before the mappings in GGTT are suspended calling
217  * i915_ggtt_suspend().
218  */
219 void intel_dpt_suspend(struct drm_i915_private *i915)
220 {
221 	struct drm_framebuffer *drm_fb;
222 
223 	if (!HAS_DISPLAY(i915))
224 		return;
225 
226 	mutex_lock(&i915->drm.mode_config.fb_lock);
227 
228 	drm_for_each_fb(drm_fb, &i915->drm) {
229 		struct intel_framebuffer *fb = to_intel_framebuffer(drm_fb);
230 
231 		if (fb->dpt_vm)
232 			i915_ggtt_suspend_vm(fb->dpt_vm);
233 	}
234 
235 	mutex_unlock(&i915->drm.mode_config.fb_lock);
236 }
237 
238 struct i915_address_space *
239 intel_dpt_create(struct intel_framebuffer *fb)
240 {
241 	struct drm_gem_object *obj = &intel_fb_obj(&fb->base)->base;
242 	struct drm_i915_private *i915 = to_i915(obj->dev);
243 	struct drm_i915_gem_object *dpt_obj;
244 	struct i915_address_space *vm;
245 	struct i915_dpt *dpt;
246 	size_t size;
247 	int ret;
248 
249 	if (intel_fb_needs_pot_stride_remap(fb))
250 		size = intel_remapped_info_size(&fb->remapped_view.gtt.remapped);
251 	else
252 		size = DIV_ROUND_UP_ULL(obj->size, I915_GTT_PAGE_SIZE);
253 
254 	size = round_up(size * sizeof(gen8_pte_t), I915_GTT_PAGE_SIZE);
255 
256 	dpt_obj = i915_gem_object_create_lmem(i915, size, I915_BO_ALLOC_CONTIGUOUS);
257 	if (IS_ERR(dpt_obj) && i915_ggtt_has_aperture(to_gt(i915)->ggtt))
258 		dpt_obj = i915_gem_object_create_stolen(i915, size);
259 	if (IS_ERR(dpt_obj) && !HAS_LMEM(i915)) {
260 		drm_dbg_kms(&i915->drm, "Allocating dpt from smem\n");
261 		dpt_obj = i915_gem_object_create_internal(i915, size);
262 	}
263 	if (IS_ERR(dpt_obj))
264 		return ERR_CAST(dpt_obj);
265 
266 	ret = i915_gem_object_lock_interruptible(dpt_obj, NULL);
267 	if (!ret) {
268 		ret = i915_gem_object_set_cache_level(dpt_obj, I915_CACHE_NONE);
269 		i915_gem_object_unlock(dpt_obj);
270 	}
271 	if (ret) {
272 		i915_gem_object_put(dpt_obj);
273 		return ERR_PTR(ret);
274 	}
275 
276 	dpt = kzalloc(sizeof(*dpt), GFP_KERNEL);
277 	if (!dpt) {
278 		i915_gem_object_put(dpt_obj);
279 		return ERR_PTR(-ENOMEM);
280 	}
281 
282 	vm = &dpt->vm;
283 
284 	vm->gt = to_gt(i915);
285 	vm->i915 = i915;
286 	vm->dma = i915->drm.dev;
287 	vm->total = (size / sizeof(gen8_pte_t)) * I915_GTT_PAGE_SIZE;
288 	vm->is_dpt = true;
289 
290 	i915_address_space_init(vm, VM_CLASS_DPT);
291 
292 	vm->insert_page = dpt_insert_page;
293 	vm->clear_range = dpt_clear_range;
294 	vm->insert_entries = dpt_insert_entries;
295 	vm->cleanup = dpt_cleanup;
296 
297 	vm->vma_ops.bind_vma    = dpt_bind_vma;
298 	vm->vma_ops.unbind_vma  = dpt_unbind_vma;
299 
300 	vm->pte_encode = gen8_ggtt_pte_encode;
301 
302 	dpt->obj = dpt_obj;
303 
304 	return &dpt->vm;
305 }
306 
307 void intel_dpt_destroy(struct i915_address_space *vm)
308 {
309 	struct i915_dpt *dpt = i915_vm_to_dpt(vm);
310 
311 	i915_vm_put(&dpt->vm);
312 }
313