1 /* 2 * Copyright © 2012-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #ifndef _INTEL_DPLL_MGR_H_ 26 #define _INTEL_DPLL_MGR_H_ 27 28 #include <linux/types.h> 29 30 #include "intel_wakeref.h" 31 32 /*FIXME: Move this to a more appropriate place. */ 33 #define abs_diff(a, b) ({ \ 34 typeof(a) __a = (a); \ 35 typeof(b) __b = (b); \ 36 (void) (&__a == &__b); \ 37 __a > __b ? (__a - __b) : (__b - __a); }) 38 39 enum tc_port; 40 struct drm_device; 41 struct drm_i915_private; 42 struct intel_atomic_state; 43 struct intel_crtc; 44 struct intel_crtc_state; 45 struct intel_encoder; 46 struct intel_shared_dpll; 47 struct intel_shared_dpll_funcs; 48 49 /** 50 * enum intel_dpll_id - possible DPLL ids 51 * 52 * Enumeration of possible IDs for a DPLL. Real shared dpll ids must be >= 0. 53 */ 54 enum intel_dpll_id { 55 /** 56 * @DPLL_ID_PRIVATE: non-shared dpll in use 57 */ 58 DPLL_ID_PRIVATE = -1, 59 60 /** 61 * @DPLL_ID_PCH_PLL_A: DPLL A in ILK, SNB and IVB 62 */ 63 DPLL_ID_PCH_PLL_A = 0, 64 /** 65 * @DPLL_ID_PCH_PLL_B: DPLL B in ILK, SNB and IVB 66 */ 67 DPLL_ID_PCH_PLL_B = 1, 68 69 70 /** 71 * @DPLL_ID_WRPLL1: HSW and BDW WRPLL1 72 */ 73 DPLL_ID_WRPLL1 = 0, 74 /** 75 * @DPLL_ID_WRPLL2: HSW and BDW WRPLL2 76 */ 77 DPLL_ID_WRPLL2 = 1, 78 /** 79 * @DPLL_ID_SPLL: HSW and BDW SPLL 80 */ 81 DPLL_ID_SPLL = 2, 82 /** 83 * @DPLL_ID_LCPLL_810: HSW and BDW 0.81 GHz LCPLL 84 */ 85 DPLL_ID_LCPLL_810 = 3, 86 /** 87 * @DPLL_ID_LCPLL_1350: HSW and BDW 1.35 GHz LCPLL 88 */ 89 DPLL_ID_LCPLL_1350 = 4, 90 /** 91 * @DPLL_ID_LCPLL_2700: HSW and BDW 2.7 GHz LCPLL 92 */ 93 DPLL_ID_LCPLL_2700 = 5, 94 95 96 /** 97 * @DPLL_ID_SKL_DPLL0: SKL and later DPLL0 98 */ 99 DPLL_ID_SKL_DPLL0 = 0, 100 /** 101 * @DPLL_ID_SKL_DPLL1: SKL and later DPLL1 102 */ 103 DPLL_ID_SKL_DPLL1 = 1, 104 /** 105 * @DPLL_ID_SKL_DPLL2: SKL and later DPLL2 106 */ 107 DPLL_ID_SKL_DPLL2 = 2, 108 /** 109 * @DPLL_ID_SKL_DPLL3: SKL and later DPLL3 110 */ 111 DPLL_ID_SKL_DPLL3 = 3, 112 113 114 /** 115 * @DPLL_ID_ICL_DPLL0: ICL/TGL combo PHY DPLL0 116 */ 117 DPLL_ID_ICL_DPLL0 = 0, 118 /** 119 * @DPLL_ID_ICL_DPLL1: ICL/TGL combo PHY DPLL1 120 */ 121 DPLL_ID_ICL_DPLL1 = 1, 122 /** 123 * @DPLL_ID_EHL_DPLL4: EHL combo PHY DPLL4 124 */ 125 DPLL_ID_EHL_DPLL4 = 2, 126 /** 127 * @DPLL_ID_ICL_TBTPLL: ICL/TGL TBT PLL 128 */ 129 DPLL_ID_ICL_TBTPLL = 2, 130 /** 131 * @DPLL_ID_ICL_MGPLL1: ICL MG PLL 1 port 1 (C), 132 * TGL TC PLL 1 port 1 (TC1) 133 */ 134 DPLL_ID_ICL_MGPLL1 = 3, 135 /** 136 * @DPLL_ID_ICL_MGPLL2: ICL MG PLL 1 port 2 (D) 137 * TGL TC PLL 1 port 2 (TC2) 138 */ 139 DPLL_ID_ICL_MGPLL2 = 4, 140 /** 141 * @DPLL_ID_ICL_MGPLL3: ICL MG PLL 1 port 3 (E) 142 * TGL TC PLL 1 port 3 (TC3) 143 */ 144 DPLL_ID_ICL_MGPLL3 = 5, 145 /** 146 * @DPLL_ID_ICL_MGPLL4: ICL MG PLL 1 port 4 (F) 147 * TGL TC PLL 1 port 4 (TC4) 148 */ 149 DPLL_ID_ICL_MGPLL4 = 6, 150 /** 151 * @DPLL_ID_TGL_MGPLL5: TGL TC PLL port 5 (TC5) 152 */ 153 DPLL_ID_TGL_MGPLL5 = 7, 154 /** 155 * @DPLL_ID_TGL_MGPLL6: TGL TC PLL port 6 (TC6) 156 */ 157 DPLL_ID_TGL_MGPLL6 = 8, 158 159 /** 160 * @DPLL_ID_DG1_DPLL0: DG1 combo PHY DPLL0 161 */ 162 DPLL_ID_DG1_DPLL0 = 0, 163 /** 164 * @DPLL_ID_DG1_DPLL1: DG1 combo PHY DPLL1 165 */ 166 DPLL_ID_DG1_DPLL1 = 1, 167 /** 168 * @DPLL_ID_DG1_DPLL2: DG1 combo PHY DPLL2 169 */ 170 DPLL_ID_DG1_DPLL2 = 2, 171 /** 172 * @DPLL_ID_DG1_DPLL3: DG1 combo PHY DPLL3 173 */ 174 DPLL_ID_DG1_DPLL3 = 3, 175 }; 176 177 #define I915_NUM_PLLS 9 178 179 enum icl_port_dpll_id { 180 ICL_PORT_DPLL_DEFAULT, 181 ICL_PORT_DPLL_MG_PHY, 182 183 ICL_PORT_DPLL_COUNT, 184 }; 185 186 struct intel_dpll_hw_state { 187 /* i9xx, pch plls */ 188 u32 dpll; 189 u32 dpll_md; 190 u32 fp0; 191 u32 fp1; 192 193 /* hsw, bdw */ 194 u32 wrpll; 195 u32 spll; 196 197 /* skl */ 198 /* 199 * DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in 200 * lower part of ctrl1 and they get shifted into position when writing 201 * the register. This allows us to easily compare the state to share 202 * the DPLL. 203 */ 204 u32 ctrl1; 205 /* HDMI only, 0 when used for DP */ 206 u32 cfgcr1, cfgcr2; 207 208 /* icl */ 209 u32 cfgcr0; 210 211 /* tgl */ 212 u32 div0; 213 214 /* bxt */ 215 u32 ebb0, ebb4, pll0, pll1, pll2, pll3, pll6, pll8, pll9, pll10, pcsdw12; 216 217 /* 218 * ICL uses the following, already defined: 219 * u32 cfgcr0, cfgcr1; 220 */ 221 u32 mg_refclkin_ctl; 222 u32 mg_clktop2_coreclkctl1; 223 u32 mg_clktop2_hsclkctl; 224 u32 mg_pll_div0; 225 u32 mg_pll_div1; 226 u32 mg_pll_lf; 227 u32 mg_pll_frac_lock; 228 u32 mg_pll_ssc; 229 u32 mg_pll_bias; 230 u32 mg_pll_tdc_coldst_bias; 231 u32 mg_pll_bias_mask; 232 u32 mg_pll_tdc_coldst_bias_mask; 233 }; 234 235 /** 236 * struct intel_shared_dpll_state - hold the DPLL atomic state 237 * 238 * This structure holds an atomic state for the DPLL, that can represent 239 * either its current state (in struct &intel_shared_dpll) or a desired 240 * future state which would be applied by an atomic mode set (stored in 241 * a struct &intel_atomic_state). 242 * 243 * See also intel_reserve_shared_dplls() and intel_release_shared_dplls(). 244 */ 245 struct intel_shared_dpll_state { 246 /** 247 * @pipe_mask: mask of pipes using this DPLL, active or not 248 */ 249 u8 pipe_mask; 250 251 /** 252 * @hw_state: hardware configuration for the DPLL stored in 253 * struct &intel_dpll_hw_state. 254 */ 255 struct intel_dpll_hw_state hw_state; 256 }; 257 258 /** 259 * struct dpll_info - display PLL platform specific info 260 */ 261 struct dpll_info { 262 /** 263 * @name: DPLL name; used for logging 264 */ 265 const char *name; 266 267 /** 268 * @funcs: platform specific hooks 269 */ 270 const struct intel_shared_dpll_funcs *funcs; 271 272 /** 273 * @id: unique indentifier for this DPLL; should match the index in the 274 * dev_priv->shared_dplls array 275 */ 276 enum intel_dpll_id id; 277 278 #define INTEL_DPLL_ALWAYS_ON (1 << 0) 279 /** 280 * @flags: 281 * 282 * INTEL_DPLL_ALWAYS_ON 283 * Inform the state checker that the DPLL is kept enabled even if 284 * not in use by any CRTC. 285 */ 286 u32 flags; 287 }; 288 289 /** 290 * struct intel_shared_dpll - display PLL with tracked state and users 291 */ 292 struct intel_shared_dpll { 293 /** 294 * @state: 295 * 296 * Store the state for the pll, including its hw state 297 * and CRTCs using it. 298 */ 299 struct intel_shared_dpll_state state; 300 301 /** 302 * @active_mask: mask of active pipes (i.e. DPMS on) using this DPLL 303 */ 304 u8 active_mask; 305 306 /** 307 * @on: is the PLL actually active? Disabled during modeset 308 */ 309 bool on; 310 311 /** 312 * @info: platform specific info 313 */ 314 const struct dpll_info *info; 315 316 /** 317 * @wakeref: In some platforms a device-level runtime pm reference may 318 * need to be grabbed to disable DC states while this DPLL is enabled 319 */ 320 intel_wakeref_t wakeref; 321 }; 322 323 #define SKL_DPLL0 0 324 #define SKL_DPLL1 1 325 #define SKL_DPLL2 2 326 #define SKL_DPLL3 3 327 328 /* shared dpll functions */ 329 struct intel_shared_dpll * 330 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv, 331 enum intel_dpll_id id); 332 enum intel_dpll_id 333 intel_get_shared_dpll_id(struct drm_i915_private *dev_priv, 334 struct intel_shared_dpll *pll); 335 void assert_shared_dpll(struct drm_i915_private *dev_priv, 336 struct intel_shared_dpll *pll, 337 bool state); 338 #define assert_shared_dpll_enabled(d, p) assert_shared_dpll(d, p, true) 339 #define assert_shared_dpll_disabled(d, p) assert_shared_dpll(d, p, false) 340 bool intel_reserve_shared_dplls(struct intel_atomic_state *state, 341 struct intel_crtc *crtc, 342 struct intel_encoder *encoder); 343 void intel_release_shared_dplls(struct intel_atomic_state *state, 344 struct intel_crtc *crtc); 345 void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state, 346 enum icl_port_dpll_id port_dpll_id); 347 void intel_update_active_dpll(struct intel_atomic_state *state, 348 struct intel_crtc *crtc, 349 struct intel_encoder *encoder); 350 int intel_dpll_get_freq(struct drm_i915_private *i915, 351 const struct intel_shared_dpll *pll, 352 const struct intel_dpll_hw_state *pll_state); 353 bool intel_dpll_get_hw_state(struct drm_i915_private *i915, 354 struct intel_shared_dpll *pll, 355 struct intel_dpll_hw_state *hw_state); 356 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state); 357 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state); 358 void intel_shared_dpll_swap_state(struct intel_atomic_state *state); 359 void intel_shared_dpll_init(struct drm_device *dev); 360 void intel_dpll_update_ref_clks(struct drm_i915_private *dev_priv); 361 void intel_dpll_readout_hw_state(struct drm_i915_private *dev_priv); 362 void intel_dpll_sanitize_state(struct drm_i915_private *dev_priv); 363 364 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv, 365 const struct intel_dpll_hw_state *hw_state); 366 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port); 367 bool intel_dpll_is_combophy(enum intel_dpll_id id); 368 369 #endif /* _INTEL_DPLL_MGR_H_ */ 370