1 /*
2  * Copyright © 2006-2016 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  */
23 
24 #include <linux/math.h>
25 #include <linux/string_helpers.h>
26 
27 #include "i915_reg.h"
28 #include "intel_de.h"
29 #include "intel_display_types.h"
30 #include "intel_dkl_phy.h"
31 #include "intel_dkl_phy_regs.h"
32 #include "intel_dpio_phy.h"
33 #include "intel_dpll.h"
34 #include "intel_dpll_mgr.h"
35 #include "intel_hti.h"
36 #include "intel_mg_phy_regs.h"
37 #include "intel_pch_refclk.h"
38 #include "intel_tc.h"
39 
40 /**
41  * DOC: Display PLLs
42  *
43  * Display PLLs used for driving outputs vary by platform. While some have
44  * per-pipe or per-encoder dedicated PLLs, others allow the use of any PLL
45  * from a pool. In the latter scenario, it is possible that multiple pipes
46  * share a PLL if their configurations match.
47  *
48  * This file provides an abstraction over display PLLs. The function
49  * intel_shared_dpll_init() initializes the PLLs for the given platform.  The
50  * users of a PLL are tracked and that tracking is integrated with the atomic
51  * modset interface. During an atomic operation, required PLLs can be reserved
52  * for a given CRTC and encoder configuration by calling
53  * intel_reserve_shared_dplls() and previously reserved PLLs can be released
54  * with intel_release_shared_dplls().
55  * Changes to the users are first staged in the atomic state, and then made
56  * effective by calling intel_shared_dpll_swap_state() during the atomic
57  * commit phase.
58  */
59 
60 /* platform specific hooks for managing DPLLs */
61 struct intel_shared_dpll_funcs {
62 	/*
63 	 * Hook for enabling the pll, called from intel_enable_shared_dpll() if
64 	 * the pll is not already enabled.
65 	 */
66 	void (*enable)(struct drm_i915_private *i915,
67 		       struct intel_shared_dpll *pll);
68 
69 	/*
70 	 * Hook for disabling the pll, called from intel_disable_shared_dpll()
71 	 * only when it is safe to disable the pll, i.e., there are no more
72 	 * tracked users for it.
73 	 */
74 	void (*disable)(struct drm_i915_private *i915,
75 			struct intel_shared_dpll *pll);
76 
77 	/*
78 	 * Hook for reading the values currently programmed to the DPLL
79 	 * registers. This is used for initial hw state readout and state
80 	 * verification after a mode set.
81 	 */
82 	bool (*get_hw_state)(struct drm_i915_private *i915,
83 			     struct intel_shared_dpll *pll,
84 			     struct intel_dpll_hw_state *hw_state);
85 
86 	/*
87 	 * Hook for calculating the pll's output frequency based on its passed
88 	 * in state.
89 	 */
90 	int (*get_freq)(struct drm_i915_private *i915,
91 			const struct intel_shared_dpll *pll,
92 			const struct intel_dpll_hw_state *pll_state);
93 };
94 
95 struct intel_dpll_mgr {
96 	const struct dpll_info *dpll_info;
97 
98 	int (*compute_dplls)(struct intel_atomic_state *state,
99 			     struct intel_crtc *crtc,
100 			     struct intel_encoder *encoder);
101 	int (*get_dplls)(struct intel_atomic_state *state,
102 			 struct intel_crtc *crtc,
103 			 struct intel_encoder *encoder);
104 	void (*put_dplls)(struct intel_atomic_state *state,
105 			  struct intel_crtc *crtc);
106 	void (*update_active_dpll)(struct intel_atomic_state *state,
107 				   struct intel_crtc *crtc,
108 				   struct intel_encoder *encoder);
109 	void (*update_ref_clks)(struct drm_i915_private *i915);
110 	void (*dump_hw_state)(struct drm_i915_private *dev_priv,
111 			      const struct intel_dpll_hw_state *hw_state);
112 };
113 
114 static void
115 intel_atomic_duplicate_dpll_state(struct drm_i915_private *dev_priv,
116 				  struct intel_shared_dpll_state *shared_dpll)
117 {
118 	enum intel_dpll_id i;
119 
120 	/* Copy shared dpll state */
121 	for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
122 		struct intel_shared_dpll *pll = &dev_priv->display.dpll.shared_dplls[i];
123 
124 		shared_dpll[i] = pll->state;
125 	}
126 }
127 
128 static struct intel_shared_dpll_state *
129 intel_atomic_get_shared_dpll_state(struct drm_atomic_state *s)
130 {
131 	struct intel_atomic_state *state = to_intel_atomic_state(s);
132 
133 	drm_WARN_ON(s->dev, !drm_modeset_is_locked(&s->dev->mode_config.connection_mutex));
134 
135 	if (!state->dpll_set) {
136 		state->dpll_set = true;
137 
138 		intel_atomic_duplicate_dpll_state(to_i915(s->dev),
139 						  state->shared_dpll);
140 	}
141 
142 	return state->shared_dpll;
143 }
144 
145 /**
146  * intel_get_shared_dpll_by_id - get a DPLL given its id
147  * @dev_priv: i915 device instance
148  * @id: pll id
149  *
150  * Returns:
151  * A pointer to the DPLL with @id
152  */
153 struct intel_shared_dpll *
154 intel_get_shared_dpll_by_id(struct drm_i915_private *dev_priv,
155 			    enum intel_dpll_id id)
156 {
157 	return &dev_priv->display.dpll.shared_dplls[id];
158 }
159 
160 /* For ILK+ */
161 void assert_shared_dpll(struct drm_i915_private *dev_priv,
162 			struct intel_shared_dpll *pll,
163 			bool state)
164 {
165 	bool cur_state;
166 	struct intel_dpll_hw_state hw_state;
167 
168 	if (drm_WARN(&dev_priv->drm, !pll,
169 		     "asserting DPLL %s with no DPLL\n", str_on_off(state)))
170 		return;
171 
172 	cur_state = intel_dpll_get_hw_state(dev_priv, pll, &hw_state);
173 	I915_STATE_WARN(dev_priv, cur_state != state,
174 			"%s assertion failure (expected %s, current %s)\n",
175 			pll->info->name, str_on_off(state),
176 			str_on_off(cur_state));
177 }
178 
179 static enum tc_port icl_pll_id_to_tc_port(enum intel_dpll_id id)
180 {
181 	return TC_PORT_1 + id - DPLL_ID_ICL_MGPLL1;
182 }
183 
184 enum intel_dpll_id icl_tc_port_to_pll_id(enum tc_port tc_port)
185 {
186 	return tc_port - TC_PORT_1 + DPLL_ID_ICL_MGPLL1;
187 }
188 
189 static i915_reg_t
190 intel_combo_pll_enable_reg(struct drm_i915_private *i915,
191 			   struct intel_shared_dpll *pll)
192 {
193 	if (IS_DG1(i915))
194 		return DG1_DPLL_ENABLE(pll->info->id);
195 	else if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
196 		 (pll->info->id == DPLL_ID_EHL_DPLL4))
197 		return MG_PLL_ENABLE(0);
198 
199 	return ICL_DPLL_ENABLE(pll->info->id);
200 }
201 
202 static i915_reg_t
203 intel_tc_pll_enable_reg(struct drm_i915_private *i915,
204 			struct intel_shared_dpll *pll)
205 {
206 	const enum intel_dpll_id id = pll->info->id;
207 	enum tc_port tc_port = icl_pll_id_to_tc_port(id);
208 
209 	if (IS_ALDERLAKE_P(i915))
210 		return ADLP_PORTTC_PLL_ENABLE(tc_port);
211 
212 	return MG_PLL_ENABLE(tc_port);
213 }
214 
215 /**
216  * intel_enable_shared_dpll - enable a CRTC's shared DPLL
217  * @crtc_state: CRTC, and its state, which has a shared DPLL
218  *
219  * Enable the shared DPLL used by @crtc.
220  */
221 void intel_enable_shared_dpll(const struct intel_crtc_state *crtc_state)
222 {
223 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
224 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
225 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
226 	unsigned int pipe_mask = BIT(crtc->pipe);
227 	unsigned int old_mask;
228 
229 	if (drm_WARN_ON(&dev_priv->drm, pll == NULL))
230 		return;
231 
232 	mutex_lock(&dev_priv->display.dpll.lock);
233 	old_mask = pll->active_mask;
234 
235 	if (drm_WARN_ON(&dev_priv->drm, !(pll->state.pipe_mask & pipe_mask)) ||
236 	    drm_WARN_ON(&dev_priv->drm, pll->active_mask & pipe_mask))
237 		goto out;
238 
239 	pll->active_mask |= pipe_mask;
240 
241 	drm_dbg_kms(&dev_priv->drm,
242 		    "enable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n",
243 		    pll->info->name, pll->active_mask, pll->on,
244 		    crtc->base.base.id, crtc->base.name);
245 
246 	if (old_mask) {
247 		drm_WARN_ON(&dev_priv->drm, !pll->on);
248 		assert_shared_dpll_enabled(dev_priv, pll);
249 		goto out;
250 	}
251 	drm_WARN_ON(&dev_priv->drm, pll->on);
252 
253 	drm_dbg_kms(&dev_priv->drm, "enabling %s\n", pll->info->name);
254 	pll->info->funcs->enable(dev_priv, pll);
255 	pll->on = true;
256 
257 out:
258 	mutex_unlock(&dev_priv->display.dpll.lock);
259 }
260 
261 /**
262  * intel_disable_shared_dpll - disable a CRTC's shared DPLL
263  * @crtc_state: CRTC, and its state, which has a shared DPLL
264  *
265  * Disable the shared DPLL used by @crtc.
266  */
267 void intel_disable_shared_dpll(const struct intel_crtc_state *crtc_state)
268 {
269 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
270 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
271 	struct intel_shared_dpll *pll = crtc_state->shared_dpll;
272 	unsigned int pipe_mask = BIT(crtc->pipe);
273 
274 	/* PCH only available on ILK+ */
275 	if (DISPLAY_VER(dev_priv) < 5)
276 		return;
277 
278 	if (pll == NULL)
279 		return;
280 
281 	mutex_lock(&dev_priv->display.dpll.lock);
282 	if (drm_WARN(&dev_priv->drm, !(pll->active_mask & pipe_mask),
283 		     "%s not used by [CRTC:%d:%s]\n", pll->info->name,
284 		     crtc->base.base.id, crtc->base.name))
285 		goto out;
286 
287 	drm_dbg_kms(&dev_priv->drm,
288 		    "disable %s (active 0x%x, on? %d) for [CRTC:%d:%s]\n",
289 		    pll->info->name, pll->active_mask, pll->on,
290 		    crtc->base.base.id, crtc->base.name);
291 
292 	assert_shared_dpll_enabled(dev_priv, pll);
293 	drm_WARN_ON(&dev_priv->drm, !pll->on);
294 
295 	pll->active_mask &= ~pipe_mask;
296 	if (pll->active_mask)
297 		goto out;
298 
299 	drm_dbg_kms(&dev_priv->drm, "disabling %s\n", pll->info->name);
300 	pll->info->funcs->disable(dev_priv, pll);
301 	pll->on = false;
302 
303 out:
304 	mutex_unlock(&dev_priv->display.dpll.lock);
305 }
306 
307 static struct intel_shared_dpll *
308 intel_find_shared_dpll(struct intel_atomic_state *state,
309 		       const struct intel_crtc *crtc,
310 		       const struct intel_dpll_hw_state *pll_state,
311 		       unsigned long dpll_mask)
312 {
313 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
314 	struct intel_shared_dpll *pll, *unused_pll = NULL;
315 	struct intel_shared_dpll_state *shared_dpll;
316 	enum intel_dpll_id i;
317 
318 	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
319 
320 	drm_WARN_ON(&dev_priv->drm, dpll_mask & ~(BIT(I915_NUM_PLLS) - 1));
321 
322 	for_each_set_bit(i, &dpll_mask, I915_NUM_PLLS) {
323 		pll = &dev_priv->display.dpll.shared_dplls[i];
324 
325 		/* Only want to check enabled timings first */
326 		if (shared_dpll[i].pipe_mask == 0) {
327 			if (!unused_pll)
328 				unused_pll = pll;
329 			continue;
330 		}
331 
332 		if (memcmp(pll_state,
333 			   &shared_dpll[i].hw_state,
334 			   sizeof(*pll_state)) == 0) {
335 			drm_dbg_kms(&dev_priv->drm,
336 				    "[CRTC:%d:%s] sharing existing %s (pipe mask 0x%x, active 0x%x)\n",
337 				    crtc->base.base.id, crtc->base.name,
338 				    pll->info->name,
339 				    shared_dpll[i].pipe_mask,
340 				    pll->active_mask);
341 			return pll;
342 		}
343 	}
344 
345 	/* Ok no matching timings, maybe there's a free one? */
346 	if (unused_pll) {
347 		drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] allocated %s\n",
348 			    crtc->base.base.id, crtc->base.name,
349 			    unused_pll->info->name);
350 		return unused_pll;
351 	}
352 
353 	return NULL;
354 }
355 
356 /**
357  * intel_reference_shared_dpll_crtc - Get a DPLL reference for a CRTC
358  * @crtc: CRTC on which behalf the reference is taken
359  * @pll: DPLL for which the reference is taken
360  * @shared_dpll_state: the DPLL atomic state in which the reference is tracked
361  *
362  * Take a reference for @pll tracking the use of it by @crtc.
363  */
364 static void
365 intel_reference_shared_dpll_crtc(const struct intel_crtc *crtc,
366 				 const struct intel_shared_dpll *pll,
367 				 struct intel_shared_dpll_state *shared_dpll_state)
368 {
369 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
370 
371 	drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) != 0);
372 
373 	shared_dpll_state->pipe_mask |= BIT(crtc->pipe);
374 
375 	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] reserving %s\n",
376 		    crtc->base.base.id, crtc->base.name, pll->info->name);
377 }
378 
379 static void
380 intel_reference_shared_dpll(struct intel_atomic_state *state,
381 			    const struct intel_crtc *crtc,
382 			    const struct intel_shared_dpll *pll,
383 			    const struct intel_dpll_hw_state *pll_state)
384 {
385 	struct intel_shared_dpll_state *shared_dpll;
386 	const enum intel_dpll_id id = pll->info->id;
387 
388 	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
389 
390 	if (shared_dpll[id].pipe_mask == 0)
391 		shared_dpll[id].hw_state = *pll_state;
392 
393 	intel_reference_shared_dpll_crtc(crtc, pll, &shared_dpll[id]);
394 }
395 
396 /**
397  * intel_unreference_shared_dpll_crtc - Drop a DPLL reference for a CRTC
398  * @crtc: CRTC on which behalf the reference is dropped
399  * @pll: DPLL for which the reference is dropped
400  * @shared_dpll_state: the DPLL atomic state in which the reference is tracked
401  *
402  * Drop a reference for @pll tracking the end of use of it by @crtc.
403  */
404 void
405 intel_unreference_shared_dpll_crtc(const struct intel_crtc *crtc,
406 				   const struct intel_shared_dpll *pll,
407 				   struct intel_shared_dpll_state *shared_dpll_state)
408 {
409 	struct drm_i915_private *i915 = to_i915(crtc->base.dev);
410 
411 	drm_WARN_ON(&i915->drm, (shared_dpll_state->pipe_mask & BIT(crtc->pipe)) == 0);
412 
413 	shared_dpll_state->pipe_mask &= ~BIT(crtc->pipe);
414 
415 	drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] releasing %s\n",
416 		    crtc->base.base.id, crtc->base.name, pll->info->name);
417 }
418 
419 static void intel_unreference_shared_dpll(struct intel_atomic_state *state,
420 					  const struct intel_crtc *crtc,
421 					  const struct intel_shared_dpll *pll)
422 {
423 	struct intel_shared_dpll_state *shared_dpll;
424 	const enum intel_dpll_id id = pll->info->id;
425 
426 	shared_dpll = intel_atomic_get_shared_dpll_state(&state->base);
427 
428 	intel_unreference_shared_dpll_crtc(crtc, pll, &shared_dpll[id]);
429 }
430 
431 static void intel_put_dpll(struct intel_atomic_state *state,
432 			   struct intel_crtc *crtc)
433 {
434 	const struct intel_crtc_state *old_crtc_state =
435 		intel_atomic_get_old_crtc_state(state, crtc);
436 	struct intel_crtc_state *new_crtc_state =
437 		intel_atomic_get_new_crtc_state(state, crtc);
438 
439 	new_crtc_state->shared_dpll = NULL;
440 
441 	if (!old_crtc_state->shared_dpll)
442 		return;
443 
444 	intel_unreference_shared_dpll(state, crtc, old_crtc_state->shared_dpll);
445 }
446 
447 /**
448  * intel_shared_dpll_swap_state - make atomic DPLL configuration effective
449  * @state: atomic state
450  *
451  * This is the dpll version of drm_atomic_helper_swap_state() since the
452  * helper does not handle driver-specific global state.
453  *
454  * For consistency with atomic helpers this function does a complete swap,
455  * i.e. it also puts the current state into @state, even though there is no
456  * need for that at this moment.
457  */
458 void intel_shared_dpll_swap_state(struct intel_atomic_state *state)
459 {
460 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
461 	struct intel_shared_dpll_state *shared_dpll = state->shared_dpll;
462 	enum intel_dpll_id i;
463 
464 	if (!state->dpll_set)
465 		return;
466 
467 	for (i = 0; i < dev_priv->display.dpll.num_shared_dpll; i++) {
468 		struct intel_shared_dpll *pll =
469 			&dev_priv->display.dpll.shared_dplls[i];
470 
471 		swap(pll->state, shared_dpll[i]);
472 	}
473 }
474 
475 static bool ibx_pch_dpll_get_hw_state(struct drm_i915_private *dev_priv,
476 				      struct intel_shared_dpll *pll,
477 				      struct intel_dpll_hw_state *hw_state)
478 {
479 	const enum intel_dpll_id id = pll->info->id;
480 	intel_wakeref_t wakeref;
481 	u32 val;
482 
483 	wakeref = intel_display_power_get_if_enabled(dev_priv,
484 						     POWER_DOMAIN_DISPLAY_CORE);
485 	if (!wakeref)
486 		return false;
487 
488 	val = intel_de_read(dev_priv, PCH_DPLL(id));
489 	hw_state->dpll = val;
490 	hw_state->fp0 = intel_de_read(dev_priv, PCH_FP0(id));
491 	hw_state->fp1 = intel_de_read(dev_priv, PCH_FP1(id));
492 
493 	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
494 
495 	return val & DPLL_VCO_ENABLE;
496 }
497 
498 static void ibx_assert_pch_refclk_enabled(struct drm_i915_private *dev_priv)
499 {
500 	u32 val;
501 	bool enabled;
502 
503 	val = intel_de_read(dev_priv, PCH_DREF_CONTROL);
504 	enabled = !!(val & (DREF_SSC_SOURCE_MASK | DREF_NONSPREAD_SOURCE_MASK |
505 			    DREF_SUPERSPREAD_SOURCE_MASK));
506 	I915_STATE_WARN(dev_priv, !enabled,
507 			"PCH refclk assertion failure, should be active but is disabled\n");
508 }
509 
510 static void ibx_pch_dpll_enable(struct drm_i915_private *dev_priv,
511 				struct intel_shared_dpll *pll)
512 {
513 	const enum intel_dpll_id id = pll->info->id;
514 
515 	/* PCH refclock must be enabled first */
516 	ibx_assert_pch_refclk_enabled(dev_priv);
517 
518 	intel_de_write(dev_priv, PCH_FP0(id), pll->state.hw_state.fp0);
519 	intel_de_write(dev_priv, PCH_FP1(id), pll->state.hw_state.fp1);
520 
521 	intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll);
522 
523 	/* Wait for the clocks to stabilize. */
524 	intel_de_posting_read(dev_priv, PCH_DPLL(id));
525 	udelay(150);
526 
527 	/* The pixel multiplier can only be updated once the
528 	 * DPLL is enabled and the clocks are stable.
529 	 *
530 	 * So write it again.
531 	 */
532 	intel_de_write(dev_priv, PCH_DPLL(id), pll->state.hw_state.dpll);
533 	intel_de_posting_read(dev_priv, PCH_DPLL(id));
534 	udelay(200);
535 }
536 
537 static void ibx_pch_dpll_disable(struct drm_i915_private *dev_priv,
538 				 struct intel_shared_dpll *pll)
539 {
540 	const enum intel_dpll_id id = pll->info->id;
541 
542 	intel_de_write(dev_priv, PCH_DPLL(id), 0);
543 	intel_de_posting_read(dev_priv, PCH_DPLL(id));
544 	udelay(200);
545 }
546 
547 static int ibx_compute_dpll(struct intel_atomic_state *state,
548 			    struct intel_crtc *crtc,
549 			    struct intel_encoder *encoder)
550 {
551 	return 0;
552 }
553 
554 static int ibx_get_dpll(struct intel_atomic_state *state,
555 			struct intel_crtc *crtc,
556 			struct intel_encoder *encoder)
557 {
558 	struct intel_crtc_state *crtc_state =
559 		intel_atomic_get_new_crtc_state(state, crtc);
560 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
561 	struct intel_shared_dpll *pll;
562 	enum intel_dpll_id i;
563 
564 	if (HAS_PCH_IBX(dev_priv)) {
565 		/* Ironlake PCH has a fixed PLL->PCH pipe mapping. */
566 		i = (enum intel_dpll_id) crtc->pipe;
567 		pll = &dev_priv->display.dpll.shared_dplls[i];
568 
569 		drm_dbg_kms(&dev_priv->drm,
570 			    "[CRTC:%d:%s] using pre-allocated %s\n",
571 			    crtc->base.base.id, crtc->base.name,
572 			    pll->info->name);
573 	} else {
574 		pll = intel_find_shared_dpll(state, crtc,
575 					     &crtc_state->dpll_hw_state,
576 					     BIT(DPLL_ID_PCH_PLL_B) |
577 					     BIT(DPLL_ID_PCH_PLL_A));
578 	}
579 
580 	if (!pll)
581 		return -EINVAL;
582 
583 	/* reference the pll */
584 	intel_reference_shared_dpll(state, crtc,
585 				    pll, &crtc_state->dpll_hw_state);
586 
587 	crtc_state->shared_dpll = pll;
588 
589 	return 0;
590 }
591 
592 static void ibx_dump_hw_state(struct drm_i915_private *dev_priv,
593 			      const struct intel_dpll_hw_state *hw_state)
594 {
595 	drm_dbg_kms(&dev_priv->drm,
596 		    "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
597 		    "fp0: 0x%x, fp1: 0x%x\n",
598 		    hw_state->dpll,
599 		    hw_state->dpll_md,
600 		    hw_state->fp0,
601 		    hw_state->fp1);
602 }
603 
604 static const struct intel_shared_dpll_funcs ibx_pch_dpll_funcs = {
605 	.enable = ibx_pch_dpll_enable,
606 	.disable = ibx_pch_dpll_disable,
607 	.get_hw_state = ibx_pch_dpll_get_hw_state,
608 };
609 
610 static const struct dpll_info pch_plls[] = {
611 	{ "PCH DPLL A", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_A, 0 },
612 	{ "PCH DPLL B", &ibx_pch_dpll_funcs, DPLL_ID_PCH_PLL_B, 0 },
613 	{ },
614 };
615 
616 static const struct intel_dpll_mgr pch_pll_mgr = {
617 	.dpll_info = pch_plls,
618 	.compute_dplls = ibx_compute_dpll,
619 	.get_dplls = ibx_get_dpll,
620 	.put_dplls = intel_put_dpll,
621 	.dump_hw_state = ibx_dump_hw_state,
622 };
623 
624 static void hsw_ddi_wrpll_enable(struct drm_i915_private *dev_priv,
625 				 struct intel_shared_dpll *pll)
626 {
627 	const enum intel_dpll_id id = pll->info->id;
628 
629 	intel_de_write(dev_priv, WRPLL_CTL(id), pll->state.hw_state.wrpll);
630 	intel_de_posting_read(dev_priv, WRPLL_CTL(id));
631 	udelay(20);
632 }
633 
634 static void hsw_ddi_spll_enable(struct drm_i915_private *dev_priv,
635 				struct intel_shared_dpll *pll)
636 {
637 	intel_de_write(dev_priv, SPLL_CTL, pll->state.hw_state.spll);
638 	intel_de_posting_read(dev_priv, SPLL_CTL);
639 	udelay(20);
640 }
641 
642 static void hsw_ddi_wrpll_disable(struct drm_i915_private *dev_priv,
643 				  struct intel_shared_dpll *pll)
644 {
645 	const enum intel_dpll_id id = pll->info->id;
646 
647 	intel_de_rmw(dev_priv, WRPLL_CTL(id), WRPLL_PLL_ENABLE, 0);
648 	intel_de_posting_read(dev_priv, WRPLL_CTL(id));
649 
650 	/*
651 	 * Try to set up the PCH reference clock once all DPLLs
652 	 * that depend on it have been shut down.
653 	 */
654 	if (dev_priv->display.dpll.pch_ssc_use & BIT(id))
655 		intel_init_pch_refclk(dev_priv);
656 }
657 
658 static void hsw_ddi_spll_disable(struct drm_i915_private *dev_priv,
659 				 struct intel_shared_dpll *pll)
660 {
661 	enum intel_dpll_id id = pll->info->id;
662 
663 	intel_de_rmw(dev_priv, SPLL_CTL, SPLL_PLL_ENABLE, 0);
664 	intel_de_posting_read(dev_priv, SPLL_CTL);
665 
666 	/*
667 	 * Try to set up the PCH reference clock once all DPLLs
668 	 * that depend on it have been shut down.
669 	 */
670 	if (dev_priv->display.dpll.pch_ssc_use & BIT(id))
671 		intel_init_pch_refclk(dev_priv);
672 }
673 
674 static bool hsw_ddi_wrpll_get_hw_state(struct drm_i915_private *dev_priv,
675 				       struct intel_shared_dpll *pll,
676 				       struct intel_dpll_hw_state *hw_state)
677 {
678 	const enum intel_dpll_id id = pll->info->id;
679 	intel_wakeref_t wakeref;
680 	u32 val;
681 
682 	wakeref = intel_display_power_get_if_enabled(dev_priv,
683 						     POWER_DOMAIN_DISPLAY_CORE);
684 	if (!wakeref)
685 		return false;
686 
687 	val = intel_de_read(dev_priv, WRPLL_CTL(id));
688 	hw_state->wrpll = val;
689 
690 	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
691 
692 	return val & WRPLL_PLL_ENABLE;
693 }
694 
695 static bool hsw_ddi_spll_get_hw_state(struct drm_i915_private *dev_priv,
696 				      struct intel_shared_dpll *pll,
697 				      struct intel_dpll_hw_state *hw_state)
698 {
699 	intel_wakeref_t wakeref;
700 	u32 val;
701 
702 	wakeref = intel_display_power_get_if_enabled(dev_priv,
703 						     POWER_DOMAIN_DISPLAY_CORE);
704 	if (!wakeref)
705 		return false;
706 
707 	val = intel_de_read(dev_priv, SPLL_CTL);
708 	hw_state->spll = val;
709 
710 	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
711 
712 	return val & SPLL_PLL_ENABLE;
713 }
714 
715 #define LC_FREQ 2700
716 #define LC_FREQ_2K U64_C(LC_FREQ * 2000)
717 
718 #define P_MIN 2
719 #define P_MAX 64
720 #define P_INC 2
721 
722 /* Constraints for PLL good behavior */
723 #define REF_MIN 48
724 #define REF_MAX 400
725 #define VCO_MIN 2400
726 #define VCO_MAX 4800
727 
728 struct hsw_wrpll_rnp {
729 	unsigned p, n2, r2;
730 };
731 
732 static unsigned hsw_wrpll_get_budget_for_freq(int clock)
733 {
734 	switch (clock) {
735 	case 25175000:
736 	case 25200000:
737 	case 27000000:
738 	case 27027000:
739 	case 37762500:
740 	case 37800000:
741 	case 40500000:
742 	case 40541000:
743 	case 54000000:
744 	case 54054000:
745 	case 59341000:
746 	case 59400000:
747 	case 72000000:
748 	case 74176000:
749 	case 74250000:
750 	case 81000000:
751 	case 81081000:
752 	case 89012000:
753 	case 89100000:
754 	case 108000000:
755 	case 108108000:
756 	case 111264000:
757 	case 111375000:
758 	case 148352000:
759 	case 148500000:
760 	case 162000000:
761 	case 162162000:
762 	case 222525000:
763 	case 222750000:
764 	case 296703000:
765 	case 297000000:
766 		return 0;
767 	case 233500000:
768 	case 245250000:
769 	case 247750000:
770 	case 253250000:
771 	case 298000000:
772 		return 1500;
773 	case 169128000:
774 	case 169500000:
775 	case 179500000:
776 	case 202000000:
777 		return 2000;
778 	case 256250000:
779 	case 262500000:
780 	case 270000000:
781 	case 272500000:
782 	case 273750000:
783 	case 280750000:
784 	case 281250000:
785 	case 286000000:
786 	case 291750000:
787 		return 4000;
788 	case 267250000:
789 	case 268500000:
790 		return 5000;
791 	default:
792 		return 1000;
793 	}
794 }
795 
796 static void hsw_wrpll_update_rnp(u64 freq2k, unsigned int budget,
797 				 unsigned int r2, unsigned int n2,
798 				 unsigned int p,
799 				 struct hsw_wrpll_rnp *best)
800 {
801 	u64 a, b, c, d, diff, diff_best;
802 
803 	/* No best (r,n,p) yet */
804 	if (best->p == 0) {
805 		best->p = p;
806 		best->n2 = n2;
807 		best->r2 = r2;
808 		return;
809 	}
810 
811 	/*
812 	 * Output clock is (LC_FREQ_2K / 2000) * N / (P * R), which compares to
813 	 * freq2k.
814 	 *
815 	 * delta = 1e6 *
816 	 *	   abs(freq2k - (LC_FREQ_2K * n2/(p * r2))) /
817 	 *	   freq2k;
818 	 *
819 	 * and we would like delta <= budget.
820 	 *
821 	 * If the discrepancy is above the PPM-based budget, always prefer to
822 	 * improve upon the previous solution.  However, if you're within the
823 	 * budget, try to maximize Ref * VCO, that is N / (P * R^2).
824 	 */
825 	a = freq2k * budget * p * r2;
826 	b = freq2k * budget * best->p * best->r2;
827 	diff = abs_diff(freq2k * p * r2, LC_FREQ_2K * n2);
828 	diff_best = abs_diff(freq2k * best->p * best->r2,
829 			     LC_FREQ_2K * best->n2);
830 	c = 1000000 * diff;
831 	d = 1000000 * diff_best;
832 
833 	if (a < c && b < d) {
834 		/* If both are above the budget, pick the closer */
835 		if (best->p * best->r2 * diff < p * r2 * diff_best) {
836 			best->p = p;
837 			best->n2 = n2;
838 			best->r2 = r2;
839 		}
840 	} else if (a >= c && b < d) {
841 		/* If A is below the threshold but B is above it?  Update. */
842 		best->p = p;
843 		best->n2 = n2;
844 		best->r2 = r2;
845 	} else if (a >= c && b >= d) {
846 		/* Both are below the limit, so pick the higher n2/(r2*r2) */
847 		if (n2 * best->r2 * best->r2 > best->n2 * r2 * r2) {
848 			best->p = p;
849 			best->n2 = n2;
850 			best->r2 = r2;
851 		}
852 	}
853 	/* Otherwise a < c && b >= d, do nothing */
854 }
855 
856 static void
857 hsw_ddi_calculate_wrpll(int clock /* in Hz */,
858 			unsigned *r2_out, unsigned *n2_out, unsigned *p_out)
859 {
860 	u64 freq2k;
861 	unsigned p, n2, r2;
862 	struct hsw_wrpll_rnp best = {};
863 	unsigned budget;
864 
865 	freq2k = clock / 100;
866 
867 	budget = hsw_wrpll_get_budget_for_freq(clock);
868 
869 	/* Special case handling for 540 pixel clock: bypass WR PLL entirely
870 	 * and directly pass the LC PLL to it. */
871 	if (freq2k == 5400000) {
872 		*n2_out = 2;
873 		*p_out = 1;
874 		*r2_out = 2;
875 		return;
876 	}
877 
878 	/*
879 	 * Ref = LC_FREQ / R, where Ref is the actual reference input seen by
880 	 * the WR PLL.
881 	 *
882 	 * We want R so that REF_MIN <= Ref <= REF_MAX.
883 	 * Injecting R2 = 2 * R gives:
884 	 *   REF_MAX * r2 > LC_FREQ * 2 and
885 	 *   REF_MIN * r2 < LC_FREQ * 2
886 	 *
887 	 * Which means the desired boundaries for r2 are:
888 	 *  LC_FREQ * 2 / REF_MAX < r2 < LC_FREQ * 2 / REF_MIN
889 	 *
890 	 */
891 	for (r2 = LC_FREQ * 2 / REF_MAX + 1;
892 	     r2 <= LC_FREQ * 2 / REF_MIN;
893 	     r2++) {
894 
895 		/*
896 		 * VCO = N * Ref, that is: VCO = N * LC_FREQ / R
897 		 *
898 		 * Once again we want VCO_MIN <= VCO <= VCO_MAX.
899 		 * Injecting R2 = 2 * R and N2 = 2 * N, we get:
900 		 *   VCO_MAX * r2 > n2 * LC_FREQ and
901 		 *   VCO_MIN * r2 < n2 * LC_FREQ)
902 		 *
903 		 * Which means the desired boundaries for n2 are:
904 		 * VCO_MIN * r2 / LC_FREQ < n2 < VCO_MAX * r2 / LC_FREQ
905 		 */
906 		for (n2 = VCO_MIN * r2 / LC_FREQ + 1;
907 		     n2 <= VCO_MAX * r2 / LC_FREQ;
908 		     n2++) {
909 
910 			for (p = P_MIN; p <= P_MAX; p += P_INC)
911 				hsw_wrpll_update_rnp(freq2k, budget,
912 						     r2, n2, p, &best);
913 		}
914 	}
915 
916 	*n2_out = best.n2;
917 	*p_out = best.p;
918 	*r2_out = best.r2;
919 }
920 
921 static int hsw_ddi_wrpll_get_freq(struct drm_i915_private *dev_priv,
922 				  const struct intel_shared_dpll *pll,
923 				  const struct intel_dpll_hw_state *pll_state)
924 {
925 	int refclk;
926 	int n, p, r;
927 	u32 wrpll = pll_state->wrpll;
928 
929 	switch (wrpll & WRPLL_REF_MASK) {
930 	case WRPLL_REF_SPECIAL_HSW:
931 		/* Muxed-SSC for BDW, non-SSC for non-ULT HSW. */
932 		if (IS_HASWELL(dev_priv) && !IS_HASWELL_ULT(dev_priv)) {
933 			refclk = dev_priv->display.dpll.ref_clks.nssc;
934 			break;
935 		}
936 		fallthrough;
937 	case WRPLL_REF_PCH_SSC:
938 		/*
939 		 * We could calculate spread here, but our checking
940 		 * code only cares about 5% accuracy, and spread is a max of
941 		 * 0.5% downspread.
942 		 */
943 		refclk = dev_priv->display.dpll.ref_clks.ssc;
944 		break;
945 	case WRPLL_REF_LCPLL:
946 		refclk = 2700000;
947 		break;
948 	default:
949 		MISSING_CASE(wrpll);
950 		return 0;
951 	}
952 
953 	r = wrpll & WRPLL_DIVIDER_REF_MASK;
954 	p = (wrpll & WRPLL_DIVIDER_POST_MASK) >> WRPLL_DIVIDER_POST_SHIFT;
955 	n = (wrpll & WRPLL_DIVIDER_FB_MASK) >> WRPLL_DIVIDER_FB_SHIFT;
956 
957 	/* Convert to KHz, p & r have a fixed point portion */
958 	return (refclk * n / 10) / (p * r) * 2;
959 }
960 
961 static int
962 hsw_ddi_wrpll_compute_dpll(struct intel_atomic_state *state,
963 			   struct intel_crtc *crtc)
964 {
965 	struct drm_i915_private *i915 = to_i915(state->base.dev);
966 	struct intel_crtc_state *crtc_state =
967 		intel_atomic_get_new_crtc_state(state, crtc);
968 	unsigned int p, n2, r2;
969 
970 	hsw_ddi_calculate_wrpll(crtc_state->port_clock * 1000, &r2, &n2, &p);
971 
972 	crtc_state->dpll_hw_state.wrpll =
973 		WRPLL_PLL_ENABLE | WRPLL_REF_LCPLL |
974 		WRPLL_DIVIDER_REFERENCE(r2) | WRPLL_DIVIDER_FEEDBACK(n2) |
975 		WRPLL_DIVIDER_POST(p);
976 
977 	crtc_state->port_clock = hsw_ddi_wrpll_get_freq(i915, NULL,
978 							&crtc_state->dpll_hw_state);
979 
980 	return 0;
981 }
982 
983 static struct intel_shared_dpll *
984 hsw_ddi_wrpll_get_dpll(struct intel_atomic_state *state,
985 		       struct intel_crtc *crtc)
986 {
987 	struct intel_crtc_state *crtc_state =
988 		intel_atomic_get_new_crtc_state(state, crtc);
989 
990 	return intel_find_shared_dpll(state, crtc,
991 				      &crtc_state->dpll_hw_state,
992 				      BIT(DPLL_ID_WRPLL2) |
993 				      BIT(DPLL_ID_WRPLL1));
994 }
995 
996 static int
997 hsw_ddi_lcpll_compute_dpll(struct intel_crtc_state *crtc_state)
998 {
999 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1000 	int clock = crtc_state->port_clock;
1001 
1002 	switch (clock / 2) {
1003 	case 81000:
1004 	case 135000:
1005 	case 270000:
1006 		return 0;
1007 	default:
1008 		drm_dbg_kms(&dev_priv->drm, "Invalid clock for DP: %d\n",
1009 			    clock);
1010 		return -EINVAL;
1011 	}
1012 }
1013 
1014 static struct intel_shared_dpll *
1015 hsw_ddi_lcpll_get_dpll(struct intel_crtc_state *crtc_state)
1016 {
1017 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
1018 	struct intel_shared_dpll *pll;
1019 	enum intel_dpll_id pll_id;
1020 	int clock = crtc_state->port_clock;
1021 
1022 	switch (clock / 2) {
1023 	case 81000:
1024 		pll_id = DPLL_ID_LCPLL_810;
1025 		break;
1026 	case 135000:
1027 		pll_id = DPLL_ID_LCPLL_1350;
1028 		break;
1029 	case 270000:
1030 		pll_id = DPLL_ID_LCPLL_2700;
1031 		break;
1032 	default:
1033 		MISSING_CASE(clock / 2);
1034 		return NULL;
1035 	}
1036 
1037 	pll = intel_get_shared_dpll_by_id(dev_priv, pll_id);
1038 
1039 	if (!pll)
1040 		return NULL;
1041 
1042 	return pll;
1043 }
1044 
1045 static int hsw_ddi_lcpll_get_freq(struct drm_i915_private *i915,
1046 				  const struct intel_shared_dpll *pll,
1047 				  const struct intel_dpll_hw_state *pll_state)
1048 {
1049 	int link_clock = 0;
1050 
1051 	switch (pll->info->id) {
1052 	case DPLL_ID_LCPLL_810:
1053 		link_clock = 81000;
1054 		break;
1055 	case DPLL_ID_LCPLL_1350:
1056 		link_clock = 135000;
1057 		break;
1058 	case DPLL_ID_LCPLL_2700:
1059 		link_clock = 270000;
1060 		break;
1061 	default:
1062 		drm_WARN(&i915->drm, 1, "bad port clock sel\n");
1063 		break;
1064 	}
1065 
1066 	return link_clock * 2;
1067 }
1068 
1069 static int
1070 hsw_ddi_spll_compute_dpll(struct intel_atomic_state *state,
1071 			  struct intel_crtc *crtc)
1072 {
1073 	struct intel_crtc_state *crtc_state =
1074 		intel_atomic_get_new_crtc_state(state, crtc);
1075 
1076 	if (drm_WARN_ON(crtc->base.dev, crtc_state->port_clock / 2 != 135000))
1077 		return -EINVAL;
1078 
1079 	crtc_state->dpll_hw_state.spll =
1080 		SPLL_PLL_ENABLE | SPLL_FREQ_1350MHz | SPLL_REF_MUXED_SSC;
1081 
1082 	return 0;
1083 }
1084 
1085 static struct intel_shared_dpll *
1086 hsw_ddi_spll_get_dpll(struct intel_atomic_state *state,
1087 		      struct intel_crtc *crtc)
1088 {
1089 	struct intel_crtc_state *crtc_state =
1090 		intel_atomic_get_new_crtc_state(state, crtc);
1091 
1092 	return intel_find_shared_dpll(state, crtc, &crtc_state->dpll_hw_state,
1093 				      BIT(DPLL_ID_SPLL));
1094 }
1095 
1096 static int hsw_ddi_spll_get_freq(struct drm_i915_private *i915,
1097 				 const struct intel_shared_dpll *pll,
1098 				 const struct intel_dpll_hw_state *pll_state)
1099 {
1100 	int link_clock = 0;
1101 
1102 	switch (pll_state->spll & SPLL_FREQ_MASK) {
1103 	case SPLL_FREQ_810MHz:
1104 		link_clock = 81000;
1105 		break;
1106 	case SPLL_FREQ_1350MHz:
1107 		link_clock = 135000;
1108 		break;
1109 	case SPLL_FREQ_2700MHz:
1110 		link_clock = 270000;
1111 		break;
1112 	default:
1113 		drm_WARN(&i915->drm, 1, "bad spll freq\n");
1114 		break;
1115 	}
1116 
1117 	return link_clock * 2;
1118 }
1119 
1120 static int hsw_compute_dpll(struct intel_atomic_state *state,
1121 			    struct intel_crtc *crtc,
1122 			    struct intel_encoder *encoder)
1123 {
1124 	struct intel_crtc_state *crtc_state =
1125 		intel_atomic_get_new_crtc_state(state, crtc);
1126 
1127 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1128 		return hsw_ddi_wrpll_compute_dpll(state, crtc);
1129 	else if (intel_crtc_has_dp_encoder(crtc_state))
1130 		return hsw_ddi_lcpll_compute_dpll(crtc_state);
1131 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1132 		return hsw_ddi_spll_compute_dpll(state, crtc);
1133 	else
1134 		return -EINVAL;
1135 }
1136 
1137 static int hsw_get_dpll(struct intel_atomic_state *state,
1138 			struct intel_crtc *crtc,
1139 			struct intel_encoder *encoder)
1140 {
1141 	struct intel_crtc_state *crtc_state =
1142 		intel_atomic_get_new_crtc_state(state, crtc);
1143 	struct intel_shared_dpll *pll = NULL;
1144 
1145 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1146 		pll = hsw_ddi_wrpll_get_dpll(state, crtc);
1147 	else if (intel_crtc_has_dp_encoder(crtc_state))
1148 		pll = hsw_ddi_lcpll_get_dpll(crtc_state);
1149 	else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG))
1150 		pll = hsw_ddi_spll_get_dpll(state, crtc);
1151 
1152 	if (!pll)
1153 		return -EINVAL;
1154 
1155 	intel_reference_shared_dpll(state, crtc,
1156 				    pll, &crtc_state->dpll_hw_state);
1157 
1158 	crtc_state->shared_dpll = pll;
1159 
1160 	return 0;
1161 }
1162 
1163 static void hsw_update_dpll_ref_clks(struct drm_i915_private *i915)
1164 {
1165 	i915->display.dpll.ref_clks.ssc = 135000;
1166 	/* Non-SSC is only used on non-ULT HSW. */
1167 	if (intel_de_read(i915, FUSE_STRAP3) & HSW_REF_CLK_SELECT)
1168 		i915->display.dpll.ref_clks.nssc = 24000;
1169 	else
1170 		i915->display.dpll.ref_clks.nssc = 135000;
1171 }
1172 
1173 static void hsw_dump_hw_state(struct drm_i915_private *dev_priv,
1174 			      const struct intel_dpll_hw_state *hw_state)
1175 {
1176 	drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: wrpll: 0x%x spll: 0x%x\n",
1177 		    hw_state->wrpll, hw_state->spll);
1178 }
1179 
1180 static const struct intel_shared_dpll_funcs hsw_ddi_wrpll_funcs = {
1181 	.enable = hsw_ddi_wrpll_enable,
1182 	.disable = hsw_ddi_wrpll_disable,
1183 	.get_hw_state = hsw_ddi_wrpll_get_hw_state,
1184 	.get_freq = hsw_ddi_wrpll_get_freq,
1185 };
1186 
1187 static const struct intel_shared_dpll_funcs hsw_ddi_spll_funcs = {
1188 	.enable = hsw_ddi_spll_enable,
1189 	.disable = hsw_ddi_spll_disable,
1190 	.get_hw_state = hsw_ddi_spll_get_hw_state,
1191 	.get_freq = hsw_ddi_spll_get_freq,
1192 };
1193 
1194 static void hsw_ddi_lcpll_enable(struct drm_i915_private *dev_priv,
1195 				 struct intel_shared_dpll *pll)
1196 {
1197 }
1198 
1199 static void hsw_ddi_lcpll_disable(struct drm_i915_private *dev_priv,
1200 				  struct intel_shared_dpll *pll)
1201 {
1202 }
1203 
1204 static bool hsw_ddi_lcpll_get_hw_state(struct drm_i915_private *dev_priv,
1205 				       struct intel_shared_dpll *pll,
1206 				       struct intel_dpll_hw_state *hw_state)
1207 {
1208 	return true;
1209 }
1210 
1211 static const struct intel_shared_dpll_funcs hsw_ddi_lcpll_funcs = {
1212 	.enable = hsw_ddi_lcpll_enable,
1213 	.disable = hsw_ddi_lcpll_disable,
1214 	.get_hw_state = hsw_ddi_lcpll_get_hw_state,
1215 	.get_freq = hsw_ddi_lcpll_get_freq,
1216 };
1217 
1218 static const struct dpll_info hsw_plls[] = {
1219 	{ "WRPLL 1",    &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL1,     0 },
1220 	{ "WRPLL 2",    &hsw_ddi_wrpll_funcs, DPLL_ID_WRPLL2,     0 },
1221 	{ "SPLL",       &hsw_ddi_spll_funcs,  DPLL_ID_SPLL,       0 },
1222 	{ "LCPLL 810",  &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_810,  INTEL_DPLL_ALWAYS_ON },
1223 	{ "LCPLL 1350", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_1350, INTEL_DPLL_ALWAYS_ON },
1224 	{ "LCPLL 2700", &hsw_ddi_lcpll_funcs, DPLL_ID_LCPLL_2700, INTEL_DPLL_ALWAYS_ON },
1225 	{ },
1226 };
1227 
1228 static const struct intel_dpll_mgr hsw_pll_mgr = {
1229 	.dpll_info = hsw_plls,
1230 	.compute_dplls = hsw_compute_dpll,
1231 	.get_dplls = hsw_get_dpll,
1232 	.put_dplls = intel_put_dpll,
1233 	.update_ref_clks = hsw_update_dpll_ref_clks,
1234 	.dump_hw_state = hsw_dump_hw_state,
1235 };
1236 
1237 struct skl_dpll_regs {
1238 	i915_reg_t ctl, cfgcr1, cfgcr2;
1239 };
1240 
1241 /* this array is indexed by the *shared* pll id */
1242 static const struct skl_dpll_regs skl_dpll_regs[4] = {
1243 	{
1244 		/* DPLL 0 */
1245 		.ctl = LCPLL1_CTL,
1246 		/* DPLL 0 doesn't support HDMI mode */
1247 	},
1248 	{
1249 		/* DPLL 1 */
1250 		.ctl = LCPLL2_CTL,
1251 		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL1),
1252 		.cfgcr2 = DPLL_CFGCR2(SKL_DPLL1),
1253 	},
1254 	{
1255 		/* DPLL 2 */
1256 		.ctl = WRPLL_CTL(0),
1257 		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL2),
1258 		.cfgcr2 = DPLL_CFGCR2(SKL_DPLL2),
1259 	},
1260 	{
1261 		/* DPLL 3 */
1262 		.ctl = WRPLL_CTL(1),
1263 		.cfgcr1 = DPLL_CFGCR1(SKL_DPLL3),
1264 		.cfgcr2 = DPLL_CFGCR2(SKL_DPLL3),
1265 	},
1266 };
1267 
1268 static void skl_ddi_pll_write_ctrl1(struct drm_i915_private *dev_priv,
1269 				    struct intel_shared_dpll *pll)
1270 {
1271 	const enum intel_dpll_id id = pll->info->id;
1272 
1273 	intel_de_rmw(dev_priv, DPLL_CTRL1,
1274 		     DPLL_CTRL1_HDMI_MODE(id) | DPLL_CTRL1_SSC(id) | DPLL_CTRL1_LINK_RATE_MASK(id),
1275 		     pll->state.hw_state.ctrl1 << (id * 6));
1276 	intel_de_posting_read(dev_priv, DPLL_CTRL1);
1277 }
1278 
1279 static void skl_ddi_pll_enable(struct drm_i915_private *dev_priv,
1280 			       struct intel_shared_dpll *pll)
1281 {
1282 	const struct skl_dpll_regs *regs = skl_dpll_regs;
1283 	const enum intel_dpll_id id = pll->info->id;
1284 
1285 	skl_ddi_pll_write_ctrl1(dev_priv, pll);
1286 
1287 	intel_de_write(dev_priv, regs[id].cfgcr1, pll->state.hw_state.cfgcr1);
1288 	intel_de_write(dev_priv, regs[id].cfgcr2, pll->state.hw_state.cfgcr2);
1289 	intel_de_posting_read(dev_priv, regs[id].cfgcr1);
1290 	intel_de_posting_read(dev_priv, regs[id].cfgcr2);
1291 
1292 	/* the enable bit is always bit 31 */
1293 	intel_de_rmw(dev_priv, regs[id].ctl, 0, LCPLL_PLL_ENABLE);
1294 
1295 	if (intel_de_wait_for_set(dev_priv, DPLL_STATUS, DPLL_LOCK(id), 5))
1296 		drm_err(&dev_priv->drm, "DPLL %d not locked\n", id);
1297 }
1298 
1299 static void skl_ddi_dpll0_enable(struct drm_i915_private *dev_priv,
1300 				 struct intel_shared_dpll *pll)
1301 {
1302 	skl_ddi_pll_write_ctrl1(dev_priv, pll);
1303 }
1304 
1305 static void skl_ddi_pll_disable(struct drm_i915_private *dev_priv,
1306 				struct intel_shared_dpll *pll)
1307 {
1308 	const struct skl_dpll_regs *regs = skl_dpll_regs;
1309 	const enum intel_dpll_id id = pll->info->id;
1310 
1311 	/* the enable bit is always bit 31 */
1312 	intel_de_rmw(dev_priv, regs[id].ctl, LCPLL_PLL_ENABLE, 0);
1313 	intel_de_posting_read(dev_priv, regs[id].ctl);
1314 }
1315 
1316 static void skl_ddi_dpll0_disable(struct drm_i915_private *dev_priv,
1317 				  struct intel_shared_dpll *pll)
1318 {
1319 }
1320 
1321 static bool skl_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
1322 				     struct intel_shared_dpll *pll,
1323 				     struct intel_dpll_hw_state *hw_state)
1324 {
1325 	u32 val;
1326 	const struct skl_dpll_regs *regs = skl_dpll_regs;
1327 	const enum intel_dpll_id id = pll->info->id;
1328 	intel_wakeref_t wakeref;
1329 	bool ret;
1330 
1331 	wakeref = intel_display_power_get_if_enabled(dev_priv,
1332 						     POWER_DOMAIN_DISPLAY_CORE);
1333 	if (!wakeref)
1334 		return false;
1335 
1336 	ret = false;
1337 
1338 	val = intel_de_read(dev_priv, regs[id].ctl);
1339 	if (!(val & LCPLL_PLL_ENABLE))
1340 		goto out;
1341 
1342 	val = intel_de_read(dev_priv, DPLL_CTRL1);
1343 	hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1344 
1345 	/* avoid reading back stale values if HDMI mode is not enabled */
1346 	if (val & DPLL_CTRL1_HDMI_MODE(id)) {
1347 		hw_state->cfgcr1 = intel_de_read(dev_priv, regs[id].cfgcr1);
1348 		hw_state->cfgcr2 = intel_de_read(dev_priv, regs[id].cfgcr2);
1349 	}
1350 	ret = true;
1351 
1352 out:
1353 	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
1354 
1355 	return ret;
1356 }
1357 
1358 static bool skl_ddi_dpll0_get_hw_state(struct drm_i915_private *dev_priv,
1359 				       struct intel_shared_dpll *pll,
1360 				       struct intel_dpll_hw_state *hw_state)
1361 {
1362 	const struct skl_dpll_regs *regs = skl_dpll_regs;
1363 	const enum intel_dpll_id id = pll->info->id;
1364 	intel_wakeref_t wakeref;
1365 	u32 val;
1366 	bool ret;
1367 
1368 	wakeref = intel_display_power_get_if_enabled(dev_priv,
1369 						     POWER_DOMAIN_DISPLAY_CORE);
1370 	if (!wakeref)
1371 		return false;
1372 
1373 	ret = false;
1374 
1375 	/* DPLL0 is always enabled since it drives CDCLK */
1376 	val = intel_de_read(dev_priv, regs[id].ctl);
1377 	if (drm_WARN_ON(&dev_priv->drm, !(val & LCPLL_PLL_ENABLE)))
1378 		goto out;
1379 
1380 	val = intel_de_read(dev_priv, DPLL_CTRL1);
1381 	hw_state->ctrl1 = (val >> (id * 6)) & 0x3f;
1382 
1383 	ret = true;
1384 
1385 out:
1386 	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
1387 
1388 	return ret;
1389 }
1390 
1391 struct skl_wrpll_context {
1392 	u64 min_deviation;		/* current minimal deviation */
1393 	u64 central_freq;		/* chosen central freq */
1394 	u64 dco_freq;			/* chosen dco freq */
1395 	unsigned int p;			/* chosen divider */
1396 };
1397 
1398 /* DCO freq must be within +1%/-6%  of the DCO central freq */
1399 #define SKL_DCO_MAX_PDEVIATION	100
1400 #define SKL_DCO_MAX_NDEVIATION	600
1401 
1402 static void skl_wrpll_try_divider(struct skl_wrpll_context *ctx,
1403 				  u64 central_freq,
1404 				  u64 dco_freq,
1405 				  unsigned int divider)
1406 {
1407 	u64 deviation;
1408 
1409 	deviation = div64_u64(10000 * abs_diff(dco_freq, central_freq),
1410 			      central_freq);
1411 
1412 	/* positive deviation */
1413 	if (dco_freq >= central_freq) {
1414 		if (deviation < SKL_DCO_MAX_PDEVIATION &&
1415 		    deviation < ctx->min_deviation) {
1416 			ctx->min_deviation = deviation;
1417 			ctx->central_freq = central_freq;
1418 			ctx->dco_freq = dco_freq;
1419 			ctx->p = divider;
1420 		}
1421 	/* negative deviation */
1422 	} else if (deviation < SKL_DCO_MAX_NDEVIATION &&
1423 		   deviation < ctx->min_deviation) {
1424 		ctx->min_deviation = deviation;
1425 		ctx->central_freq = central_freq;
1426 		ctx->dco_freq = dco_freq;
1427 		ctx->p = divider;
1428 	}
1429 }
1430 
1431 static void skl_wrpll_get_multipliers(unsigned int p,
1432 				      unsigned int *p0 /* out */,
1433 				      unsigned int *p1 /* out */,
1434 				      unsigned int *p2 /* out */)
1435 {
1436 	/* even dividers */
1437 	if (p % 2 == 0) {
1438 		unsigned int half = p / 2;
1439 
1440 		if (half == 1 || half == 2 || half == 3 || half == 5) {
1441 			*p0 = 2;
1442 			*p1 = 1;
1443 			*p2 = half;
1444 		} else if (half % 2 == 0) {
1445 			*p0 = 2;
1446 			*p1 = half / 2;
1447 			*p2 = 2;
1448 		} else if (half % 3 == 0) {
1449 			*p0 = 3;
1450 			*p1 = half / 3;
1451 			*p2 = 2;
1452 		} else if (half % 7 == 0) {
1453 			*p0 = 7;
1454 			*p1 = half / 7;
1455 			*p2 = 2;
1456 		}
1457 	} else if (p == 3 || p == 9) {  /* 3, 5, 7, 9, 15, 21, 35 */
1458 		*p0 = 3;
1459 		*p1 = 1;
1460 		*p2 = p / 3;
1461 	} else if (p == 5 || p == 7) {
1462 		*p0 = p;
1463 		*p1 = 1;
1464 		*p2 = 1;
1465 	} else if (p == 15) {
1466 		*p0 = 3;
1467 		*p1 = 1;
1468 		*p2 = 5;
1469 	} else if (p == 21) {
1470 		*p0 = 7;
1471 		*p1 = 1;
1472 		*p2 = 3;
1473 	} else if (p == 35) {
1474 		*p0 = 7;
1475 		*p1 = 1;
1476 		*p2 = 5;
1477 	}
1478 }
1479 
1480 struct skl_wrpll_params {
1481 	u32 dco_fraction;
1482 	u32 dco_integer;
1483 	u32 qdiv_ratio;
1484 	u32 qdiv_mode;
1485 	u32 kdiv;
1486 	u32 pdiv;
1487 	u32 central_freq;
1488 };
1489 
1490 static void skl_wrpll_params_populate(struct skl_wrpll_params *params,
1491 				      u64 afe_clock,
1492 				      int ref_clock,
1493 				      u64 central_freq,
1494 				      u32 p0, u32 p1, u32 p2)
1495 {
1496 	u64 dco_freq;
1497 
1498 	switch (central_freq) {
1499 	case 9600000000ULL:
1500 		params->central_freq = 0;
1501 		break;
1502 	case 9000000000ULL:
1503 		params->central_freq = 1;
1504 		break;
1505 	case 8400000000ULL:
1506 		params->central_freq = 3;
1507 	}
1508 
1509 	switch (p0) {
1510 	case 1:
1511 		params->pdiv = 0;
1512 		break;
1513 	case 2:
1514 		params->pdiv = 1;
1515 		break;
1516 	case 3:
1517 		params->pdiv = 2;
1518 		break;
1519 	case 7:
1520 		params->pdiv = 4;
1521 		break;
1522 	default:
1523 		WARN(1, "Incorrect PDiv\n");
1524 	}
1525 
1526 	switch (p2) {
1527 	case 5:
1528 		params->kdiv = 0;
1529 		break;
1530 	case 2:
1531 		params->kdiv = 1;
1532 		break;
1533 	case 3:
1534 		params->kdiv = 2;
1535 		break;
1536 	case 1:
1537 		params->kdiv = 3;
1538 		break;
1539 	default:
1540 		WARN(1, "Incorrect KDiv\n");
1541 	}
1542 
1543 	params->qdiv_ratio = p1;
1544 	params->qdiv_mode = (params->qdiv_ratio == 1) ? 0 : 1;
1545 
1546 	dco_freq = p0 * p1 * p2 * afe_clock;
1547 
1548 	/*
1549 	 * Intermediate values are in Hz.
1550 	 * Divide by MHz to match bsepc
1551 	 */
1552 	params->dco_integer = div_u64(dco_freq, ref_clock * KHz(1));
1553 	params->dco_fraction =
1554 		div_u64((div_u64(dco_freq, ref_clock / KHz(1)) -
1555 			 params->dco_integer * MHz(1)) * 0x8000, MHz(1));
1556 }
1557 
1558 static int
1559 skl_ddi_calculate_wrpll(int clock /* in Hz */,
1560 			int ref_clock,
1561 			struct skl_wrpll_params *wrpll_params)
1562 {
1563 	static const u64 dco_central_freq[3] = { 8400000000ULL,
1564 						 9000000000ULL,
1565 						 9600000000ULL };
1566 	static const u8 even_dividers[] = {  4,  6,  8, 10, 12, 14, 16, 18, 20,
1567 					    24, 28, 30, 32, 36, 40, 42, 44,
1568 					    48, 52, 54, 56, 60, 64, 66, 68,
1569 					    70, 72, 76, 78, 80, 84, 88, 90,
1570 					    92, 96, 98 };
1571 	static const u8 odd_dividers[] = { 3, 5, 7, 9, 15, 21, 35 };
1572 	static const struct {
1573 		const u8 *list;
1574 		int n_dividers;
1575 	} dividers[] = {
1576 		{ even_dividers, ARRAY_SIZE(even_dividers) },
1577 		{ odd_dividers, ARRAY_SIZE(odd_dividers) },
1578 	};
1579 	struct skl_wrpll_context ctx = {
1580 		.min_deviation = U64_MAX,
1581 	};
1582 	unsigned int dco, d, i;
1583 	unsigned int p0, p1, p2;
1584 	u64 afe_clock = clock * 5; /* AFE Clock is 5x Pixel clock */
1585 
1586 	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
1587 		for (dco = 0; dco < ARRAY_SIZE(dco_central_freq); dco++) {
1588 			for (i = 0; i < dividers[d].n_dividers; i++) {
1589 				unsigned int p = dividers[d].list[i];
1590 				u64 dco_freq = p * afe_clock;
1591 
1592 				skl_wrpll_try_divider(&ctx,
1593 						      dco_central_freq[dco],
1594 						      dco_freq,
1595 						      p);
1596 				/*
1597 				 * Skip the remaining dividers if we're sure to
1598 				 * have found the definitive divider, we can't
1599 				 * improve a 0 deviation.
1600 				 */
1601 				if (ctx.min_deviation == 0)
1602 					goto skip_remaining_dividers;
1603 			}
1604 		}
1605 
1606 skip_remaining_dividers:
1607 		/*
1608 		 * If a solution is found with an even divider, prefer
1609 		 * this one.
1610 		 */
1611 		if (d == 0 && ctx.p)
1612 			break;
1613 	}
1614 
1615 	if (!ctx.p)
1616 		return -EINVAL;
1617 
1618 	/*
1619 	 * gcc incorrectly analyses that these can be used without being
1620 	 * initialized. To be fair, it's hard to guess.
1621 	 */
1622 	p0 = p1 = p2 = 0;
1623 	skl_wrpll_get_multipliers(ctx.p, &p0, &p1, &p2);
1624 	skl_wrpll_params_populate(wrpll_params, afe_clock, ref_clock,
1625 				  ctx.central_freq, p0, p1, p2);
1626 
1627 	return 0;
1628 }
1629 
1630 static int skl_ddi_wrpll_get_freq(struct drm_i915_private *i915,
1631 				  const struct intel_shared_dpll *pll,
1632 				  const struct intel_dpll_hw_state *pll_state)
1633 {
1634 	int ref_clock = i915->display.dpll.ref_clks.nssc;
1635 	u32 p0, p1, p2, dco_freq;
1636 
1637 	p0 = pll_state->cfgcr2 & DPLL_CFGCR2_PDIV_MASK;
1638 	p2 = pll_state->cfgcr2 & DPLL_CFGCR2_KDIV_MASK;
1639 
1640 	if (pll_state->cfgcr2 &  DPLL_CFGCR2_QDIV_MODE(1))
1641 		p1 = (pll_state->cfgcr2 & DPLL_CFGCR2_QDIV_RATIO_MASK) >> 8;
1642 	else
1643 		p1 = 1;
1644 
1645 
1646 	switch (p0) {
1647 	case DPLL_CFGCR2_PDIV_1:
1648 		p0 = 1;
1649 		break;
1650 	case DPLL_CFGCR2_PDIV_2:
1651 		p0 = 2;
1652 		break;
1653 	case DPLL_CFGCR2_PDIV_3:
1654 		p0 = 3;
1655 		break;
1656 	case DPLL_CFGCR2_PDIV_7_INVALID:
1657 		/*
1658 		 * Incorrect ASUS-Z170M BIOS setting, the HW seems to ignore bit#0,
1659 		 * handling it the same way as PDIV_7.
1660 		 */
1661 		drm_dbg_kms(&i915->drm, "Invalid WRPLL PDIV divider value, fixing it.\n");
1662 		fallthrough;
1663 	case DPLL_CFGCR2_PDIV_7:
1664 		p0 = 7;
1665 		break;
1666 	default:
1667 		MISSING_CASE(p0);
1668 		return 0;
1669 	}
1670 
1671 	switch (p2) {
1672 	case DPLL_CFGCR2_KDIV_5:
1673 		p2 = 5;
1674 		break;
1675 	case DPLL_CFGCR2_KDIV_2:
1676 		p2 = 2;
1677 		break;
1678 	case DPLL_CFGCR2_KDIV_3:
1679 		p2 = 3;
1680 		break;
1681 	case DPLL_CFGCR2_KDIV_1:
1682 		p2 = 1;
1683 		break;
1684 	default:
1685 		MISSING_CASE(p2);
1686 		return 0;
1687 	}
1688 
1689 	dco_freq = (pll_state->cfgcr1 & DPLL_CFGCR1_DCO_INTEGER_MASK) *
1690 		   ref_clock;
1691 
1692 	dco_freq += ((pll_state->cfgcr1 & DPLL_CFGCR1_DCO_FRACTION_MASK) >> 9) *
1693 		    ref_clock / 0x8000;
1694 
1695 	if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
1696 		return 0;
1697 
1698 	return dco_freq / (p0 * p1 * p2 * 5);
1699 }
1700 
1701 static int skl_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state)
1702 {
1703 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
1704 	struct skl_wrpll_params wrpll_params = {};
1705 	u32 ctrl1, cfgcr1, cfgcr2;
1706 	int ret;
1707 
1708 	/*
1709 	 * See comment in intel_dpll_hw_state to understand why we always use 0
1710 	 * as the DPLL id in this function.
1711 	 */
1712 	ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1713 
1714 	ctrl1 |= DPLL_CTRL1_HDMI_MODE(0);
1715 
1716 	ret = skl_ddi_calculate_wrpll(crtc_state->port_clock * 1000,
1717 				      i915->display.dpll.ref_clks.nssc, &wrpll_params);
1718 	if (ret)
1719 		return ret;
1720 
1721 	cfgcr1 = DPLL_CFGCR1_FREQ_ENABLE |
1722 		DPLL_CFGCR1_DCO_FRACTION(wrpll_params.dco_fraction) |
1723 		wrpll_params.dco_integer;
1724 
1725 	cfgcr2 = DPLL_CFGCR2_QDIV_RATIO(wrpll_params.qdiv_ratio) |
1726 		DPLL_CFGCR2_QDIV_MODE(wrpll_params.qdiv_mode) |
1727 		DPLL_CFGCR2_KDIV(wrpll_params.kdiv) |
1728 		DPLL_CFGCR2_PDIV(wrpll_params.pdiv) |
1729 		wrpll_params.central_freq;
1730 
1731 	crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1732 	crtc_state->dpll_hw_state.cfgcr1 = cfgcr1;
1733 	crtc_state->dpll_hw_state.cfgcr2 = cfgcr2;
1734 
1735 	crtc_state->port_clock = skl_ddi_wrpll_get_freq(i915, NULL,
1736 							&crtc_state->dpll_hw_state);
1737 
1738 	return 0;
1739 }
1740 
1741 static int
1742 skl_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
1743 {
1744 	u32 ctrl1;
1745 
1746 	/*
1747 	 * See comment in intel_dpll_hw_state to understand why we always use 0
1748 	 * as the DPLL id in this function.
1749 	 */
1750 	ctrl1 = DPLL_CTRL1_OVERRIDE(0);
1751 	switch (crtc_state->port_clock / 2) {
1752 	case 81000:
1753 		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_810, 0);
1754 		break;
1755 	case 135000:
1756 		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1350, 0);
1757 		break;
1758 	case 270000:
1759 		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2700, 0);
1760 		break;
1761 		/* eDP 1.4 rates */
1762 	case 162000:
1763 		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1620, 0);
1764 		break;
1765 	case 108000:
1766 		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_1080, 0);
1767 		break;
1768 	case 216000:
1769 		ctrl1 |= DPLL_CTRL1_LINK_RATE(DPLL_CTRL1_LINK_RATE_2160, 0);
1770 		break;
1771 	}
1772 
1773 	crtc_state->dpll_hw_state.ctrl1 = ctrl1;
1774 
1775 	return 0;
1776 }
1777 
1778 static int skl_ddi_lcpll_get_freq(struct drm_i915_private *i915,
1779 				  const struct intel_shared_dpll *pll,
1780 				  const struct intel_dpll_hw_state *pll_state)
1781 {
1782 	int link_clock = 0;
1783 
1784 	switch ((pll_state->ctrl1 & DPLL_CTRL1_LINK_RATE_MASK(0)) >>
1785 		DPLL_CTRL1_LINK_RATE_SHIFT(0)) {
1786 	case DPLL_CTRL1_LINK_RATE_810:
1787 		link_clock = 81000;
1788 		break;
1789 	case DPLL_CTRL1_LINK_RATE_1080:
1790 		link_clock = 108000;
1791 		break;
1792 	case DPLL_CTRL1_LINK_RATE_1350:
1793 		link_clock = 135000;
1794 		break;
1795 	case DPLL_CTRL1_LINK_RATE_1620:
1796 		link_clock = 162000;
1797 		break;
1798 	case DPLL_CTRL1_LINK_RATE_2160:
1799 		link_clock = 216000;
1800 		break;
1801 	case DPLL_CTRL1_LINK_RATE_2700:
1802 		link_clock = 270000;
1803 		break;
1804 	default:
1805 		drm_WARN(&i915->drm, 1, "Unsupported link rate\n");
1806 		break;
1807 	}
1808 
1809 	return link_clock * 2;
1810 }
1811 
1812 static int skl_compute_dpll(struct intel_atomic_state *state,
1813 			    struct intel_crtc *crtc,
1814 			    struct intel_encoder *encoder)
1815 {
1816 	struct intel_crtc_state *crtc_state =
1817 		intel_atomic_get_new_crtc_state(state, crtc);
1818 
1819 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
1820 		return skl_ddi_hdmi_pll_dividers(crtc_state);
1821 	else if (intel_crtc_has_dp_encoder(crtc_state))
1822 		return skl_ddi_dp_set_dpll_hw_state(crtc_state);
1823 	else
1824 		return -EINVAL;
1825 }
1826 
1827 static int skl_get_dpll(struct intel_atomic_state *state,
1828 			struct intel_crtc *crtc,
1829 			struct intel_encoder *encoder)
1830 {
1831 	struct intel_crtc_state *crtc_state =
1832 		intel_atomic_get_new_crtc_state(state, crtc);
1833 	struct intel_shared_dpll *pll;
1834 
1835 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_EDP))
1836 		pll = intel_find_shared_dpll(state, crtc,
1837 					     &crtc_state->dpll_hw_state,
1838 					     BIT(DPLL_ID_SKL_DPLL0));
1839 	else
1840 		pll = intel_find_shared_dpll(state, crtc,
1841 					     &crtc_state->dpll_hw_state,
1842 					     BIT(DPLL_ID_SKL_DPLL3) |
1843 					     BIT(DPLL_ID_SKL_DPLL2) |
1844 					     BIT(DPLL_ID_SKL_DPLL1));
1845 	if (!pll)
1846 		return -EINVAL;
1847 
1848 	intel_reference_shared_dpll(state, crtc,
1849 				    pll, &crtc_state->dpll_hw_state);
1850 
1851 	crtc_state->shared_dpll = pll;
1852 
1853 	return 0;
1854 }
1855 
1856 static int skl_ddi_pll_get_freq(struct drm_i915_private *i915,
1857 				const struct intel_shared_dpll *pll,
1858 				const struct intel_dpll_hw_state *pll_state)
1859 {
1860 	/*
1861 	 * ctrl1 register is already shifted for each pll, just use 0 to get
1862 	 * the internal shift for each field
1863 	 */
1864 	if (pll_state->ctrl1 & DPLL_CTRL1_HDMI_MODE(0))
1865 		return skl_ddi_wrpll_get_freq(i915, pll, pll_state);
1866 	else
1867 		return skl_ddi_lcpll_get_freq(i915, pll, pll_state);
1868 }
1869 
1870 static void skl_update_dpll_ref_clks(struct drm_i915_private *i915)
1871 {
1872 	/* No SSC ref */
1873 	i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
1874 }
1875 
1876 static void skl_dump_hw_state(struct drm_i915_private *dev_priv,
1877 			      const struct intel_dpll_hw_state *hw_state)
1878 {
1879 	drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: "
1880 		      "ctrl1: 0x%x, cfgcr1: 0x%x, cfgcr2: 0x%x\n",
1881 		      hw_state->ctrl1,
1882 		      hw_state->cfgcr1,
1883 		      hw_state->cfgcr2);
1884 }
1885 
1886 static const struct intel_shared_dpll_funcs skl_ddi_pll_funcs = {
1887 	.enable = skl_ddi_pll_enable,
1888 	.disable = skl_ddi_pll_disable,
1889 	.get_hw_state = skl_ddi_pll_get_hw_state,
1890 	.get_freq = skl_ddi_pll_get_freq,
1891 };
1892 
1893 static const struct intel_shared_dpll_funcs skl_ddi_dpll0_funcs = {
1894 	.enable = skl_ddi_dpll0_enable,
1895 	.disable = skl_ddi_dpll0_disable,
1896 	.get_hw_state = skl_ddi_dpll0_get_hw_state,
1897 	.get_freq = skl_ddi_pll_get_freq,
1898 };
1899 
1900 static const struct dpll_info skl_plls[] = {
1901 	{ "DPLL 0", &skl_ddi_dpll0_funcs, DPLL_ID_SKL_DPLL0, INTEL_DPLL_ALWAYS_ON },
1902 	{ "DPLL 1", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL1, 0 },
1903 	{ "DPLL 2", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL2, 0 },
1904 	{ "DPLL 3", &skl_ddi_pll_funcs,   DPLL_ID_SKL_DPLL3, 0 },
1905 	{ },
1906 };
1907 
1908 static const struct intel_dpll_mgr skl_pll_mgr = {
1909 	.dpll_info = skl_plls,
1910 	.compute_dplls = skl_compute_dpll,
1911 	.get_dplls = skl_get_dpll,
1912 	.put_dplls = intel_put_dpll,
1913 	.update_ref_clks = skl_update_dpll_ref_clks,
1914 	.dump_hw_state = skl_dump_hw_state,
1915 };
1916 
1917 static void bxt_ddi_pll_enable(struct drm_i915_private *dev_priv,
1918 				struct intel_shared_dpll *pll)
1919 {
1920 	u32 temp;
1921 	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
1922 	enum dpio_phy phy;
1923 	enum dpio_channel ch;
1924 
1925 	bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
1926 
1927 	/* Non-SSC reference */
1928 	intel_de_rmw(dev_priv, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_REF_SEL);
1929 
1930 	if (IS_GEMINILAKE(dev_priv)) {
1931 		intel_de_rmw(dev_priv, BXT_PORT_PLL_ENABLE(port),
1932 			     0, PORT_PLL_POWER_ENABLE);
1933 
1934 		if (wait_for_us((intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) &
1935 				 PORT_PLL_POWER_STATE), 200))
1936 			drm_err(&dev_priv->drm,
1937 				"Power state not set for PLL:%d\n", port);
1938 	}
1939 
1940 	/* Disable 10 bit clock */
1941 	intel_de_rmw(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch),
1942 		     PORT_PLL_10BIT_CLK_ENABLE, 0);
1943 
1944 	/* Write P1 & P2 */
1945 	intel_de_rmw(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch),
1946 		     PORT_PLL_P1_MASK | PORT_PLL_P2_MASK, pll->state.hw_state.ebb0);
1947 
1948 	/* Write M2 integer */
1949 	intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 0),
1950 		     PORT_PLL_M2_INT_MASK, pll->state.hw_state.pll0);
1951 
1952 	/* Write N */
1953 	intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 1),
1954 		     PORT_PLL_N_MASK, pll->state.hw_state.pll1);
1955 
1956 	/* Write M2 fraction */
1957 	intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 2),
1958 		     PORT_PLL_M2_FRAC_MASK, pll->state.hw_state.pll2);
1959 
1960 	/* Write M2 fraction enable */
1961 	intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 3),
1962 		     PORT_PLL_M2_FRAC_ENABLE, pll->state.hw_state.pll3);
1963 
1964 	/* Write coeff */
1965 	temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 6));
1966 	temp &= ~PORT_PLL_PROP_COEFF_MASK;
1967 	temp &= ~PORT_PLL_INT_COEFF_MASK;
1968 	temp &= ~PORT_PLL_GAIN_CTL_MASK;
1969 	temp |= pll->state.hw_state.pll6;
1970 	intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 6), temp);
1971 
1972 	/* Write calibration val */
1973 	intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 8),
1974 		     PORT_PLL_TARGET_CNT_MASK, pll->state.hw_state.pll8);
1975 
1976 	intel_de_rmw(dev_priv, BXT_PORT_PLL(phy, ch, 9),
1977 		     PORT_PLL_LOCK_THRESHOLD_MASK, pll->state.hw_state.pll9);
1978 
1979 	temp = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 10));
1980 	temp &= ~PORT_PLL_DCO_AMP_OVR_EN_H;
1981 	temp &= ~PORT_PLL_DCO_AMP_MASK;
1982 	temp |= pll->state.hw_state.pll10;
1983 	intel_de_write(dev_priv, BXT_PORT_PLL(phy, ch, 10), temp);
1984 
1985 	/* Recalibrate with new settings */
1986 	temp = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch));
1987 	temp |= PORT_PLL_RECALIBRATE;
1988 	intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), temp);
1989 	temp &= ~PORT_PLL_10BIT_CLK_ENABLE;
1990 	temp |= pll->state.hw_state.ebb4;
1991 	intel_de_write(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch), temp);
1992 
1993 	/* Enable PLL */
1994 	intel_de_rmw(dev_priv, BXT_PORT_PLL_ENABLE(port), 0, PORT_PLL_ENABLE);
1995 	intel_de_posting_read(dev_priv, BXT_PORT_PLL_ENABLE(port));
1996 
1997 	if (wait_for_us((intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) & PORT_PLL_LOCK),
1998 			200))
1999 		drm_err(&dev_priv->drm, "PLL %d not locked\n", port);
2000 
2001 	if (IS_GEMINILAKE(dev_priv)) {
2002 		temp = intel_de_read(dev_priv, BXT_PORT_TX_DW5_LN0(phy, ch));
2003 		temp |= DCC_DELAY_RANGE_2;
2004 		intel_de_write(dev_priv, BXT_PORT_TX_DW5_GRP(phy, ch), temp);
2005 	}
2006 
2007 	/*
2008 	 * While we write to the group register to program all lanes at once we
2009 	 * can read only lane registers and we pick lanes 0/1 for that.
2010 	 */
2011 	temp = intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN01(phy, ch));
2012 	temp &= ~LANE_STAGGER_MASK;
2013 	temp &= ~LANESTAGGER_STRAP_OVRD;
2014 	temp |= pll->state.hw_state.pcsdw12;
2015 	intel_de_write(dev_priv, BXT_PORT_PCS_DW12_GRP(phy, ch), temp);
2016 }
2017 
2018 static void bxt_ddi_pll_disable(struct drm_i915_private *dev_priv,
2019 					struct intel_shared_dpll *pll)
2020 {
2021 	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
2022 
2023 	intel_de_rmw(dev_priv, BXT_PORT_PLL_ENABLE(port), PORT_PLL_ENABLE, 0);
2024 	intel_de_posting_read(dev_priv, BXT_PORT_PLL_ENABLE(port));
2025 
2026 	if (IS_GEMINILAKE(dev_priv)) {
2027 		intel_de_rmw(dev_priv, BXT_PORT_PLL_ENABLE(port),
2028 			     PORT_PLL_POWER_ENABLE, 0);
2029 
2030 		if (wait_for_us(!(intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port)) &
2031 				  PORT_PLL_POWER_STATE), 200))
2032 			drm_err(&dev_priv->drm,
2033 				"Power state not reset for PLL:%d\n", port);
2034 	}
2035 }
2036 
2037 static bool bxt_ddi_pll_get_hw_state(struct drm_i915_private *dev_priv,
2038 					struct intel_shared_dpll *pll,
2039 					struct intel_dpll_hw_state *hw_state)
2040 {
2041 	enum port port = (enum port)pll->info->id; /* 1:1 port->PLL mapping */
2042 	intel_wakeref_t wakeref;
2043 	enum dpio_phy phy;
2044 	enum dpio_channel ch;
2045 	u32 val;
2046 	bool ret;
2047 
2048 	bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
2049 
2050 	wakeref = intel_display_power_get_if_enabled(dev_priv,
2051 						     POWER_DOMAIN_DISPLAY_CORE);
2052 	if (!wakeref)
2053 		return false;
2054 
2055 	ret = false;
2056 
2057 	val = intel_de_read(dev_priv, BXT_PORT_PLL_ENABLE(port));
2058 	if (!(val & PORT_PLL_ENABLE))
2059 		goto out;
2060 
2061 	hw_state->ebb0 = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_0(phy, ch));
2062 	hw_state->ebb0 &= PORT_PLL_P1_MASK | PORT_PLL_P2_MASK;
2063 
2064 	hw_state->ebb4 = intel_de_read(dev_priv, BXT_PORT_PLL_EBB_4(phy, ch));
2065 	hw_state->ebb4 &= PORT_PLL_10BIT_CLK_ENABLE;
2066 
2067 	hw_state->pll0 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 0));
2068 	hw_state->pll0 &= PORT_PLL_M2_INT_MASK;
2069 
2070 	hw_state->pll1 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 1));
2071 	hw_state->pll1 &= PORT_PLL_N_MASK;
2072 
2073 	hw_state->pll2 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 2));
2074 	hw_state->pll2 &= PORT_PLL_M2_FRAC_MASK;
2075 
2076 	hw_state->pll3 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 3));
2077 	hw_state->pll3 &= PORT_PLL_M2_FRAC_ENABLE;
2078 
2079 	hw_state->pll6 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 6));
2080 	hw_state->pll6 &= PORT_PLL_PROP_COEFF_MASK |
2081 			  PORT_PLL_INT_COEFF_MASK |
2082 			  PORT_PLL_GAIN_CTL_MASK;
2083 
2084 	hw_state->pll8 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 8));
2085 	hw_state->pll8 &= PORT_PLL_TARGET_CNT_MASK;
2086 
2087 	hw_state->pll9 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 9));
2088 	hw_state->pll9 &= PORT_PLL_LOCK_THRESHOLD_MASK;
2089 
2090 	hw_state->pll10 = intel_de_read(dev_priv, BXT_PORT_PLL(phy, ch, 10));
2091 	hw_state->pll10 &= PORT_PLL_DCO_AMP_OVR_EN_H |
2092 			   PORT_PLL_DCO_AMP_MASK;
2093 
2094 	/*
2095 	 * While we write to the group register to program all lanes at once we
2096 	 * can read only lane registers. We configure all lanes the same way, so
2097 	 * here just read out lanes 0/1 and output a note if lanes 2/3 differ.
2098 	 */
2099 	hw_state->pcsdw12 = intel_de_read(dev_priv,
2100 					  BXT_PORT_PCS_DW12_LN01(phy, ch));
2101 	if (intel_de_read(dev_priv, BXT_PORT_PCS_DW12_LN23(phy, ch)) != hw_state->pcsdw12)
2102 		drm_dbg(&dev_priv->drm,
2103 			"lane stagger config different for lane 01 (%08x) and 23 (%08x)\n",
2104 			hw_state->pcsdw12,
2105 			intel_de_read(dev_priv,
2106 				      BXT_PORT_PCS_DW12_LN23(phy, ch)));
2107 	hw_state->pcsdw12 &= LANE_STAGGER_MASK | LANESTAGGER_STRAP_OVRD;
2108 
2109 	ret = true;
2110 
2111 out:
2112 	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
2113 
2114 	return ret;
2115 }
2116 
2117 /* pre-calculated values for DP linkrates */
2118 static const struct dpll bxt_dp_clk_val[] = {
2119 	/* m2 is .22 binary fixed point */
2120 	{ .dot = 162000, .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
2121 	{ .dot = 270000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
2122 	{ .dot = 540000, .p1 = 2, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 /* 27.0 */ },
2123 	{ .dot = 216000, .p1 = 3, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
2124 	{ .dot = 243000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6133333 /* 24.3 */ },
2125 	{ .dot = 324000, .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
2126 	{ .dot = 432000, .p1 = 3, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x819999a /* 32.4 */ },
2127 };
2128 
2129 static int
2130 bxt_ddi_hdmi_pll_dividers(struct intel_crtc_state *crtc_state,
2131 			  struct dpll *clk_div)
2132 {
2133 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2134 
2135 	/* Calculate HDMI div */
2136 	/*
2137 	 * FIXME: tie the following calculation into
2138 	 * i9xx_crtc_compute_clock
2139 	 */
2140 	if (!bxt_find_best_dpll(crtc_state, clk_div))
2141 		return -EINVAL;
2142 
2143 	drm_WARN_ON(&i915->drm, clk_div->m1 != 2);
2144 
2145 	return 0;
2146 }
2147 
2148 static void bxt_ddi_dp_pll_dividers(struct intel_crtc_state *crtc_state,
2149 				    struct dpll *clk_div)
2150 {
2151 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2152 	int i;
2153 
2154 	*clk_div = bxt_dp_clk_val[0];
2155 	for (i = 0; i < ARRAY_SIZE(bxt_dp_clk_val); ++i) {
2156 		if (crtc_state->port_clock == bxt_dp_clk_val[i].dot) {
2157 			*clk_div = bxt_dp_clk_val[i];
2158 			break;
2159 		}
2160 	}
2161 
2162 	chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, clk_div);
2163 
2164 	drm_WARN_ON(&i915->drm, clk_div->vco == 0 ||
2165 		    clk_div->dot != crtc_state->port_clock);
2166 }
2167 
2168 static int bxt_ddi_set_dpll_hw_state(struct intel_crtc_state *crtc_state,
2169 				     const struct dpll *clk_div)
2170 {
2171 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2172 	struct intel_dpll_hw_state *dpll_hw_state = &crtc_state->dpll_hw_state;
2173 	int clock = crtc_state->port_clock;
2174 	int vco = clk_div->vco;
2175 	u32 prop_coef, int_coef, gain_ctl, targ_cnt;
2176 	u32 lanestagger;
2177 
2178 	if (vco >= 6200000 && vco <= 6700000) {
2179 		prop_coef = 4;
2180 		int_coef = 9;
2181 		gain_ctl = 3;
2182 		targ_cnt = 8;
2183 	} else if ((vco > 5400000 && vco < 6200000) ||
2184 			(vco >= 4800000 && vco < 5400000)) {
2185 		prop_coef = 5;
2186 		int_coef = 11;
2187 		gain_ctl = 3;
2188 		targ_cnt = 9;
2189 	} else if (vco == 5400000) {
2190 		prop_coef = 3;
2191 		int_coef = 8;
2192 		gain_ctl = 1;
2193 		targ_cnt = 9;
2194 	} else {
2195 		drm_err(&i915->drm, "Invalid VCO\n");
2196 		return -EINVAL;
2197 	}
2198 
2199 	if (clock > 270000)
2200 		lanestagger = 0x18;
2201 	else if (clock > 135000)
2202 		lanestagger = 0x0d;
2203 	else if (clock > 67000)
2204 		lanestagger = 0x07;
2205 	else if (clock > 33000)
2206 		lanestagger = 0x04;
2207 	else
2208 		lanestagger = 0x02;
2209 
2210 	dpll_hw_state->ebb0 = PORT_PLL_P1(clk_div->p1) | PORT_PLL_P2(clk_div->p2);
2211 	dpll_hw_state->pll0 = PORT_PLL_M2_INT(clk_div->m2 >> 22);
2212 	dpll_hw_state->pll1 = PORT_PLL_N(clk_div->n);
2213 	dpll_hw_state->pll2 = PORT_PLL_M2_FRAC(clk_div->m2 & 0x3fffff);
2214 
2215 	if (clk_div->m2 & 0x3fffff)
2216 		dpll_hw_state->pll3 = PORT_PLL_M2_FRAC_ENABLE;
2217 
2218 	dpll_hw_state->pll6 = PORT_PLL_PROP_COEFF(prop_coef) |
2219 		PORT_PLL_INT_COEFF(int_coef) |
2220 		PORT_PLL_GAIN_CTL(gain_ctl);
2221 
2222 	dpll_hw_state->pll8 = PORT_PLL_TARGET_CNT(targ_cnt);
2223 
2224 	dpll_hw_state->pll9 = PORT_PLL_LOCK_THRESHOLD(5);
2225 
2226 	dpll_hw_state->pll10 = PORT_PLL_DCO_AMP(15) |
2227 		PORT_PLL_DCO_AMP_OVR_EN_H;
2228 
2229 	dpll_hw_state->ebb4 = PORT_PLL_10BIT_CLK_ENABLE;
2230 
2231 	dpll_hw_state->pcsdw12 = LANESTAGGER_STRAP_OVRD | lanestagger;
2232 
2233 	return 0;
2234 }
2235 
2236 static int bxt_ddi_pll_get_freq(struct drm_i915_private *i915,
2237 				const struct intel_shared_dpll *pll,
2238 				const struct intel_dpll_hw_state *pll_state)
2239 {
2240 	struct dpll clock;
2241 
2242 	clock.m1 = 2;
2243 	clock.m2 = REG_FIELD_GET(PORT_PLL_M2_INT_MASK, pll_state->pll0) << 22;
2244 	if (pll_state->pll3 & PORT_PLL_M2_FRAC_ENABLE)
2245 		clock.m2 |= REG_FIELD_GET(PORT_PLL_M2_FRAC_MASK, pll_state->pll2);
2246 	clock.n = REG_FIELD_GET(PORT_PLL_N_MASK, pll_state->pll1);
2247 	clock.p1 = REG_FIELD_GET(PORT_PLL_P1_MASK, pll_state->ebb0);
2248 	clock.p2 = REG_FIELD_GET(PORT_PLL_P2_MASK, pll_state->ebb0);
2249 
2250 	return chv_calc_dpll_params(i915->display.dpll.ref_clks.nssc, &clock);
2251 }
2252 
2253 static int
2254 bxt_ddi_dp_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
2255 {
2256 	struct dpll clk_div = {};
2257 
2258 	bxt_ddi_dp_pll_dividers(crtc_state, &clk_div);
2259 
2260 	return bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
2261 }
2262 
2263 static int
2264 bxt_ddi_hdmi_set_dpll_hw_state(struct intel_crtc_state *crtc_state)
2265 {
2266 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2267 	struct dpll clk_div = {};
2268 	int ret;
2269 
2270 	bxt_ddi_hdmi_pll_dividers(crtc_state, &clk_div);
2271 
2272 	ret = bxt_ddi_set_dpll_hw_state(crtc_state, &clk_div);
2273 	if (ret)
2274 		return ret;
2275 
2276 	crtc_state->port_clock = bxt_ddi_pll_get_freq(i915, NULL,
2277 						      &crtc_state->dpll_hw_state);
2278 
2279 	return 0;
2280 }
2281 
2282 static int bxt_compute_dpll(struct intel_atomic_state *state,
2283 			    struct intel_crtc *crtc,
2284 			    struct intel_encoder *encoder)
2285 {
2286 	struct intel_crtc_state *crtc_state =
2287 		intel_atomic_get_new_crtc_state(state, crtc);
2288 
2289 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI))
2290 		return bxt_ddi_hdmi_set_dpll_hw_state(crtc_state);
2291 	else if (intel_crtc_has_dp_encoder(crtc_state))
2292 		return bxt_ddi_dp_set_dpll_hw_state(crtc_state);
2293 	else
2294 		return -EINVAL;
2295 }
2296 
2297 static int bxt_get_dpll(struct intel_atomic_state *state,
2298 			struct intel_crtc *crtc,
2299 			struct intel_encoder *encoder)
2300 {
2301 	struct intel_crtc_state *crtc_state =
2302 		intel_atomic_get_new_crtc_state(state, crtc);
2303 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
2304 	struct intel_shared_dpll *pll;
2305 	enum intel_dpll_id id;
2306 
2307 	/* 1:1 mapping between ports and PLLs */
2308 	id = (enum intel_dpll_id) encoder->port;
2309 	pll = intel_get_shared_dpll_by_id(dev_priv, id);
2310 
2311 	drm_dbg_kms(&dev_priv->drm, "[CRTC:%d:%s] using pre-allocated %s\n",
2312 		    crtc->base.base.id, crtc->base.name, pll->info->name);
2313 
2314 	intel_reference_shared_dpll(state, crtc,
2315 				    pll, &crtc_state->dpll_hw_state);
2316 
2317 	crtc_state->shared_dpll = pll;
2318 
2319 	return 0;
2320 }
2321 
2322 static void bxt_update_dpll_ref_clks(struct drm_i915_private *i915)
2323 {
2324 	i915->display.dpll.ref_clks.ssc = 100000;
2325 	i915->display.dpll.ref_clks.nssc = 100000;
2326 	/* DSI non-SSC ref 19.2MHz */
2327 }
2328 
2329 static void bxt_dump_hw_state(struct drm_i915_private *dev_priv,
2330 			      const struct intel_dpll_hw_state *hw_state)
2331 {
2332 	drm_dbg_kms(&dev_priv->drm, "dpll_hw_state: ebb0: 0x%x, ebb4: 0x%x,"
2333 		    "pll0: 0x%x, pll1: 0x%x, pll2: 0x%x, pll3: 0x%x, "
2334 		    "pll6: 0x%x, pll8: 0x%x, pll9: 0x%x, pll10: 0x%x, pcsdw12: 0x%x\n",
2335 		    hw_state->ebb0,
2336 		    hw_state->ebb4,
2337 		    hw_state->pll0,
2338 		    hw_state->pll1,
2339 		    hw_state->pll2,
2340 		    hw_state->pll3,
2341 		    hw_state->pll6,
2342 		    hw_state->pll8,
2343 		    hw_state->pll9,
2344 		    hw_state->pll10,
2345 		    hw_state->pcsdw12);
2346 }
2347 
2348 static const struct intel_shared_dpll_funcs bxt_ddi_pll_funcs = {
2349 	.enable = bxt_ddi_pll_enable,
2350 	.disable = bxt_ddi_pll_disable,
2351 	.get_hw_state = bxt_ddi_pll_get_hw_state,
2352 	.get_freq = bxt_ddi_pll_get_freq,
2353 };
2354 
2355 static const struct dpll_info bxt_plls[] = {
2356 	{ "PORT PLL A", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL0, 0 },
2357 	{ "PORT PLL B", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL1, 0 },
2358 	{ "PORT PLL C", &bxt_ddi_pll_funcs, DPLL_ID_SKL_DPLL2, 0 },
2359 	{ },
2360 };
2361 
2362 static const struct intel_dpll_mgr bxt_pll_mgr = {
2363 	.dpll_info = bxt_plls,
2364 	.compute_dplls = bxt_compute_dpll,
2365 	.get_dplls = bxt_get_dpll,
2366 	.put_dplls = intel_put_dpll,
2367 	.update_ref_clks = bxt_update_dpll_ref_clks,
2368 	.dump_hw_state = bxt_dump_hw_state,
2369 };
2370 
2371 static void icl_wrpll_get_multipliers(int bestdiv, int *pdiv,
2372 				      int *qdiv, int *kdiv)
2373 {
2374 	/* even dividers */
2375 	if (bestdiv % 2 == 0) {
2376 		if (bestdiv == 2) {
2377 			*pdiv = 2;
2378 			*qdiv = 1;
2379 			*kdiv = 1;
2380 		} else if (bestdiv % 4 == 0) {
2381 			*pdiv = 2;
2382 			*qdiv = bestdiv / 4;
2383 			*kdiv = 2;
2384 		} else if (bestdiv % 6 == 0) {
2385 			*pdiv = 3;
2386 			*qdiv = bestdiv / 6;
2387 			*kdiv = 2;
2388 		} else if (bestdiv % 5 == 0) {
2389 			*pdiv = 5;
2390 			*qdiv = bestdiv / 10;
2391 			*kdiv = 2;
2392 		} else if (bestdiv % 14 == 0) {
2393 			*pdiv = 7;
2394 			*qdiv = bestdiv / 14;
2395 			*kdiv = 2;
2396 		}
2397 	} else {
2398 		if (bestdiv == 3 || bestdiv == 5 || bestdiv == 7) {
2399 			*pdiv = bestdiv;
2400 			*qdiv = 1;
2401 			*kdiv = 1;
2402 		} else { /* 9, 15, 21 */
2403 			*pdiv = bestdiv / 3;
2404 			*qdiv = 1;
2405 			*kdiv = 3;
2406 		}
2407 	}
2408 }
2409 
2410 static void icl_wrpll_params_populate(struct skl_wrpll_params *params,
2411 				      u32 dco_freq, u32 ref_freq,
2412 				      int pdiv, int qdiv, int kdiv)
2413 {
2414 	u32 dco;
2415 
2416 	switch (kdiv) {
2417 	case 1:
2418 		params->kdiv = 1;
2419 		break;
2420 	case 2:
2421 		params->kdiv = 2;
2422 		break;
2423 	case 3:
2424 		params->kdiv = 4;
2425 		break;
2426 	default:
2427 		WARN(1, "Incorrect KDiv\n");
2428 	}
2429 
2430 	switch (pdiv) {
2431 	case 2:
2432 		params->pdiv = 1;
2433 		break;
2434 	case 3:
2435 		params->pdiv = 2;
2436 		break;
2437 	case 5:
2438 		params->pdiv = 4;
2439 		break;
2440 	case 7:
2441 		params->pdiv = 8;
2442 		break;
2443 	default:
2444 		WARN(1, "Incorrect PDiv\n");
2445 	}
2446 
2447 	WARN_ON(kdiv != 2 && qdiv != 1);
2448 
2449 	params->qdiv_ratio = qdiv;
2450 	params->qdiv_mode = (qdiv == 1) ? 0 : 1;
2451 
2452 	dco = div_u64((u64)dco_freq << 15, ref_freq);
2453 
2454 	params->dco_integer = dco >> 15;
2455 	params->dco_fraction = dco & 0x7fff;
2456 }
2457 
2458 /*
2459  * Display WA #22010492432: ehl, tgl, adl-s, adl-p
2460  * Program half of the nominal DCO divider fraction value.
2461  */
2462 static bool
2463 ehl_combo_pll_div_frac_wa_needed(struct drm_i915_private *i915)
2464 {
2465 	return ((IS_ELKHARTLAKE(i915) &&
2466 		 IS_DISPLAY_STEP(i915, STEP_B0, STEP_FOREVER)) ||
2467 		 IS_TIGERLAKE(i915) || IS_ALDERLAKE_S(i915) || IS_ALDERLAKE_P(i915)) &&
2468 		 i915->display.dpll.ref_clks.nssc == 38400;
2469 }
2470 
2471 struct icl_combo_pll_params {
2472 	int clock;
2473 	struct skl_wrpll_params wrpll;
2474 };
2475 
2476 /*
2477  * These values alrea already adjusted: they're the bits we write to the
2478  * registers, not the logical values.
2479  */
2480 static const struct icl_combo_pll_params icl_dp_combo_pll_24MHz_values[] = {
2481 	{ 540000,
2482 	  { .dco_integer = 0x151, .dco_fraction = 0x4000,		/* [0]: 5.4 */
2483 	    .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2484 	{ 270000,
2485 	  { .dco_integer = 0x151, .dco_fraction = 0x4000,		/* [1]: 2.7 */
2486 	    .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2487 	{ 162000,
2488 	  { .dco_integer = 0x151, .dco_fraction = 0x4000,		/* [2]: 1.62 */
2489 	    .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2490 	{ 324000,
2491 	  { .dco_integer = 0x151, .dco_fraction = 0x4000,		/* [3]: 3.24 */
2492 	    .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2493 	{ 216000,
2494 	  { .dco_integer = 0x168, .dco_fraction = 0x0000,		/* [4]: 2.16 */
2495 	    .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2, }, },
2496 	{ 432000,
2497 	  { .dco_integer = 0x168, .dco_fraction = 0x0000,		/* [5]: 4.32 */
2498 	    .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2499 	{ 648000,
2500 	  { .dco_integer = 0x195, .dco_fraction = 0x0000,		/* [6]: 6.48 */
2501 	    .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2502 	{ 810000,
2503 	  { .dco_integer = 0x151, .dco_fraction = 0x4000,		/* [7]: 8.1 */
2504 	    .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2505 };
2506 
2507 
2508 /* Also used for 38.4 MHz values. */
2509 static const struct icl_combo_pll_params icl_dp_combo_pll_19_2MHz_values[] = {
2510 	{ 540000,
2511 	  { .dco_integer = 0x1A5, .dco_fraction = 0x7000,		/* [0]: 5.4 */
2512 	    .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2513 	{ 270000,
2514 	  { .dco_integer = 0x1A5, .dco_fraction = 0x7000,		/* [1]: 2.7 */
2515 	    .pdiv = 0x2 /* 3 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2516 	{ 162000,
2517 	  { .dco_integer = 0x1A5, .dco_fraction = 0x7000,		/* [2]: 1.62 */
2518 	    .pdiv = 0x4 /* 5 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2519 	{ 324000,
2520 	  { .dco_integer = 0x1A5, .dco_fraction = 0x7000,		/* [3]: 3.24 */
2521 	    .pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2522 	{ 216000,
2523 	  { .dco_integer = 0x1C2, .dco_fraction = 0x0000,		/* [4]: 2.16 */
2524 	    .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 1, .qdiv_ratio = 2, }, },
2525 	{ 432000,
2526 	  { .dco_integer = 0x1C2, .dco_fraction = 0x0000,		/* [5]: 4.32 */
2527 	    .pdiv = 0x1 /* 2 */, .kdiv = 2, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2528 	{ 648000,
2529 	  { .dco_integer = 0x1FA, .dco_fraction = 0x2000,		/* [6]: 6.48 */
2530 	    .pdiv = 0x2 /* 3 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2531 	{ 810000,
2532 	  { .dco_integer = 0x1A5, .dco_fraction = 0x7000,		/* [7]: 8.1 */
2533 	    .pdiv = 0x1 /* 2 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0, }, },
2534 };
2535 
2536 static const struct skl_wrpll_params icl_tbt_pll_24MHz_values = {
2537 	.dco_integer = 0x151, .dco_fraction = 0x4000,
2538 	.pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
2539 };
2540 
2541 static const struct skl_wrpll_params icl_tbt_pll_19_2MHz_values = {
2542 	.dco_integer = 0x1A5, .dco_fraction = 0x7000,
2543 	.pdiv = 0x4 /* 5 */, .kdiv = 1, .qdiv_mode = 0, .qdiv_ratio = 0,
2544 };
2545 
2546 static const struct skl_wrpll_params tgl_tbt_pll_19_2MHz_values = {
2547 	.dco_integer = 0x54, .dco_fraction = 0x3000,
2548 	/* the following params are unused */
2549 	.pdiv = 0, .kdiv = 0, .qdiv_mode = 0, .qdiv_ratio = 0,
2550 };
2551 
2552 static const struct skl_wrpll_params tgl_tbt_pll_24MHz_values = {
2553 	.dco_integer = 0x43, .dco_fraction = 0x4000,
2554 	/* the following params are unused */
2555 };
2556 
2557 static int icl_calc_dp_combo_pll(struct intel_crtc_state *crtc_state,
2558 				 struct skl_wrpll_params *pll_params)
2559 {
2560 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2561 	const struct icl_combo_pll_params *params =
2562 		dev_priv->display.dpll.ref_clks.nssc == 24000 ?
2563 		icl_dp_combo_pll_24MHz_values :
2564 		icl_dp_combo_pll_19_2MHz_values;
2565 	int clock = crtc_state->port_clock;
2566 	int i;
2567 
2568 	for (i = 0; i < ARRAY_SIZE(icl_dp_combo_pll_24MHz_values); i++) {
2569 		if (clock == params[i].clock) {
2570 			*pll_params = params[i].wrpll;
2571 			return 0;
2572 		}
2573 	}
2574 
2575 	MISSING_CASE(clock);
2576 	return -EINVAL;
2577 }
2578 
2579 static int icl_calc_tbt_pll(struct intel_crtc_state *crtc_state,
2580 			    struct skl_wrpll_params *pll_params)
2581 {
2582 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2583 
2584 	if (DISPLAY_VER(dev_priv) >= 12) {
2585 		switch (dev_priv->display.dpll.ref_clks.nssc) {
2586 		default:
2587 			MISSING_CASE(dev_priv->display.dpll.ref_clks.nssc);
2588 			fallthrough;
2589 		case 19200:
2590 		case 38400:
2591 			*pll_params = tgl_tbt_pll_19_2MHz_values;
2592 			break;
2593 		case 24000:
2594 			*pll_params = tgl_tbt_pll_24MHz_values;
2595 			break;
2596 		}
2597 	} else {
2598 		switch (dev_priv->display.dpll.ref_clks.nssc) {
2599 		default:
2600 			MISSING_CASE(dev_priv->display.dpll.ref_clks.nssc);
2601 			fallthrough;
2602 		case 19200:
2603 		case 38400:
2604 			*pll_params = icl_tbt_pll_19_2MHz_values;
2605 			break;
2606 		case 24000:
2607 			*pll_params = icl_tbt_pll_24MHz_values;
2608 			break;
2609 		}
2610 	}
2611 
2612 	return 0;
2613 }
2614 
2615 static int icl_ddi_tbt_pll_get_freq(struct drm_i915_private *i915,
2616 				    const struct intel_shared_dpll *pll,
2617 				    const struct intel_dpll_hw_state *pll_state)
2618 {
2619 	/*
2620 	 * The PLL outputs multiple frequencies at the same time, selection is
2621 	 * made at DDI clock mux level.
2622 	 */
2623 	drm_WARN_ON(&i915->drm, 1);
2624 
2625 	return 0;
2626 }
2627 
2628 static int icl_wrpll_ref_clock(struct drm_i915_private *i915)
2629 {
2630 	int ref_clock = i915->display.dpll.ref_clks.nssc;
2631 
2632 	/*
2633 	 * For ICL+, the spec states: if reference frequency is 38.4,
2634 	 * use 19.2 because the DPLL automatically divides that by 2.
2635 	 */
2636 	if (ref_clock == 38400)
2637 		ref_clock = 19200;
2638 
2639 	return ref_clock;
2640 }
2641 
2642 static int
2643 icl_calc_wrpll(struct intel_crtc_state *crtc_state,
2644 	       struct skl_wrpll_params *wrpll_params)
2645 {
2646 	struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev);
2647 	int ref_clock = icl_wrpll_ref_clock(i915);
2648 	u32 afe_clock = crtc_state->port_clock * 5;
2649 	u32 dco_min = 7998000;
2650 	u32 dco_max = 10000000;
2651 	u32 dco_mid = (dco_min + dco_max) / 2;
2652 	static const int dividers[] = {  2,  4,  6,  8, 10, 12,  14,  16,
2653 					 18, 20, 24, 28, 30, 32,  36,  40,
2654 					 42, 44, 48, 50, 52, 54,  56,  60,
2655 					 64, 66, 68, 70, 72, 76,  78,  80,
2656 					 84, 88, 90, 92, 96, 98, 100, 102,
2657 					  3,  5,  7,  9, 15, 21 };
2658 	u32 dco, best_dco = 0, dco_centrality = 0;
2659 	u32 best_dco_centrality = U32_MAX; /* Spec meaning of 999999 MHz */
2660 	int d, best_div = 0, pdiv = 0, qdiv = 0, kdiv = 0;
2661 
2662 	for (d = 0; d < ARRAY_SIZE(dividers); d++) {
2663 		dco = afe_clock * dividers[d];
2664 
2665 		if (dco <= dco_max && dco >= dco_min) {
2666 			dco_centrality = abs(dco - dco_mid);
2667 
2668 			if (dco_centrality < best_dco_centrality) {
2669 				best_dco_centrality = dco_centrality;
2670 				best_div = dividers[d];
2671 				best_dco = dco;
2672 			}
2673 		}
2674 	}
2675 
2676 	if (best_div == 0)
2677 		return -EINVAL;
2678 
2679 	icl_wrpll_get_multipliers(best_div, &pdiv, &qdiv, &kdiv);
2680 	icl_wrpll_params_populate(wrpll_params, best_dco, ref_clock,
2681 				  pdiv, qdiv, kdiv);
2682 
2683 	return 0;
2684 }
2685 
2686 static int icl_ddi_combo_pll_get_freq(struct drm_i915_private *i915,
2687 				      const struct intel_shared_dpll *pll,
2688 				      const struct intel_dpll_hw_state *pll_state)
2689 {
2690 	int ref_clock = icl_wrpll_ref_clock(i915);
2691 	u32 dco_fraction;
2692 	u32 p0, p1, p2, dco_freq;
2693 
2694 	p0 = pll_state->cfgcr1 & DPLL_CFGCR1_PDIV_MASK;
2695 	p2 = pll_state->cfgcr1 & DPLL_CFGCR1_KDIV_MASK;
2696 
2697 	if (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_MODE(1))
2698 		p1 = (pll_state->cfgcr1 & DPLL_CFGCR1_QDIV_RATIO_MASK) >>
2699 			DPLL_CFGCR1_QDIV_RATIO_SHIFT;
2700 	else
2701 		p1 = 1;
2702 
2703 	switch (p0) {
2704 	case DPLL_CFGCR1_PDIV_2:
2705 		p0 = 2;
2706 		break;
2707 	case DPLL_CFGCR1_PDIV_3:
2708 		p0 = 3;
2709 		break;
2710 	case DPLL_CFGCR1_PDIV_5:
2711 		p0 = 5;
2712 		break;
2713 	case DPLL_CFGCR1_PDIV_7:
2714 		p0 = 7;
2715 		break;
2716 	}
2717 
2718 	switch (p2) {
2719 	case DPLL_CFGCR1_KDIV_1:
2720 		p2 = 1;
2721 		break;
2722 	case DPLL_CFGCR1_KDIV_2:
2723 		p2 = 2;
2724 		break;
2725 	case DPLL_CFGCR1_KDIV_3:
2726 		p2 = 3;
2727 		break;
2728 	}
2729 
2730 	dco_freq = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_INTEGER_MASK) *
2731 		   ref_clock;
2732 
2733 	dco_fraction = (pll_state->cfgcr0 & DPLL_CFGCR0_DCO_FRACTION_MASK) >>
2734 		       DPLL_CFGCR0_DCO_FRACTION_SHIFT;
2735 
2736 	if (ehl_combo_pll_div_frac_wa_needed(i915))
2737 		dco_fraction *= 2;
2738 
2739 	dco_freq += (dco_fraction * ref_clock) / 0x8000;
2740 
2741 	if (drm_WARN_ON(&i915->drm, p0 == 0 || p1 == 0 || p2 == 0))
2742 		return 0;
2743 
2744 	return dco_freq / (p0 * p1 * p2 * 5);
2745 }
2746 
2747 static void icl_calc_dpll_state(struct drm_i915_private *i915,
2748 				const struct skl_wrpll_params *pll_params,
2749 				struct intel_dpll_hw_state *pll_state)
2750 {
2751 	u32 dco_fraction = pll_params->dco_fraction;
2752 
2753 	if (ehl_combo_pll_div_frac_wa_needed(i915))
2754 		dco_fraction = DIV_ROUND_CLOSEST(dco_fraction, 2);
2755 
2756 	pll_state->cfgcr0 = DPLL_CFGCR0_DCO_FRACTION(dco_fraction) |
2757 			    pll_params->dco_integer;
2758 
2759 	pll_state->cfgcr1 = DPLL_CFGCR1_QDIV_RATIO(pll_params->qdiv_ratio) |
2760 			    DPLL_CFGCR1_QDIV_MODE(pll_params->qdiv_mode) |
2761 			    DPLL_CFGCR1_KDIV(pll_params->kdiv) |
2762 			    DPLL_CFGCR1_PDIV(pll_params->pdiv);
2763 
2764 	if (DISPLAY_VER(i915) >= 12)
2765 		pll_state->cfgcr1 |= TGL_DPLL_CFGCR1_CFSELOVRD_NORMAL_XTAL;
2766 	else
2767 		pll_state->cfgcr1 |= DPLL_CFGCR1_CENTRAL_FREQ_8400;
2768 
2769 	if (i915->display.vbt.override_afc_startup)
2770 		pll_state->div0 = TGL_DPLL0_DIV0_AFC_STARTUP(i915->display.vbt.override_afc_startup_val);
2771 }
2772 
2773 static int icl_mg_pll_find_divisors(int clock_khz, bool is_dp, bool use_ssc,
2774 				    u32 *target_dco_khz,
2775 				    struct intel_dpll_hw_state *state,
2776 				    bool is_dkl)
2777 {
2778 	static const u8 div1_vals[] = { 7, 5, 3, 2 };
2779 	u32 dco_min_freq, dco_max_freq;
2780 	unsigned int i;
2781 	int div2;
2782 
2783 	dco_min_freq = is_dp ? 8100000 : use_ssc ? 8000000 : 7992000;
2784 	dco_max_freq = is_dp ? 8100000 : 10000000;
2785 
2786 	for (i = 0; i < ARRAY_SIZE(div1_vals); i++) {
2787 		int div1 = div1_vals[i];
2788 
2789 		for (div2 = 10; div2 > 0; div2--) {
2790 			int dco = div1 * div2 * clock_khz * 5;
2791 			int a_divratio, tlinedrv, inputsel;
2792 			u32 hsdiv;
2793 
2794 			if (dco < dco_min_freq || dco > dco_max_freq)
2795 				continue;
2796 
2797 			if (div2 >= 2) {
2798 				/*
2799 				 * Note: a_divratio not matching TGL BSpec
2800 				 * algorithm but matching hardcoded values and
2801 				 * working on HW for DP alt-mode at least
2802 				 */
2803 				a_divratio = is_dp ? 10 : 5;
2804 				tlinedrv = is_dkl ? 1 : 2;
2805 			} else {
2806 				a_divratio = 5;
2807 				tlinedrv = 0;
2808 			}
2809 			inputsel = is_dp ? 0 : 1;
2810 
2811 			switch (div1) {
2812 			default:
2813 				MISSING_CASE(div1);
2814 				fallthrough;
2815 			case 2:
2816 				hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2;
2817 				break;
2818 			case 3:
2819 				hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3;
2820 				break;
2821 			case 5:
2822 				hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5;
2823 				break;
2824 			case 7:
2825 				hsdiv = MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7;
2826 				break;
2827 			}
2828 
2829 			*target_dco_khz = dco;
2830 
2831 			state->mg_refclkin_ctl = MG_REFCLKIN_CTL_OD_2_MUX(1);
2832 
2833 			state->mg_clktop2_coreclkctl1 =
2834 				MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO(a_divratio);
2835 
2836 			state->mg_clktop2_hsclkctl =
2837 				MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL(tlinedrv) |
2838 				MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL(inputsel) |
2839 				hsdiv |
2840 				MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO(div2);
2841 
2842 			return 0;
2843 		}
2844 	}
2845 
2846 	return -EINVAL;
2847 }
2848 
2849 /*
2850  * The specification for this function uses real numbers, so the math had to be
2851  * adapted to integer-only calculation, that's why it looks so different.
2852  */
2853 static int icl_calc_mg_pll_state(struct intel_crtc_state *crtc_state,
2854 				 struct intel_dpll_hw_state *pll_state)
2855 {
2856 	struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev);
2857 	int refclk_khz = dev_priv->display.dpll.ref_clks.nssc;
2858 	int clock = crtc_state->port_clock;
2859 	u32 dco_khz, m1div, m2div_int, m2div_rem, m2div_frac;
2860 	u32 iref_ndiv, iref_trim, iref_pulse_w;
2861 	u32 prop_coeff, int_coeff;
2862 	u32 tdc_targetcnt, feedfwgain;
2863 	u64 ssc_stepsize, ssc_steplen, ssc_steplog;
2864 	u64 tmp;
2865 	bool use_ssc = false;
2866 	bool is_dp = !intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI);
2867 	bool is_dkl = DISPLAY_VER(dev_priv) >= 12;
2868 	int ret;
2869 
2870 	ret = icl_mg_pll_find_divisors(clock, is_dp, use_ssc, &dco_khz,
2871 				       pll_state, is_dkl);
2872 	if (ret)
2873 		return ret;
2874 
2875 	m1div = 2;
2876 	m2div_int = dco_khz / (refclk_khz * m1div);
2877 	if (m2div_int > 255) {
2878 		if (!is_dkl) {
2879 			m1div = 4;
2880 			m2div_int = dco_khz / (refclk_khz * m1div);
2881 		}
2882 
2883 		if (m2div_int > 255)
2884 			return -EINVAL;
2885 	}
2886 	m2div_rem = dco_khz % (refclk_khz * m1div);
2887 
2888 	tmp = (u64)m2div_rem * (1 << 22);
2889 	do_div(tmp, refclk_khz * m1div);
2890 	m2div_frac = tmp;
2891 
2892 	switch (refclk_khz) {
2893 	case 19200:
2894 		iref_ndiv = 1;
2895 		iref_trim = 28;
2896 		iref_pulse_w = 1;
2897 		break;
2898 	case 24000:
2899 		iref_ndiv = 1;
2900 		iref_trim = 25;
2901 		iref_pulse_w = 2;
2902 		break;
2903 	case 38400:
2904 		iref_ndiv = 2;
2905 		iref_trim = 28;
2906 		iref_pulse_w = 1;
2907 		break;
2908 	default:
2909 		MISSING_CASE(refclk_khz);
2910 		return -EINVAL;
2911 	}
2912 
2913 	/*
2914 	 * tdc_res = 0.000003
2915 	 * tdc_targetcnt = int(2 / (tdc_res * 8 * 50 * 1.1) / refclk_mhz + 0.5)
2916 	 *
2917 	 * The multiplication by 1000 is due to refclk MHz to KHz conversion. It
2918 	 * was supposed to be a division, but we rearranged the operations of
2919 	 * the formula to avoid early divisions so we don't multiply the
2920 	 * rounding errors.
2921 	 *
2922 	 * 0.000003 * 8 * 50 * 1.1 = 0.00132, also known as 132 / 100000, which
2923 	 * we also rearrange to work with integers.
2924 	 *
2925 	 * The 0.5 transformed to 5 results in a multiplication by 10 and the
2926 	 * last division by 10.
2927 	 */
2928 	tdc_targetcnt = (2 * 1000 * 100000 * 10 / (132 * refclk_khz) + 5) / 10;
2929 
2930 	/*
2931 	 * Here we divide dco_khz by 10 in order to allow the dividend to fit in
2932 	 * 32 bits. That's not a problem since we round the division down
2933 	 * anyway.
2934 	 */
2935 	feedfwgain = (use_ssc || m2div_rem > 0) ?
2936 		m1div * 1000000 * 100 / (dco_khz * 3 / 10) : 0;
2937 
2938 	if (dco_khz >= 9000000) {
2939 		prop_coeff = 5;
2940 		int_coeff = 10;
2941 	} else {
2942 		prop_coeff = 4;
2943 		int_coeff = 8;
2944 	}
2945 
2946 	if (use_ssc) {
2947 		tmp = mul_u32_u32(dco_khz, 47 * 32);
2948 		do_div(tmp, refclk_khz * m1div * 10000);
2949 		ssc_stepsize = tmp;
2950 
2951 		tmp = mul_u32_u32(dco_khz, 1000);
2952 		ssc_steplen = DIV_ROUND_UP_ULL(tmp, 32 * 2 * 32);
2953 	} else {
2954 		ssc_stepsize = 0;
2955 		ssc_steplen = 0;
2956 	}
2957 	ssc_steplog = 4;
2958 
2959 	/* write pll_state calculations */
2960 	if (is_dkl) {
2961 		pll_state->mg_pll_div0 = DKL_PLL_DIV0_INTEG_COEFF(int_coeff) |
2962 					 DKL_PLL_DIV0_PROP_COEFF(prop_coeff) |
2963 					 DKL_PLL_DIV0_FBPREDIV(m1div) |
2964 					 DKL_PLL_DIV0_FBDIV_INT(m2div_int);
2965 		if (dev_priv->display.vbt.override_afc_startup) {
2966 			u8 val = dev_priv->display.vbt.override_afc_startup_val;
2967 
2968 			pll_state->mg_pll_div0 |= DKL_PLL_DIV0_AFC_STARTUP(val);
2969 		}
2970 
2971 		pll_state->mg_pll_div1 = DKL_PLL_DIV1_IREF_TRIM(iref_trim) |
2972 					 DKL_PLL_DIV1_TDC_TARGET_CNT(tdc_targetcnt);
2973 
2974 		pll_state->mg_pll_ssc = DKL_PLL_SSC_IREF_NDIV_RATIO(iref_ndiv) |
2975 					DKL_PLL_SSC_STEP_LEN(ssc_steplen) |
2976 					DKL_PLL_SSC_STEP_NUM(ssc_steplog) |
2977 					(use_ssc ? DKL_PLL_SSC_EN : 0);
2978 
2979 		pll_state->mg_pll_bias = (m2div_frac ? DKL_PLL_BIAS_FRAC_EN_H : 0) |
2980 					  DKL_PLL_BIAS_FBDIV_FRAC(m2div_frac);
2981 
2982 		pll_state->mg_pll_tdc_coldst_bias =
2983 				DKL_PLL_TDC_SSC_STEP_SIZE(ssc_stepsize) |
2984 				DKL_PLL_TDC_FEED_FWD_GAIN(feedfwgain);
2985 
2986 	} else {
2987 		pll_state->mg_pll_div0 =
2988 			(m2div_rem > 0 ? MG_PLL_DIV0_FRACNEN_H : 0) |
2989 			MG_PLL_DIV0_FBDIV_FRAC(m2div_frac) |
2990 			MG_PLL_DIV0_FBDIV_INT(m2div_int);
2991 
2992 		pll_state->mg_pll_div1 =
2993 			MG_PLL_DIV1_IREF_NDIVRATIO(iref_ndiv) |
2994 			MG_PLL_DIV1_DITHER_DIV_2 |
2995 			MG_PLL_DIV1_NDIVRATIO(1) |
2996 			MG_PLL_DIV1_FBPREDIV(m1div);
2997 
2998 		pll_state->mg_pll_lf =
2999 			MG_PLL_LF_TDCTARGETCNT(tdc_targetcnt) |
3000 			MG_PLL_LF_AFCCNTSEL_512 |
3001 			MG_PLL_LF_GAINCTRL(1) |
3002 			MG_PLL_LF_INT_COEFF(int_coeff) |
3003 			MG_PLL_LF_PROP_COEFF(prop_coeff);
3004 
3005 		pll_state->mg_pll_frac_lock =
3006 			MG_PLL_FRAC_LOCK_TRUELOCK_CRIT_32 |
3007 			MG_PLL_FRAC_LOCK_EARLYLOCK_CRIT_32 |
3008 			MG_PLL_FRAC_LOCK_LOCKTHRESH(10) |
3009 			MG_PLL_FRAC_LOCK_DCODITHEREN |
3010 			MG_PLL_FRAC_LOCK_FEEDFWRDGAIN(feedfwgain);
3011 		if (use_ssc || m2div_rem > 0)
3012 			pll_state->mg_pll_frac_lock |=
3013 				MG_PLL_FRAC_LOCK_FEEDFWRDCAL_EN;
3014 
3015 		pll_state->mg_pll_ssc =
3016 			(use_ssc ? MG_PLL_SSC_EN : 0) |
3017 			MG_PLL_SSC_TYPE(2) |
3018 			MG_PLL_SSC_STEPLENGTH(ssc_steplen) |
3019 			MG_PLL_SSC_STEPNUM(ssc_steplog) |
3020 			MG_PLL_SSC_FLLEN |
3021 			MG_PLL_SSC_STEPSIZE(ssc_stepsize);
3022 
3023 		pll_state->mg_pll_tdc_coldst_bias =
3024 			MG_PLL_TDC_COLDST_COLDSTART |
3025 			MG_PLL_TDC_COLDST_IREFINT_EN |
3026 			MG_PLL_TDC_COLDST_REFBIAS_START_PULSE_W(iref_pulse_w) |
3027 			MG_PLL_TDC_TDCOVCCORR_EN |
3028 			MG_PLL_TDC_TDCSEL(3);
3029 
3030 		pll_state->mg_pll_bias =
3031 			MG_PLL_BIAS_BIAS_GB_SEL(3) |
3032 			MG_PLL_BIAS_INIT_DCOAMP(0x3F) |
3033 			MG_PLL_BIAS_BIAS_BONUS(10) |
3034 			MG_PLL_BIAS_BIASCAL_EN |
3035 			MG_PLL_BIAS_CTRIM(12) |
3036 			MG_PLL_BIAS_VREF_RDAC(4) |
3037 			MG_PLL_BIAS_IREFTRIM(iref_trim);
3038 
3039 		if (refclk_khz == 38400) {
3040 			pll_state->mg_pll_tdc_coldst_bias_mask =
3041 				MG_PLL_TDC_COLDST_COLDSTART;
3042 			pll_state->mg_pll_bias_mask = 0;
3043 		} else {
3044 			pll_state->mg_pll_tdc_coldst_bias_mask = -1U;
3045 			pll_state->mg_pll_bias_mask = -1U;
3046 		}
3047 
3048 		pll_state->mg_pll_tdc_coldst_bias &=
3049 			pll_state->mg_pll_tdc_coldst_bias_mask;
3050 		pll_state->mg_pll_bias &= pll_state->mg_pll_bias_mask;
3051 	}
3052 
3053 	return 0;
3054 }
3055 
3056 static int icl_ddi_mg_pll_get_freq(struct drm_i915_private *dev_priv,
3057 				   const struct intel_shared_dpll *pll,
3058 				   const struct intel_dpll_hw_state *pll_state)
3059 {
3060 	u32 m1, m2_int, m2_frac, div1, div2, ref_clock;
3061 	u64 tmp;
3062 
3063 	ref_clock = dev_priv->display.dpll.ref_clks.nssc;
3064 
3065 	if (DISPLAY_VER(dev_priv) >= 12) {
3066 		m1 = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBPREDIV_MASK;
3067 		m1 = m1 >> DKL_PLL_DIV0_FBPREDIV_SHIFT;
3068 		m2_int = pll_state->mg_pll_div0 & DKL_PLL_DIV0_FBDIV_INT_MASK;
3069 
3070 		if (pll_state->mg_pll_bias & DKL_PLL_BIAS_FRAC_EN_H) {
3071 			m2_frac = pll_state->mg_pll_bias &
3072 				  DKL_PLL_BIAS_FBDIV_FRAC_MASK;
3073 			m2_frac = m2_frac >> DKL_PLL_BIAS_FBDIV_SHIFT;
3074 		} else {
3075 			m2_frac = 0;
3076 		}
3077 	} else {
3078 		m1 = pll_state->mg_pll_div1 & MG_PLL_DIV1_FBPREDIV_MASK;
3079 		m2_int = pll_state->mg_pll_div0 & MG_PLL_DIV0_FBDIV_INT_MASK;
3080 
3081 		if (pll_state->mg_pll_div0 & MG_PLL_DIV0_FRACNEN_H) {
3082 			m2_frac = pll_state->mg_pll_div0 &
3083 				  MG_PLL_DIV0_FBDIV_FRAC_MASK;
3084 			m2_frac = m2_frac >> MG_PLL_DIV0_FBDIV_FRAC_SHIFT;
3085 		} else {
3086 			m2_frac = 0;
3087 		}
3088 	}
3089 
3090 	switch (pll_state->mg_clktop2_hsclkctl &
3091 		MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK) {
3092 	case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_2:
3093 		div1 = 2;
3094 		break;
3095 	case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_3:
3096 		div1 = 3;
3097 		break;
3098 	case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_5:
3099 		div1 = 5;
3100 		break;
3101 	case MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_7:
3102 		div1 = 7;
3103 		break;
3104 	default:
3105 		MISSING_CASE(pll_state->mg_clktop2_hsclkctl);
3106 		return 0;
3107 	}
3108 
3109 	div2 = (pll_state->mg_clktop2_hsclkctl &
3110 		MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK) >>
3111 		MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_SHIFT;
3112 
3113 	/* div2 value of 0 is same as 1 means no div */
3114 	if (div2 == 0)
3115 		div2 = 1;
3116 
3117 	/*
3118 	 * Adjust the original formula to delay the division by 2^22 in order to
3119 	 * minimize possible rounding errors.
3120 	 */
3121 	tmp = (u64)m1 * m2_int * ref_clock +
3122 	      (((u64)m1 * m2_frac * ref_clock) >> 22);
3123 	tmp = div_u64(tmp, 5 * div1 * div2);
3124 
3125 	return tmp;
3126 }
3127 
3128 /**
3129  * icl_set_active_port_dpll - select the active port DPLL for a given CRTC
3130  * @crtc_state: state for the CRTC to select the DPLL for
3131  * @port_dpll_id: the active @port_dpll_id to select
3132  *
3133  * Select the given @port_dpll_id instance from the DPLLs reserved for the
3134  * CRTC.
3135  */
3136 void icl_set_active_port_dpll(struct intel_crtc_state *crtc_state,
3137 			      enum icl_port_dpll_id port_dpll_id)
3138 {
3139 	struct icl_port_dpll *port_dpll =
3140 		&crtc_state->icl_port_dplls[port_dpll_id];
3141 
3142 	crtc_state->shared_dpll = port_dpll->pll;
3143 	crtc_state->dpll_hw_state = port_dpll->hw_state;
3144 }
3145 
3146 static void icl_update_active_dpll(struct intel_atomic_state *state,
3147 				   struct intel_crtc *crtc,
3148 				   struct intel_encoder *encoder)
3149 {
3150 	struct intel_crtc_state *crtc_state =
3151 		intel_atomic_get_new_crtc_state(state, crtc);
3152 	struct intel_digital_port *primary_port;
3153 	enum icl_port_dpll_id port_dpll_id = ICL_PORT_DPLL_DEFAULT;
3154 
3155 	primary_port = encoder->type == INTEL_OUTPUT_DP_MST ?
3156 		enc_to_mst(encoder)->primary :
3157 		enc_to_dig_port(encoder);
3158 
3159 	if (primary_port &&
3160 	    (intel_tc_port_in_dp_alt_mode(primary_port) ||
3161 	     intel_tc_port_in_legacy_mode(primary_port)))
3162 		port_dpll_id = ICL_PORT_DPLL_MG_PHY;
3163 
3164 	icl_set_active_port_dpll(crtc_state, port_dpll_id);
3165 }
3166 
3167 static int icl_compute_combo_phy_dpll(struct intel_atomic_state *state,
3168 				      struct intel_crtc *crtc)
3169 {
3170 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3171 	struct intel_crtc_state *crtc_state =
3172 		intel_atomic_get_new_crtc_state(state, crtc);
3173 	struct icl_port_dpll *port_dpll =
3174 		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3175 	struct skl_wrpll_params pll_params = {};
3176 	int ret;
3177 
3178 	if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) ||
3179 	    intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI))
3180 		ret = icl_calc_wrpll(crtc_state, &pll_params);
3181 	else
3182 		ret = icl_calc_dp_combo_pll(crtc_state, &pll_params);
3183 
3184 	if (ret)
3185 		return ret;
3186 
3187 	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
3188 
3189 	/* this is mainly for the fastset check */
3190 	icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_DEFAULT);
3191 
3192 	crtc_state->port_clock = icl_ddi_combo_pll_get_freq(dev_priv, NULL,
3193 							    &port_dpll->hw_state);
3194 
3195 	return 0;
3196 }
3197 
3198 static int icl_get_combo_phy_dpll(struct intel_atomic_state *state,
3199 				  struct intel_crtc *crtc,
3200 				  struct intel_encoder *encoder)
3201 {
3202 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
3203 	struct intel_crtc_state *crtc_state =
3204 		intel_atomic_get_new_crtc_state(state, crtc);
3205 	struct icl_port_dpll *port_dpll =
3206 		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3207 	enum port port = encoder->port;
3208 	unsigned long dpll_mask;
3209 
3210 	if (IS_ALDERLAKE_S(dev_priv)) {
3211 		dpll_mask =
3212 			BIT(DPLL_ID_DG1_DPLL3) |
3213 			BIT(DPLL_ID_DG1_DPLL2) |
3214 			BIT(DPLL_ID_ICL_DPLL1) |
3215 			BIT(DPLL_ID_ICL_DPLL0);
3216 	} else if (IS_DG1(dev_priv)) {
3217 		if (port == PORT_D || port == PORT_E) {
3218 			dpll_mask =
3219 				BIT(DPLL_ID_DG1_DPLL2) |
3220 				BIT(DPLL_ID_DG1_DPLL3);
3221 		} else {
3222 			dpll_mask =
3223 				BIT(DPLL_ID_DG1_DPLL0) |
3224 				BIT(DPLL_ID_DG1_DPLL1);
3225 		}
3226 	} else if (IS_ROCKETLAKE(dev_priv)) {
3227 		dpll_mask =
3228 			BIT(DPLL_ID_EHL_DPLL4) |
3229 			BIT(DPLL_ID_ICL_DPLL1) |
3230 			BIT(DPLL_ID_ICL_DPLL0);
3231 	} else if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
3232 				port != PORT_A) {
3233 		dpll_mask =
3234 			BIT(DPLL_ID_EHL_DPLL4) |
3235 			BIT(DPLL_ID_ICL_DPLL1) |
3236 			BIT(DPLL_ID_ICL_DPLL0);
3237 	} else {
3238 		dpll_mask = BIT(DPLL_ID_ICL_DPLL1) | BIT(DPLL_ID_ICL_DPLL0);
3239 	}
3240 
3241 	/* Eliminate DPLLs from consideration if reserved by HTI */
3242 	dpll_mask &= ~intel_hti_dpll_mask(dev_priv);
3243 
3244 	port_dpll->pll = intel_find_shared_dpll(state, crtc,
3245 						&port_dpll->hw_state,
3246 						dpll_mask);
3247 	if (!port_dpll->pll)
3248 		return -EINVAL;
3249 
3250 	intel_reference_shared_dpll(state, crtc,
3251 				    port_dpll->pll, &port_dpll->hw_state);
3252 
3253 	icl_update_active_dpll(state, crtc, encoder);
3254 
3255 	return 0;
3256 }
3257 
3258 static int icl_compute_tc_phy_dplls(struct intel_atomic_state *state,
3259 				    struct intel_crtc *crtc)
3260 {
3261 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3262 	struct intel_crtc_state *crtc_state =
3263 		intel_atomic_get_new_crtc_state(state, crtc);
3264 	struct icl_port_dpll *port_dpll =
3265 		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3266 	struct skl_wrpll_params pll_params = {};
3267 	int ret;
3268 
3269 	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3270 	ret = icl_calc_tbt_pll(crtc_state, &pll_params);
3271 	if (ret)
3272 		return ret;
3273 
3274 	icl_calc_dpll_state(dev_priv, &pll_params, &port_dpll->hw_state);
3275 
3276 	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
3277 	ret = icl_calc_mg_pll_state(crtc_state, &port_dpll->hw_state);
3278 	if (ret)
3279 		return ret;
3280 
3281 	/* this is mainly for the fastset check */
3282 	icl_set_active_port_dpll(crtc_state, ICL_PORT_DPLL_MG_PHY);
3283 
3284 	crtc_state->port_clock = icl_ddi_mg_pll_get_freq(dev_priv, NULL,
3285 							 &port_dpll->hw_state);
3286 
3287 	return 0;
3288 }
3289 
3290 static int icl_get_tc_phy_dplls(struct intel_atomic_state *state,
3291 				struct intel_crtc *crtc,
3292 				struct intel_encoder *encoder)
3293 {
3294 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3295 	struct intel_crtc_state *crtc_state =
3296 		intel_atomic_get_new_crtc_state(state, crtc);
3297 	struct icl_port_dpll *port_dpll =
3298 		&crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3299 	enum intel_dpll_id dpll_id;
3300 	int ret;
3301 
3302 	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3303 	port_dpll->pll = intel_find_shared_dpll(state, crtc,
3304 						&port_dpll->hw_state,
3305 						BIT(DPLL_ID_ICL_TBTPLL));
3306 	if (!port_dpll->pll)
3307 		return -EINVAL;
3308 	intel_reference_shared_dpll(state, crtc,
3309 				    port_dpll->pll, &port_dpll->hw_state);
3310 
3311 
3312 	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_MG_PHY];
3313 	dpll_id = icl_tc_port_to_pll_id(intel_port_to_tc(dev_priv,
3314 							 encoder->port));
3315 	port_dpll->pll = intel_find_shared_dpll(state, crtc,
3316 						&port_dpll->hw_state,
3317 						BIT(dpll_id));
3318 	if (!port_dpll->pll) {
3319 		ret = -EINVAL;
3320 		goto err_unreference_tbt_pll;
3321 	}
3322 	intel_reference_shared_dpll(state, crtc,
3323 				    port_dpll->pll, &port_dpll->hw_state);
3324 
3325 	icl_update_active_dpll(state, crtc, encoder);
3326 
3327 	return 0;
3328 
3329 err_unreference_tbt_pll:
3330 	port_dpll = &crtc_state->icl_port_dplls[ICL_PORT_DPLL_DEFAULT];
3331 	intel_unreference_shared_dpll(state, crtc, port_dpll->pll);
3332 
3333 	return ret;
3334 }
3335 
3336 static int icl_compute_dplls(struct intel_atomic_state *state,
3337 			     struct intel_crtc *crtc,
3338 			     struct intel_encoder *encoder)
3339 {
3340 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3341 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3342 
3343 	if (intel_phy_is_combo(dev_priv, phy))
3344 		return icl_compute_combo_phy_dpll(state, crtc);
3345 	else if (intel_phy_is_tc(dev_priv, phy))
3346 		return icl_compute_tc_phy_dplls(state, crtc);
3347 
3348 	MISSING_CASE(phy);
3349 
3350 	return 0;
3351 }
3352 
3353 static int icl_get_dplls(struct intel_atomic_state *state,
3354 			 struct intel_crtc *crtc,
3355 			 struct intel_encoder *encoder)
3356 {
3357 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
3358 	enum phy phy = intel_port_to_phy(dev_priv, encoder->port);
3359 
3360 	if (intel_phy_is_combo(dev_priv, phy))
3361 		return icl_get_combo_phy_dpll(state, crtc, encoder);
3362 	else if (intel_phy_is_tc(dev_priv, phy))
3363 		return icl_get_tc_phy_dplls(state, crtc, encoder);
3364 
3365 	MISSING_CASE(phy);
3366 
3367 	return -EINVAL;
3368 }
3369 
3370 static void icl_put_dplls(struct intel_atomic_state *state,
3371 			  struct intel_crtc *crtc)
3372 {
3373 	const struct intel_crtc_state *old_crtc_state =
3374 		intel_atomic_get_old_crtc_state(state, crtc);
3375 	struct intel_crtc_state *new_crtc_state =
3376 		intel_atomic_get_new_crtc_state(state, crtc);
3377 	enum icl_port_dpll_id id;
3378 
3379 	new_crtc_state->shared_dpll = NULL;
3380 
3381 	for (id = ICL_PORT_DPLL_DEFAULT; id < ICL_PORT_DPLL_COUNT; id++) {
3382 		const struct icl_port_dpll *old_port_dpll =
3383 			&old_crtc_state->icl_port_dplls[id];
3384 		struct icl_port_dpll *new_port_dpll =
3385 			&new_crtc_state->icl_port_dplls[id];
3386 
3387 		new_port_dpll->pll = NULL;
3388 
3389 		if (!old_port_dpll->pll)
3390 			continue;
3391 
3392 		intel_unreference_shared_dpll(state, crtc, old_port_dpll->pll);
3393 	}
3394 }
3395 
3396 static bool mg_pll_get_hw_state(struct drm_i915_private *dev_priv,
3397 				struct intel_shared_dpll *pll,
3398 				struct intel_dpll_hw_state *hw_state)
3399 {
3400 	const enum intel_dpll_id id = pll->info->id;
3401 	enum tc_port tc_port = icl_pll_id_to_tc_port(id);
3402 	intel_wakeref_t wakeref;
3403 	bool ret = false;
3404 	u32 val;
3405 
3406 	i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll);
3407 
3408 	wakeref = intel_display_power_get_if_enabled(dev_priv,
3409 						     POWER_DOMAIN_DISPLAY_CORE);
3410 	if (!wakeref)
3411 		return false;
3412 
3413 	val = intel_de_read(dev_priv, enable_reg);
3414 	if (!(val & PLL_ENABLE))
3415 		goto out;
3416 
3417 	hw_state->mg_refclkin_ctl = intel_de_read(dev_priv,
3418 						  MG_REFCLKIN_CTL(tc_port));
3419 	hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
3420 
3421 	hw_state->mg_clktop2_coreclkctl1 =
3422 		intel_de_read(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port));
3423 	hw_state->mg_clktop2_coreclkctl1 &=
3424 		MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3425 
3426 	hw_state->mg_clktop2_hsclkctl =
3427 		intel_de_read(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port));
3428 	hw_state->mg_clktop2_hsclkctl &=
3429 		MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3430 		MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3431 		MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3432 		MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
3433 
3434 	hw_state->mg_pll_div0 = intel_de_read(dev_priv, MG_PLL_DIV0(tc_port));
3435 	hw_state->mg_pll_div1 = intel_de_read(dev_priv, MG_PLL_DIV1(tc_port));
3436 	hw_state->mg_pll_lf = intel_de_read(dev_priv, MG_PLL_LF(tc_port));
3437 	hw_state->mg_pll_frac_lock = intel_de_read(dev_priv,
3438 						   MG_PLL_FRAC_LOCK(tc_port));
3439 	hw_state->mg_pll_ssc = intel_de_read(dev_priv, MG_PLL_SSC(tc_port));
3440 
3441 	hw_state->mg_pll_bias = intel_de_read(dev_priv, MG_PLL_BIAS(tc_port));
3442 	hw_state->mg_pll_tdc_coldst_bias =
3443 		intel_de_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port));
3444 
3445 	if (dev_priv->display.dpll.ref_clks.nssc == 38400) {
3446 		hw_state->mg_pll_tdc_coldst_bias_mask = MG_PLL_TDC_COLDST_COLDSTART;
3447 		hw_state->mg_pll_bias_mask = 0;
3448 	} else {
3449 		hw_state->mg_pll_tdc_coldst_bias_mask = -1U;
3450 		hw_state->mg_pll_bias_mask = -1U;
3451 	}
3452 
3453 	hw_state->mg_pll_tdc_coldst_bias &= hw_state->mg_pll_tdc_coldst_bias_mask;
3454 	hw_state->mg_pll_bias &= hw_state->mg_pll_bias_mask;
3455 
3456 	ret = true;
3457 out:
3458 	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
3459 	return ret;
3460 }
3461 
3462 static bool dkl_pll_get_hw_state(struct drm_i915_private *dev_priv,
3463 				 struct intel_shared_dpll *pll,
3464 				 struct intel_dpll_hw_state *hw_state)
3465 {
3466 	const enum intel_dpll_id id = pll->info->id;
3467 	enum tc_port tc_port = icl_pll_id_to_tc_port(id);
3468 	intel_wakeref_t wakeref;
3469 	bool ret = false;
3470 	u32 val;
3471 
3472 	wakeref = intel_display_power_get_if_enabled(dev_priv,
3473 						     POWER_DOMAIN_DISPLAY_CORE);
3474 	if (!wakeref)
3475 		return false;
3476 
3477 	val = intel_de_read(dev_priv, intel_tc_pll_enable_reg(dev_priv, pll));
3478 	if (!(val & PLL_ENABLE))
3479 		goto out;
3480 
3481 	/*
3482 	 * All registers read here have the same HIP_INDEX_REG even though
3483 	 * they are on different building blocks
3484 	 */
3485 	hw_state->mg_refclkin_ctl = intel_dkl_phy_read(dev_priv,
3486 						       DKL_REFCLKIN_CTL(tc_port));
3487 	hw_state->mg_refclkin_ctl &= MG_REFCLKIN_CTL_OD_2_MUX_MASK;
3488 
3489 	hw_state->mg_clktop2_hsclkctl =
3490 		intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port));
3491 	hw_state->mg_clktop2_hsclkctl &=
3492 		MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3493 		MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3494 		MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3495 		MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK;
3496 
3497 	hw_state->mg_clktop2_coreclkctl1 =
3498 		intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port));
3499 	hw_state->mg_clktop2_coreclkctl1 &=
3500 		MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3501 
3502 	hw_state->mg_pll_div0 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV0(tc_port));
3503 	val = DKL_PLL_DIV0_MASK;
3504 	if (dev_priv->display.vbt.override_afc_startup)
3505 		val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
3506 	hw_state->mg_pll_div0 &= val;
3507 
3508 	hw_state->mg_pll_div1 = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port));
3509 	hw_state->mg_pll_div1 &= (DKL_PLL_DIV1_IREF_TRIM_MASK |
3510 				  DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
3511 
3512 	hw_state->mg_pll_ssc = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port));
3513 	hw_state->mg_pll_ssc &= (DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
3514 				 DKL_PLL_SSC_STEP_LEN_MASK |
3515 				 DKL_PLL_SSC_STEP_NUM_MASK |
3516 				 DKL_PLL_SSC_EN);
3517 
3518 	hw_state->mg_pll_bias = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port));
3519 	hw_state->mg_pll_bias &= (DKL_PLL_BIAS_FRAC_EN_H |
3520 				  DKL_PLL_BIAS_FBDIV_FRAC_MASK);
3521 
3522 	hw_state->mg_pll_tdc_coldst_bias =
3523 		intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port));
3524 	hw_state->mg_pll_tdc_coldst_bias &= (DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
3525 					     DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
3526 
3527 	ret = true;
3528 out:
3529 	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
3530 	return ret;
3531 }
3532 
3533 static bool icl_pll_get_hw_state(struct drm_i915_private *dev_priv,
3534 				 struct intel_shared_dpll *pll,
3535 				 struct intel_dpll_hw_state *hw_state,
3536 				 i915_reg_t enable_reg)
3537 {
3538 	const enum intel_dpll_id id = pll->info->id;
3539 	intel_wakeref_t wakeref;
3540 	bool ret = false;
3541 	u32 val;
3542 
3543 	wakeref = intel_display_power_get_if_enabled(dev_priv,
3544 						     POWER_DOMAIN_DISPLAY_CORE);
3545 	if (!wakeref)
3546 		return false;
3547 
3548 	val = intel_de_read(dev_priv, enable_reg);
3549 	if (!(val & PLL_ENABLE))
3550 		goto out;
3551 
3552 	if (IS_ALDERLAKE_S(dev_priv)) {
3553 		hw_state->cfgcr0 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR0(id));
3554 		hw_state->cfgcr1 = intel_de_read(dev_priv, ADLS_DPLL_CFGCR1(id));
3555 	} else if (IS_DG1(dev_priv)) {
3556 		hw_state->cfgcr0 = intel_de_read(dev_priv, DG1_DPLL_CFGCR0(id));
3557 		hw_state->cfgcr1 = intel_de_read(dev_priv, DG1_DPLL_CFGCR1(id));
3558 	} else if (IS_ROCKETLAKE(dev_priv)) {
3559 		hw_state->cfgcr0 = intel_de_read(dev_priv,
3560 						 RKL_DPLL_CFGCR0(id));
3561 		hw_state->cfgcr1 = intel_de_read(dev_priv,
3562 						 RKL_DPLL_CFGCR1(id));
3563 	} else if (DISPLAY_VER(dev_priv) >= 12) {
3564 		hw_state->cfgcr0 = intel_de_read(dev_priv,
3565 						 TGL_DPLL_CFGCR0(id));
3566 		hw_state->cfgcr1 = intel_de_read(dev_priv,
3567 						 TGL_DPLL_CFGCR1(id));
3568 		if (dev_priv->display.vbt.override_afc_startup) {
3569 			hw_state->div0 = intel_de_read(dev_priv, TGL_DPLL0_DIV0(id));
3570 			hw_state->div0 &= TGL_DPLL0_DIV0_AFC_STARTUP_MASK;
3571 		}
3572 	} else {
3573 		if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
3574 		    id == DPLL_ID_EHL_DPLL4) {
3575 			hw_state->cfgcr0 = intel_de_read(dev_priv,
3576 							 ICL_DPLL_CFGCR0(4));
3577 			hw_state->cfgcr1 = intel_de_read(dev_priv,
3578 							 ICL_DPLL_CFGCR1(4));
3579 		} else {
3580 			hw_state->cfgcr0 = intel_de_read(dev_priv,
3581 							 ICL_DPLL_CFGCR0(id));
3582 			hw_state->cfgcr1 = intel_de_read(dev_priv,
3583 							 ICL_DPLL_CFGCR1(id));
3584 		}
3585 	}
3586 
3587 	ret = true;
3588 out:
3589 	intel_display_power_put(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref);
3590 	return ret;
3591 }
3592 
3593 static bool combo_pll_get_hw_state(struct drm_i915_private *dev_priv,
3594 				   struct intel_shared_dpll *pll,
3595 				   struct intel_dpll_hw_state *hw_state)
3596 {
3597 	i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
3598 
3599 	return icl_pll_get_hw_state(dev_priv, pll, hw_state, enable_reg);
3600 }
3601 
3602 static bool tbt_pll_get_hw_state(struct drm_i915_private *dev_priv,
3603 				 struct intel_shared_dpll *pll,
3604 				 struct intel_dpll_hw_state *hw_state)
3605 {
3606 	return icl_pll_get_hw_state(dev_priv, pll, hw_state, TBT_PLL_ENABLE);
3607 }
3608 
3609 static void icl_dpll_write(struct drm_i915_private *dev_priv,
3610 			   struct intel_shared_dpll *pll)
3611 {
3612 	struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
3613 	const enum intel_dpll_id id = pll->info->id;
3614 	i915_reg_t cfgcr0_reg, cfgcr1_reg, div0_reg = INVALID_MMIO_REG;
3615 
3616 	if (IS_ALDERLAKE_S(dev_priv)) {
3617 		cfgcr0_reg = ADLS_DPLL_CFGCR0(id);
3618 		cfgcr1_reg = ADLS_DPLL_CFGCR1(id);
3619 	} else if (IS_DG1(dev_priv)) {
3620 		cfgcr0_reg = DG1_DPLL_CFGCR0(id);
3621 		cfgcr1_reg = DG1_DPLL_CFGCR1(id);
3622 	} else if (IS_ROCKETLAKE(dev_priv)) {
3623 		cfgcr0_reg = RKL_DPLL_CFGCR0(id);
3624 		cfgcr1_reg = RKL_DPLL_CFGCR1(id);
3625 	} else if (DISPLAY_VER(dev_priv) >= 12) {
3626 		cfgcr0_reg = TGL_DPLL_CFGCR0(id);
3627 		cfgcr1_reg = TGL_DPLL_CFGCR1(id);
3628 		div0_reg = TGL_DPLL0_DIV0(id);
3629 	} else {
3630 		if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
3631 		    id == DPLL_ID_EHL_DPLL4) {
3632 			cfgcr0_reg = ICL_DPLL_CFGCR0(4);
3633 			cfgcr1_reg = ICL_DPLL_CFGCR1(4);
3634 		} else {
3635 			cfgcr0_reg = ICL_DPLL_CFGCR0(id);
3636 			cfgcr1_reg = ICL_DPLL_CFGCR1(id);
3637 		}
3638 	}
3639 
3640 	intel_de_write(dev_priv, cfgcr0_reg, hw_state->cfgcr0);
3641 	intel_de_write(dev_priv, cfgcr1_reg, hw_state->cfgcr1);
3642 	drm_WARN_ON_ONCE(&dev_priv->drm, dev_priv->display.vbt.override_afc_startup &&
3643 			 !i915_mmio_reg_valid(div0_reg));
3644 	if (dev_priv->display.vbt.override_afc_startup &&
3645 	    i915_mmio_reg_valid(div0_reg))
3646 		intel_de_rmw(dev_priv, div0_reg,
3647 			     TGL_DPLL0_DIV0_AFC_STARTUP_MASK, hw_state->div0);
3648 	intel_de_posting_read(dev_priv, cfgcr1_reg);
3649 }
3650 
3651 static void icl_mg_pll_write(struct drm_i915_private *dev_priv,
3652 			     struct intel_shared_dpll *pll)
3653 {
3654 	struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
3655 	enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
3656 
3657 	/*
3658 	 * Some of the following registers have reserved fields, so program
3659 	 * these with RMW based on a mask. The mask can be fixed or generated
3660 	 * during the calc/readout phase if the mask depends on some other HW
3661 	 * state like refclk, see icl_calc_mg_pll_state().
3662 	 */
3663 	intel_de_rmw(dev_priv, MG_REFCLKIN_CTL(tc_port),
3664 		     MG_REFCLKIN_CTL_OD_2_MUX_MASK, hw_state->mg_refclkin_ctl);
3665 
3666 	intel_de_rmw(dev_priv, MG_CLKTOP2_CORECLKCTL1(tc_port),
3667 		     MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK,
3668 		     hw_state->mg_clktop2_coreclkctl1);
3669 
3670 	intel_de_rmw(dev_priv, MG_CLKTOP2_HSCLKCTL(tc_port),
3671 		     MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3672 		     MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3673 		     MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3674 		     MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK,
3675 		     hw_state->mg_clktop2_hsclkctl);
3676 
3677 	intel_de_write(dev_priv, MG_PLL_DIV0(tc_port), hw_state->mg_pll_div0);
3678 	intel_de_write(dev_priv, MG_PLL_DIV1(tc_port), hw_state->mg_pll_div1);
3679 	intel_de_write(dev_priv, MG_PLL_LF(tc_port), hw_state->mg_pll_lf);
3680 	intel_de_write(dev_priv, MG_PLL_FRAC_LOCK(tc_port),
3681 		       hw_state->mg_pll_frac_lock);
3682 	intel_de_write(dev_priv, MG_PLL_SSC(tc_port), hw_state->mg_pll_ssc);
3683 
3684 	intel_de_rmw(dev_priv, MG_PLL_BIAS(tc_port),
3685 		     hw_state->mg_pll_bias_mask, hw_state->mg_pll_bias);
3686 
3687 	intel_de_rmw(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port),
3688 		     hw_state->mg_pll_tdc_coldst_bias_mask,
3689 		     hw_state->mg_pll_tdc_coldst_bias);
3690 
3691 	intel_de_posting_read(dev_priv, MG_PLL_TDC_COLDST_BIAS(tc_port));
3692 }
3693 
3694 static void dkl_pll_write(struct drm_i915_private *dev_priv,
3695 			  struct intel_shared_dpll *pll)
3696 {
3697 	struct intel_dpll_hw_state *hw_state = &pll->state.hw_state;
3698 	enum tc_port tc_port = icl_pll_id_to_tc_port(pll->info->id);
3699 	u32 val;
3700 
3701 	/*
3702 	 * All registers programmed here have the same HIP_INDEX_REG even
3703 	 * though on different building block
3704 	 */
3705 	/* All the registers are RMW */
3706 	val = intel_dkl_phy_read(dev_priv, DKL_REFCLKIN_CTL(tc_port));
3707 	val &= ~MG_REFCLKIN_CTL_OD_2_MUX_MASK;
3708 	val |= hw_state->mg_refclkin_ctl;
3709 	intel_dkl_phy_write(dev_priv, DKL_REFCLKIN_CTL(tc_port), val);
3710 
3711 	val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port));
3712 	val &= ~MG_CLKTOP2_CORECLKCTL1_A_DIVRATIO_MASK;
3713 	val |= hw_state->mg_clktop2_coreclkctl1;
3714 	intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_CORECLKCTL1(tc_port), val);
3715 
3716 	val = intel_dkl_phy_read(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port));
3717 	val &= ~(MG_CLKTOP2_HSCLKCTL_TLINEDRV_CLKSEL_MASK |
3718 		 MG_CLKTOP2_HSCLKCTL_CORE_INPUTSEL_MASK |
3719 		 MG_CLKTOP2_HSCLKCTL_HSDIV_RATIO_MASK |
3720 		 MG_CLKTOP2_HSCLKCTL_DSDIV_RATIO_MASK);
3721 	val |= hw_state->mg_clktop2_hsclkctl;
3722 	intel_dkl_phy_write(dev_priv, DKL_CLKTOP2_HSCLKCTL(tc_port), val);
3723 
3724 	val = DKL_PLL_DIV0_MASK;
3725 	if (dev_priv->display.vbt.override_afc_startup)
3726 		val |= DKL_PLL_DIV0_AFC_STARTUP_MASK;
3727 	intel_dkl_phy_rmw(dev_priv, DKL_PLL_DIV0(tc_port), val,
3728 			  hw_state->mg_pll_div0);
3729 
3730 	val = intel_dkl_phy_read(dev_priv, DKL_PLL_DIV1(tc_port));
3731 	val &= ~(DKL_PLL_DIV1_IREF_TRIM_MASK |
3732 		 DKL_PLL_DIV1_TDC_TARGET_CNT_MASK);
3733 	val |= hw_state->mg_pll_div1;
3734 	intel_dkl_phy_write(dev_priv, DKL_PLL_DIV1(tc_port), val);
3735 
3736 	val = intel_dkl_phy_read(dev_priv, DKL_PLL_SSC(tc_port));
3737 	val &= ~(DKL_PLL_SSC_IREF_NDIV_RATIO_MASK |
3738 		 DKL_PLL_SSC_STEP_LEN_MASK |
3739 		 DKL_PLL_SSC_STEP_NUM_MASK |
3740 		 DKL_PLL_SSC_EN);
3741 	val |= hw_state->mg_pll_ssc;
3742 	intel_dkl_phy_write(dev_priv, DKL_PLL_SSC(tc_port), val);
3743 
3744 	val = intel_dkl_phy_read(dev_priv, DKL_PLL_BIAS(tc_port));
3745 	val &= ~(DKL_PLL_BIAS_FRAC_EN_H |
3746 		 DKL_PLL_BIAS_FBDIV_FRAC_MASK);
3747 	val |= hw_state->mg_pll_bias;
3748 	intel_dkl_phy_write(dev_priv, DKL_PLL_BIAS(tc_port), val);
3749 
3750 	val = intel_dkl_phy_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port));
3751 	val &= ~(DKL_PLL_TDC_SSC_STEP_SIZE_MASK |
3752 		 DKL_PLL_TDC_FEED_FWD_GAIN_MASK);
3753 	val |= hw_state->mg_pll_tdc_coldst_bias;
3754 	intel_dkl_phy_write(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port), val);
3755 
3756 	intel_dkl_phy_posting_read(dev_priv, DKL_PLL_TDC_COLDST_BIAS(tc_port));
3757 }
3758 
3759 static void icl_pll_power_enable(struct drm_i915_private *dev_priv,
3760 				 struct intel_shared_dpll *pll,
3761 				 i915_reg_t enable_reg)
3762 {
3763 	intel_de_rmw(dev_priv, enable_reg, 0, PLL_POWER_ENABLE);
3764 
3765 	/*
3766 	 * The spec says we need to "wait" but it also says it should be
3767 	 * immediate.
3768 	 */
3769 	if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_POWER_STATE, 1))
3770 		drm_err(&dev_priv->drm, "PLL %d Power not enabled\n",
3771 			pll->info->id);
3772 }
3773 
3774 static void icl_pll_enable(struct drm_i915_private *dev_priv,
3775 			   struct intel_shared_dpll *pll,
3776 			   i915_reg_t enable_reg)
3777 {
3778 	intel_de_rmw(dev_priv, enable_reg, 0, PLL_ENABLE);
3779 
3780 	/* Timeout is actually 600us. */
3781 	if (intel_de_wait_for_set(dev_priv, enable_reg, PLL_LOCK, 1))
3782 		drm_err(&dev_priv->drm, "PLL %d not locked\n", pll->info->id);
3783 }
3784 
3785 static void adlp_cmtg_clock_gating_wa(struct drm_i915_private *i915, struct intel_shared_dpll *pll)
3786 {
3787 	u32 val;
3788 
3789 	if (!(IS_ALDERLAKE_P(i915) && IS_DISPLAY_STEP(i915, STEP_A0, STEP_B0)) ||
3790 	    pll->info->id != DPLL_ID_ICL_DPLL0)
3791 		return;
3792 	/*
3793 	 * Wa_16011069516:adl-p[a0]
3794 	 *
3795 	 * All CMTG regs are unreliable until CMTG clock gating is disabled,
3796 	 * so we can only assume the default TRANS_CMTG_CHICKEN reg value and
3797 	 * sanity check this assumption with a double read, which presumably
3798 	 * returns the correct value even with clock gating on.
3799 	 *
3800 	 * Instead of the usual place for workarounds we apply this one here,
3801 	 * since TRANS_CMTG_CHICKEN is only accessible while DPLL0 is enabled.
3802 	 */
3803 	val = intel_de_read(i915, TRANS_CMTG_CHICKEN);
3804 	val = intel_de_rmw(i915, TRANS_CMTG_CHICKEN, ~0, DISABLE_DPT_CLK_GATING);
3805 	if (drm_WARN_ON(&i915->drm, val & ~DISABLE_DPT_CLK_GATING))
3806 		drm_dbg_kms(&i915->drm, "Unexpected flags in TRANS_CMTG_CHICKEN: %08x\n", val);
3807 }
3808 
3809 static void combo_pll_enable(struct drm_i915_private *dev_priv,
3810 			     struct intel_shared_dpll *pll)
3811 {
3812 	i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
3813 
3814 	if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
3815 	    pll->info->id == DPLL_ID_EHL_DPLL4) {
3816 
3817 		/*
3818 		 * We need to disable DC states when this DPLL is enabled.
3819 		 * This can be done by taking a reference on DPLL4 power
3820 		 * domain.
3821 		 */
3822 		pll->wakeref = intel_display_power_get(dev_priv,
3823 						       POWER_DOMAIN_DC_OFF);
3824 	}
3825 
3826 	icl_pll_power_enable(dev_priv, pll, enable_reg);
3827 
3828 	icl_dpll_write(dev_priv, pll);
3829 
3830 	/*
3831 	 * DVFS pre sequence would be here, but in our driver the cdclk code
3832 	 * paths should already be setting the appropriate voltage, hence we do
3833 	 * nothing here.
3834 	 */
3835 
3836 	icl_pll_enable(dev_priv, pll, enable_reg);
3837 
3838 	adlp_cmtg_clock_gating_wa(dev_priv, pll);
3839 
3840 	/* DVFS post sequence would be here. See the comment above. */
3841 }
3842 
3843 static void tbt_pll_enable(struct drm_i915_private *dev_priv,
3844 			   struct intel_shared_dpll *pll)
3845 {
3846 	icl_pll_power_enable(dev_priv, pll, TBT_PLL_ENABLE);
3847 
3848 	icl_dpll_write(dev_priv, pll);
3849 
3850 	/*
3851 	 * DVFS pre sequence would be here, but in our driver the cdclk code
3852 	 * paths should already be setting the appropriate voltage, hence we do
3853 	 * nothing here.
3854 	 */
3855 
3856 	icl_pll_enable(dev_priv, pll, TBT_PLL_ENABLE);
3857 
3858 	/* DVFS post sequence would be here. See the comment above. */
3859 }
3860 
3861 static void mg_pll_enable(struct drm_i915_private *dev_priv,
3862 			  struct intel_shared_dpll *pll)
3863 {
3864 	i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll);
3865 
3866 	icl_pll_power_enable(dev_priv, pll, enable_reg);
3867 
3868 	if (DISPLAY_VER(dev_priv) >= 12)
3869 		dkl_pll_write(dev_priv, pll);
3870 	else
3871 		icl_mg_pll_write(dev_priv, pll);
3872 
3873 	/*
3874 	 * DVFS pre sequence would be here, but in our driver the cdclk code
3875 	 * paths should already be setting the appropriate voltage, hence we do
3876 	 * nothing here.
3877 	 */
3878 
3879 	icl_pll_enable(dev_priv, pll, enable_reg);
3880 
3881 	/* DVFS post sequence would be here. See the comment above. */
3882 }
3883 
3884 static void icl_pll_disable(struct drm_i915_private *dev_priv,
3885 			    struct intel_shared_dpll *pll,
3886 			    i915_reg_t enable_reg)
3887 {
3888 	/* The first steps are done by intel_ddi_post_disable(). */
3889 
3890 	/*
3891 	 * DVFS pre sequence would be here, but in our driver the cdclk code
3892 	 * paths should already be setting the appropriate voltage, hence we do
3893 	 * nothing here.
3894 	 */
3895 
3896 	intel_de_rmw(dev_priv, enable_reg, PLL_ENABLE, 0);
3897 
3898 	/* Timeout is actually 1us. */
3899 	if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_LOCK, 1))
3900 		drm_err(&dev_priv->drm, "PLL %d locked\n", pll->info->id);
3901 
3902 	/* DVFS post sequence would be here. See the comment above. */
3903 
3904 	intel_de_rmw(dev_priv, enable_reg, PLL_POWER_ENABLE, 0);
3905 
3906 	/*
3907 	 * The spec says we need to "wait" but it also says it should be
3908 	 * immediate.
3909 	 */
3910 	if (intel_de_wait_for_clear(dev_priv, enable_reg, PLL_POWER_STATE, 1))
3911 		drm_err(&dev_priv->drm, "PLL %d Power not disabled\n",
3912 			pll->info->id);
3913 }
3914 
3915 static void combo_pll_disable(struct drm_i915_private *dev_priv,
3916 			      struct intel_shared_dpll *pll)
3917 {
3918 	i915_reg_t enable_reg = intel_combo_pll_enable_reg(dev_priv, pll);
3919 
3920 	icl_pll_disable(dev_priv, pll, enable_reg);
3921 
3922 	if ((IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv)) &&
3923 	    pll->info->id == DPLL_ID_EHL_DPLL4)
3924 		intel_display_power_put(dev_priv, POWER_DOMAIN_DC_OFF,
3925 					pll->wakeref);
3926 }
3927 
3928 static void tbt_pll_disable(struct drm_i915_private *dev_priv,
3929 			    struct intel_shared_dpll *pll)
3930 {
3931 	icl_pll_disable(dev_priv, pll, TBT_PLL_ENABLE);
3932 }
3933 
3934 static void mg_pll_disable(struct drm_i915_private *dev_priv,
3935 			   struct intel_shared_dpll *pll)
3936 {
3937 	i915_reg_t enable_reg = intel_tc_pll_enable_reg(dev_priv, pll);
3938 
3939 	icl_pll_disable(dev_priv, pll, enable_reg);
3940 }
3941 
3942 static void icl_update_dpll_ref_clks(struct drm_i915_private *i915)
3943 {
3944 	/* No SSC ref */
3945 	i915->display.dpll.ref_clks.nssc = i915->display.cdclk.hw.ref;
3946 }
3947 
3948 static void icl_dump_hw_state(struct drm_i915_private *dev_priv,
3949 			      const struct intel_dpll_hw_state *hw_state)
3950 {
3951 	drm_dbg_kms(&dev_priv->drm,
3952 		    "dpll_hw_state: cfgcr0: 0x%x, cfgcr1: 0x%x, div0: 0x%x, "
3953 		    "mg_refclkin_ctl: 0x%x, hg_clktop2_coreclkctl1: 0x%x, "
3954 		    "mg_clktop2_hsclkctl: 0x%x, mg_pll_div0: 0x%x, "
3955 		    "mg_pll_div2: 0x%x, mg_pll_lf: 0x%x, "
3956 		    "mg_pll_frac_lock: 0x%x, mg_pll_ssc: 0x%x, "
3957 		    "mg_pll_bias: 0x%x, mg_pll_tdc_coldst_bias: 0x%x\n",
3958 		    hw_state->cfgcr0, hw_state->cfgcr1,
3959 		    hw_state->div0,
3960 		    hw_state->mg_refclkin_ctl,
3961 		    hw_state->mg_clktop2_coreclkctl1,
3962 		    hw_state->mg_clktop2_hsclkctl,
3963 		    hw_state->mg_pll_div0,
3964 		    hw_state->mg_pll_div1,
3965 		    hw_state->mg_pll_lf,
3966 		    hw_state->mg_pll_frac_lock,
3967 		    hw_state->mg_pll_ssc,
3968 		    hw_state->mg_pll_bias,
3969 		    hw_state->mg_pll_tdc_coldst_bias);
3970 }
3971 
3972 static const struct intel_shared_dpll_funcs combo_pll_funcs = {
3973 	.enable = combo_pll_enable,
3974 	.disable = combo_pll_disable,
3975 	.get_hw_state = combo_pll_get_hw_state,
3976 	.get_freq = icl_ddi_combo_pll_get_freq,
3977 };
3978 
3979 static const struct intel_shared_dpll_funcs tbt_pll_funcs = {
3980 	.enable = tbt_pll_enable,
3981 	.disable = tbt_pll_disable,
3982 	.get_hw_state = tbt_pll_get_hw_state,
3983 	.get_freq = icl_ddi_tbt_pll_get_freq,
3984 };
3985 
3986 static const struct intel_shared_dpll_funcs mg_pll_funcs = {
3987 	.enable = mg_pll_enable,
3988 	.disable = mg_pll_disable,
3989 	.get_hw_state = mg_pll_get_hw_state,
3990 	.get_freq = icl_ddi_mg_pll_get_freq,
3991 };
3992 
3993 static const struct dpll_info icl_plls[] = {
3994 	{ "DPLL 0",   &combo_pll_funcs, DPLL_ID_ICL_DPLL0,  0 },
3995 	{ "DPLL 1",   &combo_pll_funcs, DPLL_ID_ICL_DPLL1,  0 },
3996 	{ "TBT PLL",  &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
3997 	{ "MG PLL 1", &mg_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
3998 	{ "MG PLL 2", &mg_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
3999 	{ "MG PLL 3", &mg_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
4000 	{ "MG PLL 4", &mg_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
4001 	{ },
4002 };
4003 
4004 static const struct intel_dpll_mgr icl_pll_mgr = {
4005 	.dpll_info = icl_plls,
4006 	.compute_dplls = icl_compute_dplls,
4007 	.get_dplls = icl_get_dplls,
4008 	.put_dplls = icl_put_dplls,
4009 	.update_active_dpll = icl_update_active_dpll,
4010 	.update_ref_clks = icl_update_dpll_ref_clks,
4011 	.dump_hw_state = icl_dump_hw_state,
4012 };
4013 
4014 static const struct dpll_info ehl_plls[] = {
4015 	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4016 	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4017 	{ "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
4018 	{ },
4019 };
4020 
4021 static const struct intel_dpll_mgr ehl_pll_mgr = {
4022 	.dpll_info = ehl_plls,
4023 	.compute_dplls = icl_compute_dplls,
4024 	.get_dplls = icl_get_dplls,
4025 	.put_dplls = icl_put_dplls,
4026 	.update_ref_clks = icl_update_dpll_ref_clks,
4027 	.dump_hw_state = icl_dump_hw_state,
4028 };
4029 
4030 static const struct intel_shared_dpll_funcs dkl_pll_funcs = {
4031 	.enable = mg_pll_enable,
4032 	.disable = mg_pll_disable,
4033 	.get_hw_state = dkl_pll_get_hw_state,
4034 	.get_freq = icl_ddi_mg_pll_get_freq,
4035 };
4036 
4037 static const struct dpll_info tgl_plls[] = {
4038 	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0,  0 },
4039 	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1,  0 },
4040 	{ "TBT PLL",  &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
4041 	{ "TC PLL 1", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
4042 	{ "TC PLL 2", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
4043 	{ "TC PLL 3", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
4044 	{ "TC PLL 4", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
4045 	{ "TC PLL 5", &dkl_pll_funcs, DPLL_ID_TGL_MGPLL5, 0 },
4046 	{ "TC PLL 6", &dkl_pll_funcs, DPLL_ID_TGL_MGPLL6, 0 },
4047 	{ },
4048 };
4049 
4050 static const struct intel_dpll_mgr tgl_pll_mgr = {
4051 	.dpll_info = tgl_plls,
4052 	.compute_dplls = icl_compute_dplls,
4053 	.get_dplls = icl_get_dplls,
4054 	.put_dplls = icl_put_dplls,
4055 	.update_active_dpll = icl_update_active_dpll,
4056 	.update_ref_clks = icl_update_dpll_ref_clks,
4057 	.dump_hw_state = icl_dump_hw_state,
4058 };
4059 
4060 static const struct dpll_info rkl_plls[] = {
4061 	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4062 	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4063 	{ "DPLL 4", &combo_pll_funcs, DPLL_ID_EHL_DPLL4, 0 },
4064 	{ },
4065 };
4066 
4067 static const struct intel_dpll_mgr rkl_pll_mgr = {
4068 	.dpll_info = rkl_plls,
4069 	.compute_dplls = icl_compute_dplls,
4070 	.get_dplls = icl_get_dplls,
4071 	.put_dplls = icl_put_dplls,
4072 	.update_ref_clks = icl_update_dpll_ref_clks,
4073 	.dump_hw_state = icl_dump_hw_state,
4074 };
4075 
4076 static const struct dpll_info dg1_plls[] = {
4077 	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_DG1_DPLL0, 0 },
4078 	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_DG1_DPLL1, 0 },
4079 	{ "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
4080 	{ "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
4081 	{ },
4082 };
4083 
4084 static const struct intel_dpll_mgr dg1_pll_mgr = {
4085 	.dpll_info = dg1_plls,
4086 	.compute_dplls = icl_compute_dplls,
4087 	.get_dplls = icl_get_dplls,
4088 	.put_dplls = icl_put_dplls,
4089 	.update_ref_clks = icl_update_dpll_ref_clks,
4090 	.dump_hw_state = icl_dump_hw_state,
4091 };
4092 
4093 static const struct dpll_info adls_plls[] = {
4094 	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0, 0 },
4095 	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1, 0 },
4096 	{ "DPLL 2", &combo_pll_funcs, DPLL_ID_DG1_DPLL2, 0 },
4097 	{ "DPLL 3", &combo_pll_funcs, DPLL_ID_DG1_DPLL3, 0 },
4098 	{ },
4099 };
4100 
4101 static const struct intel_dpll_mgr adls_pll_mgr = {
4102 	.dpll_info = adls_plls,
4103 	.compute_dplls = icl_compute_dplls,
4104 	.get_dplls = icl_get_dplls,
4105 	.put_dplls = icl_put_dplls,
4106 	.update_ref_clks = icl_update_dpll_ref_clks,
4107 	.dump_hw_state = icl_dump_hw_state,
4108 };
4109 
4110 static const struct dpll_info adlp_plls[] = {
4111 	{ "DPLL 0", &combo_pll_funcs, DPLL_ID_ICL_DPLL0,  0 },
4112 	{ "DPLL 1", &combo_pll_funcs, DPLL_ID_ICL_DPLL1,  0 },
4113 	{ "TBT PLL",  &tbt_pll_funcs, DPLL_ID_ICL_TBTPLL, 0 },
4114 	{ "TC PLL 1", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL1, 0 },
4115 	{ "TC PLL 2", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL2, 0 },
4116 	{ "TC PLL 3", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL3, 0 },
4117 	{ "TC PLL 4", &dkl_pll_funcs, DPLL_ID_ICL_MGPLL4, 0 },
4118 	{ },
4119 };
4120 
4121 static const struct intel_dpll_mgr adlp_pll_mgr = {
4122 	.dpll_info = adlp_plls,
4123 	.compute_dplls = icl_compute_dplls,
4124 	.get_dplls = icl_get_dplls,
4125 	.put_dplls = icl_put_dplls,
4126 	.update_active_dpll = icl_update_active_dpll,
4127 	.update_ref_clks = icl_update_dpll_ref_clks,
4128 	.dump_hw_state = icl_dump_hw_state,
4129 };
4130 
4131 /**
4132  * intel_shared_dpll_init - Initialize shared DPLLs
4133  * @dev_priv: i915 device
4134  *
4135  * Initialize shared DPLLs for @dev_priv.
4136  */
4137 void intel_shared_dpll_init(struct drm_i915_private *dev_priv)
4138 {
4139 	const struct intel_dpll_mgr *dpll_mgr = NULL;
4140 	const struct dpll_info *dpll_info;
4141 	int i;
4142 
4143 	mutex_init(&dev_priv->display.dpll.lock);
4144 
4145 	if (DISPLAY_VER(dev_priv) >= 14 || IS_DG2(dev_priv))
4146 		/* No shared DPLLs on DG2; port PLLs are part of the PHY */
4147 		dpll_mgr = NULL;
4148 	else if (IS_ALDERLAKE_P(dev_priv))
4149 		dpll_mgr = &adlp_pll_mgr;
4150 	else if (IS_ALDERLAKE_S(dev_priv))
4151 		dpll_mgr = &adls_pll_mgr;
4152 	else if (IS_DG1(dev_priv))
4153 		dpll_mgr = &dg1_pll_mgr;
4154 	else if (IS_ROCKETLAKE(dev_priv))
4155 		dpll_mgr = &rkl_pll_mgr;
4156 	else if (DISPLAY_VER(dev_priv) >= 12)
4157 		dpll_mgr = &tgl_pll_mgr;
4158 	else if (IS_JASPERLAKE(dev_priv) || IS_ELKHARTLAKE(dev_priv))
4159 		dpll_mgr = &ehl_pll_mgr;
4160 	else if (DISPLAY_VER(dev_priv) >= 11)
4161 		dpll_mgr = &icl_pll_mgr;
4162 	else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
4163 		dpll_mgr = &bxt_pll_mgr;
4164 	else if (DISPLAY_VER(dev_priv) == 9)
4165 		dpll_mgr = &skl_pll_mgr;
4166 	else if (HAS_DDI(dev_priv))
4167 		dpll_mgr = &hsw_pll_mgr;
4168 	else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))
4169 		dpll_mgr = &pch_pll_mgr;
4170 
4171 	if (!dpll_mgr) {
4172 		dev_priv->display.dpll.num_shared_dpll = 0;
4173 		return;
4174 	}
4175 
4176 	dpll_info = dpll_mgr->dpll_info;
4177 
4178 	for (i = 0; dpll_info[i].name; i++) {
4179 		if (drm_WARN_ON(&dev_priv->drm,
4180 				i >= ARRAY_SIZE(dev_priv->display.dpll.shared_dplls)))
4181 			break;
4182 
4183 		drm_WARN_ON(&dev_priv->drm, i != dpll_info[i].id);
4184 		dev_priv->display.dpll.shared_dplls[i].info = &dpll_info[i];
4185 	}
4186 
4187 	dev_priv->display.dpll.mgr = dpll_mgr;
4188 	dev_priv->display.dpll.num_shared_dpll = i;
4189 }
4190 
4191 /**
4192  * intel_compute_shared_dplls - compute DPLL state CRTC and encoder combination
4193  * @state: atomic state
4194  * @crtc: CRTC to compute DPLLs for
4195  * @encoder: encoder
4196  *
4197  * This function computes the DPLL state for the given CRTC and encoder.
4198  *
4199  * The new configuration in the atomic commit @state is made effective by
4200  * calling intel_shared_dpll_swap_state().
4201  *
4202  * Returns:
4203  * 0 on success, negative error code on falure.
4204  */
4205 int intel_compute_shared_dplls(struct intel_atomic_state *state,
4206 			       struct intel_crtc *crtc,
4207 			       struct intel_encoder *encoder)
4208 {
4209 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4210 	const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr;
4211 
4212 	if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
4213 		return -EINVAL;
4214 
4215 	return dpll_mgr->compute_dplls(state, crtc, encoder);
4216 }
4217 
4218 /**
4219  * intel_reserve_shared_dplls - reserve DPLLs for CRTC and encoder combination
4220  * @state: atomic state
4221  * @crtc: CRTC to reserve DPLLs for
4222  * @encoder: encoder
4223  *
4224  * This function reserves all required DPLLs for the given CRTC and encoder
4225  * combination in the current atomic commit @state and the new @crtc atomic
4226  * state.
4227  *
4228  * The new configuration in the atomic commit @state is made effective by
4229  * calling intel_shared_dpll_swap_state().
4230  *
4231  * The reserved DPLLs should be released by calling
4232  * intel_release_shared_dplls().
4233  *
4234  * Returns:
4235  * 0 if all required DPLLs were successfully reserved,
4236  * negative error code otherwise.
4237  */
4238 int intel_reserve_shared_dplls(struct intel_atomic_state *state,
4239 			       struct intel_crtc *crtc,
4240 			       struct intel_encoder *encoder)
4241 {
4242 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4243 	const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr;
4244 
4245 	if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
4246 		return -EINVAL;
4247 
4248 	return dpll_mgr->get_dplls(state, crtc, encoder);
4249 }
4250 
4251 /**
4252  * intel_release_shared_dplls - end use of DPLLs by CRTC in atomic state
4253  * @state: atomic state
4254  * @crtc: crtc from which the DPLLs are to be released
4255  *
4256  * This function releases all DPLLs reserved by intel_reserve_shared_dplls()
4257  * from the current atomic commit @state and the old @crtc atomic state.
4258  *
4259  * The new configuration in the atomic commit @state is made effective by
4260  * calling intel_shared_dpll_swap_state().
4261  */
4262 void intel_release_shared_dplls(struct intel_atomic_state *state,
4263 				struct intel_crtc *crtc)
4264 {
4265 	struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4266 	const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr;
4267 
4268 	/*
4269 	 * FIXME: this function is called for every platform having a
4270 	 * compute_clock hook, even though the platform doesn't yet support
4271 	 * the shared DPLL framework and intel_reserve_shared_dplls() is not
4272 	 * called on those.
4273 	 */
4274 	if (!dpll_mgr)
4275 		return;
4276 
4277 	dpll_mgr->put_dplls(state, crtc);
4278 }
4279 
4280 /**
4281  * intel_update_active_dpll - update the active DPLL for a CRTC/encoder
4282  * @state: atomic state
4283  * @crtc: the CRTC for which to update the active DPLL
4284  * @encoder: encoder determining the type of port DPLL
4285  *
4286  * Update the active DPLL for the given @crtc/@encoder in @crtc's atomic state,
4287  * from the port DPLLs reserved previously by intel_reserve_shared_dplls(). The
4288  * DPLL selected will be based on the current mode of the encoder's port.
4289  */
4290 void intel_update_active_dpll(struct intel_atomic_state *state,
4291 			      struct intel_crtc *crtc,
4292 			      struct intel_encoder *encoder)
4293 {
4294 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
4295 	const struct intel_dpll_mgr *dpll_mgr = dev_priv->display.dpll.mgr;
4296 
4297 	if (drm_WARN_ON(&dev_priv->drm, !dpll_mgr))
4298 		return;
4299 
4300 	dpll_mgr->update_active_dpll(state, crtc, encoder);
4301 }
4302 
4303 /**
4304  * intel_dpll_get_freq - calculate the DPLL's output frequency
4305  * @i915: i915 device
4306  * @pll: DPLL for which to calculate the output frequency
4307  * @pll_state: DPLL state from which to calculate the output frequency
4308  *
4309  * Return the output frequency corresponding to @pll's passed in @pll_state.
4310  */
4311 int intel_dpll_get_freq(struct drm_i915_private *i915,
4312 			const struct intel_shared_dpll *pll,
4313 			const struct intel_dpll_hw_state *pll_state)
4314 {
4315 	if (drm_WARN_ON(&i915->drm, !pll->info->funcs->get_freq))
4316 		return 0;
4317 
4318 	return pll->info->funcs->get_freq(i915, pll, pll_state);
4319 }
4320 
4321 /**
4322  * intel_dpll_get_hw_state - readout the DPLL's hardware state
4323  * @i915: i915 device
4324  * @pll: DPLL for which to calculate the output frequency
4325  * @hw_state: DPLL's hardware state
4326  *
4327  * Read out @pll's hardware state into @hw_state.
4328  */
4329 bool intel_dpll_get_hw_state(struct drm_i915_private *i915,
4330 			     struct intel_shared_dpll *pll,
4331 			     struct intel_dpll_hw_state *hw_state)
4332 {
4333 	return pll->info->funcs->get_hw_state(i915, pll, hw_state);
4334 }
4335 
4336 static void readout_dpll_hw_state(struct drm_i915_private *i915,
4337 				  struct intel_shared_dpll *pll)
4338 {
4339 	struct intel_crtc *crtc;
4340 
4341 	pll->on = intel_dpll_get_hw_state(i915, pll, &pll->state.hw_state);
4342 
4343 	if ((IS_JASPERLAKE(i915) || IS_ELKHARTLAKE(i915)) &&
4344 	    pll->on &&
4345 	    pll->info->id == DPLL_ID_EHL_DPLL4) {
4346 		pll->wakeref = intel_display_power_get(i915,
4347 						       POWER_DOMAIN_DC_OFF);
4348 	}
4349 
4350 	pll->state.pipe_mask = 0;
4351 	for_each_intel_crtc(&i915->drm, crtc) {
4352 		struct intel_crtc_state *crtc_state =
4353 			to_intel_crtc_state(crtc->base.state);
4354 
4355 		if (crtc_state->hw.active && crtc_state->shared_dpll == pll)
4356 			intel_reference_shared_dpll_crtc(crtc, pll, &pll->state);
4357 	}
4358 	pll->active_mask = pll->state.pipe_mask;
4359 
4360 	drm_dbg_kms(&i915->drm,
4361 		    "%s hw state readout: pipe_mask 0x%x, on %i\n",
4362 		    pll->info->name, pll->state.pipe_mask, pll->on);
4363 }
4364 
4365 void intel_dpll_update_ref_clks(struct drm_i915_private *i915)
4366 {
4367 	if (i915->display.dpll.mgr && i915->display.dpll.mgr->update_ref_clks)
4368 		i915->display.dpll.mgr->update_ref_clks(i915);
4369 }
4370 
4371 void intel_dpll_readout_hw_state(struct drm_i915_private *i915)
4372 {
4373 	int i;
4374 
4375 	for (i = 0; i < i915->display.dpll.num_shared_dpll; i++)
4376 		readout_dpll_hw_state(i915, &i915->display.dpll.shared_dplls[i]);
4377 }
4378 
4379 static void sanitize_dpll_state(struct drm_i915_private *i915,
4380 				struct intel_shared_dpll *pll)
4381 {
4382 	if (!pll->on)
4383 		return;
4384 
4385 	adlp_cmtg_clock_gating_wa(i915, pll);
4386 
4387 	if (pll->active_mask)
4388 		return;
4389 
4390 	drm_dbg_kms(&i915->drm,
4391 		    "%s enabled but not in use, disabling\n",
4392 		    pll->info->name);
4393 
4394 	pll->info->funcs->disable(i915, pll);
4395 	pll->on = false;
4396 }
4397 
4398 void intel_dpll_sanitize_state(struct drm_i915_private *i915)
4399 {
4400 	int i;
4401 
4402 	for (i = 0; i < i915->display.dpll.num_shared_dpll; i++)
4403 		sanitize_dpll_state(i915, &i915->display.dpll.shared_dplls[i]);
4404 }
4405 
4406 /**
4407  * intel_dpll_dump_hw_state - write hw_state to dmesg
4408  * @dev_priv: i915 drm device
4409  * @hw_state: hw state to be written to the log
4410  *
4411  * Write the relevant values in @hw_state to dmesg using drm_dbg_kms.
4412  */
4413 void intel_dpll_dump_hw_state(struct drm_i915_private *dev_priv,
4414 			      const struct intel_dpll_hw_state *hw_state)
4415 {
4416 	if (dev_priv->display.dpll.mgr) {
4417 		dev_priv->display.dpll.mgr->dump_hw_state(dev_priv, hw_state);
4418 	} else {
4419 		/* fallback for platforms that don't use the shared dpll
4420 		 * infrastructure
4421 		 */
4422 		drm_dbg_kms(&dev_priv->drm,
4423 			    "dpll_hw_state: dpll: 0x%x, dpll_md: 0x%x, "
4424 			    "fp0: 0x%x, fp1: 0x%x\n",
4425 			    hw_state->dpll,
4426 			    hw_state->dpll_md,
4427 			    hw_state->fp0,
4428 			    hw_state->fp1);
4429 	}
4430 }
4431 
4432 static void
4433 verify_single_dpll_state(struct drm_i915_private *dev_priv,
4434 			 struct intel_shared_dpll *pll,
4435 			 struct intel_crtc *crtc,
4436 			 struct intel_crtc_state *new_crtc_state)
4437 {
4438 	struct intel_dpll_hw_state dpll_hw_state;
4439 	u8 pipe_mask;
4440 	bool active;
4441 
4442 	memset(&dpll_hw_state, 0, sizeof(dpll_hw_state));
4443 
4444 	drm_dbg_kms(&dev_priv->drm, "%s\n", pll->info->name);
4445 
4446 	active = intel_dpll_get_hw_state(dev_priv, pll, &dpll_hw_state);
4447 
4448 	if (!(pll->info->flags & INTEL_DPLL_ALWAYS_ON)) {
4449 		I915_STATE_WARN(dev_priv, !pll->on && pll->active_mask,
4450 				"pll in active use but not on in sw tracking\n");
4451 		I915_STATE_WARN(dev_priv, pll->on && !pll->active_mask,
4452 				"pll is on but not used by any active pipe\n");
4453 		I915_STATE_WARN(dev_priv, pll->on != active,
4454 				"pll on state mismatch (expected %i, found %i)\n",
4455 				pll->on, active);
4456 	}
4457 
4458 	if (!crtc) {
4459 		I915_STATE_WARN(dev_priv,
4460 				pll->active_mask & ~pll->state.pipe_mask,
4461 				"more active pll users than references: 0x%x vs 0x%x\n",
4462 				pll->active_mask, pll->state.pipe_mask);
4463 
4464 		return;
4465 	}
4466 
4467 	pipe_mask = BIT(crtc->pipe);
4468 
4469 	if (new_crtc_state->hw.active)
4470 		I915_STATE_WARN(dev_priv, !(pll->active_mask & pipe_mask),
4471 				"pll active mismatch (expected pipe %c in active mask 0x%x)\n",
4472 				pipe_name(crtc->pipe), pll->active_mask);
4473 	else
4474 		I915_STATE_WARN(dev_priv, pll->active_mask & pipe_mask,
4475 				"pll active mismatch (didn't expect pipe %c in active mask 0x%x)\n",
4476 				pipe_name(crtc->pipe), pll->active_mask);
4477 
4478 	I915_STATE_WARN(dev_priv, !(pll->state.pipe_mask & pipe_mask),
4479 			"pll enabled crtcs mismatch (expected 0x%x in 0x%x)\n",
4480 			pipe_mask, pll->state.pipe_mask);
4481 
4482 	I915_STATE_WARN(dev_priv,
4483 			pll->on && memcmp(&pll->state.hw_state, &dpll_hw_state,
4484 					  sizeof(dpll_hw_state)),
4485 			"pll hw state mismatch\n");
4486 }
4487 
4488 void intel_shared_dpll_state_verify(struct intel_crtc *crtc,
4489 				    struct intel_crtc_state *old_crtc_state,
4490 				    struct intel_crtc_state *new_crtc_state)
4491 {
4492 	struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
4493 
4494 	if (new_crtc_state->shared_dpll)
4495 		verify_single_dpll_state(dev_priv, new_crtc_state->shared_dpll,
4496 					 crtc, new_crtc_state);
4497 
4498 	if (old_crtc_state->shared_dpll &&
4499 	    old_crtc_state->shared_dpll != new_crtc_state->shared_dpll) {
4500 		u8 pipe_mask = BIT(crtc->pipe);
4501 		struct intel_shared_dpll *pll = old_crtc_state->shared_dpll;
4502 
4503 		I915_STATE_WARN(dev_priv, pll->active_mask & pipe_mask,
4504 				"pll active mismatch (didn't expect pipe %c in active mask (0x%x))\n",
4505 				pipe_name(crtc->pipe), pll->active_mask);
4506 		I915_STATE_WARN(dev_priv, pll->state.pipe_mask & pipe_mask,
4507 				"pll enabled crtcs mismatch (found %x in enabled mask (0x%x))\n",
4508 				pipe_name(crtc->pipe), pll->state.pipe_mask);
4509 	}
4510 }
4511 
4512 void intel_shared_dpll_verify_disabled(struct drm_i915_private *i915)
4513 {
4514 	int i;
4515 
4516 	for (i = 0; i < i915->display.dpll.num_shared_dpll; i++)
4517 		verify_single_dpll_state(i915, &i915->display.dpll.shared_dplls[i],
4518 					 NULL, NULL);
4519 }
4520