1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/kernel.h> 7 8 #include "intel_crtc.h" 9 #include "intel_de.h" 10 #include "intel_display.h" 11 #include "intel_display_types.h" 12 #include "intel_dpll.h" 13 #include "intel_lvds.h" 14 #include "intel_panel.h" 15 #include "intel_pps.h" 16 #include "intel_snps_phy.h" 17 #include "vlv_sideband.h" 18 19 struct intel_limit { 20 struct { 21 int min, max; 22 } dot, vco, n, m, m1, m2, p, p1; 23 24 struct { 25 int dot_limit; 26 int p2_slow, p2_fast; 27 } p2; 28 }; 29 static const struct intel_limit intel_limits_i8xx_dac = { 30 .dot = { .min = 25000, .max = 350000 }, 31 .vco = { .min = 908000, .max = 1512000 }, 32 .n = { .min = 2, .max = 16 }, 33 .m = { .min = 96, .max = 140 }, 34 .m1 = { .min = 18, .max = 26 }, 35 .m2 = { .min = 6, .max = 16 }, 36 .p = { .min = 4, .max = 128 }, 37 .p1 = { .min = 2, .max = 33 }, 38 .p2 = { .dot_limit = 165000, 39 .p2_slow = 4, .p2_fast = 2 }, 40 }; 41 42 static const struct intel_limit intel_limits_i8xx_dvo = { 43 .dot = { .min = 25000, .max = 350000 }, 44 .vco = { .min = 908000, .max = 1512000 }, 45 .n = { .min = 2, .max = 16 }, 46 .m = { .min = 96, .max = 140 }, 47 .m1 = { .min = 18, .max = 26 }, 48 .m2 = { .min = 6, .max = 16 }, 49 .p = { .min = 4, .max = 128 }, 50 .p1 = { .min = 2, .max = 33 }, 51 .p2 = { .dot_limit = 165000, 52 .p2_slow = 4, .p2_fast = 4 }, 53 }; 54 55 static const struct intel_limit intel_limits_i8xx_lvds = { 56 .dot = { .min = 25000, .max = 350000 }, 57 .vco = { .min = 908000, .max = 1512000 }, 58 .n = { .min = 2, .max = 16 }, 59 .m = { .min = 96, .max = 140 }, 60 .m1 = { .min = 18, .max = 26 }, 61 .m2 = { .min = 6, .max = 16 }, 62 .p = { .min = 4, .max = 128 }, 63 .p1 = { .min = 1, .max = 6 }, 64 .p2 = { .dot_limit = 165000, 65 .p2_slow = 14, .p2_fast = 7 }, 66 }; 67 68 static const struct intel_limit intel_limits_i9xx_sdvo = { 69 .dot = { .min = 20000, .max = 400000 }, 70 .vco = { .min = 1400000, .max = 2800000 }, 71 .n = { .min = 1, .max = 6 }, 72 .m = { .min = 70, .max = 120 }, 73 .m1 = { .min = 8, .max = 18 }, 74 .m2 = { .min = 3, .max = 7 }, 75 .p = { .min = 5, .max = 80 }, 76 .p1 = { .min = 1, .max = 8 }, 77 .p2 = { .dot_limit = 200000, 78 .p2_slow = 10, .p2_fast = 5 }, 79 }; 80 81 static const struct intel_limit intel_limits_i9xx_lvds = { 82 .dot = { .min = 20000, .max = 400000 }, 83 .vco = { .min = 1400000, .max = 2800000 }, 84 .n = { .min = 1, .max = 6 }, 85 .m = { .min = 70, .max = 120 }, 86 .m1 = { .min = 8, .max = 18 }, 87 .m2 = { .min = 3, .max = 7 }, 88 .p = { .min = 7, .max = 98 }, 89 .p1 = { .min = 1, .max = 8 }, 90 .p2 = { .dot_limit = 112000, 91 .p2_slow = 14, .p2_fast = 7 }, 92 }; 93 94 95 static const struct intel_limit intel_limits_g4x_sdvo = { 96 .dot = { .min = 25000, .max = 270000 }, 97 .vco = { .min = 1750000, .max = 3500000}, 98 .n = { .min = 1, .max = 4 }, 99 .m = { .min = 104, .max = 138 }, 100 .m1 = { .min = 17, .max = 23 }, 101 .m2 = { .min = 5, .max = 11 }, 102 .p = { .min = 10, .max = 30 }, 103 .p1 = { .min = 1, .max = 3}, 104 .p2 = { .dot_limit = 270000, 105 .p2_slow = 10, 106 .p2_fast = 10 107 }, 108 }; 109 110 static const struct intel_limit intel_limits_g4x_hdmi = { 111 .dot = { .min = 22000, .max = 400000 }, 112 .vco = { .min = 1750000, .max = 3500000}, 113 .n = { .min = 1, .max = 4 }, 114 .m = { .min = 104, .max = 138 }, 115 .m1 = { .min = 16, .max = 23 }, 116 .m2 = { .min = 5, .max = 11 }, 117 .p = { .min = 5, .max = 80 }, 118 .p1 = { .min = 1, .max = 8}, 119 .p2 = { .dot_limit = 165000, 120 .p2_slow = 10, .p2_fast = 5 }, 121 }; 122 123 static const struct intel_limit intel_limits_g4x_single_channel_lvds = { 124 .dot = { .min = 20000, .max = 115000 }, 125 .vco = { .min = 1750000, .max = 3500000 }, 126 .n = { .min = 1, .max = 3 }, 127 .m = { .min = 104, .max = 138 }, 128 .m1 = { .min = 17, .max = 23 }, 129 .m2 = { .min = 5, .max = 11 }, 130 .p = { .min = 28, .max = 112 }, 131 .p1 = { .min = 2, .max = 8 }, 132 .p2 = { .dot_limit = 0, 133 .p2_slow = 14, .p2_fast = 14 134 }, 135 }; 136 137 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { 138 .dot = { .min = 80000, .max = 224000 }, 139 .vco = { .min = 1750000, .max = 3500000 }, 140 .n = { .min = 1, .max = 3 }, 141 .m = { .min = 104, .max = 138 }, 142 .m1 = { .min = 17, .max = 23 }, 143 .m2 = { .min = 5, .max = 11 }, 144 .p = { .min = 14, .max = 42 }, 145 .p1 = { .min = 2, .max = 6 }, 146 .p2 = { .dot_limit = 0, 147 .p2_slow = 7, .p2_fast = 7 148 }, 149 }; 150 151 static const struct intel_limit pnv_limits_sdvo = { 152 .dot = { .min = 20000, .max = 400000}, 153 .vco = { .min = 1700000, .max = 3500000 }, 154 /* Pineview's Ncounter is a ring counter */ 155 .n = { .min = 3, .max = 6 }, 156 .m = { .min = 2, .max = 256 }, 157 /* Pineview only has one combined m divider, which we treat as m2. */ 158 .m1 = { .min = 0, .max = 0 }, 159 .m2 = { .min = 0, .max = 254 }, 160 .p = { .min = 5, .max = 80 }, 161 .p1 = { .min = 1, .max = 8 }, 162 .p2 = { .dot_limit = 200000, 163 .p2_slow = 10, .p2_fast = 5 }, 164 }; 165 166 static const struct intel_limit pnv_limits_lvds = { 167 .dot = { .min = 20000, .max = 400000 }, 168 .vco = { .min = 1700000, .max = 3500000 }, 169 .n = { .min = 3, .max = 6 }, 170 .m = { .min = 2, .max = 256 }, 171 .m1 = { .min = 0, .max = 0 }, 172 .m2 = { .min = 0, .max = 254 }, 173 .p = { .min = 7, .max = 112 }, 174 .p1 = { .min = 1, .max = 8 }, 175 .p2 = { .dot_limit = 112000, 176 .p2_slow = 14, .p2_fast = 14 }, 177 }; 178 179 /* Ironlake / Sandybridge 180 * 181 * We calculate clock using (register_value + 2) for N/M1/M2, so here 182 * the range value for them is (actual_value - 2). 183 */ 184 static const struct intel_limit ilk_limits_dac = { 185 .dot = { .min = 25000, .max = 350000 }, 186 .vco = { .min = 1760000, .max = 3510000 }, 187 .n = { .min = 1, .max = 5 }, 188 .m = { .min = 79, .max = 127 }, 189 .m1 = { .min = 12, .max = 22 }, 190 .m2 = { .min = 5, .max = 9 }, 191 .p = { .min = 5, .max = 80 }, 192 .p1 = { .min = 1, .max = 8 }, 193 .p2 = { .dot_limit = 225000, 194 .p2_slow = 10, .p2_fast = 5 }, 195 }; 196 197 static const struct intel_limit ilk_limits_single_lvds = { 198 .dot = { .min = 25000, .max = 350000 }, 199 .vco = { .min = 1760000, .max = 3510000 }, 200 .n = { .min = 1, .max = 3 }, 201 .m = { .min = 79, .max = 118 }, 202 .m1 = { .min = 12, .max = 22 }, 203 .m2 = { .min = 5, .max = 9 }, 204 .p = { .min = 28, .max = 112 }, 205 .p1 = { .min = 2, .max = 8 }, 206 .p2 = { .dot_limit = 225000, 207 .p2_slow = 14, .p2_fast = 14 }, 208 }; 209 210 static const struct intel_limit ilk_limits_dual_lvds = { 211 .dot = { .min = 25000, .max = 350000 }, 212 .vco = { .min = 1760000, .max = 3510000 }, 213 .n = { .min = 1, .max = 3 }, 214 .m = { .min = 79, .max = 127 }, 215 .m1 = { .min = 12, .max = 22 }, 216 .m2 = { .min = 5, .max = 9 }, 217 .p = { .min = 14, .max = 56 }, 218 .p1 = { .min = 2, .max = 8 }, 219 .p2 = { .dot_limit = 225000, 220 .p2_slow = 7, .p2_fast = 7 }, 221 }; 222 223 /* LVDS 100mhz refclk limits. */ 224 static const struct intel_limit ilk_limits_single_lvds_100m = { 225 .dot = { .min = 25000, .max = 350000 }, 226 .vco = { .min = 1760000, .max = 3510000 }, 227 .n = { .min = 1, .max = 2 }, 228 .m = { .min = 79, .max = 126 }, 229 .m1 = { .min = 12, .max = 22 }, 230 .m2 = { .min = 5, .max = 9 }, 231 .p = { .min = 28, .max = 112 }, 232 .p1 = { .min = 2, .max = 8 }, 233 .p2 = { .dot_limit = 225000, 234 .p2_slow = 14, .p2_fast = 14 }, 235 }; 236 237 static const struct intel_limit ilk_limits_dual_lvds_100m = { 238 .dot = { .min = 25000, .max = 350000 }, 239 .vco = { .min = 1760000, .max = 3510000 }, 240 .n = { .min = 1, .max = 3 }, 241 .m = { .min = 79, .max = 126 }, 242 .m1 = { .min = 12, .max = 22 }, 243 .m2 = { .min = 5, .max = 9 }, 244 .p = { .min = 14, .max = 42 }, 245 .p1 = { .min = 2, .max = 6 }, 246 .p2 = { .dot_limit = 225000, 247 .p2_slow = 7, .p2_fast = 7 }, 248 }; 249 250 static const struct intel_limit intel_limits_vlv = { 251 /* 252 * These are the data rate limits (measured in fast clocks) 253 * since those are the strictest limits we have. The fast 254 * clock and actual rate limits are more relaxed, so checking 255 * them would make no difference. 256 */ 257 .dot = { .min = 25000 * 5, .max = 270000 * 5 }, 258 .vco = { .min = 4000000, .max = 6000000 }, 259 .n = { .min = 1, .max = 7 }, 260 .m1 = { .min = 2, .max = 3 }, 261 .m2 = { .min = 11, .max = 156 }, 262 .p1 = { .min = 2, .max = 3 }, 263 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ 264 }; 265 266 static const struct intel_limit intel_limits_chv = { 267 /* 268 * These are the data rate limits (measured in fast clocks) 269 * since those are the strictest limits we have. The fast 270 * clock and actual rate limits are more relaxed, so checking 271 * them would make no difference. 272 */ 273 .dot = { .min = 25000 * 5, .max = 540000 * 5}, 274 .vco = { .min = 4800000, .max = 6480000 }, 275 .n = { .min = 1, .max = 1 }, 276 .m1 = { .min = 2, .max = 2 }, 277 .m2 = { .min = 24 << 22, .max = 175 << 22 }, 278 .p1 = { .min = 2, .max = 4 }, 279 .p2 = { .p2_slow = 1, .p2_fast = 14 }, 280 }; 281 282 static const struct intel_limit intel_limits_bxt = { 283 /* FIXME: find real dot limits */ 284 .dot = { .min = 0, .max = INT_MAX }, 285 .vco = { .min = 4800000, .max = 6700000 }, 286 .n = { .min = 1, .max = 1 }, 287 .m1 = { .min = 2, .max = 2 }, 288 /* FIXME: find real m2 limits */ 289 .m2 = { .min = 2 << 22, .max = 255 << 22 }, 290 .p1 = { .min = 2, .max = 4 }, 291 .p2 = { .p2_slow = 1, .p2_fast = 20 }, 292 }; 293 294 /* 295 * Platform specific helpers to calculate the port PLL loopback- (clock.m), 296 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast 297 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. 298 * The helpers' return value is the rate of the clock that is fed to the 299 * display engine's pipe which can be the above fast dot clock rate or a 300 * divided-down version of it. 301 */ 302 /* m1 is reserved as 0 in Pineview, n is a ring counter */ 303 int pnv_calc_dpll_params(int refclk, struct dpll *clock) 304 { 305 clock->m = clock->m2 + 2; 306 clock->p = clock->p1 * clock->p2; 307 if (WARN_ON(clock->n == 0 || clock->p == 0)) 308 return 0; 309 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 310 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 311 312 return clock->dot; 313 } 314 315 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) 316 { 317 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); 318 } 319 320 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) 321 { 322 clock->m = i9xx_dpll_compute_m(clock); 323 clock->p = clock->p1 * clock->p2; 324 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) 325 return 0; 326 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); 327 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 328 329 return clock->dot; 330 } 331 332 int vlv_calc_dpll_params(int refclk, struct dpll *clock) 333 { 334 clock->m = clock->m1 * clock->m2; 335 clock->p = clock->p1 * clock->p2; 336 if (WARN_ON(clock->n == 0 || clock->p == 0)) 337 return 0; 338 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 339 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 340 341 return clock->dot / 5; 342 } 343 344 int chv_calc_dpll_params(int refclk, struct dpll *clock) 345 { 346 clock->m = clock->m1 * clock->m2; 347 clock->p = clock->p1 * clock->p2; 348 if (WARN_ON(clock->n == 0 || clock->p == 0)) 349 return 0; 350 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), 351 clock->n << 22); 352 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 353 354 return clock->dot / 5; 355 } 356 357 /* 358 * Returns whether the given set of divisors are valid for a given refclk with 359 * the given connectors. 360 */ 361 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv, 362 const struct intel_limit *limit, 363 const struct dpll *clock) 364 { 365 if (clock->n < limit->n.min || limit->n.max < clock->n) 366 return false; 367 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 368 return false; 369 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 370 return false; 371 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 372 return false; 373 374 if (!IS_PINEVIEW(dev_priv) && !IS_LP(dev_priv)) 375 if (clock->m1 <= clock->m2) 376 return false; 377 378 if (!IS_LP(dev_priv)) { 379 if (clock->p < limit->p.min || limit->p.max < clock->p) 380 return false; 381 if (clock->m < limit->m.min || limit->m.max < clock->m) 382 return false; 383 } 384 385 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 386 return false; 387 /* XXX: We may need to be checking "Dot clock" depending on the multiplier, 388 * connector, etc., rather than just a single range. 389 */ 390 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 391 return false; 392 393 return true; 394 } 395 396 static int 397 i9xx_select_p2_div(const struct intel_limit *limit, 398 const struct intel_crtc_state *crtc_state, 399 int target) 400 { 401 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 402 403 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 404 /* 405 * For LVDS just rely on its current settings for dual-channel. 406 * We haven't figured out how to reliably set up different 407 * single/dual channel state, if we even can. 408 */ 409 if (intel_is_dual_link_lvds(dev_priv)) 410 return limit->p2.p2_fast; 411 else 412 return limit->p2.p2_slow; 413 } else { 414 if (target < limit->p2.dot_limit) 415 return limit->p2.p2_slow; 416 else 417 return limit->p2.p2_fast; 418 } 419 } 420 421 /* 422 * Returns a set of divisors for the desired target clock with the given 423 * refclk, or FALSE. The returned values represent the clock equation: 424 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 425 * 426 * Target and reference clocks are specified in kHz. 427 * 428 * If match_clock is provided, then best_clock P divider must match the P 429 * divider from @match_clock used for LVDS downclocking. 430 */ 431 static bool 432 i9xx_find_best_dpll(const struct intel_limit *limit, 433 struct intel_crtc_state *crtc_state, 434 int target, int refclk, 435 const struct dpll *match_clock, 436 struct dpll *best_clock) 437 { 438 struct drm_device *dev = crtc_state->uapi.crtc->dev; 439 struct dpll clock; 440 int err = target; 441 442 memset(best_clock, 0, sizeof(*best_clock)); 443 444 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 445 446 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 447 clock.m1++) { 448 for (clock.m2 = limit->m2.min; 449 clock.m2 <= limit->m2.max; clock.m2++) { 450 if (clock.m2 >= clock.m1) 451 break; 452 for (clock.n = limit->n.min; 453 clock.n <= limit->n.max; clock.n++) { 454 for (clock.p1 = limit->p1.min; 455 clock.p1 <= limit->p1.max; clock.p1++) { 456 int this_err; 457 458 i9xx_calc_dpll_params(refclk, &clock); 459 if (!intel_pll_is_valid(to_i915(dev), 460 limit, 461 &clock)) 462 continue; 463 if (match_clock && 464 clock.p != match_clock->p) 465 continue; 466 467 this_err = abs(clock.dot - target); 468 if (this_err < err) { 469 *best_clock = clock; 470 err = this_err; 471 } 472 } 473 } 474 } 475 } 476 477 return (err != target); 478 } 479 480 /* 481 * Returns a set of divisors for the desired target clock with the given 482 * refclk, or FALSE. The returned values represent the clock equation: 483 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 484 * 485 * Target and reference clocks are specified in kHz. 486 * 487 * If match_clock is provided, then best_clock P divider must match the P 488 * divider from @match_clock used for LVDS downclocking. 489 */ 490 static bool 491 pnv_find_best_dpll(const struct intel_limit *limit, 492 struct intel_crtc_state *crtc_state, 493 int target, int refclk, 494 const struct dpll *match_clock, 495 struct dpll *best_clock) 496 { 497 struct drm_device *dev = crtc_state->uapi.crtc->dev; 498 struct dpll clock; 499 int err = target; 500 501 memset(best_clock, 0, sizeof(*best_clock)); 502 503 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 504 505 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 506 clock.m1++) { 507 for (clock.m2 = limit->m2.min; 508 clock.m2 <= limit->m2.max; clock.m2++) { 509 for (clock.n = limit->n.min; 510 clock.n <= limit->n.max; clock.n++) { 511 for (clock.p1 = limit->p1.min; 512 clock.p1 <= limit->p1.max; clock.p1++) { 513 int this_err; 514 515 pnv_calc_dpll_params(refclk, &clock); 516 if (!intel_pll_is_valid(to_i915(dev), 517 limit, 518 &clock)) 519 continue; 520 if (match_clock && 521 clock.p != match_clock->p) 522 continue; 523 524 this_err = abs(clock.dot - target); 525 if (this_err < err) { 526 *best_clock = clock; 527 err = this_err; 528 } 529 } 530 } 531 } 532 } 533 534 return (err != target); 535 } 536 537 /* 538 * Returns a set of divisors for the desired target clock with the given 539 * refclk, or FALSE. The returned values represent the clock equation: 540 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 541 * 542 * Target and reference clocks are specified in kHz. 543 * 544 * If match_clock is provided, then best_clock P divider must match the P 545 * divider from @match_clock used for LVDS downclocking. 546 */ 547 static bool 548 g4x_find_best_dpll(const struct intel_limit *limit, 549 struct intel_crtc_state *crtc_state, 550 int target, int refclk, 551 const struct dpll *match_clock, 552 struct dpll *best_clock) 553 { 554 struct drm_device *dev = crtc_state->uapi.crtc->dev; 555 struct dpll clock; 556 int max_n; 557 bool found = false; 558 /* approximately equals target * 0.00585 */ 559 int err_most = (target >> 8) + (target >> 9); 560 561 memset(best_clock, 0, sizeof(*best_clock)); 562 563 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 564 565 max_n = limit->n.max; 566 /* based on hardware requirement, prefer smaller n to precision */ 567 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 568 /* based on hardware requirement, prefere larger m1,m2 */ 569 for (clock.m1 = limit->m1.max; 570 clock.m1 >= limit->m1.min; clock.m1--) { 571 for (clock.m2 = limit->m2.max; 572 clock.m2 >= limit->m2.min; clock.m2--) { 573 for (clock.p1 = limit->p1.max; 574 clock.p1 >= limit->p1.min; clock.p1--) { 575 int this_err; 576 577 i9xx_calc_dpll_params(refclk, &clock); 578 if (!intel_pll_is_valid(to_i915(dev), 579 limit, 580 &clock)) 581 continue; 582 583 this_err = abs(clock.dot - target); 584 if (this_err < err_most) { 585 *best_clock = clock; 586 err_most = this_err; 587 max_n = clock.n; 588 found = true; 589 } 590 } 591 } 592 } 593 } 594 return found; 595 } 596 597 /* 598 * Check if the calculated PLL configuration is more optimal compared to the 599 * best configuration and error found so far. Return the calculated error. 600 */ 601 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, 602 const struct dpll *calculated_clock, 603 const struct dpll *best_clock, 604 unsigned int best_error_ppm, 605 unsigned int *error_ppm) 606 { 607 /* 608 * For CHV ignore the error and consider only the P value. 609 * Prefer a bigger P value based on HW requirements. 610 */ 611 if (IS_CHERRYVIEW(to_i915(dev))) { 612 *error_ppm = 0; 613 614 return calculated_clock->p > best_clock->p; 615 } 616 617 if (drm_WARN_ON_ONCE(dev, !target_freq)) 618 return false; 619 620 *error_ppm = div_u64(1000000ULL * 621 abs(target_freq - calculated_clock->dot), 622 target_freq); 623 /* 624 * Prefer a better P value over a better (smaller) error if the error 625 * is small. Ensure this preference for future configurations too by 626 * setting the error to 0. 627 */ 628 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { 629 *error_ppm = 0; 630 631 return true; 632 } 633 634 return *error_ppm + 10 < best_error_ppm; 635 } 636 637 /* 638 * Returns a set of divisors for the desired target clock with the given 639 * refclk, or FALSE. The returned values represent the clock equation: 640 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 641 */ 642 static bool 643 vlv_find_best_dpll(const struct intel_limit *limit, 644 struct intel_crtc_state *crtc_state, 645 int target, int refclk, 646 const struct dpll *match_clock, 647 struct dpll *best_clock) 648 { 649 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 650 struct drm_device *dev = crtc->base.dev; 651 struct dpll clock; 652 unsigned int bestppm = 1000000; 653 /* min update 19.2 MHz */ 654 int max_n = min(limit->n.max, refclk / 19200); 655 bool found = false; 656 657 target *= 5; /* fast clock */ 658 659 memset(best_clock, 0, sizeof(*best_clock)); 660 661 /* based on hardware requirement, prefer smaller n to precision */ 662 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 663 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 664 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; 665 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 666 clock.p = clock.p1 * clock.p2; 667 /* based on hardware requirement, prefer bigger m1,m2 values */ 668 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { 669 unsigned int ppm; 670 671 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, 672 refclk * clock.m1); 673 674 vlv_calc_dpll_params(refclk, &clock); 675 676 if (!intel_pll_is_valid(to_i915(dev), 677 limit, 678 &clock)) 679 continue; 680 681 if (!vlv_PLL_is_optimal(dev, target, 682 &clock, 683 best_clock, 684 bestppm, &ppm)) 685 continue; 686 687 *best_clock = clock; 688 bestppm = ppm; 689 found = true; 690 } 691 } 692 } 693 } 694 695 return found; 696 } 697 698 /* 699 * Returns a set of divisors for the desired target clock with the given 700 * refclk, or FALSE. The returned values represent the clock equation: 701 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 702 */ 703 static bool 704 chv_find_best_dpll(const struct intel_limit *limit, 705 struct intel_crtc_state *crtc_state, 706 int target, int refclk, 707 const struct dpll *match_clock, 708 struct dpll *best_clock) 709 { 710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 711 struct drm_device *dev = crtc->base.dev; 712 unsigned int best_error_ppm; 713 struct dpll clock; 714 u64 m2; 715 int found = false; 716 717 memset(best_clock, 0, sizeof(*best_clock)); 718 best_error_ppm = 1000000; 719 720 /* 721 * Based on hardware doc, the n always set to 1, and m1 always 722 * set to 2. If requires to support 200Mhz refclk, we need to 723 * revisit this because n may not 1 anymore. 724 */ 725 clock.n = 1; 726 clock.m1 = 2; 727 target *= 5; /* fast clock */ 728 729 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 730 for (clock.p2 = limit->p2.p2_fast; 731 clock.p2 >= limit->p2.p2_slow; 732 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 733 unsigned int error_ppm; 734 735 clock.p = clock.p1 * clock.p2; 736 737 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22, 738 refclk * clock.m1); 739 740 if (m2 > INT_MAX/clock.m1) 741 continue; 742 743 clock.m2 = m2; 744 745 chv_calc_dpll_params(refclk, &clock); 746 747 if (!intel_pll_is_valid(to_i915(dev), limit, &clock)) 748 continue; 749 750 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, 751 best_error_ppm, &error_ppm)) 752 continue; 753 754 *best_clock = clock; 755 best_error_ppm = error_ppm; 756 found = true; 757 } 758 } 759 760 return found; 761 } 762 763 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, 764 struct dpll *best_clock) 765 { 766 int refclk = 100000; 767 const struct intel_limit *limit = &intel_limits_bxt; 768 769 return chv_find_best_dpll(limit, crtc_state, 770 crtc_state->port_clock, refclk, 771 NULL, best_clock); 772 } 773 774 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) 775 { 776 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; 777 } 778 779 static u32 pnv_dpll_compute_fp(const struct dpll *dpll) 780 { 781 return (1 << dpll->n) << 16 | dpll->m2; 782 } 783 784 static void i9xx_update_pll_dividers(struct intel_crtc_state *crtc_state, 785 const struct dpll *clock, 786 const struct dpll *reduced_clock) 787 { 788 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 789 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 790 u32 fp, fp2; 791 792 if (IS_PINEVIEW(dev_priv)) { 793 fp = pnv_dpll_compute_fp(clock); 794 fp2 = pnv_dpll_compute_fp(reduced_clock); 795 } else { 796 fp = i9xx_dpll_compute_fp(clock); 797 fp2 = i9xx_dpll_compute_fp(reduced_clock); 798 } 799 800 crtc_state->dpll_hw_state.fp0 = fp; 801 crtc_state->dpll_hw_state.fp1 = fp2; 802 } 803 804 static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, 805 const struct dpll *clock, 806 const struct dpll *reduced_clock) 807 { 808 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 809 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 810 u32 dpll; 811 812 i9xx_update_pll_dividers(crtc_state, clock, reduced_clock); 813 814 dpll = DPLL_VGA_MODE_DIS; 815 816 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) 817 dpll |= DPLLB_MODE_LVDS; 818 else 819 dpll |= DPLLB_MODE_DAC_SERIAL; 820 821 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 822 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 823 dpll |= (crtc_state->pixel_multiplier - 1) 824 << SDVO_MULTIPLIER_SHIFT_HIRES; 825 } 826 827 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || 828 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 829 dpll |= DPLL_SDVO_HIGH_SPEED; 830 831 if (intel_crtc_has_dp_encoder(crtc_state)) 832 dpll |= DPLL_SDVO_HIGH_SPEED; 833 834 /* compute bitmask from p1 value */ 835 if (IS_G4X(dev_priv)) { 836 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 837 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 838 } else if (IS_PINEVIEW(dev_priv)) { 839 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; 840 WARN_ON(reduced_clock->p1 != clock->p1); 841 } else { 842 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 843 WARN_ON(reduced_clock->p1 != clock->p1); 844 } 845 846 switch (clock->p2) { 847 case 5: 848 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 849 break; 850 case 7: 851 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 852 break; 853 case 10: 854 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 855 break; 856 case 14: 857 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 858 break; 859 } 860 WARN_ON(reduced_clock->p2 != clock->p2); 861 862 if (DISPLAY_VER(dev_priv) >= 4) 863 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 864 865 if (crtc_state->sdvo_tv_clock) 866 dpll |= PLL_REF_INPUT_TVCLKINBC; 867 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 868 intel_panel_use_ssc(dev_priv)) 869 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 870 else 871 dpll |= PLL_REF_INPUT_DREFCLK; 872 873 dpll |= DPLL_VCO_ENABLE; 874 crtc_state->dpll_hw_state.dpll = dpll; 875 876 if (DISPLAY_VER(dev_priv) >= 4) { 877 u32 dpll_md = (crtc_state->pixel_multiplier - 1) 878 << DPLL_MD_UDI_MULTIPLIER_SHIFT; 879 crtc_state->dpll_hw_state.dpll_md = dpll_md; 880 } 881 } 882 883 static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state, 884 const struct dpll *clock, 885 const struct dpll *reduced_clock) 886 { 887 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 888 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 889 u32 dpll; 890 891 i9xx_update_pll_dividers(crtc_state, clock, reduced_clock); 892 893 dpll = DPLL_VGA_MODE_DIS; 894 895 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 896 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 897 } else { 898 if (clock->p1 == 2) 899 dpll |= PLL_P1_DIVIDE_BY_TWO; 900 else 901 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; 902 if (clock->p2 == 4) 903 dpll |= PLL_P2_DIVIDE_BY_4; 904 } 905 WARN_ON(reduced_clock->p1 != clock->p1); 906 WARN_ON(reduced_clock->p2 != clock->p2); 907 908 /* 909 * Bspec: 910 * "[Almador Errata}: For the correct operation of the muxed DVO pins 911 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, 912 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock 913 * Enable) must be set to “1” in both the DPLL A Control Register 914 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." 915 * 916 * For simplicity We simply keep both bits always enabled in 917 * both DPLLS. The spec says we should disable the DVO 2X clock 918 * when not needed, but this seems to work fine in practice. 919 */ 920 if (IS_I830(dev_priv) || 921 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) 922 dpll |= DPLL_DVO_2X_MODE; 923 924 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 925 intel_panel_use_ssc(dev_priv)) 926 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 927 else 928 dpll |= PLL_REF_INPUT_DREFCLK; 929 930 dpll |= DPLL_VCO_ENABLE; 931 crtc_state->dpll_hw_state.dpll = dpll; 932 } 933 934 static int hsw_crtc_compute_clock(struct intel_crtc_state *crtc_state) 935 { 936 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 937 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 938 struct intel_atomic_state *state = 939 to_intel_atomic_state(crtc_state->uapi.state); 940 struct intel_encoder *encoder = 941 intel_get_crtc_new_encoder(state, crtc_state); 942 943 if (IS_DG2(dev_priv)) 944 return intel_mpllb_calc_state(crtc_state, encoder); 945 946 if (DISPLAY_VER(dev_priv) < 11 && 947 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 948 return 0; 949 950 if (!intel_reserve_shared_dplls(state, crtc, encoder)) { 951 drm_dbg_kms(&dev_priv->drm, 952 "failed to find PLL for pipe %c\n", 953 pipe_name(crtc->pipe)); 954 return -EINVAL; 955 } 956 957 return 0; 958 } 959 960 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) 961 { 962 return dpll->m < factor * dpll->n; 963 } 964 965 static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state, 966 const struct dpll *clock, 967 const struct dpll *reduced_clock) 968 { 969 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 970 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 971 u32 fp, fp2; 972 int factor; 973 974 /* Enable autotuning of the PLL clock (if permissible) */ 975 factor = 21; 976 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 977 if ((intel_panel_use_ssc(dev_priv) && 978 dev_priv->vbt.lvds_ssc_freq == 100000) || 979 (HAS_PCH_IBX(dev_priv) && 980 intel_is_dual_link_lvds(dev_priv))) 981 factor = 25; 982 } else if (crtc_state->sdvo_tv_clock) { 983 factor = 20; 984 } 985 986 fp = i9xx_dpll_compute_fp(clock); 987 if (ilk_needs_fb_cb_tune(clock, factor)) 988 fp |= FP_CB_TUNE; 989 990 fp2 = i9xx_dpll_compute_fp(reduced_clock); 991 if (ilk_needs_fb_cb_tune(reduced_clock, factor)) 992 fp2 |= FP_CB_TUNE; 993 994 crtc_state->dpll_hw_state.fp0 = fp; 995 crtc_state->dpll_hw_state.fp1 = fp2; 996 } 997 998 static void ilk_compute_dpll(struct intel_crtc_state *crtc_state, 999 const struct dpll *clock, 1000 const struct dpll *reduced_clock) 1001 { 1002 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1003 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1004 u32 dpll; 1005 1006 ilk_update_pll_dividers(crtc_state, clock, reduced_clock); 1007 1008 dpll = 0; 1009 1010 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) 1011 dpll |= DPLLB_MODE_LVDS; 1012 else 1013 dpll |= DPLLB_MODE_DAC_SERIAL; 1014 1015 dpll |= (crtc_state->pixel_multiplier - 1) 1016 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 1017 1018 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || 1019 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1020 dpll |= DPLL_SDVO_HIGH_SPEED; 1021 1022 if (intel_crtc_has_dp_encoder(crtc_state)) 1023 dpll |= DPLL_SDVO_HIGH_SPEED; 1024 1025 /* 1026 * The high speed IO clock is only really required for 1027 * SDVO/HDMI/DP, but we also enable it for CRT to make it 1028 * possible to share the DPLL between CRT and HDMI. Enabling 1029 * the clock needlessly does no real harm, except use up a 1030 * bit of power potentially. 1031 * 1032 * We'll limit this to IVB with 3 pipes, since it has only two 1033 * DPLLs and so DPLL sharing is the only way to get three pipes 1034 * driving PCH ports at the same time. On SNB we could do this, 1035 * and potentially avoid enabling the second DPLL, but it's not 1036 * clear if it''s a win or loss power wise. No point in doing 1037 * this on ILK at all since it has a fixed DPLL<->pipe mapping. 1038 */ 1039 if (INTEL_NUM_PIPES(dev_priv) == 3 && 1040 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1041 dpll |= DPLL_SDVO_HIGH_SPEED; 1042 1043 /* compute bitmask from p1 value */ 1044 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 1045 /* also FPA1 */ 1046 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 1047 1048 switch (clock->p2) { 1049 case 5: 1050 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 1051 break; 1052 case 7: 1053 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 1054 break; 1055 case 10: 1056 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 1057 break; 1058 case 14: 1059 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 1060 break; 1061 } 1062 WARN_ON(reduced_clock->p2 != clock->p2); 1063 1064 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 1065 intel_panel_use_ssc(dev_priv)) 1066 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 1067 else 1068 dpll |= PLL_REF_INPUT_DREFCLK; 1069 1070 dpll |= DPLL_VCO_ENABLE; 1071 1072 crtc_state->dpll_hw_state.dpll = dpll; 1073 } 1074 1075 static int ilk_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1076 { 1077 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1078 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1079 struct intel_atomic_state *state = 1080 to_intel_atomic_state(crtc_state->uapi.state); 1081 const struct intel_limit *limit; 1082 int refclk = 120000; 1083 1084 memset(&crtc_state->dpll_hw_state, 0, 1085 sizeof(crtc_state->dpll_hw_state)); 1086 1087 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 1088 if (!crtc_state->has_pch_encoder) 1089 return 0; 1090 1091 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1092 if (intel_panel_use_ssc(dev_priv)) { 1093 drm_dbg_kms(&dev_priv->drm, 1094 "using SSC reference clock of %d kHz\n", 1095 dev_priv->vbt.lvds_ssc_freq); 1096 refclk = dev_priv->vbt.lvds_ssc_freq; 1097 } 1098 1099 if (intel_is_dual_link_lvds(dev_priv)) { 1100 if (refclk == 100000) 1101 limit = &ilk_limits_dual_lvds_100m; 1102 else 1103 limit = &ilk_limits_dual_lvds; 1104 } else { 1105 if (refclk == 100000) 1106 limit = &ilk_limits_single_lvds_100m; 1107 else 1108 limit = &ilk_limits_single_lvds; 1109 } 1110 } else { 1111 limit = &ilk_limits_dac; 1112 } 1113 1114 if (!crtc_state->clock_set && 1115 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1116 refclk, NULL, &crtc_state->dpll)) { 1117 drm_err(&dev_priv->drm, 1118 "Couldn't find PLL settings for mode!\n"); 1119 return -EINVAL; 1120 } 1121 1122 ilk_compute_dpll(crtc_state, &crtc_state->dpll, 1123 &crtc_state->dpll); 1124 1125 if (!intel_reserve_shared_dplls(state, crtc, NULL)) { 1126 drm_dbg_kms(&dev_priv->drm, 1127 "failed to find PLL for pipe %c\n", 1128 pipe_name(crtc->pipe)); 1129 return -EINVAL; 1130 } 1131 1132 return 0; 1133 } 1134 1135 void vlv_compute_dpll(struct intel_crtc_state *crtc_state) 1136 { 1137 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1138 1139 crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | 1140 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1141 if (crtc->pipe != PIPE_A) 1142 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 1143 1144 /* DPLL not used with DSI, but still need the rest set up */ 1145 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1146 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | 1147 DPLL_EXT_BUFFER_ENABLE_VLV; 1148 1149 crtc_state->dpll_hw_state.dpll_md = 1150 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 1151 } 1152 1153 void chv_compute_dpll(struct intel_crtc_state *crtc_state) 1154 { 1155 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1156 1157 crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | 1158 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1159 if (crtc->pipe != PIPE_A) 1160 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 1161 1162 /* DPLL not used with DSI, but still need the rest set up */ 1163 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1164 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; 1165 1166 crtc_state->dpll_hw_state.dpll_md = 1167 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 1168 } 1169 1170 static int chv_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1171 { 1172 int refclk = 100000; 1173 const struct intel_limit *limit = &intel_limits_chv; 1174 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1175 1176 memset(&crtc_state->dpll_hw_state, 0, 1177 sizeof(crtc_state->dpll_hw_state)); 1178 1179 if (!crtc_state->clock_set && 1180 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1181 refclk, NULL, &crtc_state->dpll)) { 1182 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); 1183 return -EINVAL; 1184 } 1185 1186 chv_compute_dpll(crtc_state); 1187 1188 return 0; 1189 } 1190 1191 static int vlv_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1192 { 1193 int refclk = 100000; 1194 const struct intel_limit *limit = &intel_limits_vlv; 1195 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1196 1197 memset(&crtc_state->dpll_hw_state, 0, 1198 sizeof(crtc_state->dpll_hw_state)); 1199 1200 if (!crtc_state->clock_set && 1201 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1202 refclk, NULL, &crtc_state->dpll)) { 1203 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); 1204 return -EINVAL; 1205 } 1206 1207 vlv_compute_dpll(crtc_state); 1208 1209 return 0; 1210 } 1211 1212 static int g4x_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1213 { 1214 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1215 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1216 const struct intel_limit *limit; 1217 int refclk = 96000; 1218 1219 memset(&crtc_state->dpll_hw_state, 0, 1220 sizeof(crtc_state->dpll_hw_state)); 1221 1222 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1223 if (intel_panel_use_ssc(dev_priv)) { 1224 refclk = dev_priv->vbt.lvds_ssc_freq; 1225 drm_dbg_kms(&dev_priv->drm, 1226 "using SSC reference clock of %d kHz\n", 1227 refclk); 1228 } 1229 1230 if (intel_is_dual_link_lvds(dev_priv)) 1231 limit = &intel_limits_g4x_dual_channel_lvds; 1232 else 1233 limit = &intel_limits_g4x_single_channel_lvds; 1234 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || 1235 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1236 limit = &intel_limits_g4x_hdmi; 1237 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { 1238 limit = &intel_limits_g4x_sdvo; 1239 } else { 1240 /* The option is for other outputs */ 1241 limit = &intel_limits_i9xx_sdvo; 1242 } 1243 1244 if (!crtc_state->clock_set && 1245 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1246 refclk, NULL, &crtc_state->dpll)) { 1247 drm_err(&dev_priv->drm, 1248 "Couldn't find PLL settings for mode!\n"); 1249 return -EINVAL; 1250 } 1251 1252 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, 1253 &crtc_state->dpll); 1254 1255 return 0; 1256 } 1257 1258 static int pnv_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1259 { 1260 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1261 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1262 const struct intel_limit *limit; 1263 int refclk = 96000; 1264 1265 memset(&crtc_state->dpll_hw_state, 0, 1266 sizeof(crtc_state->dpll_hw_state)); 1267 1268 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1269 if (intel_panel_use_ssc(dev_priv)) { 1270 refclk = dev_priv->vbt.lvds_ssc_freq; 1271 drm_dbg_kms(&dev_priv->drm, 1272 "using SSC reference clock of %d kHz\n", 1273 refclk); 1274 } 1275 1276 limit = &pnv_limits_lvds; 1277 } else { 1278 limit = &pnv_limits_sdvo; 1279 } 1280 1281 if (!crtc_state->clock_set && 1282 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1283 refclk, NULL, &crtc_state->dpll)) { 1284 drm_err(&dev_priv->drm, 1285 "Couldn't find PLL settings for mode!\n"); 1286 return -EINVAL; 1287 } 1288 1289 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, 1290 &crtc_state->dpll); 1291 1292 return 0; 1293 } 1294 1295 static int i9xx_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1296 { 1297 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1298 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1299 const struct intel_limit *limit; 1300 int refclk = 96000; 1301 1302 memset(&crtc_state->dpll_hw_state, 0, 1303 sizeof(crtc_state->dpll_hw_state)); 1304 1305 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1306 if (intel_panel_use_ssc(dev_priv)) { 1307 refclk = dev_priv->vbt.lvds_ssc_freq; 1308 drm_dbg_kms(&dev_priv->drm, 1309 "using SSC reference clock of %d kHz\n", 1310 refclk); 1311 } 1312 1313 limit = &intel_limits_i9xx_lvds; 1314 } else { 1315 limit = &intel_limits_i9xx_sdvo; 1316 } 1317 1318 if (!crtc_state->clock_set && 1319 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1320 refclk, NULL, &crtc_state->dpll)) { 1321 drm_err(&dev_priv->drm, 1322 "Couldn't find PLL settings for mode!\n"); 1323 return -EINVAL; 1324 } 1325 1326 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, 1327 &crtc_state->dpll); 1328 1329 return 0; 1330 } 1331 1332 static int i8xx_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1333 { 1334 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1335 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1336 const struct intel_limit *limit; 1337 int refclk = 48000; 1338 1339 memset(&crtc_state->dpll_hw_state, 0, 1340 sizeof(crtc_state->dpll_hw_state)); 1341 1342 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1343 if (intel_panel_use_ssc(dev_priv)) { 1344 refclk = dev_priv->vbt.lvds_ssc_freq; 1345 drm_dbg_kms(&dev_priv->drm, 1346 "using SSC reference clock of %d kHz\n", 1347 refclk); 1348 } 1349 1350 limit = &intel_limits_i8xx_lvds; 1351 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { 1352 limit = &intel_limits_i8xx_dvo; 1353 } else { 1354 limit = &intel_limits_i8xx_dac; 1355 } 1356 1357 if (!crtc_state->clock_set && 1358 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1359 refclk, NULL, &crtc_state->dpll)) { 1360 drm_err(&dev_priv->drm, 1361 "Couldn't find PLL settings for mode!\n"); 1362 return -EINVAL; 1363 } 1364 1365 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, 1366 &crtc_state->dpll); 1367 1368 return 0; 1369 } 1370 1371 static const struct intel_dpll_funcs hsw_dpll_funcs = { 1372 .crtc_compute_clock = hsw_crtc_compute_clock, 1373 }; 1374 1375 static const struct intel_dpll_funcs ilk_dpll_funcs = { 1376 .crtc_compute_clock = ilk_crtc_compute_clock, 1377 }; 1378 1379 static const struct intel_dpll_funcs chv_dpll_funcs = { 1380 .crtc_compute_clock = chv_crtc_compute_clock, 1381 }; 1382 1383 static const struct intel_dpll_funcs vlv_dpll_funcs = { 1384 .crtc_compute_clock = vlv_crtc_compute_clock, 1385 }; 1386 1387 static const struct intel_dpll_funcs g4x_dpll_funcs = { 1388 .crtc_compute_clock = g4x_crtc_compute_clock, 1389 }; 1390 1391 static const struct intel_dpll_funcs pnv_dpll_funcs = { 1392 .crtc_compute_clock = pnv_crtc_compute_clock, 1393 }; 1394 1395 static const struct intel_dpll_funcs i9xx_dpll_funcs = { 1396 .crtc_compute_clock = i9xx_crtc_compute_clock, 1397 }; 1398 1399 static const struct intel_dpll_funcs i8xx_dpll_funcs = { 1400 .crtc_compute_clock = i8xx_crtc_compute_clock, 1401 }; 1402 1403 void 1404 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv) 1405 { 1406 if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv)) 1407 dev_priv->dpll_funcs = &hsw_dpll_funcs; 1408 else if (HAS_PCH_SPLIT(dev_priv)) 1409 dev_priv->dpll_funcs = &ilk_dpll_funcs; 1410 else if (IS_CHERRYVIEW(dev_priv)) 1411 dev_priv->dpll_funcs = &chv_dpll_funcs; 1412 else if (IS_VALLEYVIEW(dev_priv)) 1413 dev_priv->dpll_funcs = &vlv_dpll_funcs; 1414 else if (IS_G4X(dev_priv)) 1415 dev_priv->dpll_funcs = &g4x_dpll_funcs; 1416 else if (IS_PINEVIEW(dev_priv)) 1417 dev_priv->dpll_funcs = &pnv_dpll_funcs; 1418 else if (DISPLAY_VER(dev_priv) != 2) 1419 dev_priv->dpll_funcs = &i9xx_dpll_funcs; 1420 else 1421 dev_priv->dpll_funcs = &i8xx_dpll_funcs; 1422 } 1423 1424 static bool i9xx_has_pps(struct drm_i915_private *dev_priv) 1425 { 1426 if (IS_I830(dev_priv)) 1427 return false; 1428 1429 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 1430 } 1431 1432 void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) 1433 { 1434 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1435 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1436 u32 dpll = crtc_state->dpll_hw_state.dpll; 1437 enum pipe pipe = crtc->pipe; 1438 int i; 1439 1440 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1441 1442 /* PLL is protected by panel, make sure we can write it */ 1443 if (i9xx_has_pps(dev_priv)) 1444 assert_pps_unlocked(dev_priv, pipe); 1445 1446 intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0); 1447 intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1); 1448 1449 /* 1450 * Apparently we need to have VGA mode enabled prior to changing 1451 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 1452 * dividers, even though the register value does change. 1453 */ 1454 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 1455 intel_de_write(dev_priv, DPLL(pipe), dpll); 1456 1457 /* Wait for the clocks to stabilize. */ 1458 intel_de_posting_read(dev_priv, DPLL(pipe)); 1459 udelay(150); 1460 1461 if (DISPLAY_VER(dev_priv) >= 4) { 1462 intel_de_write(dev_priv, DPLL_MD(pipe), 1463 crtc_state->dpll_hw_state.dpll_md); 1464 } else { 1465 /* The pixel multiplier can only be updated once the 1466 * DPLL is enabled and the clocks are stable. 1467 * 1468 * So write it again. 1469 */ 1470 intel_de_write(dev_priv, DPLL(pipe), dpll); 1471 } 1472 1473 /* We do this three times for luck */ 1474 for (i = 0; i < 3; i++) { 1475 intel_de_write(dev_priv, DPLL(pipe), dpll); 1476 intel_de_posting_read(dev_priv, DPLL(pipe)); 1477 udelay(150); /* wait for warmup */ 1478 } 1479 } 1480 1481 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, 1482 enum pipe pipe) 1483 { 1484 u32 reg_val; 1485 1486 /* 1487 * PLLB opamp always calibrates to max value of 0x3f, force enable it 1488 * and set it to a reasonable value instead. 1489 */ 1490 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); 1491 reg_val &= 0xffffff00; 1492 reg_val |= 0x00000030; 1493 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); 1494 1495 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); 1496 reg_val &= 0x00ffffff; 1497 reg_val |= 0x8c000000; 1498 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 1499 1500 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); 1501 reg_val &= 0xffffff00; 1502 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); 1503 1504 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); 1505 reg_val &= 0x00ffffff; 1506 reg_val |= 0xb0000000; 1507 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 1508 } 1509 1510 static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) 1511 { 1512 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1513 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1514 enum pipe pipe = crtc->pipe; 1515 u32 mdiv; 1516 u32 bestn, bestm1, bestm2, bestp1, bestp2; 1517 u32 coreclk, reg_val; 1518 1519 vlv_dpio_get(dev_priv); 1520 1521 bestn = crtc_state->dpll.n; 1522 bestm1 = crtc_state->dpll.m1; 1523 bestm2 = crtc_state->dpll.m2; 1524 bestp1 = crtc_state->dpll.p1; 1525 bestp2 = crtc_state->dpll.p2; 1526 1527 /* See eDP HDMI DPIO driver vbios notes doc */ 1528 1529 /* PLL B needs special handling */ 1530 if (pipe == PIPE_B) 1531 vlv_pllb_recal_opamp(dev_priv, pipe); 1532 1533 /* Set up Tx target for periodic Rcomp update */ 1534 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); 1535 1536 /* Disable target IRef on PLL */ 1537 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); 1538 reg_val &= 0x00ffffff; 1539 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); 1540 1541 /* Disable fast lock */ 1542 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); 1543 1544 /* Set idtafcrecal before PLL is enabled */ 1545 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); 1546 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); 1547 mdiv |= ((bestn << DPIO_N_SHIFT)); 1548 mdiv |= (1 << DPIO_K_SHIFT); 1549 1550 /* 1551 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, 1552 * but we don't support that). 1553 * Note: don't use the DAC post divider as it seems unstable. 1554 */ 1555 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); 1556 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); 1557 1558 mdiv |= DPIO_ENABLE_CALIBRATION; 1559 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); 1560 1561 /* Set HBR and RBR LPF coefficients */ 1562 if (crtc_state->port_clock == 162000 || 1563 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) || 1564 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1565 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 1566 0x009f0003); 1567 else 1568 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 1569 0x00d0000f); 1570 1571 if (intel_crtc_has_dp_encoder(crtc_state)) { 1572 /* Use SSC source */ 1573 if (pipe == PIPE_A) 1574 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1575 0x0df40000); 1576 else 1577 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1578 0x0df70000); 1579 } else { /* HDMI or VGA */ 1580 /* Use bend source */ 1581 if (pipe == PIPE_A) 1582 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1583 0x0df70000); 1584 else 1585 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1586 0x0df40000); 1587 } 1588 1589 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); 1590 coreclk = (coreclk & 0x0000ff00) | 0x01c00000; 1591 if (intel_crtc_has_dp_encoder(crtc_state)) 1592 coreclk |= 0x01000000; 1593 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); 1594 1595 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); 1596 1597 vlv_dpio_put(dev_priv); 1598 } 1599 1600 static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state) 1601 { 1602 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1603 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1604 enum pipe pipe = crtc->pipe; 1605 1606 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); 1607 intel_de_posting_read(dev_priv, DPLL(pipe)); 1608 udelay(150); 1609 1610 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) 1611 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); 1612 } 1613 1614 void vlv_enable_pll(const struct intel_crtc_state *crtc_state) 1615 { 1616 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1617 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1618 enum pipe pipe = crtc->pipe; 1619 1620 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1621 1622 /* PLL is protected by panel, make sure we can write it */ 1623 assert_pps_unlocked(dev_priv, pipe); 1624 1625 /* Enable Refclk */ 1626 intel_de_write(dev_priv, DPLL(pipe), 1627 crtc_state->dpll_hw_state.dpll & 1628 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); 1629 1630 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { 1631 vlv_prepare_pll(crtc_state); 1632 _vlv_enable_pll(crtc_state); 1633 } 1634 1635 intel_de_write(dev_priv, DPLL_MD(pipe), 1636 crtc_state->dpll_hw_state.dpll_md); 1637 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); 1638 } 1639 1640 static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) 1641 { 1642 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1643 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1644 enum pipe pipe = crtc->pipe; 1645 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1646 u32 loopfilter, tribuf_calcntr; 1647 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; 1648 u32 dpio_val; 1649 int vco; 1650 1651 bestn = crtc_state->dpll.n; 1652 bestm2_frac = crtc_state->dpll.m2 & 0x3fffff; 1653 bestm1 = crtc_state->dpll.m1; 1654 bestm2 = crtc_state->dpll.m2 >> 22; 1655 bestp1 = crtc_state->dpll.p1; 1656 bestp2 = crtc_state->dpll.p2; 1657 vco = crtc_state->dpll.vco; 1658 dpio_val = 0; 1659 loopfilter = 0; 1660 1661 vlv_dpio_get(dev_priv); 1662 1663 /* p1 and p2 divider */ 1664 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), 1665 5 << DPIO_CHV_S1_DIV_SHIFT | 1666 bestp1 << DPIO_CHV_P1_DIV_SHIFT | 1667 bestp2 << DPIO_CHV_P2_DIV_SHIFT | 1668 1 << DPIO_CHV_K_DIV_SHIFT); 1669 1670 /* Feedback post-divider - m2 */ 1671 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); 1672 1673 /* Feedback refclk divider - n and m1 */ 1674 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), 1675 DPIO_CHV_M1_DIV_BY_2 | 1676 1 << DPIO_CHV_N_DIV_SHIFT); 1677 1678 /* M2 fraction division */ 1679 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); 1680 1681 /* M2 fraction division enable */ 1682 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 1683 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); 1684 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); 1685 if (bestm2_frac) 1686 dpio_val |= DPIO_CHV_FRAC_DIV_EN; 1687 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); 1688 1689 /* Program digital lock detect threshold */ 1690 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); 1691 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | 1692 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); 1693 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); 1694 if (!bestm2_frac) 1695 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; 1696 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); 1697 1698 /* Loop filter */ 1699 if (vco == 5400000) { 1700 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); 1701 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); 1702 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); 1703 tribuf_calcntr = 0x9; 1704 } else if (vco <= 6200000) { 1705 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); 1706 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); 1707 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1708 tribuf_calcntr = 0x9; 1709 } else if (vco <= 6480000) { 1710 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 1711 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 1712 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1713 tribuf_calcntr = 0x8; 1714 } else { 1715 /* Not supported. Apply the same limits as in the max case */ 1716 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 1717 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 1718 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1719 tribuf_calcntr = 0; 1720 } 1721 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); 1722 1723 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); 1724 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; 1725 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); 1726 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); 1727 1728 /* AFC Recal */ 1729 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), 1730 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | 1731 DPIO_AFC_RECAL); 1732 1733 vlv_dpio_put(dev_priv); 1734 } 1735 1736 static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) 1737 { 1738 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1739 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1740 enum pipe pipe = crtc->pipe; 1741 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1742 u32 tmp; 1743 1744 vlv_dpio_get(dev_priv); 1745 1746 /* Enable back the 10bit clock to display controller */ 1747 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); 1748 tmp |= DPIO_DCLKP_EN; 1749 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); 1750 1751 vlv_dpio_put(dev_priv); 1752 1753 /* 1754 * Need to wait > 100ns between dclkp clock enable bit and PLL enable. 1755 */ 1756 udelay(1); 1757 1758 /* Enable PLL */ 1759 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); 1760 1761 /* Check PLL is locked */ 1762 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) 1763 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); 1764 } 1765 1766 void chv_enable_pll(const struct intel_crtc_state *crtc_state) 1767 { 1768 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1769 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1770 enum pipe pipe = crtc->pipe; 1771 1772 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1773 1774 /* PLL is protected by panel, make sure we can write it */ 1775 assert_pps_unlocked(dev_priv, pipe); 1776 1777 /* Enable Refclk and SSC */ 1778 intel_de_write(dev_priv, DPLL(pipe), 1779 crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); 1780 1781 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { 1782 chv_prepare_pll(crtc_state); 1783 _chv_enable_pll(crtc_state); 1784 } 1785 1786 if (pipe != PIPE_A) { 1787 /* 1788 * WaPixelRepeatModeFixForC0:chv 1789 * 1790 * DPLLCMD is AWOL. Use chicken bits to propagate 1791 * the value from DPLLBMD to either pipe B or C. 1792 */ 1793 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); 1794 intel_de_write(dev_priv, DPLL_MD(PIPE_B), 1795 crtc_state->dpll_hw_state.dpll_md); 1796 intel_de_write(dev_priv, CBR4_VLV, 0); 1797 dev_priv->chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md; 1798 1799 /* 1800 * DPLLB VGA mode also seems to cause problems. 1801 * We should always have it disabled. 1802 */ 1803 drm_WARN_ON(&dev_priv->drm, 1804 (intel_de_read(dev_priv, DPLL(PIPE_B)) & 1805 DPLL_VGA_MODE_DIS) == 0); 1806 } else { 1807 intel_de_write(dev_priv, DPLL_MD(pipe), 1808 crtc_state->dpll_hw_state.dpll_md); 1809 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); 1810 } 1811 } 1812 1813 /** 1814 * vlv_force_pll_on - forcibly enable just the PLL 1815 * @dev_priv: i915 private structure 1816 * @pipe: pipe PLL to enable 1817 * @dpll: PLL configuration 1818 * 1819 * Enable the PLL for @pipe using the supplied @dpll config. To be used 1820 * in cases where we need the PLL enabled even when @pipe is not going to 1821 * be enabled. 1822 */ 1823 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, 1824 const struct dpll *dpll) 1825 { 1826 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 1827 struct intel_crtc_state *crtc_state; 1828 1829 crtc_state = intel_crtc_state_alloc(crtc); 1830 if (!crtc_state) 1831 return -ENOMEM; 1832 1833 crtc_state->cpu_transcoder = (enum transcoder)pipe; 1834 crtc_state->pixel_multiplier = 1; 1835 crtc_state->dpll = *dpll; 1836 crtc_state->output_types = BIT(INTEL_OUTPUT_EDP); 1837 1838 if (IS_CHERRYVIEW(dev_priv)) { 1839 chv_compute_dpll(crtc_state); 1840 chv_enable_pll(crtc_state); 1841 } else { 1842 vlv_compute_dpll(crtc_state); 1843 vlv_enable_pll(crtc_state); 1844 } 1845 1846 kfree(crtc_state); 1847 1848 return 0; 1849 } 1850 1851 void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 1852 { 1853 u32 val; 1854 1855 /* Make sure the pipe isn't still relying on us */ 1856 assert_transcoder_disabled(dev_priv, (enum transcoder)pipe); 1857 1858 val = DPLL_INTEGRATED_REF_CLK_VLV | 1859 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1860 if (pipe != PIPE_A) 1861 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1862 1863 intel_de_write(dev_priv, DPLL(pipe), val); 1864 intel_de_posting_read(dev_priv, DPLL(pipe)); 1865 } 1866 1867 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 1868 { 1869 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1870 u32 val; 1871 1872 /* Make sure the pipe isn't still relying on us */ 1873 assert_transcoder_disabled(dev_priv, (enum transcoder)pipe); 1874 1875 val = DPLL_SSC_REF_CLK_CHV | 1876 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1877 if (pipe != PIPE_A) 1878 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1879 1880 intel_de_write(dev_priv, DPLL(pipe), val); 1881 intel_de_posting_read(dev_priv, DPLL(pipe)); 1882 1883 vlv_dpio_get(dev_priv); 1884 1885 /* Disable 10bit clock to display controller */ 1886 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); 1887 val &= ~DPIO_DCLKP_EN; 1888 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); 1889 1890 vlv_dpio_put(dev_priv); 1891 } 1892 1893 void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) 1894 { 1895 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1896 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1897 enum pipe pipe = crtc->pipe; 1898 1899 /* Don't disable pipe or pipe PLLs if needed */ 1900 if (IS_I830(dev_priv)) 1901 return; 1902 1903 /* Make sure the pipe isn't still relying on us */ 1904 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1905 1906 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 1907 intel_de_posting_read(dev_priv, DPLL(pipe)); 1908 } 1909 1910 1911 /** 1912 * vlv_force_pll_off - forcibly disable just the PLL 1913 * @dev_priv: i915 private structure 1914 * @pipe: pipe PLL to disable 1915 * 1916 * Disable the PLL for @pipe. To be used in cases where we need 1917 * the PLL enabled even when @pipe is not going to be enabled. 1918 */ 1919 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) 1920 { 1921 if (IS_CHERRYVIEW(dev_priv)) 1922 chv_disable_pll(dev_priv, pipe); 1923 else 1924 vlv_disable_pll(dev_priv, pipe); 1925 } 1926 1927 /* Only for pre-ILK configs */ 1928 static void assert_pll(struct drm_i915_private *dev_priv, 1929 enum pipe pipe, bool state) 1930 { 1931 bool cur_state; 1932 1933 cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; 1934 I915_STATE_WARN(cur_state != state, 1935 "PLL state assertion failure (expected %s, current %s)\n", 1936 onoff(state), onoff(cur_state)); 1937 } 1938 1939 void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe) 1940 { 1941 assert_pll(i915, pipe, true); 1942 } 1943 1944 void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe) 1945 { 1946 assert_pll(i915, pipe, false); 1947 } 1948