1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 #include <linux/kernel.h> 6 #include "intel_crtc.h" 7 #include "intel_display_types.h" 8 #include "intel_display.h" 9 #include "intel_dpll.h" 10 #include "intel_lvds.h" 11 #include "intel_panel.h" 12 #include "intel_sideband.h" 13 14 struct intel_limit { 15 struct { 16 int min, max; 17 } dot, vco, n, m, m1, m2, p, p1; 18 19 struct { 20 int dot_limit; 21 int p2_slow, p2_fast; 22 } p2; 23 }; 24 static const struct intel_limit intel_limits_i8xx_dac = { 25 .dot = { .min = 25000, .max = 350000 }, 26 .vco = { .min = 908000, .max = 1512000 }, 27 .n = { .min = 2, .max = 16 }, 28 .m = { .min = 96, .max = 140 }, 29 .m1 = { .min = 18, .max = 26 }, 30 .m2 = { .min = 6, .max = 16 }, 31 .p = { .min = 4, .max = 128 }, 32 .p1 = { .min = 2, .max = 33 }, 33 .p2 = { .dot_limit = 165000, 34 .p2_slow = 4, .p2_fast = 2 }, 35 }; 36 37 static const struct intel_limit intel_limits_i8xx_dvo = { 38 .dot = { .min = 25000, .max = 350000 }, 39 .vco = { .min = 908000, .max = 1512000 }, 40 .n = { .min = 2, .max = 16 }, 41 .m = { .min = 96, .max = 140 }, 42 .m1 = { .min = 18, .max = 26 }, 43 .m2 = { .min = 6, .max = 16 }, 44 .p = { .min = 4, .max = 128 }, 45 .p1 = { .min = 2, .max = 33 }, 46 .p2 = { .dot_limit = 165000, 47 .p2_slow = 4, .p2_fast = 4 }, 48 }; 49 50 static const struct intel_limit intel_limits_i8xx_lvds = { 51 .dot = { .min = 25000, .max = 350000 }, 52 .vco = { .min = 908000, .max = 1512000 }, 53 .n = { .min = 2, .max = 16 }, 54 .m = { .min = 96, .max = 140 }, 55 .m1 = { .min = 18, .max = 26 }, 56 .m2 = { .min = 6, .max = 16 }, 57 .p = { .min = 4, .max = 128 }, 58 .p1 = { .min = 1, .max = 6 }, 59 .p2 = { .dot_limit = 165000, 60 .p2_slow = 14, .p2_fast = 7 }, 61 }; 62 63 static const struct intel_limit intel_limits_i9xx_sdvo = { 64 .dot = { .min = 20000, .max = 400000 }, 65 .vco = { .min = 1400000, .max = 2800000 }, 66 .n = { .min = 1, .max = 6 }, 67 .m = { .min = 70, .max = 120 }, 68 .m1 = { .min = 8, .max = 18 }, 69 .m2 = { .min = 3, .max = 7 }, 70 .p = { .min = 5, .max = 80 }, 71 .p1 = { .min = 1, .max = 8 }, 72 .p2 = { .dot_limit = 200000, 73 .p2_slow = 10, .p2_fast = 5 }, 74 }; 75 76 static const struct intel_limit intel_limits_i9xx_lvds = { 77 .dot = { .min = 20000, .max = 400000 }, 78 .vco = { .min = 1400000, .max = 2800000 }, 79 .n = { .min = 1, .max = 6 }, 80 .m = { .min = 70, .max = 120 }, 81 .m1 = { .min = 8, .max = 18 }, 82 .m2 = { .min = 3, .max = 7 }, 83 .p = { .min = 7, .max = 98 }, 84 .p1 = { .min = 1, .max = 8 }, 85 .p2 = { .dot_limit = 112000, 86 .p2_slow = 14, .p2_fast = 7 }, 87 }; 88 89 90 static const struct intel_limit intel_limits_g4x_sdvo = { 91 .dot = { .min = 25000, .max = 270000 }, 92 .vco = { .min = 1750000, .max = 3500000}, 93 .n = { .min = 1, .max = 4 }, 94 .m = { .min = 104, .max = 138 }, 95 .m1 = { .min = 17, .max = 23 }, 96 .m2 = { .min = 5, .max = 11 }, 97 .p = { .min = 10, .max = 30 }, 98 .p1 = { .min = 1, .max = 3}, 99 .p2 = { .dot_limit = 270000, 100 .p2_slow = 10, 101 .p2_fast = 10 102 }, 103 }; 104 105 static const struct intel_limit intel_limits_g4x_hdmi = { 106 .dot = { .min = 22000, .max = 400000 }, 107 .vco = { .min = 1750000, .max = 3500000}, 108 .n = { .min = 1, .max = 4 }, 109 .m = { .min = 104, .max = 138 }, 110 .m1 = { .min = 16, .max = 23 }, 111 .m2 = { .min = 5, .max = 11 }, 112 .p = { .min = 5, .max = 80 }, 113 .p1 = { .min = 1, .max = 8}, 114 .p2 = { .dot_limit = 165000, 115 .p2_slow = 10, .p2_fast = 5 }, 116 }; 117 118 static const struct intel_limit intel_limits_g4x_single_channel_lvds = { 119 .dot = { .min = 20000, .max = 115000 }, 120 .vco = { .min = 1750000, .max = 3500000 }, 121 .n = { .min = 1, .max = 3 }, 122 .m = { .min = 104, .max = 138 }, 123 .m1 = { .min = 17, .max = 23 }, 124 .m2 = { .min = 5, .max = 11 }, 125 .p = { .min = 28, .max = 112 }, 126 .p1 = { .min = 2, .max = 8 }, 127 .p2 = { .dot_limit = 0, 128 .p2_slow = 14, .p2_fast = 14 129 }, 130 }; 131 132 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { 133 .dot = { .min = 80000, .max = 224000 }, 134 .vco = { .min = 1750000, .max = 3500000 }, 135 .n = { .min = 1, .max = 3 }, 136 .m = { .min = 104, .max = 138 }, 137 .m1 = { .min = 17, .max = 23 }, 138 .m2 = { .min = 5, .max = 11 }, 139 .p = { .min = 14, .max = 42 }, 140 .p1 = { .min = 2, .max = 6 }, 141 .p2 = { .dot_limit = 0, 142 .p2_slow = 7, .p2_fast = 7 143 }, 144 }; 145 146 static const struct intel_limit pnv_limits_sdvo = { 147 .dot = { .min = 20000, .max = 400000}, 148 .vco = { .min = 1700000, .max = 3500000 }, 149 /* Pineview's Ncounter is a ring counter */ 150 .n = { .min = 3, .max = 6 }, 151 .m = { .min = 2, .max = 256 }, 152 /* Pineview only has one combined m divider, which we treat as m2. */ 153 .m1 = { .min = 0, .max = 0 }, 154 .m2 = { .min = 0, .max = 254 }, 155 .p = { .min = 5, .max = 80 }, 156 .p1 = { .min = 1, .max = 8 }, 157 .p2 = { .dot_limit = 200000, 158 .p2_slow = 10, .p2_fast = 5 }, 159 }; 160 161 static const struct intel_limit pnv_limits_lvds = { 162 .dot = { .min = 20000, .max = 400000 }, 163 .vco = { .min = 1700000, .max = 3500000 }, 164 .n = { .min = 3, .max = 6 }, 165 .m = { .min = 2, .max = 256 }, 166 .m1 = { .min = 0, .max = 0 }, 167 .m2 = { .min = 0, .max = 254 }, 168 .p = { .min = 7, .max = 112 }, 169 .p1 = { .min = 1, .max = 8 }, 170 .p2 = { .dot_limit = 112000, 171 .p2_slow = 14, .p2_fast = 14 }, 172 }; 173 174 /* Ironlake / Sandybridge 175 * 176 * We calculate clock using (register_value + 2) for N/M1/M2, so here 177 * the range value for them is (actual_value - 2). 178 */ 179 static const struct intel_limit ilk_limits_dac = { 180 .dot = { .min = 25000, .max = 350000 }, 181 .vco = { .min = 1760000, .max = 3510000 }, 182 .n = { .min = 1, .max = 5 }, 183 .m = { .min = 79, .max = 127 }, 184 .m1 = { .min = 12, .max = 22 }, 185 .m2 = { .min = 5, .max = 9 }, 186 .p = { .min = 5, .max = 80 }, 187 .p1 = { .min = 1, .max = 8 }, 188 .p2 = { .dot_limit = 225000, 189 .p2_slow = 10, .p2_fast = 5 }, 190 }; 191 192 static const struct intel_limit ilk_limits_single_lvds = { 193 .dot = { .min = 25000, .max = 350000 }, 194 .vco = { .min = 1760000, .max = 3510000 }, 195 .n = { .min = 1, .max = 3 }, 196 .m = { .min = 79, .max = 118 }, 197 .m1 = { .min = 12, .max = 22 }, 198 .m2 = { .min = 5, .max = 9 }, 199 .p = { .min = 28, .max = 112 }, 200 .p1 = { .min = 2, .max = 8 }, 201 .p2 = { .dot_limit = 225000, 202 .p2_slow = 14, .p2_fast = 14 }, 203 }; 204 205 static const struct intel_limit ilk_limits_dual_lvds = { 206 .dot = { .min = 25000, .max = 350000 }, 207 .vco = { .min = 1760000, .max = 3510000 }, 208 .n = { .min = 1, .max = 3 }, 209 .m = { .min = 79, .max = 127 }, 210 .m1 = { .min = 12, .max = 22 }, 211 .m2 = { .min = 5, .max = 9 }, 212 .p = { .min = 14, .max = 56 }, 213 .p1 = { .min = 2, .max = 8 }, 214 .p2 = { .dot_limit = 225000, 215 .p2_slow = 7, .p2_fast = 7 }, 216 }; 217 218 /* LVDS 100mhz refclk limits. */ 219 static const struct intel_limit ilk_limits_single_lvds_100m = { 220 .dot = { .min = 25000, .max = 350000 }, 221 .vco = { .min = 1760000, .max = 3510000 }, 222 .n = { .min = 1, .max = 2 }, 223 .m = { .min = 79, .max = 126 }, 224 .m1 = { .min = 12, .max = 22 }, 225 .m2 = { .min = 5, .max = 9 }, 226 .p = { .min = 28, .max = 112 }, 227 .p1 = { .min = 2, .max = 8 }, 228 .p2 = { .dot_limit = 225000, 229 .p2_slow = 14, .p2_fast = 14 }, 230 }; 231 232 static const struct intel_limit ilk_limits_dual_lvds_100m = { 233 .dot = { .min = 25000, .max = 350000 }, 234 .vco = { .min = 1760000, .max = 3510000 }, 235 .n = { .min = 1, .max = 3 }, 236 .m = { .min = 79, .max = 126 }, 237 .m1 = { .min = 12, .max = 22 }, 238 .m2 = { .min = 5, .max = 9 }, 239 .p = { .min = 14, .max = 42 }, 240 .p1 = { .min = 2, .max = 6 }, 241 .p2 = { .dot_limit = 225000, 242 .p2_slow = 7, .p2_fast = 7 }, 243 }; 244 245 static const struct intel_limit intel_limits_vlv = { 246 /* 247 * These are the data rate limits (measured in fast clocks) 248 * since those are the strictest limits we have. The fast 249 * clock and actual rate limits are more relaxed, so checking 250 * them would make no difference. 251 */ 252 .dot = { .min = 25000 * 5, .max = 270000 * 5 }, 253 .vco = { .min = 4000000, .max = 6000000 }, 254 .n = { .min = 1, .max = 7 }, 255 .m1 = { .min = 2, .max = 3 }, 256 .m2 = { .min = 11, .max = 156 }, 257 .p1 = { .min = 2, .max = 3 }, 258 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ 259 }; 260 261 static const struct intel_limit intel_limits_chv = { 262 /* 263 * These are the data rate limits (measured in fast clocks) 264 * since those are the strictest limits we have. The fast 265 * clock and actual rate limits are more relaxed, so checking 266 * them would make no difference. 267 */ 268 .dot = { .min = 25000 * 5, .max = 540000 * 5}, 269 .vco = { .min = 4800000, .max = 6480000 }, 270 .n = { .min = 1, .max = 1 }, 271 .m1 = { .min = 2, .max = 2 }, 272 .m2 = { .min = 24 << 22, .max = 175 << 22 }, 273 .p1 = { .min = 2, .max = 4 }, 274 .p2 = { .p2_slow = 1, .p2_fast = 14 }, 275 }; 276 277 static const struct intel_limit intel_limits_bxt = { 278 /* FIXME: find real dot limits */ 279 .dot = { .min = 0, .max = INT_MAX }, 280 .vco = { .min = 4800000, .max = 6700000 }, 281 .n = { .min = 1, .max = 1 }, 282 .m1 = { .min = 2, .max = 2 }, 283 /* FIXME: find real m2 limits */ 284 .m2 = { .min = 2 << 22, .max = 255 << 22 }, 285 .p1 = { .min = 2, .max = 4 }, 286 .p2 = { .p2_slow = 1, .p2_fast = 20 }, 287 }; 288 289 /* 290 * Platform specific helpers to calculate the port PLL loopback- (clock.m), 291 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast 292 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. 293 * The helpers' return value is the rate of the clock that is fed to the 294 * display engine's pipe which can be the above fast dot clock rate or a 295 * divided-down version of it. 296 */ 297 /* m1 is reserved as 0 in Pineview, n is a ring counter */ 298 int pnv_calc_dpll_params(int refclk, struct dpll *clock) 299 { 300 clock->m = clock->m2 + 2; 301 clock->p = clock->p1 * clock->p2; 302 if (WARN_ON(clock->n == 0 || clock->p == 0)) 303 return 0; 304 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 305 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 306 307 return clock->dot; 308 } 309 310 static u32 i9xx_dpll_compute_m(struct dpll *dpll) 311 { 312 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); 313 } 314 315 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) 316 { 317 clock->m = i9xx_dpll_compute_m(clock); 318 clock->p = clock->p1 * clock->p2; 319 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) 320 return 0; 321 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); 322 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 323 324 return clock->dot; 325 } 326 327 int vlv_calc_dpll_params(int refclk, struct dpll *clock) 328 { 329 clock->m = clock->m1 * clock->m2; 330 clock->p = clock->p1 * clock->p2; 331 if (WARN_ON(clock->n == 0 || clock->p == 0)) 332 return 0; 333 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 334 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 335 336 return clock->dot / 5; 337 } 338 339 int chv_calc_dpll_params(int refclk, struct dpll *clock) 340 { 341 clock->m = clock->m1 * clock->m2; 342 clock->p = clock->p1 * clock->p2; 343 if (WARN_ON(clock->n == 0 || clock->p == 0)) 344 return 0; 345 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), 346 clock->n << 22); 347 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 348 349 return clock->dot / 5; 350 } 351 352 /* 353 * Returns whether the given set of divisors are valid for a given refclk with 354 * the given connectors. 355 */ 356 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv, 357 const struct intel_limit *limit, 358 const struct dpll *clock) 359 { 360 if (clock->n < limit->n.min || limit->n.max < clock->n) 361 return false; 362 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 363 return false; 364 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 365 return false; 366 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 367 return false; 368 369 if (!IS_PINEVIEW(dev_priv) && !IS_VALLEYVIEW(dev_priv) && 370 !IS_CHERRYVIEW(dev_priv) && !IS_GEN9_LP(dev_priv)) 371 if (clock->m1 <= clock->m2) 372 return false; 373 374 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && 375 !IS_GEN9_LP(dev_priv)) { 376 if (clock->p < limit->p.min || limit->p.max < clock->p) 377 return false; 378 if (clock->m < limit->m.min || limit->m.max < clock->m) 379 return false; 380 } 381 382 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 383 return false; 384 /* XXX: We may need to be checking "Dot clock" depending on the multiplier, 385 * connector, etc., rather than just a single range. 386 */ 387 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 388 return false; 389 390 return true; 391 } 392 393 static int 394 i9xx_select_p2_div(const struct intel_limit *limit, 395 const struct intel_crtc_state *crtc_state, 396 int target) 397 { 398 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 399 400 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 401 /* 402 * For LVDS just rely on its current settings for dual-channel. 403 * We haven't figured out how to reliably set up different 404 * single/dual channel state, if we even can. 405 */ 406 if (intel_is_dual_link_lvds(dev_priv)) 407 return limit->p2.p2_fast; 408 else 409 return limit->p2.p2_slow; 410 } else { 411 if (target < limit->p2.dot_limit) 412 return limit->p2.p2_slow; 413 else 414 return limit->p2.p2_fast; 415 } 416 } 417 418 /* 419 * Returns a set of divisors for the desired target clock with the given 420 * refclk, or FALSE. The returned values represent the clock equation: 421 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 422 * 423 * Target and reference clocks are specified in kHz. 424 * 425 * If match_clock is provided, then best_clock P divider must match the P 426 * divider from @match_clock used for LVDS downclocking. 427 */ 428 static bool 429 i9xx_find_best_dpll(const struct intel_limit *limit, 430 struct intel_crtc_state *crtc_state, 431 int target, int refclk, struct dpll *match_clock, 432 struct dpll *best_clock) 433 { 434 struct drm_device *dev = crtc_state->uapi.crtc->dev; 435 struct dpll clock; 436 int err = target; 437 438 memset(best_clock, 0, sizeof(*best_clock)); 439 440 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 441 442 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 443 clock.m1++) { 444 for (clock.m2 = limit->m2.min; 445 clock.m2 <= limit->m2.max; clock.m2++) { 446 if (clock.m2 >= clock.m1) 447 break; 448 for (clock.n = limit->n.min; 449 clock.n <= limit->n.max; clock.n++) { 450 for (clock.p1 = limit->p1.min; 451 clock.p1 <= limit->p1.max; clock.p1++) { 452 int this_err; 453 454 i9xx_calc_dpll_params(refclk, &clock); 455 if (!intel_pll_is_valid(to_i915(dev), 456 limit, 457 &clock)) 458 continue; 459 if (match_clock && 460 clock.p != match_clock->p) 461 continue; 462 463 this_err = abs(clock.dot - target); 464 if (this_err < err) { 465 *best_clock = clock; 466 err = this_err; 467 } 468 } 469 } 470 } 471 } 472 473 return (err != target); 474 } 475 476 /* 477 * Returns a set of divisors for the desired target clock with the given 478 * refclk, or FALSE. The returned values represent the clock equation: 479 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 480 * 481 * Target and reference clocks are specified in kHz. 482 * 483 * If match_clock is provided, then best_clock P divider must match the P 484 * divider from @match_clock used for LVDS downclocking. 485 */ 486 static bool 487 pnv_find_best_dpll(const struct intel_limit *limit, 488 struct intel_crtc_state *crtc_state, 489 int target, int refclk, struct dpll *match_clock, 490 struct dpll *best_clock) 491 { 492 struct drm_device *dev = crtc_state->uapi.crtc->dev; 493 struct dpll clock; 494 int err = target; 495 496 memset(best_clock, 0, sizeof(*best_clock)); 497 498 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 499 500 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 501 clock.m1++) { 502 for (clock.m2 = limit->m2.min; 503 clock.m2 <= limit->m2.max; clock.m2++) { 504 for (clock.n = limit->n.min; 505 clock.n <= limit->n.max; clock.n++) { 506 for (clock.p1 = limit->p1.min; 507 clock.p1 <= limit->p1.max; clock.p1++) { 508 int this_err; 509 510 pnv_calc_dpll_params(refclk, &clock); 511 if (!intel_pll_is_valid(to_i915(dev), 512 limit, 513 &clock)) 514 continue; 515 if (match_clock && 516 clock.p != match_clock->p) 517 continue; 518 519 this_err = abs(clock.dot - target); 520 if (this_err < err) { 521 *best_clock = clock; 522 err = this_err; 523 } 524 } 525 } 526 } 527 } 528 529 return (err != target); 530 } 531 532 /* 533 * Returns a set of divisors for the desired target clock with the given 534 * refclk, or FALSE. The returned values represent the clock equation: 535 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 536 * 537 * Target and reference clocks are specified in kHz. 538 * 539 * If match_clock is provided, then best_clock P divider must match the P 540 * divider from @match_clock used for LVDS downclocking. 541 */ 542 static bool 543 g4x_find_best_dpll(const struct intel_limit *limit, 544 struct intel_crtc_state *crtc_state, 545 int target, int refclk, struct dpll *match_clock, 546 struct dpll *best_clock) 547 { 548 struct drm_device *dev = crtc_state->uapi.crtc->dev; 549 struct dpll clock; 550 int max_n; 551 bool found = false; 552 /* approximately equals target * 0.00585 */ 553 int err_most = (target >> 8) + (target >> 9); 554 555 memset(best_clock, 0, sizeof(*best_clock)); 556 557 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 558 559 max_n = limit->n.max; 560 /* based on hardware requirement, prefer smaller n to precision */ 561 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 562 /* based on hardware requirement, prefere larger m1,m2 */ 563 for (clock.m1 = limit->m1.max; 564 clock.m1 >= limit->m1.min; clock.m1--) { 565 for (clock.m2 = limit->m2.max; 566 clock.m2 >= limit->m2.min; clock.m2--) { 567 for (clock.p1 = limit->p1.max; 568 clock.p1 >= limit->p1.min; clock.p1--) { 569 int this_err; 570 571 i9xx_calc_dpll_params(refclk, &clock); 572 if (!intel_pll_is_valid(to_i915(dev), 573 limit, 574 &clock)) 575 continue; 576 577 this_err = abs(clock.dot - target); 578 if (this_err < err_most) { 579 *best_clock = clock; 580 err_most = this_err; 581 max_n = clock.n; 582 found = true; 583 } 584 } 585 } 586 } 587 } 588 return found; 589 } 590 591 /* 592 * Check if the calculated PLL configuration is more optimal compared to the 593 * best configuration and error found so far. Return the calculated error. 594 */ 595 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, 596 const struct dpll *calculated_clock, 597 const struct dpll *best_clock, 598 unsigned int best_error_ppm, 599 unsigned int *error_ppm) 600 { 601 /* 602 * For CHV ignore the error and consider only the P value. 603 * Prefer a bigger P value based on HW requirements. 604 */ 605 if (IS_CHERRYVIEW(to_i915(dev))) { 606 *error_ppm = 0; 607 608 return calculated_clock->p > best_clock->p; 609 } 610 611 if (drm_WARN_ON_ONCE(dev, !target_freq)) 612 return false; 613 614 *error_ppm = div_u64(1000000ULL * 615 abs(target_freq - calculated_clock->dot), 616 target_freq); 617 /* 618 * Prefer a better P value over a better (smaller) error if the error 619 * is small. Ensure this preference for future configurations too by 620 * setting the error to 0. 621 */ 622 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { 623 *error_ppm = 0; 624 625 return true; 626 } 627 628 return *error_ppm + 10 < best_error_ppm; 629 } 630 631 /* 632 * Returns a set of divisors for the desired target clock with the given 633 * refclk, or FALSE. The returned values represent the clock equation: 634 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 635 */ 636 static bool 637 vlv_find_best_dpll(const struct intel_limit *limit, 638 struct intel_crtc_state *crtc_state, 639 int target, int refclk, struct dpll *match_clock, 640 struct dpll *best_clock) 641 { 642 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 643 struct drm_device *dev = crtc->base.dev; 644 struct dpll clock; 645 unsigned int bestppm = 1000000; 646 /* min update 19.2 MHz */ 647 int max_n = min(limit->n.max, refclk / 19200); 648 bool found = false; 649 650 target *= 5; /* fast clock */ 651 652 memset(best_clock, 0, sizeof(*best_clock)); 653 654 /* based on hardware requirement, prefer smaller n to precision */ 655 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 656 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 657 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; 658 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 659 clock.p = clock.p1 * clock.p2; 660 /* based on hardware requirement, prefer bigger m1,m2 values */ 661 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { 662 unsigned int ppm; 663 664 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, 665 refclk * clock.m1); 666 667 vlv_calc_dpll_params(refclk, &clock); 668 669 if (!intel_pll_is_valid(to_i915(dev), 670 limit, 671 &clock)) 672 continue; 673 674 if (!vlv_PLL_is_optimal(dev, target, 675 &clock, 676 best_clock, 677 bestppm, &ppm)) 678 continue; 679 680 *best_clock = clock; 681 bestppm = ppm; 682 found = true; 683 } 684 } 685 } 686 } 687 688 return found; 689 } 690 691 /* 692 * Returns a set of divisors for the desired target clock with the given 693 * refclk, or FALSE. The returned values represent the clock equation: 694 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 695 */ 696 static bool 697 chv_find_best_dpll(const struct intel_limit *limit, 698 struct intel_crtc_state *crtc_state, 699 int target, int refclk, struct dpll *match_clock, 700 struct dpll *best_clock) 701 { 702 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 703 struct drm_device *dev = crtc->base.dev; 704 unsigned int best_error_ppm; 705 struct dpll clock; 706 u64 m2; 707 int found = false; 708 709 memset(best_clock, 0, sizeof(*best_clock)); 710 best_error_ppm = 1000000; 711 712 /* 713 * Based on hardware doc, the n always set to 1, and m1 always 714 * set to 2. If requires to support 200Mhz refclk, we need to 715 * revisit this because n may not 1 anymore. 716 */ 717 clock.n = 1; 718 clock.m1 = 2; 719 target *= 5; /* fast clock */ 720 721 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 722 for (clock.p2 = limit->p2.p2_fast; 723 clock.p2 >= limit->p2.p2_slow; 724 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 725 unsigned int error_ppm; 726 727 clock.p = clock.p1 * clock.p2; 728 729 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22, 730 refclk * clock.m1); 731 732 if (m2 > INT_MAX/clock.m1) 733 continue; 734 735 clock.m2 = m2; 736 737 chv_calc_dpll_params(refclk, &clock); 738 739 if (!intel_pll_is_valid(to_i915(dev), limit, &clock)) 740 continue; 741 742 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, 743 best_error_ppm, &error_ppm)) 744 continue; 745 746 *best_clock = clock; 747 best_error_ppm = error_ppm; 748 found = true; 749 } 750 } 751 752 return found; 753 } 754 755 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, 756 struct dpll *best_clock) 757 { 758 int refclk = 100000; 759 const struct intel_limit *limit = &intel_limits_bxt; 760 761 return chv_find_best_dpll(limit, crtc_state, 762 crtc_state->port_clock, refclk, 763 NULL, best_clock); 764 } 765 766 static u32 pnv_dpll_compute_fp(struct dpll *dpll) 767 { 768 return (1 << dpll->n) << 16 | dpll->m2; 769 } 770 771 static void i9xx_update_pll_dividers(struct intel_crtc *crtc, 772 struct intel_crtc_state *crtc_state, 773 struct dpll *reduced_clock) 774 { 775 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 776 u32 fp, fp2 = 0; 777 778 if (IS_PINEVIEW(dev_priv)) { 779 fp = pnv_dpll_compute_fp(&crtc_state->dpll); 780 if (reduced_clock) 781 fp2 = pnv_dpll_compute_fp(reduced_clock); 782 } else { 783 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); 784 if (reduced_clock) 785 fp2 = i9xx_dpll_compute_fp(reduced_clock); 786 } 787 788 crtc_state->dpll_hw_state.fp0 = fp; 789 790 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 791 reduced_clock) { 792 crtc_state->dpll_hw_state.fp1 = fp2; 793 } else { 794 crtc_state->dpll_hw_state.fp1 = fp; 795 } 796 } 797 798 static void i9xx_compute_dpll(struct intel_crtc *crtc, 799 struct intel_crtc_state *crtc_state, 800 struct dpll *reduced_clock) 801 { 802 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 803 u32 dpll; 804 struct dpll *clock = &crtc_state->dpll; 805 806 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); 807 808 dpll = DPLL_VGA_MODE_DIS; 809 810 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) 811 dpll |= DPLLB_MODE_LVDS; 812 else 813 dpll |= DPLLB_MODE_DAC_SERIAL; 814 815 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 816 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 817 dpll |= (crtc_state->pixel_multiplier - 1) 818 << SDVO_MULTIPLIER_SHIFT_HIRES; 819 } 820 821 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || 822 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 823 dpll |= DPLL_SDVO_HIGH_SPEED; 824 825 if (intel_crtc_has_dp_encoder(crtc_state)) 826 dpll |= DPLL_SDVO_HIGH_SPEED; 827 828 /* compute bitmask from p1 value */ 829 if (IS_PINEVIEW(dev_priv)) 830 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; 831 else { 832 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 833 if (IS_G4X(dev_priv) && reduced_clock) 834 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 835 } 836 switch (clock->p2) { 837 case 5: 838 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 839 break; 840 case 7: 841 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 842 break; 843 case 10: 844 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 845 break; 846 case 14: 847 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 848 break; 849 } 850 if (DISPLAY_VER(dev_priv) >= 4) 851 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 852 853 if (crtc_state->sdvo_tv_clock) 854 dpll |= PLL_REF_INPUT_TVCLKINBC; 855 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 856 intel_panel_use_ssc(dev_priv)) 857 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 858 else 859 dpll |= PLL_REF_INPUT_DREFCLK; 860 861 dpll |= DPLL_VCO_ENABLE; 862 crtc_state->dpll_hw_state.dpll = dpll; 863 864 if (DISPLAY_VER(dev_priv) >= 4) { 865 u32 dpll_md = (crtc_state->pixel_multiplier - 1) 866 << DPLL_MD_UDI_MULTIPLIER_SHIFT; 867 crtc_state->dpll_hw_state.dpll_md = dpll_md; 868 } 869 } 870 871 static void i8xx_compute_dpll(struct intel_crtc *crtc, 872 struct intel_crtc_state *crtc_state, 873 struct dpll *reduced_clock) 874 { 875 struct drm_device *dev = crtc->base.dev; 876 struct drm_i915_private *dev_priv = to_i915(dev); 877 u32 dpll; 878 struct dpll *clock = &crtc_state->dpll; 879 880 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); 881 882 dpll = DPLL_VGA_MODE_DIS; 883 884 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 885 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 886 } else { 887 if (clock->p1 == 2) 888 dpll |= PLL_P1_DIVIDE_BY_TWO; 889 else 890 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; 891 if (clock->p2 == 4) 892 dpll |= PLL_P2_DIVIDE_BY_4; 893 } 894 895 /* 896 * Bspec: 897 * "[Almador Errata}: For the correct operation of the muxed DVO pins 898 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, 899 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock 900 * Enable) must be set to “1” in both the DPLL A Control Register 901 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." 902 * 903 * For simplicity We simply keep both bits always enabled in 904 * both DPLLS. The spec says we should disable the DVO 2X clock 905 * when not needed, but this seems to work fine in practice. 906 */ 907 if (IS_I830(dev_priv) || 908 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) 909 dpll |= DPLL_DVO_2X_MODE; 910 911 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 912 intel_panel_use_ssc(dev_priv)) 913 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 914 else 915 dpll |= PLL_REF_INPUT_DREFCLK; 916 917 dpll |= DPLL_VCO_ENABLE; 918 crtc_state->dpll_hw_state.dpll = dpll; 919 } 920 921 static int hsw_crtc_compute_clock(struct intel_crtc *crtc, 922 struct intel_crtc_state *crtc_state) 923 { 924 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 925 struct intel_atomic_state *state = 926 to_intel_atomic_state(crtc_state->uapi.state); 927 928 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) || 929 DISPLAY_VER(dev_priv) >= 11) { 930 struct intel_encoder *encoder = 931 intel_get_crtc_new_encoder(state, crtc_state); 932 933 if (!intel_reserve_shared_dplls(state, crtc, encoder)) { 934 drm_dbg_kms(&dev_priv->drm, 935 "failed to find PLL for pipe %c\n", 936 pipe_name(crtc->pipe)); 937 return -EINVAL; 938 } 939 } 940 941 return 0; 942 } 943 944 static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor) 945 { 946 return i9xx_dpll_compute_m(dpll) < factor * dpll->n; 947 } 948 949 950 static void ilk_compute_dpll(struct intel_crtc *crtc, 951 struct intel_crtc_state *crtc_state, 952 struct dpll *reduced_clock) 953 { 954 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 955 u32 dpll, fp, fp2; 956 int factor; 957 958 /* Enable autotuning of the PLL clock (if permissible) */ 959 factor = 21; 960 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 961 if ((intel_panel_use_ssc(dev_priv) && 962 dev_priv->vbt.lvds_ssc_freq == 100000) || 963 (HAS_PCH_IBX(dev_priv) && 964 intel_is_dual_link_lvds(dev_priv))) 965 factor = 25; 966 } else if (crtc_state->sdvo_tv_clock) { 967 factor = 20; 968 } 969 970 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); 971 972 if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor)) 973 fp |= FP_CB_TUNE; 974 975 if (reduced_clock) { 976 fp2 = i9xx_dpll_compute_fp(reduced_clock); 977 978 if (reduced_clock->m < factor * reduced_clock->n) 979 fp2 |= FP_CB_TUNE; 980 } else { 981 fp2 = fp; 982 } 983 984 dpll = 0; 985 986 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) 987 dpll |= DPLLB_MODE_LVDS; 988 else 989 dpll |= DPLLB_MODE_DAC_SERIAL; 990 991 dpll |= (crtc_state->pixel_multiplier - 1) 992 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 993 994 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || 995 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 996 dpll |= DPLL_SDVO_HIGH_SPEED; 997 998 if (intel_crtc_has_dp_encoder(crtc_state)) 999 dpll |= DPLL_SDVO_HIGH_SPEED; 1000 1001 /* 1002 * The high speed IO clock is only really required for 1003 * SDVO/HDMI/DP, but we also enable it for CRT to make it 1004 * possible to share the DPLL between CRT and HDMI. Enabling 1005 * the clock needlessly does no real harm, except use up a 1006 * bit of power potentially. 1007 * 1008 * We'll limit this to IVB with 3 pipes, since it has only two 1009 * DPLLs and so DPLL sharing is the only way to get three pipes 1010 * driving PCH ports at the same time. On SNB we could do this, 1011 * and potentially avoid enabling the second DPLL, but it's not 1012 * clear if it''s a win or loss power wise. No point in doing 1013 * this on ILK at all since it has a fixed DPLL<->pipe mapping. 1014 */ 1015 if (INTEL_NUM_PIPES(dev_priv) == 3 && 1016 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1017 dpll |= DPLL_SDVO_HIGH_SPEED; 1018 1019 /* compute bitmask from p1 value */ 1020 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 1021 /* also FPA1 */ 1022 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 1023 1024 switch (crtc_state->dpll.p2) { 1025 case 5: 1026 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 1027 break; 1028 case 7: 1029 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 1030 break; 1031 case 10: 1032 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 1033 break; 1034 case 14: 1035 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 1036 break; 1037 } 1038 1039 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 1040 intel_panel_use_ssc(dev_priv)) 1041 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 1042 else 1043 dpll |= PLL_REF_INPUT_DREFCLK; 1044 1045 dpll |= DPLL_VCO_ENABLE; 1046 1047 crtc_state->dpll_hw_state.dpll = dpll; 1048 crtc_state->dpll_hw_state.fp0 = fp; 1049 crtc_state->dpll_hw_state.fp1 = fp2; 1050 } 1051 1052 static int ilk_crtc_compute_clock(struct intel_crtc *crtc, 1053 struct intel_crtc_state *crtc_state) 1054 { 1055 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1056 struct intel_atomic_state *state = 1057 to_intel_atomic_state(crtc_state->uapi.state); 1058 const struct intel_limit *limit; 1059 int refclk = 120000; 1060 1061 memset(&crtc_state->dpll_hw_state, 0, 1062 sizeof(crtc_state->dpll_hw_state)); 1063 1064 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 1065 if (!crtc_state->has_pch_encoder) 1066 return 0; 1067 1068 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1069 if (intel_panel_use_ssc(dev_priv)) { 1070 drm_dbg_kms(&dev_priv->drm, 1071 "using SSC reference clock of %d kHz\n", 1072 dev_priv->vbt.lvds_ssc_freq); 1073 refclk = dev_priv->vbt.lvds_ssc_freq; 1074 } 1075 1076 if (intel_is_dual_link_lvds(dev_priv)) { 1077 if (refclk == 100000) 1078 limit = &ilk_limits_dual_lvds_100m; 1079 else 1080 limit = &ilk_limits_dual_lvds; 1081 } else { 1082 if (refclk == 100000) 1083 limit = &ilk_limits_single_lvds_100m; 1084 else 1085 limit = &ilk_limits_single_lvds; 1086 } 1087 } else { 1088 limit = &ilk_limits_dac; 1089 } 1090 1091 if (!crtc_state->clock_set && 1092 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1093 refclk, NULL, &crtc_state->dpll)) { 1094 drm_err(&dev_priv->drm, 1095 "Couldn't find PLL settings for mode!\n"); 1096 return -EINVAL; 1097 } 1098 1099 ilk_compute_dpll(crtc, crtc_state, NULL); 1100 1101 if (!intel_reserve_shared_dplls(state, crtc, NULL)) { 1102 drm_dbg_kms(&dev_priv->drm, 1103 "failed to find PLL for pipe %c\n", 1104 pipe_name(crtc->pipe)); 1105 return -EINVAL; 1106 } 1107 1108 return 0; 1109 } 1110 1111 void vlv_compute_dpll(struct intel_crtc *crtc, 1112 struct intel_crtc_state *pipe_config) 1113 { 1114 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | 1115 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1116 if (crtc->pipe != PIPE_A) 1117 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 1118 1119 /* DPLL not used with DSI, but still need the rest set up */ 1120 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) 1121 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | 1122 DPLL_EXT_BUFFER_ENABLE_VLV; 1123 1124 pipe_config->dpll_hw_state.dpll_md = 1125 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 1126 } 1127 1128 void chv_compute_dpll(struct intel_crtc *crtc, 1129 struct intel_crtc_state *pipe_config) 1130 { 1131 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | 1132 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1133 if (crtc->pipe != PIPE_A) 1134 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 1135 1136 /* DPLL not used with DSI, but still need the rest set up */ 1137 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) 1138 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; 1139 1140 pipe_config->dpll_hw_state.dpll_md = 1141 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 1142 } 1143 1144 static int chv_crtc_compute_clock(struct intel_crtc *crtc, 1145 struct intel_crtc_state *crtc_state) 1146 { 1147 int refclk = 100000; 1148 const struct intel_limit *limit = &intel_limits_chv; 1149 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1150 1151 memset(&crtc_state->dpll_hw_state, 0, 1152 sizeof(crtc_state->dpll_hw_state)); 1153 1154 if (!crtc_state->clock_set && 1155 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1156 refclk, NULL, &crtc_state->dpll)) { 1157 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); 1158 return -EINVAL; 1159 } 1160 1161 chv_compute_dpll(crtc, crtc_state); 1162 1163 return 0; 1164 } 1165 1166 static int vlv_crtc_compute_clock(struct intel_crtc *crtc, 1167 struct intel_crtc_state *crtc_state) 1168 { 1169 int refclk = 100000; 1170 const struct intel_limit *limit = &intel_limits_vlv; 1171 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1172 1173 memset(&crtc_state->dpll_hw_state, 0, 1174 sizeof(crtc_state->dpll_hw_state)); 1175 1176 if (!crtc_state->clock_set && 1177 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1178 refclk, NULL, &crtc_state->dpll)) { 1179 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); 1180 return -EINVAL; 1181 } 1182 1183 vlv_compute_dpll(crtc, crtc_state); 1184 1185 return 0; 1186 } 1187 1188 static int g4x_crtc_compute_clock(struct intel_crtc *crtc, 1189 struct intel_crtc_state *crtc_state) 1190 { 1191 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1192 const struct intel_limit *limit; 1193 int refclk = 96000; 1194 1195 memset(&crtc_state->dpll_hw_state, 0, 1196 sizeof(crtc_state->dpll_hw_state)); 1197 1198 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1199 if (intel_panel_use_ssc(dev_priv)) { 1200 refclk = dev_priv->vbt.lvds_ssc_freq; 1201 drm_dbg_kms(&dev_priv->drm, 1202 "using SSC reference clock of %d kHz\n", 1203 refclk); 1204 } 1205 1206 if (intel_is_dual_link_lvds(dev_priv)) 1207 limit = &intel_limits_g4x_dual_channel_lvds; 1208 else 1209 limit = &intel_limits_g4x_single_channel_lvds; 1210 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || 1211 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1212 limit = &intel_limits_g4x_hdmi; 1213 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { 1214 limit = &intel_limits_g4x_sdvo; 1215 } else { 1216 /* The option is for other outputs */ 1217 limit = &intel_limits_i9xx_sdvo; 1218 } 1219 1220 if (!crtc_state->clock_set && 1221 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1222 refclk, NULL, &crtc_state->dpll)) { 1223 drm_err(&dev_priv->drm, 1224 "Couldn't find PLL settings for mode!\n"); 1225 return -EINVAL; 1226 } 1227 1228 i9xx_compute_dpll(crtc, crtc_state, NULL); 1229 1230 return 0; 1231 } 1232 1233 static int pnv_crtc_compute_clock(struct intel_crtc *crtc, 1234 struct intel_crtc_state *crtc_state) 1235 { 1236 struct drm_device *dev = crtc->base.dev; 1237 struct drm_i915_private *dev_priv = to_i915(dev); 1238 const struct intel_limit *limit; 1239 int refclk = 96000; 1240 1241 memset(&crtc_state->dpll_hw_state, 0, 1242 sizeof(crtc_state->dpll_hw_state)); 1243 1244 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1245 if (intel_panel_use_ssc(dev_priv)) { 1246 refclk = dev_priv->vbt.lvds_ssc_freq; 1247 drm_dbg_kms(&dev_priv->drm, 1248 "using SSC reference clock of %d kHz\n", 1249 refclk); 1250 } 1251 1252 limit = &pnv_limits_lvds; 1253 } else { 1254 limit = &pnv_limits_sdvo; 1255 } 1256 1257 if (!crtc_state->clock_set && 1258 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1259 refclk, NULL, &crtc_state->dpll)) { 1260 drm_err(&dev_priv->drm, 1261 "Couldn't find PLL settings for mode!\n"); 1262 return -EINVAL; 1263 } 1264 1265 i9xx_compute_dpll(crtc, crtc_state, NULL); 1266 1267 return 0; 1268 } 1269 1270 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, 1271 struct intel_crtc_state *crtc_state) 1272 { 1273 struct drm_device *dev = crtc->base.dev; 1274 struct drm_i915_private *dev_priv = to_i915(dev); 1275 const struct intel_limit *limit; 1276 int refclk = 96000; 1277 1278 memset(&crtc_state->dpll_hw_state, 0, 1279 sizeof(crtc_state->dpll_hw_state)); 1280 1281 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1282 if (intel_panel_use_ssc(dev_priv)) { 1283 refclk = dev_priv->vbt.lvds_ssc_freq; 1284 drm_dbg_kms(&dev_priv->drm, 1285 "using SSC reference clock of %d kHz\n", 1286 refclk); 1287 } 1288 1289 limit = &intel_limits_i9xx_lvds; 1290 } else { 1291 limit = &intel_limits_i9xx_sdvo; 1292 } 1293 1294 if (!crtc_state->clock_set && 1295 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1296 refclk, NULL, &crtc_state->dpll)) { 1297 drm_err(&dev_priv->drm, 1298 "Couldn't find PLL settings for mode!\n"); 1299 return -EINVAL; 1300 } 1301 1302 i9xx_compute_dpll(crtc, crtc_state, NULL); 1303 1304 return 0; 1305 } 1306 1307 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, 1308 struct intel_crtc_state *crtc_state) 1309 { 1310 struct drm_device *dev = crtc->base.dev; 1311 struct drm_i915_private *dev_priv = to_i915(dev); 1312 const struct intel_limit *limit; 1313 int refclk = 48000; 1314 1315 memset(&crtc_state->dpll_hw_state, 0, 1316 sizeof(crtc_state->dpll_hw_state)); 1317 1318 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1319 if (intel_panel_use_ssc(dev_priv)) { 1320 refclk = dev_priv->vbt.lvds_ssc_freq; 1321 drm_dbg_kms(&dev_priv->drm, 1322 "using SSC reference clock of %d kHz\n", 1323 refclk); 1324 } 1325 1326 limit = &intel_limits_i8xx_lvds; 1327 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { 1328 limit = &intel_limits_i8xx_dvo; 1329 } else { 1330 limit = &intel_limits_i8xx_dac; 1331 } 1332 1333 if (!crtc_state->clock_set && 1334 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1335 refclk, NULL, &crtc_state->dpll)) { 1336 drm_err(&dev_priv->drm, 1337 "Couldn't find PLL settings for mode!\n"); 1338 return -EINVAL; 1339 } 1340 1341 i8xx_compute_dpll(crtc, crtc_state, NULL); 1342 1343 return 0; 1344 } 1345 1346 void 1347 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv) 1348 { 1349 if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv)) 1350 dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock; 1351 else if (HAS_PCH_SPLIT(dev_priv)) 1352 dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock; 1353 else if (IS_CHERRYVIEW(dev_priv)) 1354 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; 1355 else if (IS_VALLEYVIEW(dev_priv)) 1356 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; 1357 else if (IS_G4X(dev_priv)) 1358 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; 1359 else if (IS_PINEVIEW(dev_priv)) 1360 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; 1361 else if (!IS_DISPLAY_VER(dev_priv, 2)) 1362 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; 1363 else 1364 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; 1365 } 1366 1367 static bool i9xx_has_pps(struct drm_i915_private *dev_priv) 1368 { 1369 if (IS_I830(dev_priv)) 1370 return false; 1371 1372 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 1373 } 1374 1375 void i9xx_enable_pll(struct intel_crtc *crtc, 1376 const struct intel_crtc_state *crtc_state) 1377 { 1378 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1379 i915_reg_t reg = DPLL(crtc->pipe); 1380 u32 dpll = crtc_state->dpll_hw_state.dpll; 1381 int i; 1382 1383 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); 1384 1385 /* PLL is protected by panel, make sure we can write it */ 1386 if (i9xx_has_pps(dev_priv)) 1387 assert_panel_unlocked(dev_priv, crtc->pipe); 1388 1389 /* 1390 * Apparently we need to have VGA mode enabled prior to changing 1391 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 1392 * dividers, even though the register value does change. 1393 */ 1394 intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS); 1395 intel_de_write(dev_priv, reg, dpll); 1396 1397 /* Wait for the clocks to stabilize. */ 1398 intel_de_posting_read(dev_priv, reg); 1399 udelay(150); 1400 1401 if (DISPLAY_VER(dev_priv) >= 4) { 1402 intel_de_write(dev_priv, DPLL_MD(crtc->pipe), 1403 crtc_state->dpll_hw_state.dpll_md); 1404 } else { 1405 /* The pixel multiplier can only be updated once the 1406 * DPLL is enabled and the clocks are stable. 1407 * 1408 * So write it again. 1409 */ 1410 intel_de_write(dev_priv, reg, dpll); 1411 } 1412 1413 /* We do this three times for luck */ 1414 for (i = 0; i < 3; i++) { 1415 intel_de_write(dev_priv, reg, dpll); 1416 intel_de_posting_read(dev_priv, reg); 1417 udelay(150); /* wait for warmup */ 1418 } 1419 } 1420 1421 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, 1422 enum pipe pipe) 1423 { 1424 u32 reg_val; 1425 1426 /* 1427 * PLLB opamp always calibrates to max value of 0x3f, force enable it 1428 * and set it to a reasonable value instead. 1429 */ 1430 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); 1431 reg_val &= 0xffffff00; 1432 reg_val |= 0x00000030; 1433 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); 1434 1435 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); 1436 reg_val &= 0x00ffffff; 1437 reg_val |= 0x8c000000; 1438 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 1439 1440 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); 1441 reg_val &= 0xffffff00; 1442 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); 1443 1444 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); 1445 reg_val &= 0x00ffffff; 1446 reg_val |= 0xb0000000; 1447 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 1448 } 1449 1450 static void _vlv_enable_pll(struct intel_crtc *crtc, 1451 const struct intel_crtc_state *pipe_config) 1452 { 1453 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1454 enum pipe pipe = crtc->pipe; 1455 1456 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); 1457 intel_de_posting_read(dev_priv, DPLL(pipe)); 1458 udelay(150); 1459 1460 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) 1461 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); 1462 } 1463 1464 void vlv_enable_pll(struct intel_crtc *crtc, 1465 const struct intel_crtc_state *pipe_config) 1466 { 1467 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1468 enum pipe pipe = crtc->pipe; 1469 1470 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); 1471 1472 /* PLL is protected by panel, make sure we can write it */ 1473 assert_panel_unlocked(dev_priv, pipe); 1474 1475 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) 1476 _vlv_enable_pll(crtc, pipe_config); 1477 1478 intel_de_write(dev_priv, DPLL_MD(pipe), 1479 pipe_config->dpll_hw_state.dpll_md); 1480 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); 1481 } 1482 1483 1484 static void _chv_enable_pll(struct intel_crtc *crtc, 1485 const struct intel_crtc_state *pipe_config) 1486 { 1487 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1488 enum pipe pipe = crtc->pipe; 1489 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1490 u32 tmp; 1491 1492 vlv_dpio_get(dev_priv); 1493 1494 /* Enable back the 10bit clock to display controller */ 1495 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); 1496 tmp |= DPIO_DCLKP_EN; 1497 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); 1498 1499 vlv_dpio_put(dev_priv); 1500 1501 /* 1502 * Need to wait > 100ns between dclkp clock enable bit and PLL enable. 1503 */ 1504 udelay(1); 1505 1506 /* Enable PLL */ 1507 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); 1508 1509 /* Check PLL is locked */ 1510 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) 1511 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); 1512 } 1513 1514 void chv_enable_pll(struct intel_crtc *crtc, 1515 const struct intel_crtc_state *pipe_config) 1516 { 1517 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1518 enum pipe pipe = crtc->pipe; 1519 1520 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); 1521 1522 /* PLL is protected by panel, make sure we can write it */ 1523 assert_panel_unlocked(dev_priv, pipe); 1524 1525 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) 1526 _chv_enable_pll(crtc, pipe_config); 1527 1528 if (pipe != PIPE_A) { 1529 /* 1530 * WaPixelRepeatModeFixForC0:chv 1531 * 1532 * DPLLCMD is AWOL. Use chicken bits to propagate 1533 * the value from DPLLBMD to either pipe B or C. 1534 */ 1535 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); 1536 intel_de_write(dev_priv, DPLL_MD(PIPE_B), 1537 pipe_config->dpll_hw_state.dpll_md); 1538 intel_de_write(dev_priv, CBR4_VLV, 0); 1539 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; 1540 1541 /* 1542 * DPLLB VGA mode also seems to cause problems. 1543 * We should always have it disabled. 1544 */ 1545 drm_WARN_ON(&dev_priv->drm, 1546 (intel_de_read(dev_priv, DPLL(PIPE_B)) & 1547 DPLL_VGA_MODE_DIS) == 0); 1548 } else { 1549 intel_de_write(dev_priv, DPLL_MD(pipe), 1550 pipe_config->dpll_hw_state.dpll_md); 1551 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); 1552 } 1553 } 1554 1555 void vlv_prepare_pll(struct intel_crtc *crtc, 1556 const struct intel_crtc_state *pipe_config) 1557 { 1558 struct drm_device *dev = crtc->base.dev; 1559 struct drm_i915_private *dev_priv = to_i915(dev); 1560 enum pipe pipe = crtc->pipe; 1561 u32 mdiv; 1562 u32 bestn, bestm1, bestm2, bestp1, bestp2; 1563 u32 coreclk, reg_val; 1564 1565 /* Enable Refclk */ 1566 intel_de_write(dev_priv, DPLL(pipe), 1567 pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); 1568 1569 /* No need to actually set up the DPLL with DSI */ 1570 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 1571 return; 1572 1573 vlv_dpio_get(dev_priv); 1574 1575 bestn = pipe_config->dpll.n; 1576 bestm1 = pipe_config->dpll.m1; 1577 bestm2 = pipe_config->dpll.m2; 1578 bestp1 = pipe_config->dpll.p1; 1579 bestp2 = pipe_config->dpll.p2; 1580 1581 /* See eDP HDMI DPIO driver vbios notes doc */ 1582 1583 /* PLL B needs special handling */ 1584 if (pipe == PIPE_B) 1585 vlv_pllb_recal_opamp(dev_priv, pipe); 1586 1587 /* Set up Tx target for periodic Rcomp update */ 1588 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); 1589 1590 /* Disable target IRef on PLL */ 1591 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); 1592 reg_val &= 0x00ffffff; 1593 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); 1594 1595 /* Disable fast lock */ 1596 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); 1597 1598 /* Set idtafcrecal before PLL is enabled */ 1599 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); 1600 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); 1601 mdiv |= ((bestn << DPIO_N_SHIFT)); 1602 mdiv |= (1 << DPIO_K_SHIFT); 1603 1604 /* 1605 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, 1606 * but we don't support that). 1607 * Note: don't use the DAC post divider as it seems unstable. 1608 */ 1609 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); 1610 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); 1611 1612 mdiv |= DPIO_ENABLE_CALIBRATION; 1613 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); 1614 1615 /* Set HBR and RBR LPF coefficients */ 1616 if (pipe_config->port_clock == 162000 || 1617 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) || 1618 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) 1619 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 1620 0x009f0003); 1621 else 1622 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 1623 0x00d0000f); 1624 1625 if (intel_crtc_has_dp_encoder(pipe_config)) { 1626 /* Use SSC source */ 1627 if (pipe == PIPE_A) 1628 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1629 0x0df40000); 1630 else 1631 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1632 0x0df70000); 1633 } else { /* HDMI or VGA */ 1634 /* Use bend source */ 1635 if (pipe == PIPE_A) 1636 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1637 0x0df70000); 1638 else 1639 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1640 0x0df40000); 1641 } 1642 1643 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); 1644 coreclk = (coreclk & 0x0000ff00) | 0x01c00000; 1645 if (intel_crtc_has_dp_encoder(pipe_config)) 1646 coreclk |= 0x01000000; 1647 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); 1648 1649 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); 1650 1651 vlv_dpio_put(dev_priv); 1652 } 1653 1654 void chv_prepare_pll(struct intel_crtc *crtc, 1655 const struct intel_crtc_state *pipe_config) 1656 { 1657 struct drm_device *dev = crtc->base.dev; 1658 struct drm_i915_private *dev_priv = to_i915(dev); 1659 enum pipe pipe = crtc->pipe; 1660 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1661 u32 loopfilter, tribuf_calcntr; 1662 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; 1663 u32 dpio_val; 1664 int vco; 1665 1666 /* Enable Refclk and SSC */ 1667 intel_de_write(dev_priv, DPLL(pipe), 1668 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); 1669 1670 /* No need to actually set up the DPLL with DSI */ 1671 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 1672 return; 1673 1674 bestn = pipe_config->dpll.n; 1675 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; 1676 bestm1 = pipe_config->dpll.m1; 1677 bestm2 = pipe_config->dpll.m2 >> 22; 1678 bestp1 = pipe_config->dpll.p1; 1679 bestp2 = pipe_config->dpll.p2; 1680 vco = pipe_config->dpll.vco; 1681 dpio_val = 0; 1682 loopfilter = 0; 1683 1684 vlv_dpio_get(dev_priv); 1685 1686 /* p1 and p2 divider */ 1687 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), 1688 5 << DPIO_CHV_S1_DIV_SHIFT | 1689 bestp1 << DPIO_CHV_P1_DIV_SHIFT | 1690 bestp2 << DPIO_CHV_P2_DIV_SHIFT | 1691 1 << DPIO_CHV_K_DIV_SHIFT); 1692 1693 /* Feedback post-divider - m2 */ 1694 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); 1695 1696 /* Feedback refclk divider - n and m1 */ 1697 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), 1698 DPIO_CHV_M1_DIV_BY_2 | 1699 1 << DPIO_CHV_N_DIV_SHIFT); 1700 1701 /* M2 fraction division */ 1702 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); 1703 1704 /* M2 fraction division enable */ 1705 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 1706 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); 1707 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); 1708 if (bestm2_frac) 1709 dpio_val |= DPIO_CHV_FRAC_DIV_EN; 1710 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); 1711 1712 /* Program digital lock detect threshold */ 1713 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); 1714 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | 1715 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); 1716 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); 1717 if (!bestm2_frac) 1718 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; 1719 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); 1720 1721 /* Loop filter */ 1722 if (vco == 5400000) { 1723 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); 1724 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); 1725 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); 1726 tribuf_calcntr = 0x9; 1727 } else if (vco <= 6200000) { 1728 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); 1729 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); 1730 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1731 tribuf_calcntr = 0x9; 1732 } else if (vco <= 6480000) { 1733 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 1734 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 1735 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1736 tribuf_calcntr = 0x8; 1737 } else { 1738 /* Not supported. Apply the same limits as in the max case */ 1739 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 1740 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 1741 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1742 tribuf_calcntr = 0; 1743 } 1744 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); 1745 1746 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); 1747 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; 1748 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); 1749 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); 1750 1751 /* AFC Recal */ 1752 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), 1753 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | 1754 DPIO_AFC_RECAL); 1755 1756 vlv_dpio_put(dev_priv); 1757 } 1758 1759 /** 1760 * vlv_force_pll_on - forcibly enable just the PLL 1761 * @dev_priv: i915 private structure 1762 * @pipe: pipe PLL to enable 1763 * @dpll: PLL configuration 1764 * 1765 * Enable the PLL for @pipe using the supplied @dpll config. To be used 1766 * in cases where we need the PLL enabled even when @pipe is not going to 1767 * be enabled. 1768 */ 1769 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, 1770 const struct dpll *dpll) 1771 { 1772 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 1773 struct intel_crtc_state *pipe_config; 1774 1775 pipe_config = intel_crtc_state_alloc(crtc); 1776 if (!pipe_config) 1777 return -ENOMEM; 1778 1779 pipe_config->cpu_transcoder = (enum transcoder)pipe; 1780 pipe_config->pixel_multiplier = 1; 1781 pipe_config->dpll = *dpll; 1782 1783 if (IS_CHERRYVIEW(dev_priv)) { 1784 chv_compute_dpll(crtc, pipe_config); 1785 chv_prepare_pll(crtc, pipe_config); 1786 chv_enable_pll(crtc, pipe_config); 1787 } else { 1788 vlv_compute_dpll(crtc, pipe_config); 1789 vlv_prepare_pll(crtc, pipe_config); 1790 vlv_enable_pll(crtc, pipe_config); 1791 } 1792 1793 kfree(pipe_config); 1794 1795 return 0; 1796 } 1797 1798 void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 1799 { 1800 u32 val; 1801 1802 /* Make sure the pipe isn't still relying on us */ 1803 assert_pipe_disabled(dev_priv, (enum transcoder)pipe); 1804 1805 val = DPLL_INTEGRATED_REF_CLK_VLV | 1806 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1807 if (pipe != PIPE_A) 1808 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1809 1810 intel_de_write(dev_priv, DPLL(pipe), val); 1811 intel_de_posting_read(dev_priv, DPLL(pipe)); 1812 } 1813 1814 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 1815 { 1816 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1817 u32 val; 1818 1819 /* Make sure the pipe isn't still relying on us */ 1820 assert_pipe_disabled(dev_priv, (enum transcoder)pipe); 1821 1822 val = DPLL_SSC_REF_CLK_CHV | 1823 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1824 if (pipe != PIPE_A) 1825 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1826 1827 intel_de_write(dev_priv, DPLL(pipe), val); 1828 intel_de_posting_read(dev_priv, DPLL(pipe)); 1829 1830 vlv_dpio_get(dev_priv); 1831 1832 /* Disable 10bit clock to display controller */ 1833 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); 1834 val &= ~DPIO_DCLKP_EN; 1835 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); 1836 1837 vlv_dpio_put(dev_priv); 1838 } 1839 1840 void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) 1841 { 1842 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1843 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1844 enum pipe pipe = crtc->pipe; 1845 1846 /* Don't disable pipe or pipe PLLs if needed */ 1847 if (IS_I830(dev_priv)) 1848 return; 1849 1850 /* Make sure the pipe isn't still relying on us */ 1851 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); 1852 1853 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 1854 intel_de_posting_read(dev_priv, DPLL(pipe)); 1855 } 1856 1857 1858 /** 1859 * vlv_force_pll_off - forcibly disable just the PLL 1860 * @dev_priv: i915 private structure 1861 * @pipe: pipe PLL to disable 1862 * 1863 * Disable the PLL for @pipe. To be used in cases where we need 1864 * the PLL enabled even when @pipe is not going to be enabled. 1865 */ 1866 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) 1867 { 1868 if (IS_CHERRYVIEW(dev_priv)) 1869 chv_disable_pll(dev_priv, pipe); 1870 else 1871 vlv_disable_pll(dev_priv, pipe); 1872 } 1873