1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 #include <linux/kernel.h> 6 #include "intel_crtc.h" 7 #include "intel_de.h" 8 #include "intel_display_types.h" 9 #include "intel_display.h" 10 #include "intel_dpll.h" 11 #include "intel_lvds.h" 12 #include "intel_panel.h" 13 #include "intel_sideband.h" 14 #include "display/intel_snps_phy.h" 15 16 struct intel_limit { 17 struct { 18 int min, max; 19 } dot, vco, n, m, m1, m2, p, p1; 20 21 struct { 22 int dot_limit; 23 int p2_slow, p2_fast; 24 } p2; 25 }; 26 static const struct intel_limit intel_limits_i8xx_dac = { 27 .dot = { .min = 25000, .max = 350000 }, 28 .vco = { .min = 908000, .max = 1512000 }, 29 .n = { .min = 2, .max = 16 }, 30 .m = { .min = 96, .max = 140 }, 31 .m1 = { .min = 18, .max = 26 }, 32 .m2 = { .min = 6, .max = 16 }, 33 .p = { .min = 4, .max = 128 }, 34 .p1 = { .min = 2, .max = 33 }, 35 .p2 = { .dot_limit = 165000, 36 .p2_slow = 4, .p2_fast = 2 }, 37 }; 38 39 static const struct intel_limit intel_limits_i8xx_dvo = { 40 .dot = { .min = 25000, .max = 350000 }, 41 .vco = { .min = 908000, .max = 1512000 }, 42 .n = { .min = 2, .max = 16 }, 43 .m = { .min = 96, .max = 140 }, 44 .m1 = { .min = 18, .max = 26 }, 45 .m2 = { .min = 6, .max = 16 }, 46 .p = { .min = 4, .max = 128 }, 47 .p1 = { .min = 2, .max = 33 }, 48 .p2 = { .dot_limit = 165000, 49 .p2_slow = 4, .p2_fast = 4 }, 50 }; 51 52 static const struct intel_limit intel_limits_i8xx_lvds = { 53 .dot = { .min = 25000, .max = 350000 }, 54 .vco = { .min = 908000, .max = 1512000 }, 55 .n = { .min = 2, .max = 16 }, 56 .m = { .min = 96, .max = 140 }, 57 .m1 = { .min = 18, .max = 26 }, 58 .m2 = { .min = 6, .max = 16 }, 59 .p = { .min = 4, .max = 128 }, 60 .p1 = { .min = 1, .max = 6 }, 61 .p2 = { .dot_limit = 165000, 62 .p2_slow = 14, .p2_fast = 7 }, 63 }; 64 65 static const struct intel_limit intel_limits_i9xx_sdvo = { 66 .dot = { .min = 20000, .max = 400000 }, 67 .vco = { .min = 1400000, .max = 2800000 }, 68 .n = { .min = 1, .max = 6 }, 69 .m = { .min = 70, .max = 120 }, 70 .m1 = { .min = 8, .max = 18 }, 71 .m2 = { .min = 3, .max = 7 }, 72 .p = { .min = 5, .max = 80 }, 73 .p1 = { .min = 1, .max = 8 }, 74 .p2 = { .dot_limit = 200000, 75 .p2_slow = 10, .p2_fast = 5 }, 76 }; 77 78 static const struct intel_limit intel_limits_i9xx_lvds = { 79 .dot = { .min = 20000, .max = 400000 }, 80 .vco = { .min = 1400000, .max = 2800000 }, 81 .n = { .min = 1, .max = 6 }, 82 .m = { .min = 70, .max = 120 }, 83 .m1 = { .min = 8, .max = 18 }, 84 .m2 = { .min = 3, .max = 7 }, 85 .p = { .min = 7, .max = 98 }, 86 .p1 = { .min = 1, .max = 8 }, 87 .p2 = { .dot_limit = 112000, 88 .p2_slow = 14, .p2_fast = 7 }, 89 }; 90 91 92 static const struct intel_limit intel_limits_g4x_sdvo = { 93 .dot = { .min = 25000, .max = 270000 }, 94 .vco = { .min = 1750000, .max = 3500000}, 95 .n = { .min = 1, .max = 4 }, 96 .m = { .min = 104, .max = 138 }, 97 .m1 = { .min = 17, .max = 23 }, 98 .m2 = { .min = 5, .max = 11 }, 99 .p = { .min = 10, .max = 30 }, 100 .p1 = { .min = 1, .max = 3}, 101 .p2 = { .dot_limit = 270000, 102 .p2_slow = 10, 103 .p2_fast = 10 104 }, 105 }; 106 107 static const struct intel_limit intel_limits_g4x_hdmi = { 108 .dot = { .min = 22000, .max = 400000 }, 109 .vco = { .min = 1750000, .max = 3500000}, 110 .n = { .min = 1, .max = 4 }, 111 .m = { .min = 104, .max = 138 }, 112 .m1 = { .min = 16, .max = 23 }, 113 .m2 = { .min = 5, .max = 11 }, 114 .p = { .min = 5, .max = 80 }, 115 .p1 = { .min = 1, .max = 8}, 116 .p2 = { .dot_limit = 165000, 117 .p2_slow = 10, .p2_fast = 5 }, 118 }; 119 120 static const struct intel_limit intel_limits_g4x_single_channel_lvds = { 121 .dot = { .min = 20000, .max = 115000 }, 122 .vco = { .min = 1750000, .max = 3500000 }, 123 .n = { .min = 1, .max = 3 }, 124 .m = { .min = 104, .max = 138 }, 125 .m1 = { .min = 17, .max = 23 }, 126 .m2 = { .min = 5, .max = 11 }, 127 .p = { .min = 28, .max = 112 }, 128 .p1 = { .min = 2, .max = 8 }, 129 .p2 = { .dot_limit = 0, 130 .p2_slow = 14, .p2_fast = 14 131 }, 132 }; 133 134 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { 135 .dot = { .min = 80000, .max = 224000 }, 136 .vco = { .min = 1750000, .max = 3500000 }, 137 .n = { .min = 1, .max = 3 }, 138 .m = { .min = 104, .max = 138 }, 139 .m1 = { .min = 17, .max = 23 }, 140 .m2 = { .min = 5, .max = 11 }, 141 .p = { .min = 14, .max = 42 }, 142 .p1 = { .min = 2, .max = 6 }, 143 .p2 = { .dot_limit = 0, 144 .p2_slow = 7, .p2_fast = 7 145 }, 146 }; 147 148 static const struct intel_limit pnv_limits_sdvo = { 149 .dot = { .min = 20000, .max = 400000}, 150 .vco = { .min = 1700000, .max = 3500000 }, 151 /* Pineview's Ncounter is a ring counter */ 152 .n = { .min = 3, .max = 6 }, 153 .m = { .min = 2, .max = 256 }, 154 /* Pineview only has one combined m divider, which we treat as m2. */ 155 .m1 = { .min = 0, .max = 0 }, 156 .m2 = { .min = 0, .max = 254 }, 157 .p = { .min = 5, .max = 80 }, 158 .p1 = { .min = 1, .max = 8 }, 159 .p2 = { .dot_limit = 200000, 160 .p2_slow = 10, .p2_fast = 5 }, 161 }; 162 163 static const struct intel_limit pnv_limits_lvds = { 164 .dot = { .min = 20000, .max = 400000 }, 165 .vco = { .min = 1700000, .max = 3500000 }, 166 .n = { .min = 3, .max = 6 }, 167 .m = { .min = 2, .max = 256 }, 168 .m1 = { .min = 0, .max = 0 }, 169 .m2 = { .min = 0, .max = 254 }, 170 .p = { .min = 7, .max = 112 }, 171 .p1 = { .min = 1, .max = 8 }, 172 .p2 = { .dot_limit = 112000, 173 .p2_slow = 14, .p2_fast = 14 }, 174 }; 175 176 /* Ironlake / Sandybridge 177 * 178 * We calculate clock using (register_value + 2) for N/M1/M2, so here 179 * the range value for them is (actual_value - 2). 180 */ 181 static const struct intel_limit ilk_limits_dac = { 182 .dot = { .min = 25000, .max = 350000 }, 183 .vco = { .min = 1760000, .max = 3510000 }, 184 .n = { .min = 1, .max = 5 }, 185 .m = { .min = 79, .max = 127 }, 186 .m1 = { .min = 12, .max = 22 }, 187 .m2 = { .min = 5, .max = 9 }, 188 .p = { .min = 5, .max = 80 }, 189 .p1 = { .min = 1, .max = 8 }, 190 .p2 = { .dot_limit = 225000, 191 .p2_slow = 10, .p2_fast = 5 }, 192 }; 193 194 static const struct intel_limit ilk_limits_single_lvds = { 195 .dot = { .min = 25000, .max = 350000 }, 196 .vco = { .min = 1760000, .max = 3510000 }, 197 .n = { .min = 1, .max = 3 }, 198 .m = { .min = 79, .max = 118 }, 199 .m1 = { .min = 12, .max = 22 }, 200 .m2 = { .min = 5, .max = 9 }, 201 .p = { .min = 28, .max = 112 }, 202 .p1 = { .min = 2, .max = 8 }, 203 .p2 = { .dot_limit = 225000, 204 .p2_slow = 14, .p2_fast = 14 }, 205 }; 206 207 static const struct intel_limit ilk_limits_dual_lvds = { 208 .dot = { .min = 25000, .max = 350000 }, 209 .vco = { .min = 1760000, .max = 3510000 }, 210 .n = { .min = 1, .max = 3 }, 211 .m = { .min = 79, .max = 127 }, 212 .m1 = { .min = 12, .max = 22 }, 213 .m2 = { .min = 5, .max = 9 }, 214 .p = { .min = 14, .max = 56 }, 215 .p1 = { .min = 2, .max = 8 }, 216 .p2 = { .dot_limit = 225000, 217 .p2_slow = 7, .p2_fast = 7 }, 218 }; 219 220 /* LVDS 100mhz refclk limits. */ 221 static const struct intel_limit ilk_limits_single_lvds_100m = { 222 .dot = { .min = 25000, .max = 350000 }, 223 .vco = { .min = 1760000, .max = 3510000 }, 224 .n = { .min = 1, .max = 2 }, 225 .m = { .min = 79, .max = 126 }, 226 .m1 = { .min = 12, .max = 22 }, 227 .m2 = { .min = 5, .max = 9 }, 228 .p = { .min = 28, .max = 112 }, 229 .p1 = { .min = 2, .max = 8 }, 230 .p2 = { .dot_limit = 225000, 231 .p2_slow = 14, .p2_fast = 14 }, 232 }; 233 234 static const struct intel_limit ilk_limits_dual_lvds_100m = { 235 .dot = { .min = 25000, .max = 350000 }, 236 .vco = { .min = 1760000, .max = 3510000 }, 237 .n = { .min = 1, .max = 3 }, 238 .m = { .min = 79, .max = 126 }, 239 .m1 = { .min = 12, .max = 22 }, 240 .m2 = { .min = 5, .max = 9 }, 241 .p = { .min = 14, .max = 42 }, 242 .p1 = { .min = 2, .max = 6 }, 243 .p2 = { .dot_limit = 225000, 244 .p2_slow = 7, .p2_fast = 7 }, 245 }; 246 247 static const struct intel_limit intel_limits_vlv = { 248 /* 249 * These are the data rate limits (measured in fast clocks) 250 * since those are the strictest limits we have. The fast 251 * clock and actual rate limits are more relaxed, so checking 252 * them would make no difference. 253 */ 254 .dot = { .min = 25000 * 5, .max = 270000 * 5 }, 255 .vco = { .min = 4000000, .max = 6000000 }, 256 .n = { .min = 1, .max = 7 }, 257 .m1 = { .min = 2, .max = 3 }, 258 .m2 = { .min = 11, .max = 156 }, 259 .p1 = { .min = 2, .max = 3 }, 260 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ 261 }; 262 263 static const struct intel_limit intel_limits_chv = { 264 /* 265 * These are the data rate limits (measured in fast clocks) 266 * since those are the strictest limits we have. The fast 267 * clock and actual rate limits are more relaxed, so checking 268 * them would make no difference. 269 */ 270 .dot = { .min = 25000 * 5, .max = 540000 * 5}, 271 .vco = { .min = 4800000, .max = 6480000 }, 272 .n = { .min = 1, .max = 1 }, 273 .m1 = { .min = 2, .max = 2 }, 274 .m2 = { .min = 24 << 22, .max = 175 << 22 }, 275 .p1 = { .min = 2, .max = 4 }, 276 .p2 = { .p2_slow = 1, .p2_fast = 14 }, 277 }; 278 279 static const struct intel_limit intel_limits_bxt = { 280 /* FIXME: find real dot limits */ 281 .dot = { .min = 0, .max = INT_MAX }, 282 .vco = { .min = 4800000, .max = 6700000 }, 283 .n = { .min = 1, .max = 1 }, 284 .m1 = { .min = 2, .max = 2 }, 285 /* FIXME: find real m2 limits */ 286 .m2 = { .min = 2 << 22, .max = 255 << 22 }, 287 .p1 = { .min = 2, .max = 4 }, 288 .p2 = { .p2_slow = 1, .p2_fast = 20 }, 289 }; 290 291 /* 292 * Platform specific helpers to calculate the port PLL loopback- (clock.m), 293 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast 294 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. 295 * The helpers' return value is the rate of the clock that is fed to the 296 * display engine's pipe which can be the above fast dot clock rate or a 297 * divided-down version of it. 298 */ 299 /* m1 is reserved as 0 in Pineview, n is a ring counter */ 300 int pnv_calc_dpll_params(int refclk, struct dpll *clock) 301 { 302 clock->m = clock->m2 + 2; 303 clock->p = clock->p1 * clock->p2; 304 if (WARN_ON(clock->n == 0 || clock->p == 0)) 305 return 0; 306 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 307 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 308 309 return clock->dot; 310 } 311 312 static u32 i9xx_dpll_compute_m(struct dpll *dpll) 313 { 314 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); 315 } 316 317 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) 318 { 319 clock->m = i9xx_dpll_compute_m(clock); 320 clock->p = clock->p1 * clock->p2; 321 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) 322 return 0; 323 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); 324 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 325 326 return clock->dot; 327 } 328 329 int vlv_calc_dpll_params(int refclk, struct dpll *clock) 330 { 331 clock->m = clock->m1 * clock->m2; 332 clock->p = clock->p1 * clock->p2; 333 if (WARN_ON(clock->n == 0 || clock->p == 0)) 334 return 0; 335 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 336 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 337 338 return clock->dot / 5; 339 } 340 341 int chv_calc_dpll_params(int refclk, struct dpll *clock) 342 { 343 clock->m = clock->m1 * clock->m2; 344 clock->p = clock->p1 * clock->p2; 345 if (WARN_ON(clock->n == 0 || clock->p == 0)) 346 return 0; 347 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), 348 clock->n << 22); 349 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 350 351 return clock->dot / 5; 352 } 353 354 /* 355 * Returns whether the given set of divisors are valid for a given refclk with 356 * the given connectors. 357 */ 358 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv, 359 const struct intel_limit *limit, 360 const struct dpll *clock) 361 { 362 if (clock->n < limit->n.min || limit->n.max < clock->n) 363 return false; 364 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 365 return false; 366 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 367 return false; 368 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 369 return false; 370 371 if (!IS_PINEVIEW(dev_priv) && !IS_LP(dev_priv)) 372 if (clock->m1 <= clock->m2) 373 return false; 374 375 if (!IS_LP(dev_priv)) { 376 if (clock->p < limit->p.min || limit->p.max < clock->p) 377 return false; 378 if (clock->m < limit->m.min || limit->m.max < clock->m) 379 return false; 380 } 381 382 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 383 return false; 384 /* XXX: We may need to be checking "Dot clock" depending on the multiplier, 385 * connector, etc., rather than just a single range. 386 */ 387 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 388 return false; 389 390 return true; 391 } 392 393 static int 394 i9xx_select_p2_div(const struct intel_limit *limit, 395 const struct intel_crtc_state *crtc_state, 396 int target) 397 { 398 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 399 400 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 401 /* 402 * For LVDS just rely on its current settings for dual-channel. 403 * We haven't figured out how to reliably set up different 404 * single/dual channel state, if we even can. 405 */ 406 if (intel_is_dual_link_lvds(dev_priv)) 407 return limit->p2.p2_fast; 408 else 409 return limit->p2.p2_slow; 410 } else { 411 if (target < limit->p2.dot_limit) 412 return limit->p2.p2_slow; 413 else 414 return limit->p2.p2_fast; 415 } 416 } 417 418 /* 419 * Returns a set of divisors for the desired target clock with the given 420 * refclk, or FALSE. The returned values represent the clock equation: 421 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 422 * 423 * Target and reference clocks are specified in kHz. 424 * 425 * If match_clock is provided, then best_clock P divider must match the P 426 * divider from @match_clock used for LVDS downclocking. 427 */ 428 static bool 429 i9xx_find_best_dpll(const struct intel_limit *limit, 430 struct intel_crtc_state *crtc_state, 431 int target, int refclk, struct dpll *match_clock, 432 struct dpll *best_clock) 433 { 434 struct drm_device *dev = crtc_state->uapi.crtc->dev; 435 struct dpll clock; 436 int err = target; 437 438 memset(best_clock, 0, sizeof(*best_clock)); 439 440 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 441 442 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 443 clock.m1++) { 444 for (clock.m2 = limit->m2.min; 445 clock.m2 <= limit->m2.max; clock.m2++) { 446 if (clock.m2 >= clock.m1) 447 break; 448 for (clock.n = limit->n.min; 449 clock.n <= limit->n.max; clock.n++) { 450 for (clock.p1 = limit->p1.min; 451 clock.p1 <= limit->p1.max; clock.p1++) { 452 int this_err; 453 454 i9xx_calc_dpll_params(refclk, &clock); 455 if (!intel_pll_is_valid(to_i915(dev), 456 limit, 457 &clock)) 458 continue; 459 if (match_clock && 460 clock.p != match_clock->p) 461 continue; 462 463 this_err = abs(clock.dot - target); 464 if (this_err < err) { 465 *best_clock = clock; 466 err = this_err; 467 } 468 } 469 } 470 } 471 } 472 473 return (err != target); 474 } 475 476 /* 477 * Returns a set of divisors for the desired target clock with the given 478 * refclk, or FALSE. The returned values represent the clock equation: 479 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 480 * 481 * Target and reference clocks are specified in kHz. 482 * 483 * If match_clock is provided, then best_clock P divider must match the P 484 * divider from @match_clock used for LVDS downclocking. 485 */ 486 static bool 487 pnv_find_best_dpll(const struct intel_limit *limit, 488 struct intel_crtc_state *crtc_state, 489 int target, int refclk, struct dpll *match_clock, 490 struct dpll *best_clock) 491 { 492 struct drm_device *dev = crtc_state->uapi.crtc->dev; 493 struct dpll clock; 494 int err = target; 495 496 memset(best_clock, 0, sizeof(*best_clock)); 497 498 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 499 500 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 501 clock.m1++) { 502 for (clock.m2 = limit->m2.min; 503 clock.m2 <= limit->m2.max; clock.m2++) { 504 for (clock.n = limit->n.min; 505 clock.n <= limit->n.max; clock.n++) { 506 for (clock.p1 = limit->p1.min; 507 clock.p1 <= limit->p1.max; clock.p1++) { 508 int this_err; 509 510 pnv_calc_dpll_params(refclk, &clock); 511 if (!intel_pll_is_valid(to_i915(dev), 512 limit, 513 &clock)) 514 continue; 515 if (match_clock && 516 clock.p != match_clock->p) 517 continue; 518 519 this_err = abs(clock.dot - target); 520 if (this_err < err) { 521 *best_clock = clock; 522 err = this_err; 523 } 524 } 525 } 526 } 527 } 528 529 return (err != target); 530 } 531 532 /* 533 * Returns a set of divisors for the desired target clock with the given 534 * refclk, or FALSE. The returned values represent the clock equation: 535 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 536 * 537 * Target and reference clocks are specified in kHz. 538 * 539 * If match_clock is provided, then best_clock P divider must match the P 540 * divider from @match_clock used for LVDS downclocking. 541 */ 542 static bool 543 g4x_find_best_dpll(const struct intel_limit *limit, 544 struct intel_crtc_state *crtc_state, 545 int target, int refclk, struct dpll *match_clock, 546 struct dpll *best_clock) 547 { 548 struct drm_device *dev = crtc_state->uapi.crtc->dev; 549 struct dpll clock; 550 int max_n; 551 bool found = false; 552 /* approximately equals target * 0.00585 */ 553 int err_most = (target >> 8) + (target >> 9); 554 555 memset(best_clock, 0, sizeof(*best_clock)); 556 557 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 558 559 max_n = limit->n.max; 560 /* based on hardware requirement, prefer smaller n to precision */ 561 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 562 /* based on hardware requirement, prefere larger m1,m2 */ 563 for (clock.m1 = limit->m1.max; 564 clock.m1 >= limit->m1.min; clock.m1--) { 565 for (clock.m2 = limit->m2.max; 566 clock.m2 >= limit->m2.min; clock.m2--) { 567 for (clock.p1 = limit->p1.max; 568 clock.p1 >= limit->p1.min; clock.p1--) { 569 int this_err; 570 571 i9xx_calc_dpll_params(refclk, &clock); 572 if (!intel_pll_is_valid(to_i915(dev), 573 limit, 574 &clock)) 575 continue; 576 577 this_err = abs(clock.dot - target); 578 if (this_err < err_most) { 579 *best_clock = clock; 580 err_most = this_err; 581 max_n = clock.n; 582 found = true; 583 } 584 } 585 } 586 } 587 } 588 return found; 589 } 590 591 /* 592 * Check if the calculated PLL configuration is more optimal compared to the 593 * best configuration and error found so far. Return the calculated error. 594 */ 595 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, 596 const struct dpll *calculated_clock, 597 const struct dpll *best_clock, 598 unsigned int best_error_ppm, 599 unsigned int *error_ppm) 600 { 601 /* 602 * For CHV ignore the error and consider only the P value. 603 * Prefer a bigger P value based on HW requirements. 604 */ 605 if (IS_CHERRYVIEW(to_i915(dev))) { 606 *error_ppm = 0; 607 608 return calculated_clock->p > best_clock->p; 609 } 610 611 if (drm_WARN_ON_ONCE(dev, !target_freq)) 612 return false; 613 614 *error_ppm = div_u64(1000000ULL * 615 abs(target_freq - calculated_clock->dot), 616 target_freq); 617 /* 618 * Prefer a better P value over a better (smaller) error if the error 619 * is small. Ensure this preference for future configurations too by 620 * setting the error to 0. 621 */ 622 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { 623 *error_ppm = 0; 624 625 return true; 626 } 627 628 return *error_ppm + 10 < best_error_ppm; 629 } 630 631 /* 632 * Returns a set of divisors for the desired target clock with the given 633 * refclk, or FALSE. The returned values represent the clock equation: 634 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 635 */ 636 static bool 637 vlv_find_best_dpll(const struct intel_limit *limit, 638 struct intel_crtc_state *crtc_state, 639 int target, int refclk, struct dpll *match_clock, 640 struct dpll *best_clock) 641 { 642 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 643 struct drm_device *dev = crtc->base.dev; 644 struct dpll clock; 645 unsigned int bestppm = 1000000; 646 /* min update 19.2 MHz */ 647 int max_n = min(limit->n.max, refclk / 19200); 648 bool found = false; 649 650 target *= 5; /* fast clock */ 651 652 memset(best_clock, 0, sizeof(*best_clock)); 653 654 /* based on hardware requirement, prefer smaller n to precision */ 655 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 656 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 657 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; 658 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 659 clock.p = clock.p1 * clock.p2; 660 /* based on hardware requirement, prefer bigger m1,m2 values */ 661 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { 662 unsigned int ppm; 663 664 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, 665 refclk * clock.m1); 666 667 vlv_calc_dpll_params(refclk, &clock); 668 669 if (!intel_pll_is_valid(to_i915(dev), 670 limit, 671 &clock)) 672 continue; 673 674 if (!vlv_PLL_is_optimal(dev, target, 675 &clock, 676 best_clock, 677 bestppm, &ppm)) 678 continue; 679 680 *best_clock = clock; 681 bestppm = ppm; 682 found = true; 683 } 684 } 685 } 686 } 687 688 return found; 689 } 690 691 /* 692 * Returns a set of divisors for the desired target clock with the given 693 * refclk, or FALSE. The returned values represent the clock equation: 694 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 695 */ 696 static bool 697 chv_find_best_dpll(const struct intel_limit *limit, 698 struct intel_crtc_state *crtc_state, 699 int target, int refclk, struct dpll *match_clock, 700 struct dpll *best_clock) 701 { 702 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 703 struct drm_device *dev = crtc->base.dev; 704 unsigned int best_error_ppm; 705 struct dpll clock; 706 u64 m2; 707 int found = false; 708 709 memset(best_clock, 0, sizeof(*best_clock)); 710 best_error_ppm = 1000000; 711 712 /* 713 * Based on hardware doc, the n always set to 1, and m1 always 714 * set to 2. If requires to support 200Mhz refclk, we need to 715 * revisit this because n may not 1 anymore. 716 */ 717 clock.n = 1; 718 clock.m1 = 2; 719 target *= 5; /* fast clock */ 720 721 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 722 for (clock.p2 = limit->p2.p2_fast; 723 clock.p2 >= limit->p2.p2_slow; 724 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 725 unsigned int error_ppm; 726 727 clock.p = clock.p1 * clock.p2; 728 729 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22, 730 refclk * clock.m1); 731 732 if (m2 > INT_MAX/clock.m1) 733 continue; 734 735 clock.m2 = m2; 736 737 chv_calc_dpll_params(refclk, &clock); 738 739 if (!intel_pll_is_valid(to_i915(dev), limit, &clock)) 740 continue; 741 742 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, 743 best_error_ppm, &error_ppm)) 744 continue; 745 746 *best_clock = clock; 747 best_error_ppm = error_ppm; 748 found = true; 749 } 750 } 751 752 return found; 753 } 754 755 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, 756 struct dpll *best_clock) 757 { 758 int refclk = 100000; 759 const struct intel_limit *limit = &intel_limits_bxt; 760 761 return chv_find_best_dpll(limit, crtc_state, 762 crtc_state->port_clock, refclk, 763 NULL, best_clock); 764 } 765 766 static u32 pnv_dpll_compute_fp(struct dpll *dpll) 767 { 768 return (1 << dpll->n) << 16 | dpll->m2; 769 } 770 771 static void i9xx_update_pll_dividers(struct intel_crtc *crtc, 772 struct intel_crtc_state *crtc_state, 773 struct dpll *reduced_clock) 774 { 775 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 776 u32 fp, fp2 = 0; 777 778 if (IS_PINEVIEW(dev_priv)) { 779 fp = pnv_dpll_compute_fp(&crtc_state->dpll); 780 if (reduced_clock) 781 fp2 = pnv_dpll_compute_fp(reduced_clock); 782 } else { 783 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); 784 if (reduced_clock) 785 fp2 = i9xx_dpll_compute_fp(reduced_clock); 786 } 787 788 crtc_state->dpll_hw_state.fp0 = fp; 789 790 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 791 reduced_clock) { 792 crtc_state->dpll_hw_state.fp1 = fp2; 793 } else { 794 crtc_state->dpll_hw_state.fp1 = fp; 795 } 796 } 797 798 static void i9xx_compute_dpll(struct intel_crtc *crtc, 799 struct intel_crtc_state *crtc_state, 800 struct dpll *reduced_clock) 801 { 802 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 803 u32 dpll; 804 struct dpll *clock = &crtc_state->dpll; 805 806 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); 807 808 dpll = DPLL_VGA_MODE_DIS; 809 810 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) 811 dpll |= DPLLB_MODE_LVDS; 812 else 813 dpll |= DPLLB_MODE_DAC_SERIAL; 814 815 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 816 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 817 dpll |= (crtc_state->pixel_multiplier - 1) 818 << SDVO_MULTIPLIER_SHIFT_HIRES; 819 } 820 821 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || 822 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 823 dpll |= DPLL_SDVO_HIGH_SPEED; 824 825 if (intel_crtc_has_dp_encoder(crtc_state)) 826 dpll |= DPLL_SDVO_HIGH_SPEED; 827 828 /* compute bitmask from p1 value */ 829 if (IS_PINEVIEW(dev_priv)) 830 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; 831 else { 832 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 833 if (IS_G4X(dev_priv) && reduced_clock) 834 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 835 } 836 switch (clock->p2) { 837 case 5: 838 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 839 break; 840 case 7: 841 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 842 break; 843 case 10: 844 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 845 break; 846 case 14: 847 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 848 break; 849 } 850 if (DISPLAY_VER(dev_priv) >= 4) 851 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 852 853 if (crtc_state->sdvo_tv_clock) 854 dpll |= PLL_REF_INPUT_TVCLKINBC; 855 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 856 intel_panel_use_ssc(dev_priv)) 857 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 858 else 859 dpll |= PLL_REF_INPUT_DREFCLK; 860 861 dpll |= DPLL_VCO_ENABLE; 862 crtc_state->dpll_hw_state.dpll = dpll; 863 864 if (DISPLAY_VER(dev_priv) >= 4) { 865 u32 dpll_md = (crtc_state->pixel_multiplier - 1) 866 << DPLL_MD_UDI_MULTIPLIER_SHIFT; 867 crtc_state->dpll_hw_state.dpll_md = dpll_md; 868 } 869 } 870 871 static void i8xx_compute_dpll(struct intel_crtc *crtc, 872 struct intel_crtc_state *crtc_state, 873 struct dpll *reduced_clock) 874 { 875 struct drm_device *dev = crtc->base.dev; 876 struct drm_i915_private *dev_priv = to_i915(dev); 877 u32 dpll; 878 struct dpll *clock = &crtc_state->dpll; 879 880 i9xx_update_pll_dividers(crtc, crtc_state, reduced_clock); 881 882 dpll = DPLL_VGA_MODE_DIS; 883 884 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 885 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 886 } else { 887 if (clock->p1 == 2) 888 dpll |= PLL_P1_DIVIDE_BY_TWO; 889 else 890 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; 891 if (clock->p2 == 4) 892 dpll |= PLL_P2_DIVIDE_BY_4; 893 } 894 895 /* 896 * Bspec: 897 * "[Almador Errata}: For the correct operation of the muxed DVO pins 898 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, 899 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock 900 * Enable) must be set to “1” in both the DPLL A Control Register 901 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." 902 * 903 * For simplicity We simply keep both bits always enabled in 904 * both DPLLS. The spec says we should disable the DVO 2X clock 905 * when not needed, but this seems to work fine in practice. 906 */ 907 if (IS_I830(dev_priv) || 908 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) 909 dpll |= DPLL_DVO_2X_MODE; 910 911 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 912 intel_panel_use_ssc(dev_priv)) 913 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 914 else 915 dpll |= PLL_REF_INPUT_DREFCLK; 916 917 dpll |= DPLL_VCO_ENABLE; 918 crtc_state->dpll_hw_state.dpll = dpll; 919 } 920 921 static int hsw_crtc_compute_clock(struct intel_crtc *crtc, 922 struct intel_crtc_state *crtc_state) 923 { 924 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 925 struct intel_atomic_state *state = 926 to_intel_atomic_state(crtc_state->uapi.state); 927 struct intel_encoder *encoder = 928 intel_get_crtc_new_encoder(state, crtc_state); 929 930 if (IS_DG2(dev_priv)) { 931 return intel_mpllb_calc_state(crtc_state, encoder); 932 } else if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI) || 933 DISPLAY_VER(dev_priv) >= 11) { 934 if (!intel_reserve_shared_dplls(state, crtc, encoder)) { 935 drm_dbg_kms(&dev_priv->drm, 936 "failed to find PLL for pipe %c\n", 937 pipe_name(crtc->pipe)); 938 return -EINVAL; 939 } 940 } 941 942 return 0; 943 } 944 945 static bool ilk_needs_fb_cb_tune(struct dpll *dpll, int factor) 946 { 947 return i9xx_dpll_compute_m(dpll) < factor * dpll->n; 948 } 949 950 951 static void ilk_compute_dpll(struct intel_crtc *crtc, 952 struct intel_crtc_state *crtc_state, 953 struct dpll *reduced_clock) 954 { 955 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 956 u32 dpll, fp, fp2; 957 int factor; 958 959 /* Enable autotuning of the PLL clock (if permissible) */ 960 factor = 21; 961 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 962 if ((intel_panel_use_ssc(dev_priv) && 963 dev_priv->vbt.lvds_ssc_freq == 100000) || 964 (HAS_PCH_IBX(dev_priv) && 965 intel_is_dual_link_lvds(dev_priv))) 966 factor = 25; 967 } else if (crtc_state->sdvo_tv_clock) { 968 factor = 20; 969 } 970 971 fp = i9xx_dpll_compute_fp(&crtc_state->dpll); 972 973 if (ilk_needs_fb_cb_tune(&crtc_state->dpll, factor)) 974 fp |= FP_CB_TUNE; 975 976 if (reduced_clock) { 977 fp2 = i9xx_dpll_compute_fp(reduced_clock); 978 979 if (reduced_clock->m < factor * reduced_clock->n) 980 fp2 |= FP_CB_TUNE; 981 } else { 982 fp2 = fp; 983 } 984 985 dpll = 0; 986 987 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) 988 dpll |= DPLLB_MODE_LVDS; 989 else 990 dpll |= DPLLB_MODE_DAC_SERIAL; 991 992 dpll |= (crtc_state->pixel_multiplier - 1) 993 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 994 995 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || 996 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 997 dpll |= DPLL_SDVO_HIGH_SPEED; 998 999 if (intel_crtc_has_dp_encoder(crtc_state)) 1000 dpll |= DPLL_SDVO_HIGH_SPEED; 1001 1002 /* 1003 * The high speed IO clock is only really required for 1004 * SDVO/HDMI/DP, but we also enable it for CRT to make it 1005 * possible to share the DPLL between CRT and HDMI. Enabling 1006 * the clock needlessly does no real harm, except use up a 1007 * bit of power potentially. 1008 * 1009 * We'll limit this to IVB with 3 pipes, since it has only two 1010 * DPLLs and so DPLL sharing is the only way to get three pipes 1011 * driving PCH ports at the same time. On SNB we could do this, 1012 * and potentially avoid enabling the second DPLL, but it's not 1013 * clear if it''s a win or loss power wise. No point in doing 1014 * this on ILK at all since it has a fixed DPLL<->pipe mapping. 1015 */ 1016 if (INTEL_NUM_PIPES(dev_priv) == 3 && 1017 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1018 dpll |= DPLL_SDVO_HIGH_SPEED; 1019 1020 /* compute bitmask from p1 value */ 1021 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 1022 /* also FPA1 */ 1023 dpll |= (1 << (crtc_state->dpll.p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 1024 1025 switch (crtc_state->dpll.p2) { 1026 case 5: 1027 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 1028 break; 1029 case 7: 1030 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 1031 break; 1032 case 10: 1033 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 1034 break; 1035 case 14: 1036 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 1037 break; 1038 } 1039 1040 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 1041 intel_panel_use_ssc(dev_priv)) 1042 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 1043 else 1044 dpll |= PLL_REF_INPUT_DREFCLK; 1045 1046 dpll |= DPLL_VCO_ENABLE; 1047 1048 crtc_state->dpll_hw_state.dpll = dpll; 1049 crtc_state->dpll_hw_state.fp0 = fp; 1050 crtc_state->dpll_hw_state.fp1 = fp2; 1051 } 1052 1053 static int ilk_crtc_compute_clock(struct intel_crtc *crtc, 1054 struct intel_crtc_state *crtc_state) 1055 { 1056 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1057 struct intel_atomic_state *state = 1058 to_intel_atomic_state(crtc_state->uapi.state); 1059 const struct intel_limit *limit; 1060 int refclk = 120000; 1061 1062 memset(&crtc_state->dpll_hw_state, 0, 1063 sizeof(crtc_state->dpll_hw_state)); 1064 1065 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 1066 if (!crtc_state->has_pch_encoder) 1067 return 0; 1068 1069 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1070 if (intel_panel_use_ssc(dev_priv)) { 1071 drm_dbg_kms(&dev_priv->drm, 1072 "using SSC reference clock of %d kHz\n", 1073 dev_priv->vbt.lvds_ssc_freq); 1074 refclk = dev_priv->vbt.lvds_ssc_freq; 1075 } 1076 1077 if (intel_is_dual_link_lvds(dev_priv)) { 1078 if (refclk == 100000) 1079 limit = &ilk_limits_dual_lvds_100m; 1080 else 1081 limit = &ilk_limits_dual_lvds; 1082 } else { 1083 if (refclk == 100000) 1084 limit = &ilk_limits_single_lvds_100m; 1085 else 1086 limit = &ilk_limits_single_lvds; 1087 } 1088 } else { 1089 limit = &ilk_limits_dac; 1090 } 1091 1092 if (!crtc_state->clock_set && 1093 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1094 refclk, NULL, &crtc_state->dpll)) { 1095 drm_err(&dev_priv->drm, 1096 "Couldn't find PLL settings for mode!\n"); 1097 return -EINVAL; 1098 } 1099 1100 ilk_compute_dpll(crtc, crtc_state, NULL); 1101 1102 if (!intel_reserve_shared_dplls(state, crtc, NULL)) { 1103 drm_dbg_kms(&dev_priv->drm, 1104 "failed to find PLL for pipe %c\n", 1105 pipe_name(crtc->pipe)); 1106 return -EINVAL; 1107 } 1108 1109 return 0; 1110 } 1111 1112 void vlv_compute_dpll(struct intel_crtc *crtc, 1113 struct intel_crtc_state *pipe_config) 1114 { 1115 pipe_config->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | 1116 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1117 if (crtc->pipe != PIPE_A) 1118 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 1119 1120 /* DPLL not used with DSI, but still need the rest set up */ 1121 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) 1122 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | 1123 DPLL_EXT_BUFFER_ENABLE_VLV; 1124 1125 pipe_config->dpll_hw_state.dpll_md = 1126 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 1127 } 1128 1129 void chv_compute_dpll(struct intel_crtc *crtc, 1130 struct intel_crtc_state *pipe_config) 1131 { 1132 pipe_config->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | 1133 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1134 if (crtc->pipe != PIPE_A) 1135 pipe_config->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 1136 1137 /* DPLL not used with DSI, but still need the rest set up */ 1138 if (!intel_crtc_has_type(pipe_config, INTEL_OUTPUT_DSI)) 1139 pipe_config->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; 1140 1141 pipe_config->dpll_hw_state.dpll_md = 1142 (pipe_config->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 1143 } 1144 1145 static int chv_crtc_compute_clock(struct intel_crtc *crtc, 1146 struct intel_crtc_state *crtc_state) 1147 { 1148 int refclk = 100000; 1149 const struct intel_limit *limit = &intel_limits_chv; 1150 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1151 1152 memset(&crtc_state->dpll_hw_state, 0, 1153 sizeof(crtc_state->dpll_hw_state)); 1154 1155 if (!crtc_state->clock_set && 1156 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1157 refclk, NULL, &crtc_state->dpll)) { 1158 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); 1159 return -EINVAL; 1160 } 1161 1162 chv_compute_dpll(crtc, crtc_state); 1163 1164 return 0; 1165 } 1166 1167 static int vlv_crtc_compute_clock(struct intel_crtc *crtc, 1168 struct intel_crtc_state *crtc_state) 1169 { 1170 int refclk = 100000; 1171 const struct intel_limit *limit = &intel_limits_vlv; 1172 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1173 1174 memset(&crtc_state->dpll_hw_state, 0, 1175 sizeof(crtc_state->dpll_hw_state)); 1176 1177 if (!crtc_state->clock_set && 1178 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1179 refclk, NULL, &crtc_state->dpll)) { 1180 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); 1181 return -EINVAL; 1182 } 1183 1184 vlv_compute_dpll(crtc, crtc_state); 1185 1186 return 0; 1187 } 1188 1189 static int g4x_crtc_compute_clock(struct intel_crtc *crtc, 1190 struct intel_crtc_state *crtc_state) 1191 { 1192 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1193 const struct intel_limit *limit; 1194 int refclk = 96000; 1195 1196 memset(&crtc_state->dpll_hw_state, 0, 1197 sizeof(crtc_state->dpll_hw_state)); 1198 1199 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1200 if (intel_panel_use_ssc(dev_priv)) { 1201 refclk = dev_priv->vbt.lvds_ssc_freq; 1202 drm_dbg_kms(&dev_priv->drm, 1203 "using SSC reference clock of %d kHz\n", 1204 refclk); 1205 } 1206 1207 if (intel_is_dual_link_lvds(dev_priv)) 1208 limit = &intel_limits_g4x_dual_channel_lvds; 1209 else 1210 limit = &intel_limits_g4x_single_channel_lvds; 1211 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || 1212 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1213 limit = &intel_limits_g4x_hdmi; 1214 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { 1215 limit = &intel_limits_g4x_sdvo; 1216 } else { 1217 /* The option is for other outputs */ 1218 limit = &intel_limits_i9xx_sdvo; 1219 } 1220 1221 if (!crtc_state->clock_set && 1222 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1223 refclk, NULL, &crtc_state->dpll)) { 1224 drm_err(&dev_priv->drm, 1225 "Couldn't find PLL settings for mode!\n"); 1226 return -EINVAL; 1227 } 1228 1229 i9xx_compute_dpll(crtc, crtc_state, NULL); 1230 1231 return 0; 1232 } 1233 1234 static int pnv_crtc_compute_clock(struct intel_crtc *crtc, 1235 struct intel_crtc_state *crtc_state) 1236 { 1237 struct drm_device *dev = crtc->base.dev; 1238 struct drm_i915_private *dev_priv = to_i915(dev); 1239 const struct intel_limit *limit; 1240 int refclk = 96000; 1241 1242 memset(&crtc_state->dpll_hw_state, 0, 1243 sizeof(crtc_state->dpll_hw_state)); 1244 1245 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1246 if (intel_panel_use_ssc(dev_priv)) { 1247 refclk = dev_priv->vbt.lvds_ssc_freq; 1248 drm_dbg_kms(&dev_priv->drm, 1249 "using SSC reference clock of %d kHz\n", 1250 refclk); 1251 } 1252 1253 limit = &pnv_limits_lvds; 1254 } else { 1255 limit = &pnv_limits_sdvo; 1256 } 1257 1258 if (!crtc_state->clock_set && 1259 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1260 refclk, NULL, &crtc_state->dpll)) { 1261 drm_err(&dev_priv->drm, 1262 "Couldn't find PLL settings for mode!\n"); 1263 return -EINVAL; 1264 } 1265 1266 i9xx_compute_dpll(crtc, crtc_state, NULL); 1267 1268 return 0; 1269 } 1270 1271 static int i9xx_crtc_compute_clock(struct intel_crtc *crtc, 1272 struct intel_crtc_state *crtc_state) 1273 { 1274 struct drm_device *dev = crtc->base.dev; 1275 struct drm_i915_private *dev_priv = to_i915(dev); 1276 const struct intel_limit *limit; 1277 int refclk = 96000; 1278 1279 memset(&crtc_state->dpll_hw_state, 0, 1280 sizeof(crtc_state->dpll_hw_state)); 1281 1282 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1283 if (intel_panel_use_ssc(dev_priv)) { 1284 refclk = dev_priv->vbt.lvds_ssc_freq; 1285 drm_dbg_kms(&dev_priv->drm, 1286 "using SSC reference clock of %d kHz\n", 1287 refclk); 1288 } 1289 1290 limit = &intel_limits_i9xx_lvds; 1291 } else { 1292 limit = &intel_limits_i9xx_sdvo; 1293 } 1294 1295 if (!crtc_state->clock_set && 1296 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1297 refclk, NULL, &crtc_state->dpll)) { 1298 drm_err(&dev_priv->drm, 1299 "Couldn't find PLL settings for mode!\n"); 1300 return -EINVAL; 1301 } 1302 1303 i9xx_compute_dpll(crtc, crtc_state, NULL); 1304 1305 return 0; 1306 } 1307 1308 static int i8xx_crtc_compute_clock(struct intel_crtc *crtc, 1309 struct intel_crtc_state *crtc_state) 1310 { 1311 struct drm_device *dev = crtc->base.dev; 1312 struct drm_i915_private *dev_priv = to_i915(dev); 1313 const struct intel_limit *limit; 1314 int refclk = 48000; 1315 1316 memset(&crtc_state->dpll_hw_state, 0, 1317 sizeof(crtc_state->dpll_hw_state)); 1318 1319 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1320 if (intel_panel_use_ssc(dev_priv)) { 1321 refclk = dev_priv->vbt.lvds_ssc_freq; 1322 drm_dbg_kms(&dev_priv->drm, 1323 "using SSC reference clock of %d kHz\n", 1324 refclk); 1325 } 1326 1327 limit = &intel_limits_i8xx_lvds; 1328 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { 1329 limit = &intel_limits_i8xx_dvo; 1330 } else { 1331 limit = &intel_limits_i8xx_dac; 1332 } 1333 1334 if (!crtc_state->clock_set && 1335 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1336 refclk, NULL, &crtc_state->dpll)) { 1337 drm_err(&dev_priv->drm, 1338 "Couldn't find PLL settings for mode!\n"); 1339 return -EINVAL; 1340 } 1341 1342 i8xx_compute_dpll(crtc, crtc_state, NULL); 1343 1344 return 0; 1345 } 1346 1347 void 1348 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv) 1349 { 1350 if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv)) 1351 dev_priv->display.crtc_compute_clock = hsw_crtc_compute_clock; 1352 else if (HAS_PCH_SPLIT(dev_priv)) 1353 dev_priv->display.crtc_compute_clock = ilk_crtc_compute_clock; 1354 else if (IS_CHERRYVIEW(dev_priv)) 1355 dev_priv->display.crtc_compute_clock = chv_crtc_compute_clock; 1356 else if (IS_VALLEYVIEW(dev_priv)) 1357 dev_priv->display.crtc_compute_clock = vlv_crtc_compute_clock; 1358 else if (IS_G4X(dev_priv)) 1359 dev_priv->display.crtc_compute_clock = g4x_crtc_compute_clock; 1360 else if (IS_PINEVIEW(dev_priv)) 1361 dev_priv->display.crtc_compute_clock = pnv_crtc_compute_clock; 1362 else if (DISPLAY_VER(dev_priv) != 2) 1363 dev_priv->display.crtc_compute_clock = i9xx_crtc_compute_clock; 1364 else 1365 dev_priv->display.crtc_compute_clock = i8xx_crtc_compute_clock; 1366 } 1367 1368 static bool i9xx_has_pps(struct drm_i915_private *dev_priv) 1369 { 1370 if (IS_I830(dev_priv)) 1371 return false; 1372 1373 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 1374 } 1375 1376 void i9xx_enable_pll(struct intel_crtc *crtc, 1377 const struct intel_crtc_state *crtc_state) 1378 { 1379 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1380 i915_reg_t reg = DPLL(crtc->pipe); 1381 u32 dpll = crtc_state->dpll_hw_state.dpll; 1382 int i; 1383 1384 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); 1385 1386 /* PLL is protected by panel, make sure we can write it */ 1387 if (i9xx_has_pps(dev_priv)) 1388 assert_panel_unlocked(dev_priv, crtc->pipe); 1389 1390 /* 1391 * Apparently we need to have VGA mode enabled prior to changing 1392 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 1393 * dividers, even though the register value does change. 1394 */ 1395 intel_de_write(dev_priv, reg, dpll & ~DPLL_VGA_MODE_DIS); 1396 intel_de_write(dev_priv, reg, dpll); 1397 1398 /* Wait for the clocks to stabilize. */ 1399 intel_de_posting_read(dev_priv, reg); 1400 udelay(150); 1401 1402 if (DISPLAY_VER(dev_priv) >= 4) { 1403 intel_de_write(dev_priv, DPLL_MD(crtc->pipe), 1404 crtc_state->dpll_hw_state.dpll_md); 1405 } else { 1406 /* The pixel multiplier can only be updated once the 1407 * DPLL is enabled and the clocks are stable. 1408 * 1409 * So write it again. 1410 */ 1411 intel_de_write(dev_priv, reg, dpll); 1412 } 1413 1414 /* We do this three times for luck */ 1415 for (i = 0; i < 3; i++) { 1416 intel_de_write(dev_priv, reg, dpll); 1417 intel_de_posting_read(dev_priv, reg); 1418 udelay(150); /* wait for warmup */ 1419 } 1420 } 1421 1422 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, 1423 enum pipe pipe) 1424 { 1425 u32 reg_val; 1426 1427 /* 1428 * PLLB opamp always calibrates to max value of 0x3f, force enable it 1429 * and set it to a reasonable value instead. 1430 */ 1431 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); 1432 reg_val &= 0xffffff00; 1433 reg_val |= 0x00000030; 1434 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); 1435 1436 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); 1437 reg_val &= 0x00ffffff; 1438 reg_val |= 0x8c000000; 1439 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 1440 1441 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); 1442 reg_val &= 0xffffff00; 1443 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); 1444 1445 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); 1446 reg_val &= 0x00ffffff; 1447 reg_val |= 0xb0000000; 1448 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 1449 } 1450 1451 static void _vlv_enable_pll(struct intel_crtc *crtc, 1452 const struct intel_crtc_state *pipe_config) 1453 { 1454 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1455 enum pipe pipe = crtc->pipe; 1456 1457 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); 1458 intel_de_posting_read(dev_priv, DPLL(pipe)); 1459 udelay(150); 1460 1461 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) 1462 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); 1463 } 1464 1465 void vlv_enable_pll(struct intel_crtc *crtc, 1466 const struct intel_crtc_state *pipe_config) 1467 { 1468 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1469 enum pipe pipe = crtc->pipe; 1470 1471 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); 1472 1473 /* PLL is protected by panel, make sure we can write it */ 1474 assert_panel_unlocked(dev_priv, pipe); 1475 1476 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) 1477 _vlv_enable_pll(crtc, pipe_config); 1478 1479 intel_de_write(dev_priv, DPLL_MD(pipe), 1480 pipe_config->dpll_hw_state.dpll_md); 1481 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); 1482 } 1483 1484 1485 static void _chv_enable_pll(struct intel_crtc *crtc, 1486 const struct intel_crtc_state *pipe_config) 1487 { 1488 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1489 enum pipe pipe = crtc->pipe; 1490 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1491 u32 tmp; 1492 1493 vlv_dpio_get(dev_priv); 1494 1495 /* Enable back the 10bit clock to display controller */ 1496 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); 1497 tmp |= DPIO_DCLKP_EN; 1498 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); 1499 1500 vlv_dpio_put(dev_priv); 1501 1502 /* 1503 * Need to wait > 100ns between dclkp clock enable bit and PLL enable. 1504 */ 1505 udelay(1); 1506 1507 /* Enable PLL */ 1508 intel_de_write(dev_priv, DPLL(pipe), pipe_config->dpll_hw_state.dpll); 1509 1510 /* Check PLL is locked */ 1511 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) 1512 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); 1513 } 1514 1515 void chv_enable_pll(struct intel_crtc *crtc, 1516 const struct intel_crtc_state *pipe_config) 1517 { 1518 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1519 enum pipe pipe = crtc->pipe; 1520 1521 assert_pipe_disabled(dev_priv, pipe_config->cpu_transcoder); 1522 1523 /* PLL is protected by panel, make sure we can write it */ 1524 assert_panel_unlocked(dev_priv, pipe); 1525 1526 if (pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) 1527 _chv_enable_pll(crtc, pipe_config); 1528 1529 if (pipe != PIPE_A) { 1530 /* 1531 * WaPixelRepeatModeFixForC0:chv 1532 * 1533 * DPLLCMD is AWOL. Use chicken bits to propagate 1534 * the value from DPLLBMD to either pipe B or C. 1535 */ 1536 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); 1537 intel_de_write(dev_priv, DPLL_MD(PIPE_B), 1538 pipe_config->dpll_hw_state.dpll_md); 1539 intel_de_write(dev_priv, CBR4_VLV, 0); 1540 dev_priv->chv_dpll_md[pipe] = pipe_config->dpll_hw_state.dpll_md; 1541 1542 /* 1543 * DPLLB VGA mode also seems to cause problems. 1544 * We should always have it disabled. 1545 */ 1546 drm_WARN_ON(&dev_priv->drm, 1547 (intel_de_read(dev_priv, DPLL(PIPE_B)) & 1548 DPLL_VGA_MODE_DIS) == 0); 1549 } else { 1550 intel_de_write(dev_priv, DPLL_MD(pipe), 1551 pipe_config->dpll_hw_state.dpll_md); 1552 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); 1553 } 1554 } 1555 1556 void vlv_prepare_pll(struct intel_crtc *crtc, 1557 const struct intel_crtc_state *pipe_config) 1558 { 1559 struct drm_device *dev = crtc->base.dev; 1560 struct drm_i915_private *dev_priv = to_i915(dev); 1561 enum pipe pipe = crtc->pipe; 1562 u32 mdiv; 1563 u32 bestn, bestm1, bestm2, bestp1, bestp2; 1564 u32 coreclk, reg_val; 1565 1566 /* Enable Refclk */ 1567 intel_de_write(dev_priv, DPLL(pipe), 1568 pipe_config->dpll_hw_state.dpll & ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); 1569 1570 /* No need to actually set up the DPLL with DSI */ 1571 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 1572 return; 1573 1574 vlv_dpio_get(dev_priv); 1575 1576 bestn = pipe_config->dpll.n; 1577 bestm1 = pipe_config->dpll.m1; 1578 bestm2 = pipe_config->dpll.m2; 1579 bestp1 = pipe_config->dpll.p1; 1580 bestp2 = pipe_config->dpll.p2; 1581 1582 /* See eDP HDMI DPIO driver vbios notes doc */ 1583 1584 /* PLL B needs special handling */ 1585 if (pipe == PIPE_B) 1586 vlv_pllb_recal_opamp(dev_priv, pipe); 1587 1588 /* Set up Tx target for periodic Rcomp update */ 1589 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); 1590 1591 /* Disable target IRef on PLL */ 1592 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); 1593 reg_val &= 0x00ffffff; 1594 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); 1595 1596 /* Disable fast lock */ 1597 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); 1598 1599 /* Set idtafcrecal before PLL is enabled */ 1600 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); 1601 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); 1602 mdiv |= ((bestn << DPIO_N_SHIFT)); 1603 mdiv |= (1 << DPIO_K_SHIFT); 1604 1605 /* 1606 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, 1607 * but we don't support that). 1608 * Note: don't use the DAC post divider as it seems unstable. 1609 */ 1610 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); 1611 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); 1612 1613 mdiv |= DPIO_ENABLE_CALIBRATION; 1614 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); 1615 1616 /* Set HBR and RBR LPF coefficients */ 1617 if (pipe_config->port_clock == 162000 || 1618 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_ANALOG) || 1619 intel_crtc_has_type(pipe_config, INTEL_OUTPUT_HDMI)) 1620 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 1621 0x009f0003); 1622 else 1623 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 1624 0x00d0000f); 1625 1626 if (intel_crtc_has_dp_encoder(pipe_config)) { 1627 /* Use SSC source */ 1628 if (pipe == PIPE_A) 1629 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1630 0x0df40000); 1631 else 1632 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1633 0x0df70000); 1634 } else { /* HDMI or VGA */ 1635 /* Use bend source */ 1636 if (pipe == PIPE_A) 1637 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1638 0x0df70000); 1639 else 1640 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1641 0x0df40000); 1642 } 1643 1644 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); 1645 coreclk = (coreclk & 0x0000ff00) | 0x01c00000; 1646 if (intel_crtc_has_dp_encoder(pipe_config)) 1647 coreclk |= 0x01000000; 1648 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); 1649 1650 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); 1651 1652 vlv_dpio_put(dev_priv); 1653 } 1654 1655 void chv_prepare_pll(struct intel_crtc *crtc, 1656 const struct intel_crtc_state *pipe_config) 1657 { 1658 struct drm_device *dev = crtc->base.dev; 1659 struct drm_i915_private *dev_priv = to_i915(dev); 1660 enum pipe pipe = crtc->pipe; 1661 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1662 u32 loopfilter, tribuf_calcntr; 1663 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; 1664 u32 dpio_val; 1665 int vco; 1666 1667 /* Enable Refclk and SSC */ 1668 intel_de_write(dev_priv, DPLL(pipe), 1669 pipe_config->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); 1670 1671 /* No need to actually set up the DPLL with DSI */ 1672 if ((pipe_config->dpll_hw_state.dpll & DPLL_VCO_ENABLE) == 0) 1673 return; 1674 1675 bestn = pipe_config->dpll.n; 1676 bestm2_frac = pipe_config->dpll.m2 & 0x3fffff; 1677 bestm1 = pipe_config->dpll.m1; 1678 bestm2 = pipe_config->dpll.m2 >> 22; 1679 bestp1 = pipe_config->dpll.p1; 1680 bestp2 = pipe_config->dpll.p2; 1681 vco = pipe_config->dpll.vco; 1682 dpio_val = 0; 1683 loopfilter = 0; 1684 1685 vlv_dpio_get(dev_priv); 1686 1687 /* p1 and p2 divider */ 1688 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), 1689 5 << DPIO_CHV_S1_DIV_SHIFT | 1690 bestp1 << DPIO_CHV_P1_DIV_SHIFT | 1691 bestp2 << DPIO_CHV_P2_DIV_SHIFT | 1692 1 << DPIO_CHV_K_DIV_SHIFT); 1693 1694 /* Feedback post-divider - m2 */ 1695 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); 1696 1697 /* Feedback refclk divider - n and m1 */ 1698 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), 1699 DPIO_CHV_M1_DIV_BY_2 | 1700 1 << DPIO_CHV_N_DIV_SHIFT); 1701 1702 /* M2 fraction division */ 1703 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); 1704 1705 /* M2 fraction division enable */ 1706 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 1707 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); 1708 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); 1709 if (bestm2_frac) 1710 dpio_val |= DPIO_CHV_FRAC_DIV_EN; 1711 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); 1712 1713 /* Program digital lock detect threshold */ 1714 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); 1715 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | 1716 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); 1717 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); 1718 if (!bestm2_frac) 1719 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; 1720 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); 1721 1722 /* Loop filter */ 1723 if (vco == 5400000) { 1724 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); 1725 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); 1726 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); 1727 tribuf_calcntr = 0x9; 1728 } else if (vco <= 6200000) { 1729 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); 1730 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); 1731 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1732 tribuf_calcntr = 0x9; 1733 } else if (vco <= 6480000) { 1734 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 1735 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 1736 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1737 tribuf_calcntr = 0x8; 1738 } else { 1739 /* Not supported. Apply the same limits as in the max case */ 1740 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 1741 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 1742 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1743 tribuf_calcntr = 0; 1744 } 1745 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); 1746 1747 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); 1748 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; 1749 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); 1750 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); 1751 1752 /* AFC Recal */ 1753 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), 1754 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | 1755 DPIO_AFC_RECAL); 1756 1757 vlv_dpio_put(dev_priv); 1758 } 1759 1760 /** 1761 * vlv_force_pll_on - forcibly enable just the PLL 1762 * @dev_priv: i915 private structure 1763 * @pipe: pipe PLL to enable 1764 * @dpll: PLL configuration 1765 * 1766 * Enable the PLL for @pipe using the supplied @dpll config. To be used 1767 * in cases where we need the PLL enabled even when @pipe is not going to 1768 * be enabled. 1769 */ 1770 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, 1771 const struct dpll *dpll) 1772 { 1773 struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); 1774 struct intel_crtc_state *pipe_config; 1775 1776 pipe_config = intel_crtc_state_alloc(crtc); 1777 if (!pipe_config) 1778 return -ENOMEM; 1779 1780 pipe_config->cpu_transcoder = (enum transcoder)pipe; 1781 pipe_config->pixel_multiplier = 1; 1782 pipe_config->dpll = *dpll; 1783 1784 if (IS_CHERRYVIEW(dev_priv)) { 1785 chv_compute_dpll(crtc, pipe_config); 1786 chv_prepare_pll(crtc, pipe_config); 1787 chv_enable_pll(crtc, pipe_config); 1788 } else { 1789 vlv_compute_dpll(crtc, pipe_config); 1790 vlv_prepare_pll(crtc, pipe_config); 1791 vlv_enable_pll(crtc, pipe_config); 1792 } 1793 1794 kfree(pipe_config); 1795 1796 return 0; 1797 } 1798 1799 void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 1800 { 1801 u32 val; 1802 1803 /* Make sure the pipe isn't still relying on us */ 1804 assert_pipe_disabled(dev_priv, (enum transcoder)pipe); 1805 1806 val = DPLL_INTEGRATED_REF_CLK_VLV | 1807 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1808 if (pipe != PIPE_A) 1809 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1810 1811 intel_de_write(dev_priv, DPLL(pipe), val); 1812 intel_de_posting_read(dev_priv, DPLL(pipe)); 1813 } 1814 1815 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 1816 { 1817 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1818 u32 val; 1819 1820 /* Make sure the pipe isn't still relying on us */ 1821 assert_pipe_disabled(dev_priv, (enum transcoder)pipe); 1822 1823 val = DPLL_SSC_REF_CLK_CHV | 1824 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1825 if (pipe != PIPE_A) 1826 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1827 1828 intel_de_write(dev_priv, DPLL(pipe), val); 1829 intel_de_posting_read(dev_priv, DPLL(pipe)); 1830 1831 vlv_dpio_get(dev_priv); 1832 1833 /* Disable 10bit clock to display controller */ 1834 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); 1835 val &= ~DPIO_DCLKP_EN; 1836 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); 1837 1838 vlv_dpio_put(dev_priv); 1839 } 1840 1841 void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) 1842 { 1843 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1844 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1845 enum pipe pipe = crtc->pipe; 1846 1847 /* Don't disable pipe or pipe PLLs if needed */ 1848 if (IS_I830(dev_priv)) 1849 return; 1850 1851 /* Make sure the pipe isn't still relying on us */ 1852 assert_pipe_disabled(dev_priv, crtc_state->cpu_transcoder); 1853 1854 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 1855 intel_de_posting_read(dev_priv, DPLL(pipe)); 1856 } 1857 1858 1859 /** 1860 * vlv_force_pll_off - forcibly disable just the PLL 1861 * @dev_priv: i915 private structure 1862 * @pipe: pipe PLL to disable 1863 * 1864 * Disable the PLL for @pipe. To be used in cases where we need 1865 * the PLL enabled even when @pipe is not going to be enabled. 1866 */ 1867 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) 1868 { 1869 if (IS_CHERRYVIEW(dev_priv)) 1870 chv_disable_pll(dev_priv, pipe); 1871 else 1872 vlv_disable_pll(dev_priv, pipe); 1873 } 1874