1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/kernel.h> 7 8 #include "intel_crtc.h" 9 #include "intel_de.h" 10 #include "intel_display.h" 11 #include "intel_display_types.h" 12 #include "intel_dpll.h" 13 #include "intel_lvds.h" 14 #include "intel_panel.h" 15 #include "intel_pps.h" 16 #include "intel_snps_phy.h" 17 #include "vlv_sideband.h" 18 19 struct intel_dpll_funcs { 20 int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state); 21 }; 22 23 struct intel_limit { 24 struct { 25 int min, max; 26 } dot, vco, n, m, m1, m2, p, p1; 27 28 struct { 29 int dot_limit; 30 int p2_slow, p2_fast; 31 } p2; 32 }; 33 static const struct intel_limit intel_limits_i8xx_dac = { 34 .dot = { .min = 25000, .max = 350000 }, 35 .vco = { .min = 908000, .max = 1512000 }, 36 .n = { .min = 2, .max = 16 }, 37 .m = { .min = 96, .max = 140 }, 38 .m1 = { .min = 18, .max = 26 }, 39 .m2 = { .min = 6, .max = 16 }, 40 .p = { .min = 4, .max = 128 }, 41 .p1 = { .min = 2, .max = 33 }, 42 .p2 = { .dot_limit = 165000, 43 .p2_slow = 4, .p2_fast = 2 }, 44 }; 45 46 static const struct intel_limit intel_limits_i8xx_dvo = { 47 .dot = { .min = 25000, .max = 350000 }, 48 .vco = { .min = 908000, .max = 1512000 }, 49 .n = { .min = 2, .max = 16 }, 50 .m = { .min = 96, .max = 140 }, 51 .m1 = { .min = 18, .max = 26 }, 52 .m2 = { .min = 6, .max = 16 }, 53 .p = { .min = 4, .max = 128 }, 54 .p1 = { .min = 2, .max = 33 }, 55 .p2 = { .dot_limit = 165000, 56 .p2_slow = 4, .p2_fast = 4 }, 57 }; 58 59 static const struct intel_limit intel_limits_i8xx_lvds = { 60 .dot = { .min = 25000, .max = 350000 }, 61 .vco = { .min = 908000, .max = 1512000 }, 62 .n = { .min = 2, .max = 16 }, 63 .m = { .min = 96, .max = 140 }, 64 .m1 = { .min = 18, .max = 26 }, 65 .m2 = { .min = 6, .max = 16 }, 66 .p = { .min = 4, .max = 128 }, 67 .p1 = { .min = 1, .max = 6 }, 68 .p2 = { .dot_limit = 165000, 69 .p2_slow = 14, .p2_fast = 7 }, 70 }; 71 72 static const struct intel_limit intel_limits_i9xx_sdvo = { 73 .dot = { .min = 20000, .max = 400000 }, 74 .vco = { .min = 1400000, .max = 2800000 }, 75 .n = { .min = 1, .max = 6 }, 76 .m = { .min = 70, .max = 120 }, 77 .m1 = { .min = 8, .max = 18 }, 78 .m2 = { .min = 3, .max = 7 }, 79 .p = { .min = 5, .max = 80 }, 80 .p1 = { .min = 1, .max = 8 }, 81 .p2 = { .dot_limit = 200000, 82 .p2_slow = 10, .p2_fast = 5 }, 83 }; 84 85 static const struct intel_limit intel_limits_i9xx_lvds = { 86 .dot = { .min = 20000, .max = 400000 }, 87 .vco = { .min = 1400000, .max = 2800000 }, 88 .n = { .min = 1, .max = 6 }, 89 .m = { .min = 70, .max = 120 }, 90 .m1 = { .min = 8, .max = 18 }, 91 .m2 = { .min = 3, .max = 7 }, 92 .p = { .min = 7, .max = 98 }, 93 .p1 = { .min = 1, .max = 8 }, 94 .p2 = { .dot_limit = 112000, 95 .p2_slow = 14, .p2_fast = 7 }, 96 }; 97 98 99 static const struct intel_limit intel_limits_g4x_sdvo = { 100 .dot = { .min = 25000, .max = 270000 }, 101 .vco = { .min = 1750000, .max = 3500000}, 102 .n = { .min = 1, .max = 4 }, 103 .m = { .min = 104, .max = 138 }, 104 .m1 = { .min = 17, .max = 23 }, 105 .m2 = { .min = 5, .max = 11 }, 106 .p = { .min = 10, .max = 30 }, 107 .p1 = { .min = 1, .max = 3}, 108 .p2 = { .dot_limit = 270000, 109 .p2_slow = 10, 110 .p2_fast = 10 111 }, 112 }; 113 114 static const struct intel_limit intel_limits_g4x_hdmi = { 115 .dot = { .min = 22000, .max = 400000 }, 116 .vco = { .min = 1750000, .max = 3500000}, 117 .n = { .min = 1, .max = 4 }, 118 .m = { .min = 104, .max = 138 }, 119 .m1 = { .min = 16, .max = 23 }, 120 .m2 = { .min = 5, .max = 11 }, 121 .p = { .min = 5, .max = 80 }, 122 .p1 = { .min = 1, .max = 8}, 123 .p2 = { .dot_limit = 165000, 124 .p2_slow = 10, .p2_fast = 5 }, 125 }; 126 127 static const struct intel_limit intel_limits_g4x_single_channel_lvds = { 128 .dot = { .min = 20000, .max = 115000 }, 129 .vco = { .min = 1750000, .max = 3500000 }, 130 .n = { .min = 1, .max = 3 }, 131 .m = { .min = 104, .max = 138 }, 132 .m1 = { .min = 17, .max = 23 }, 133 .m2 = { .min = 5, .max = 11 }, 134 .p = { .min = 28, .max = 112 }, 135 .p1 = { .min = 2, .max = 8 }, 136 .p2 = { .dot_limit = 0, 137 .p2_slow = 14, .p2_fast = 14 138 }, 139 }; 140 141 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { 142 .dot = { .min = 80000, .max = 224000 }, 143 .vco = { .min = 1750000, .max = 3500000 }, 144 .n = { .min = 1, .max = 3 }, 145 .m = { .min = 104, .max = 138 }, 146 .m1 = { .min = 17, .max = 23 }, 147 .m2 = { .min = 5, .max = 11 }, 148 .p = { .min = 14, .max = 42 }, 149 .p1 = { .min = 2, .max = 6 }, 150 .p2 = { .dot_limit = 0, 151 .p2_slow = 7, .p2_fast = 7 152 }, 153 }; 154 155 static const struct intel_limit pnv_limits_sdvo = { 156 .dot = { .min = 20000, .max = 400000}, 157 .vco = { .min = 1700000, .max = 3500000 }, 158 /* Pineview's Ncounter is a ring counter */ 159 .n = { .min = 3, .max = 6 }, 160 .m = { .min = 2, .max = 256 }, 161 /* Pineview only has one combined m divider, which we treat as m2. */ 162 .m1 = { .min = 0, .max = 0 }, 163 .m2 = { .min = 0, .max = 254 }, 164 .p = { .min = 5, .max = 80 }, 165 .p1 = { .min = 1, .max = 8 }, 166 .p2 = { .dot_limit = 200000, 167 .p2_slow = 10, .p2_fast = 5 }, 168 }; 169 170 static const struct intel_limit pnv_limits_lvds = { 171 .dot = { .min = 20000, .max = 400000 }, 172 .vco = { .min = 1700000, .max = 3500000 }, 173 .n = { .min = 3, .max = 6 }, 174 .m = { .min = 2, .max = 256 }, 175 .m1 = { .min = 0, .max = 0 }, 176 .m2 = { .min = 0, .max = 254 }, 177 .p = { .min = 7, .max = 112 }, 178 .p1 = { .min = 1, .max = 8 }, 179 .p2 = { .dot_limit = 112000, 180 .p2_slow = 14, .p2_fast = 14 }, 181 }; 182 183 /* Ironlake / Sandybridge 184 * 185 * We calculate clock using (register_value + 2) for N/M1/M2, so here 186 * the range value for them is (actual_value - 2). 187 */ 188 static const struct intel_limit ilk_limits_dac = { 189 .dot = { .min = 25000, .max = 350000 }, 190 .vco = { .min = 1760000, .max = 3510000 }, 191 .n = { .min = 1, .max = 5 }, 192 .m = { .min = 79, .max = 127 }, 193 .m1 = { .min = 12, .max = 22 }, 194 .m2 = { .min = 5, .max = 9 }, 195 .p = { .min = 5, .max = 80 }, 196 .p1 = { .min = 1, .max = 8 }, 197 .p2 = { .dot_limit = 225000, 198 .p2_slow = 10, .p2_fast = 5 }, 199 }; 200 201 static const struct intel_limit ilk_limits_single_lvds = { 202 .dot = { .min = 25000, .max = 350000 }, 203 .vco = { .min = 1760000, .max = 3510000 }, 204 .n = { .min = 1, .max = 3 }, 205 .m = { .min = 79, .max = 118 }, 206 .m1 = { .min = 12, .max = 22 }, 207 .m2 = { .min = 5, .max = 9 }, 208 .p = { .min = 28, .max = 112 }, 209 .p1 = { .min = 2, .max = 8 }, 210 .p2 = { .dot_limit = 225000, 211 .p2_slow = 14, .p2_fast = 14 }, 212 }; 213 214 static const struct intel_limit ilk_limits_dual_lvds = { 215 .dot = { .min = 25000, .max = 350000 }, 216 .vco = { .min = 1760000, .max = 3510000 }, 217 .n = { .min = 1, .max = 3 }, 218 .m = { .min = 79, .max = 127 }, 219 .m1 = { .min = 12, .max = 22 }, 220 .m2 = { .min = 5, .max = 9 }, 221 .p = { .min = 14, .max = 56 }, 222 .p1 = { .min = 2, .max = 8 }, 223 .p2 = { .dot_limit = 225000, 224 .p2_slow = 7, .p2_fast = 7 }, 225 }; 226 227 /* LVDS 100mhz refclk limits. */ 228 static const struct intel_limit ilk_limits_single_lvds_100m = { 229 .dot = { .min = 25000, .max = 350000 }, 230 .vco = { .min = 1760000, .max = 3510000 }, 231 .n = { .min = 1, .max = 2 }, 232 .m = { .min = 79, .max = 126 }, 233 .m1 = { .min = 12, .max = 22 }, 234 .m2 = { .min = 5, .max = 9 }, 235 .p = { .min = 28, .max = 112 }, 236 .p1 = { .min = 2, .max = 8 }, 237 .p2 = { .dot_limit = 225000, 238 .p2_slow = 14, .p2_fast = 14 }, 239 }; 240 241 static const struct intel_limit ilk_limits_dual_lvds_100m = { 242 .dot = { .min = 25000, .max = 350000 }, 243 .vco = { .min = 1760000, .max = 3510000 }, 244 .n = { .min = 1, .max = 3 }, 245 .m = { .min = 79, .max = 126 }, 246 .m1 = { .min = 12, .max = 22 }, 247 .m2 = { .min = 5, .max = 9 }, 248 .p = { .min = 14, .max = 42 }, 249 .p1 = { .min = 2, .max = 6 }, 250 .p2 = { .dot_limit = 225000, 251 .p2_slow = 7, .p2_fast = 7 }, 252 }; 253 254 static const struct intel_limit intel_limits_vlv = { 255 /* 256 * These are the data rate limits (measured in fast clocks) 257 * since those are the strictest limits we have. The fast 258 * clock and actual rate limits are more relaxed, so checking 259 * them would make no difference. 260 */ 261 .dot = { .min = 25000 * 5, .max = 270000 * 5 }, 262 .vco = { .min = 4000000, .max = 6000000 }, 263 .n = { .min = 1, .max = 7 }, 264 .m1 = { .min = 2, .max = 3 }, 265 .m2 = { .min = 11, .max = 156 }, 266 .p1 = { .min = 2, .max = 3 }, 267 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ 268 }; 269 270 static const struct intel_limit intel_limits_chv = { 271 /* 272 * These are the data rate limits (measured in fast clocks) 273 * since those are the strictest limits we have. The fast 274 * clock and actual rate limits are more relaxed, so checking 275 * them would make no difference. 276 */ 277 .dot = { .min = 25000 * 5, .max = 540000 * 5}, 278 .vco = { .min = 4800000, .max = 6480000 }, 279 .n = { .min = 1, .max = 1 }, 280 .m1 = { .min = 2, .max = 2 }, 281 .m2 = { .min = 24 << 22, .max = 175 << 22 }, 282 .p1 = { .min = 2, .max = 4 }, 283 .p2 = { .p2_slow = 1, .p2_fast = 14 }, 284 }; 285 286 static const struct intel_limit intel_limits_bxt = { 287 /* FIXME: find real dot limits */ 288 .dot = { .min = 0, .max = INT_MAX }, 289 .vco = { .min = 4800000, .max = 6700000 }, 290 .n = { .min = 1, .max = 1 }, 291 .m1 = { .min = 2, .max = 2 }, 292 /* FIXME: find real m2 limits */ 293 .m2 = { .min = 2 << 22, .max = 255 << 22 }, 294 .p1 = { .min = 2, .max = 4 }, 295 .p2 = { .p2_slow = 1, .p2_fast = 20 }, 296 }; 297 298 /* 299 * Platform specific helpers to calculate the port PLL loopback- (clock.m), 300 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast 301 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. 302 * The helpers' return value is the rate of the clock that is fed to the 303 * display engine's pipe which can be the above fast dot clock rate or a 304 * divided-down version of it. 305 */ 306 /* m1 is reserved as 0 in Pineview, n is a ring counter */ 307 int pnv_calc_dpll_params(int refclk, struct dpll *clock) 308 { 309 clock->m = clock->m2 + 2; 310 clock->p = clock->p1 * clock->p2; 311 if (WARN_ON(clock->n == 0 || clock->p == 0)) 312 return 0; 313 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 314 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 315 316 return clock->dot; 317 } 318 319 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) 320 { 321 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); 322 } 323 324 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) 325 { 326 clock->m = i9xx_dpll_compute_m(clock); 327 clock->p = clock->p1 * clock->p2; 328 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) 329 return 0; 330 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); 331 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 332 333 return clock->dot; 334 } 335 336 int vlv_calc_dpll_params(int refclk, struct dpll *clock) 337 { 338 clock->m = clock->m1 * clock->m2; 339 clock->p = clock->p1 * clock->p2; 340 if (WARN_ON(clock->n == 0 || clock->p == 0)) 341 return 0; 342 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 343 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 344 345 return clock->dot / 5; 346 } 347 348 int chv_calc_dpll_params(int refclk, struct dpll *clock) 349 { 350 clock->m = clock->m1 * clock->m2; 351 clock->p = clock->p1 * clock->p2; 352 if (WARN_ON(clock->n == 0 || clock->p == 0)) 353 return 0; 354 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), 355 clock->n << 22); 356 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 357 358 return clock->dot / 5; 359 } 360 361 /* 362 * Returns whether the given set of divisors are valid for a given refclk with 363 * the given connectors. 364 */ 365 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv, 366 const struct intel_limit *limit, 367 const struct dpll *clock) 368 { 369 if (clock->n < limit->n.min || limit->n.max < clock->n) 370 return false; 371 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 372 return false; 373 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 374 return false; 375 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 376 return false; 377 378 if (!IS_PINEVIEW(dev_priv) && !IS_LP(dev_priv)) 379 if (clock->m1 <= clock->m2) 380 return false; 381 382 if (!IS_LP(dev_priv)) { 383 if (clock->p < limit->p.min || limit->p.max < clock->p) 384 return false; 385 if (clock->m < limit->m.min || limit->m.max < clock->m) 386 return false; 387 } 388 389 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 390 return false; 391 /* XXX: We may need to be checking "Dot clock" depending on the multiplier, 392 * connector, etc., rather than just a single range. 393 */ 394 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 395 return false; 396 397 return true; 398 } 399 400 static int 401 i9xx_select_p2_div(const struct intel_limit *limit, 402 const struct intel_crtc_state *crtc_state, 403 int target) 404 { 405 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 406 407 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 408 /* 409 * For LVDS just rely on its current settings for dual-channel. 410 * We haven't figured out how to reliably set up different 411 * single/dual channel state, if we even can. 412 */ 413 if (intel_is_dual_link_lvds(dev_priv)) 414 return limit->p2.p2_fast; 415 else 416 return limit->p2.p2_slow; 417 } else { 418 if (target < limit->p2.dot_limit) 419 return limit->p2.p2_slow; 420 else 421 return limit->p2.p2_fast; 422 } 423 } 424 425 /* 426 * Returns a set of divisors for the desired target clock with the given 427 * refclk, or FALSE. The returned values represent the clock equation: 428 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 429 * 430 * Target and reference clocks are specified in kHz. 431 * 432 * If match_clock is provided, then best_clock P divider must match the P 433 * divider from @match_clock used for LVDS downclocking. 434 */ 435 static bool 436 i9xx_find_best_dpll(const struct intel_limit *limit, 437 struct intel_crtc_state *crtc_state, 438 int target, int refclk, 439 const struct dpll *match_clock, 440 struct dpll *best_clock) 441 { 442 struct drm_device *dev = crtc_state->uapi.crtc->dev; 443 struct dpll clock; 444 int err = target; 445 446 memset(best_clock, 0, sizeof(*best_clock)); 447 448 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 449 450 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 451 clock.m1++) { 452 for (clock.m2 = limit->m2.min; 453 clock.m2 <= limit->m2.max; clock.m2++) { 454 if (clock.m2 >= clock.m1) 455 break; 456 for (clock.n = limit->n.min; 457 clock.n <= limit->n.max; clock.n++) { 458 for (clock.p1 = limit->p1.min; 459 clock.p1 <= limit->p1.max; clock.p1++) { 460 int this_err; 461 462 i9xx_calc_dpll_params(refclk, &clock); 463 if (!intel_pll_is_valid(to_i915(dev), 464 limit, 465 &clock)) 466 continue; 467 if (match_clock && 468 clock.p != match_clock->p) 469 continue; 470 471 this_err = abs(clock.dot - target); 472 if (this_err < err) { 473 *best_clock = clock; 474 err = this_err; 475 } 476 } 477 } 478 } 479 } 480 481 return (err != target); 482 } 483 484 /* 485 * Returns a set of divisors for the desired target clock with the given 486 * refclk, or FALSE. The returned values represent the clock equation: 487 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 488 * 489 * Target and reference clocks are specified in kHz. 490 * 491 * If match_clock is provided, then best_clock P divider must match the P 492 * divider from @match_clock used for LVDS downclocking. 493 */ 494 static bool 495 pnv_find_best_dpll(const struct intel_limit *limit, 496 struct intel_crtc_state *crtc_state, 497 int target, int refclk, 498 const struct dpll *match_clock, 499 struct dpll *best_clock) 500 { 501 struct drm_device *dev = crtc_state->uapi.crtc->dev; 502 struct dpll clock; 503 int err = target; 504 505 memset(best_clock, 0, sizeof(*best_clock)); 506 507 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 508 509 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 510 clock.m1++) { 511 for (clock.m2 = limit->m2.min; 512 clock.m2 <= limit->m2.max; clock.m2++) { 513 for (clock.n = limit->n.min; 514 clock.n <= limit->n.max; clock.n++) { 515 for (clock.p1 = limit->p1.min; 516 clock.p1 <= limit->p1.max; clock.p1++) { 517 int this_err; 518 519 pnv_calc_dpll_params(refclk, &clock); 520 if (!intel_pll_is_valid(to_i915(dev), 521 limit, 522 &clock)) 523 continue; 524 if (match_clock && 525 clock.p != match_clock->p) 526 continue; 527 528 this_err = abs(clock.dot - target); 529 if (this_err < err) { 530 *best_clock = clock; 531 err = this_err; 532 } 533 } 534 } 535 } 536 } 537 538 return (err != target); 539 } 540 541 /* 542 * Returns a set of divisors for the desired target clock with the given 543 * refclk, or FALSE. The returned values represent the clock equation: 544 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 545 * 546 * Target and reference clocks are specified in kHz. 547 * 548 * If match_clock is provided, then best_clock P divider must match the P 549 * divider from @match_clock used for LVDS downclocking. 550 */ 551 static bool 552 g4x_find_best_dpll(const struct intel_limit *limit, 553 struct intel_crtc_state *crtc_state, 554 int target, int refclk, 555 const struct dpll *match_clock, 556 struct dpll *best_clock) 557 { 558 struct drm_device *dev = crtc_state->uapi.crtc->dev; 559 struct dpll clock; 560 int max_n; 561 bool found = false; 562 /* approximately equals target * 0.00585 */ 563 int err_most = (target >> 8) + (target >> 9); 564 565 memset(best_clock, 0, sizeof(*best_clock)); 566 567 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 568 569 max_n = limit->n.max; 570 /* based on hardware requirement, prefer smaller n to precision */ 571 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 572 /* based on hardware requirement, prefere larger m1,m2 */ 573 for (clock.m1 = limit->m1.max; 574 clock.m1 >= limit->m1.min; clock.m1--) { 575 for (clock.m2 = limit->m2.max; 576 clock.m2 >= limit->m2.min; clock.m2--) { 577 for (clock.p1 = limit->p1.max; 578 clock.p1 >= limit->p1.min; clock.p1--) { 579 int this_err; 580 581 i9xx_calc_dpll_params(refclk, &clock); 582 if (!intel_pll_is_valid(to_i915(dev), 583 limit, 584 &clock)) 585 continue; 586 587 this_err = abs(clock.dot - target); 588 if (this_err < err_most) { 589 *best_clock = clock; 590 err_most = this_err; 591 max_n = clock.n; 592 found = true; 593 } 594 } 595 } 596 } 597 } 598 return found; 599 } 600 601 /* 602 * Check if the calculated PLL configuration is more optimal compared to the 603 * best configuration and error found so far. Return the calculated error. 604 */ 605 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, 606 const struct dpll *calculated_clock, 607 const struct dpll *best_clock, 608 unsigned int best_error_ppm, 609 unsigned int *error_ppm) 610 { 611 /* 612 * For CHV ignore the error and consider only the P value. 613 * Prefer a bigger P value based on HW requirements. 614 */ 615 if (IS_CHERRYVIEW(to_i915(dev))) { 616 *error_ppm = 0; 617 618 return calculated_clock->p > best_clock->p; 619 } 620 621 if (drm_WARN_ON_ONCE(dev, !target_freq)) 622 return false; 623 624 *error_ppm = div_u64(1000000ULL * 625 abs(target_freq - calculated_clock->dot), 626 target_freq); 627 /* 628 * Prefer a better P value over a better (smaller) error if the error 629 * is small. Ensure this preference for future configurations too by 630 * setting the error to 0. 631 */ 632 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { 633 *error_ppm = 0; 634 635 return true; 636 } 637 638 return *error_ppm + 10 < best_error_ppm; 639 } 640 641 /* 642 * Returns a set of divisors for the desired target clock with the given 643 * refclk, or FALSE. The returned values represent the clock equation: 644 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 645 */ 646 static bool 647 vlv_find_best_dpll(const struct intel_limit *limit, 648 struct intel_crtc_state *crtc_state, 649 int target, int refclk, 650 const struct dpll *match_clock, 651 struct dpll *best_clock) 652 { 653 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 654 struct drm_device *dev = crtc->base.dev; 655 struct dpll clock; 656 unsigned int bestppm = 1000000; 657 /* min update 19.2 MHz */ 658 int max_n = min(limit->n.max, refclk / 19200); 659 bool found = false; 660 661 target *= 5; /* fast clock */ 662 663 memset(best_clock, 0, sizeof(*best_clock)); 664 665 /* based on hardware requirement, prefer smaller n to precision */ 666 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 667 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 668 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; 669 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 670 clock.p = clock.p1 * clock.p2; 671 /* based on hardware requirement, prefer bigger m1,m2 values */ 672 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { 673 unsigned int ppm; 674 675 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, 676 refclk * clock.m1); 677 678 vlv_calc_dpll_params(refclk, &clock); 679 680 if (!intel_pll_is_valid(to_i915(dev), 681 limit, 682 &clock)) 683 continue; 684 685 if (!vlv_PLL_is_optimal(dev, target, 686 &clock, 687 best_clock, 688 bestppm, &ppm)) 689 continue; 690 691 *best_clock = clock; 692 bestppm = ppm; 693 found = true; 694 } 695 } 696 } 697 } 698 699 return found; 700 } 701 702 /* 703 * Returns a set of divisors for the desired target clock with the given 704 * refclk, or FALSE. The returned values represent the clock equation: 705 * reflck * (5 * (m1 + 2) + (m2 + 2)) / (n + 2) / p1 / p2. 706 */ 707 static bool 708 chv_find_best_dpll(const struct intel_limit *limit, 709 struct intel_crtc_state *crtc_state, 710 int target, int refclk, 711 const struct dpll *match_clock, 712 struct dpll *best_clock) 713 { 714 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 715 struct drm_device *dev = crtc->base.dev; 716 unsigned int best_error_ppm; 717 struct dpll clock; 718 u64 m2; 719 int found = false; 720 721 memset(best_clock, 0, sizeof(*best_clock)); 722 best_error_ppm = 1000000; 723 724 /* 725 * Based on hardware doc, the n always set to 1, and m1 always 726 * set to 2. If requires to support 200Mhz refclk, we need to 727 * revisit this because n may not 1 anymore. 728 */ 729 clock.n = 1; 730 clock.m1 = 2; 731 target *= 5; /* fast clock */ 732 733 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 734 for (clock.p2 = limit->p2.p2_fast; 735 clock.p2 >= limit->p2.p2_slow; 736 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 737 unsigned int error_ppm; 738 739 clock.p = clock.p1 * clock.p2; 740 741 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22, 742 refclk * clock.m1); 743 744 if (m2 > INT_MAX/clock.m1) 745 continue; 746 747 clock.m2 = m2; 748 749 chv_calc_dpll_params(refclk, &clock); 750 751 if (!intel_pll_is_valid(to_i915(dev), limit, &clock)) 752 continue; 753 754 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, 755 best_error_ppm, &error_ppm)) 756 continue; 757 758 *best_clock = clock; 759 best_error_ppm = error_ppm; 760 found = true; 761 } 762 } 763 764 return found; 765 } 766 767 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, 768 struct dpll *best_clock) 769 { 770 int refclk = 100000; 771 const struct intel_limit *limit = &intel_limits_bxt; 772 773 return chv_find_best_dpll(limit, crtc_state, 774 crtc_state->port_clock, refclk, 775 NULL, best_clock); 776 } 777 778 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) 779 { 780 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; 781 } 782 783 static u32 pnv_dpll_compute_fp(const struct dpll *dpll) 784 { 785 return (1 << dpll->n) << 16 | dpll->m2; 786 } 787 788 static void i9xx_update_pll_dividers(struct intel_crtc_state *crtc_state, 789 const struct dpll *clock, 790 const struct dpll *reduced_clock) 791 { 792 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 793 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 794 u32 fp, fp2; 795 796 if (IS_PINEVIEW(dev_priv)) { 797 fp = pnv_dpll_compute_fp(clock); 798 fp2 = pnv_dpll_compute_fp(reduced_clock); 799 } else { 800 fp = i9xx_dpll_compute_fp(clock); 801 fp2 = i9xx_dpll_compute_fp(reduced_clock); 802 } 803 804 crtc_state->dpll_hw_state.fp0 = fp; 805 crtc_state->dpll_hw_state.fp1 = fp2; 806 } 807 808 static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, 809 const struct dpll *clock, 810 const struct dpll *reduced_clock) 811 { 812 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 813 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 814 u32 dpll; 815 816 i9xx_update_pll_dividers(crtc_state, clock, reduced_clock); 817 818 dpll = DPLL_VGA_MODE_DIS; 819 820 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) 821 dpll |= DPLLB_MODE_LVDS; 822 else 823 dpll |= DPLLB_MODE_DAC_SERIAL; 824 825 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 826 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 827 dpll |= (crtc_state->pixel_multiplier - 1) 828 << SDVO_MULTIPLIER_SHIFT_HIRES; 829 } 830 831 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || 832 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 833 dpll |= DPLL_SDVO_HIGH_SPEED; 834 835 if (intel_crtc_has_dp_encoder(crtc_state)) 836 dpll |= DPLL_SDVO_HIGH_SPEED; 837 838 /* compute bitmask from p1 value */ 839 if (IS_G4X(dev_priv)) { 840 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 841 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 842 } else if (IS_PINEVIEW(dev_priv)) { 843 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; 844 WARN_ON(reduced_clock->p1 != clock->p1); 845 } else { 846 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 847 WARN_ON(reduced_clock->p1 != clock->p1); 848 } 849 850 switch (clock->p2) { 851 case 5: 852 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 853 break; 854 case 7: 855 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 856 break; 857 case 10: 858 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 859 break; 860 case 14: 861 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 862 break; 863 } 864 WARN_ON(reduced_clock->p2 != clock->p2); 865 866 if (DISPLAY_VER(dev_priv) >= 4) 867 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 868 869 if (crtc_state->sdvo_tv_clock) 870 dpll |= PLL_REF_INPUT_TVCLKINBC; 871 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 872 intel_panel_use_ssc(dev_priv)) 873 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 874 else 875 dpll |= PLL_REF_INPUT_DREFCLK; 876 877 dpll |= DPLL_VCO_ENABLE; 878 crtc_state->dpll_hw_state.dpll = dpll; 879 880 if (DISPLAY_VER(dev_priv) >= 4) { 881 u32 dpll_md = (crtc_state->pixel_multiplier - 1) 882 << DPLL_MD_UDI_MULTIPLIER_SHIFT; 883 crtc_state->dpll_hw_state.dpll_md = dpll_md; 884 } 885 } 886 887 static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state, 888 const struct dpll *clock, 889 const struct dpll *reduced_clock) 890 { 891 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 892 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 893 u32 dpll; 894 895 i9xx_update_pll_dividers(crtc_state, clock, reduced_clock); 896 897 dpll = DPLL_VGA_MODE_DIS; 898 899 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 900 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 901 } else { 902 if (clock->p1 == 2) 903 dpll |= PLL_P1_DIVIDE_BY_TWO; 904 else 905 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; 906 if (clock->p2 == 4) 907 dpll |= PLL_P2_DIVIDE_BY_4; 908 } 909 WARN_ON(reduced_clock->p1 != clock->p1); 910 WARN_ON(reduced_clock->p2 != clock->p2); 911 912 /* 913 * Bspec: 914 * "[Almador Errata}: For the correct operation of the muxed DVO pins 915 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, 916 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock 917 * Enable) must be set to “1” in both the DPLL A Control Register 918 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." 919 * 920 * For simplicity We simply keep both bits always enabled in 921 * both DPLLS. The spec says we should disable the DVO 2X clock 922 * when not needed, but this seems to work fine in practice. 923 */ 924 if (IS_I830(dev_priv) || 925 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) 926 dpll |= DPLL_DVO_2X_MODE; 927 928 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 929 intel_panel_use_ssc(dev_priv)) 930 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 931 else 932 dpll |= PLL_REF_INPUT_DREFCLK; 933 934 dpll |= DPLL_VCO_ENABLE; 935 crtc_state->dpll_hw_state.dpll = dpll; 936 } 937 938 static int hsw_crtc_compute_clock(struct intel_crtc_state *crtc_state) 939 { 940 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 941 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 942 struct intel_atomic_state *state = 943 to_intel_atomic_state(crtc_state->uapi.state); 944 struct intel_encoder *encoder = 945 intel_get_crtc_new_encoder(state, crtc_state); 946 947 if (IS_DG2(dev_priv)) 948 return intel_mpllb_calc_state(crtc_state, encoder); 949 950 if (DISPLAY_VER(dev_priv) < 11 && 951 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 952 return 0; 953 954 if (!intel_reserve_shared_dplls(state, crtc, encoder)) { 955 drm_dbg_kms(&dev_priv->drm, 956 "failed to find PLL for pipe %c\n", 957 pipe_name(crtc->pipe)); 958 return -EINVAL; 959 } 960 961 return 0; 962 } 963 964 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) 965 { 966 return dpll->m < factor * dpll->n; 967 } 968 969 static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state, 970 const struct dpll *clock, 971 const struct dpll *reduced_clock) 972 { 973 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 974 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 975 u32 fp, fp2; 976 int factor; 977 978 /* Enable autotuning of the PLL clock (if permissible) */ 979 factor = 21; 980 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 981 if ((intel_panel_use_ssc(dev_priv) && 982 dev_priv->vbt.lvds_ssc_freq == 100000) || 983 (HAS_PCH_IBX(dev_priv) && 984 intel_is_dual_link_lvds(dev_priv))) 985 factor = 25; 986 } else if (crtc_state->sdvo_tv_clock) { 987 factor = 20; 988 } 989 990 fp = i9xx_dpll_compute_fp(clock); 991 if (ilk_needs_fb_cb_tune(clock, factor)) 992 fp |= FP_CB_TUNE; 993 994 fp2 = i9xx_dpll_compute_fp(reduced_clock); 995 if (ilk_needs_fb_cb_tune(reduced_clock, factor)) 996 fp2 |= FP_CB_TUNE; 997 998 crtc_state->dpll_hw_state.fp0 = fp; 999 crtc_state->dpll_hw_state.fp1 = fp2; 1000 } 1001 1002 static void ilk_compute_dpll(struct intel_crtc_state *crtc_state, 1003 const struct dpll *clock, 1004 const struct dpll *reduced_clock) 1005 { 1006 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1007 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1008 u32 dpll; 1009 1010 ilk_update_pll_dividers(crtc_state, clock, reduced_clock); 1011 1012 dpll = 0; 1013 1014 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) 1015 dpll |= DPLLB_MODE_LVDS; 1016 else 1017 dpll |= DPLLB_MODE_DAC_SERIAL; 1018 1019 dpll |= (crtc_state->pixel_multiplier - 1) 1020 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 1021 1022 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || 1023 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1024 dpll |= DPLL_SDVO_HIGH_SPEED; 1025 1026 if (intel_crtc_has_dp_encoder(crtc_state)) 1027 dpll |= DPLL_SDVO_HIGH_SPEED; 1028 1029 /* 1030 * The high speed IO clock is only really required for 1031 * SDVO/HDMI/DP, but we also enable it for CRT to make it 1032 * possible to share the DPLL between CRT and HDMI. Enabling 1033 * the clock needlessly does no real harm, except use up a 1034 * bit of power potentially. 1035 * 1036 * We'll limit this to IVB with 3 pipes, since it has only two 1037 * DPLLs and so DPLL sharing is the only way to get three pipes 1038 * driving PCH ports at the same time. On SNB we could do this, 1039 * and potentially avoid enabling the second DPLL, but it's not 1040 * clear if it''s a win or loss power wise. No point in doing 1041 * this on ILK at all since it has a fixed DPLL<->pipe mapping. 1042 */ 1043 if (INTEL_NUM_PIPES(dev_priv) == 3 && 1044 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1045 dpll |= DPLL_SDVO_HIGH_SPEED; 1046 1047 /* compute bitmask from p1 value */ 1048 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 1049 /* also FPA1 */ 1050 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 1051 1052 switch (clock->p2) { 1053 case 5: 1054 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 1055 break; 1056 case 7: 1057 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 1058 break; 1059 case 10: 1060 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 1061 break; 1062 case 14: 1063 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 1064 break; 1065 } 1066 WARN_ON(reduced_clock->p2 != clock->p2); 1067 1068 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 1069 intel_panel_use_ssc(dev_priv)) 1070 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 1071 else 1072 dpll |= PLL_REF_INPUT_DREFCLK; 1073 1074 dpll |= DPLL_VCO_ENABLE; 1075 1076 crtc_state->dpll_hw_state.dpll = dpll; 1077 } 1078 1079 static int ilk_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1080 { 1081 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1082 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1083 struct intel_atomic_state *state = 1084 to_intel_atomic_state(crtc_state->uapi.state); 1085 const struct intel_limit *limit; 1086 int refclk = 120000; 1087 1088 memset(&crtc_state->dpll_hw_state, 0, 1089 sizeof(crtc_state->dpll_hw_state)); 1090 1091 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 1092 if (!crtc_state->has_pch_encoder) 1093 return 0; 1094 1095 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1096 if (intel_panel_use_ssc(dev_priv)) { 1097 drm_dbg_kms(&dev_priv->drm, 1098 "using SSC reference clock of %d kHz\n", 1099 dev_priv->vbt.lvds_ssc_freq); 1100 refclk = dev_priv->vbt.lvds_ssc_freq; 1101 } 1102 1103 if (intel_is_dual_link_lvds(dev_priv)) { 1104 if (refclk == 100000) 1105 limit = &ilk_limits_dual_lvds_100m; 1106 else 1107 limit = &ilk_limits_dual_lvds; 1108 } else { 1109 if (refclk == 100000) 1110 limit = &ilk_limits_single_lvds_100m; 1111 else 1112 limit = &ilk_limits_single_lvds; 1113 } 1114 } else { 1115 limit = &ilk_limits_dac; 1116 } 1117 1118 if (!crtc_state->clock_set && 1119 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1120 refclk, NULL, &crtc_state->dpll)) { 1121 drm_err(&dev_priv->drm, 1122 "Couldn't find PLL settings for mode!\n"); 1123 return -EINVAL; 1124 } 1125 1126 ilk_compute_dpll(crtc_state, &crtc_state->dpll, 1127 &crtc_state->dpll); 1128 1129 if (!intel_reserve_shared_dplls(state, crtc, NULL)) { 1130 drm_dbg_kms(&dev_priv->drm, 1131 "failed to find PLL for pipe %c\n", 1132 pipe_name(crtc->pipe)); 1133 return -EINVAL; 1134 } 1135 1136 return 0; 1137 } 1138 1139 void vlv_compute_dpll(struct intel_crtc_state *crtc_state) 1140 { 1141 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1142 1143 crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | 1144 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1145 if (crtc->pipe != PIPE_A) 1146 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 1147 1148 /* DPLL not used with DSI, but still need the rest set up */ 1149 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1150 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | 1151 DPLL_EXT_BUFFER_ENABLE_VLV; 1152 1153 crtc_state->dpll_hw_state.dpll_md = 1154 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 1155 } 1156 1157 void chv_compute_dpll(struct intel_crtc_state *crtc_state) 1158 { 1159 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1160 1161 crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | 1162 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1163 if (crtc->pipe != PIPE_A) 1164 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 1165 1166 /* DPLL not used with DSI, but still need the rest set up */ 1167 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1168 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; 1169 1170 crtc_state->dpll_hw_state.dpll_md = 1171 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 1172 } 1173 1174 static int chv_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1175 { 1176 int refclk = 100000; 1177 const struct intel_limit *limit = &intel_limits_chv; 1178 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1179 1180 memset(&crtc_state->dpll_hw_state, 0, 1181 sizeof(crtc_state->dpll_hw_state)); 1182 1183 if (!crtc_state->clock_set && 1184 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1185 refclk, NULL, &crtc_state->dpll)) { 1186 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); 1187 return -EINVAL; 1188 } 1189 1190 chv_compute_dpll(crtc_state); 1191 1192 return 0; 1193 } 1194 1195 static int vlv_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1196 { 1197 int refclk = 100000; 1198 const struct intel_limit *limit = &intel_limits_vlv; 1199 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1200 1201 memset(&crtc_state->dpll_hw_state, 0, 1202 sizeof(crtc_state->dpll_hw_state)); 1203 1204 if (!crtc_state->clock_set && 1205 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1206 refclk, NULL, &crtc_state->dpll)) { 1207 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); 1208 return -EINVAL; 1209 } 1210 1211 vlv_compute_dpll(crtc_state); 1212 1213 return 0; 1214 } 1215 1216 static int g4x_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1217 { 1218 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1219 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1220 const struct intel_limit *limit; 1221 int refclk = 96000; 1222 1223 memset(&crtc_state->dpll_hw_state, 0, 1224 sizeof(crtc_state->dpll_hw_state)); 1225 1226 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1227 if (intel_panel_use_ssc(dev_priv)) { 1228 refclk = dev_priv->vbt.lvds_ssc_freq; 1229 drm_dbg_kms(&dev_priv->drm, 1230 "using SSC reference clock of %d kHz\n", 1231 refclk); 1232 } 1233 1234 if (intel_is_dual_link_lvds(dev_priv)) 1235 limit = &intel_limits_g4x_dual_channel_lvds; 1236 else 1237 limit = &intel_limits_g4x_single_channel_lvds; 1238 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || 1239 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1240 limit = &intel_limits_g4x_hdmi; 1241 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { 1242 limit = &intel_limits_g4x_sdvo; 1243 } else { 1244 /* The option is for other outputs */ 1245 limit = &intel_limits_i9xx_sdvo; 1246 } 1247 1248 if (!crtc_state->clock_set && 1249 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1250 refclk, NULL, &crtc_state->dpll)) { 1251 drm_err(&dev_priv->drm, 1252 "Couldn't find PLL settings for mode!\n"); 1253 return -EINVAL; 1254 } 1255 1256 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, 1257 &crtc_state->dpll); 1258 1259 return 0; 1260 } 1261 1262 static int pnv_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1263 { 1264 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1265 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1266 const struct intel_limit *limit; 1267 int refclk = 96000; 1268 1269 memset(&crtc_state->dpll_hw_state, 0, 1270 sizeof(crtc_state->dpll_hw_state)); 1271 1272 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1273 if (intel_panel_use_ssc(dev_priv)) { 1274 refclk = dev_priv->vbt.lvds_ssc_freq; 1275 drm_dbg_kms(&dev_priv->drm, 1276 "using SSC reference clock of %d kHz\n", 1277 refclk); 1278 } 1279 1280 limit = &pnv_limits_lvds; 1281 } else { 1282 limit = &pnv_limits_sdvo; 1283 } 1284 1285 if (!crtc_state->clock_set && 1286 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1287 refclk, NULL, &crtc_state->dpll)) { 1288 drm_err(&dev_priv->drm, 1289 "Couldn't find PLL settings for mode!\n"); 1290 return -EINVAL; 1291 } 1292 1293 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, 1294 &crtc_state->dpll); 1295 1296 return 0; 1297 } 1298 1299 static int i9xx_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1300 { 1301 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1302 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1303 const struct intel_limit *limit; 1304 int refclk = 96000; 1305 1306 memset(&crtc_state->dpll_hw_state, 0, 1307 sizeof(crtc_state->dpll_hw_state)); 1308 1309 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1310 if (intel_panel_use_ssc(dev_priv)) { 1311 refclk = dev_priv->vbt.lvds_ssc_freq; 1312 drm_dbg_kms(&dev_priv->drm, 1313 "using SSC reference clock of %d kHz\n", 1314 refclk); 1315 } 1316 1317 limit = &intel_limits_i9xx_lvds; 1318 } else { 1319 limit = &intel_limits_i9xx_sdvo; 1320 } 1321 1322 if (!crtc_state->clock_set && 1323 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1324 refclk, NULL, &crtc_state->dpll)) { 1325 drm_err(&dev_priv->drm, 1326 "Couldn't find PLL settings for mode!\n"); 1327 return -EINVAL; 1328 } 1329 1330 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, 1331 &crtc_state->dpll); 1332 1333 return 0; 1334 } 1335 1336 static int i8xx_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1337 { 1338 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1339 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1340 const struct intel_limit *limit; 1341 int refclk = 48000; 1342 1343 memset(&crtc_state->dpll_hw_state, 0, 1344 sizeof(crtc_state->dpll_hw_state)); 1345 1346 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1347 if (intel_panel_use_ssc(dev_priv)) { 1348 refclk = dev_priv->vbt.lvds_ssc_freq; 1349 drm_dbg_kms(&dev_priv->drm, 1350 "using SSC reference clock of %d kHz\n", 1351 refclk); 1352 } 1353 1354 limit = &intel_limits_i8xx_lvds; 1355 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { 1356 limit = &intel_limits_i8xx_dvo; 1357 } else { 1358 limit = &intel_limits_i8xx_dac; 1359 } 1360 1361 if (!crtc_state->clock_set && 1362 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1363 refclk, NULL, &crtc_state->dpll)) { 1364 drm_err(&dev_priv->drm, 1365 "Couldn't find PLL settings for mode!\n"); 1366 return -EINVAL; 1367 } 1368 1369 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, 1370 &crtc_state->dpll); 1371 1372 return 0; 1373 } 1374 1375 static const struct intel_dpll_funcs hsw_dpll_funcs = { 1376 .crtc_compute_clock = hsw_crtc_compute_clock, 1377 }; 1378 1379 static const struct intel_dpll_funcs ilk_dpll_funcs = { 1380 .crtc_compute_clock = ilk_crtc_compute_clock, 1381 }; 1382 1383 static const struct intel_dpll_funcs chv_dpll_funcs = { 1384 .crtc_compute_clock = chv_crtc_compute_clock, 1385 }; 1386 1387 static const struct intel_dpll_funcs vlv_dpll_funcs = { 1388 .crtc_compute_clock = vlv_crtc_compute_clock, 1389 }; 1390 1391 static const struct intel_dpll_funcs g4x_dpll_funcs = { 1392 .crtc_compute_clock = g4x_crtc_compute_clock, 1393 }; 1394 1395 static const struct intel_dpll_funcs pnv_dpll_funcs = { 1396 .crtc_compute_clock = pnv_crtc_compute_clock, 1397 }; 1398 1399 static const struct intel_dpll_funcs i9xx_dpll_funcs = { 1400 .crtc_compute_clock = i9xx_crtc_compute_clock, 1401 }; 1402 1403 static const struct intel_dpll_funcs i8xx_dpll_funcs = { 1404 .crtc_compute_clock = i8xx_crtc_compute_clock, 1405 }; 1406 1407 int intel_dpll_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1408 { 1409 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1410 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1411 1412 return i915->dpll_funcs->crtc_compute_clock(crtc_state); 1413 } 1414 1415 void 1416 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv) 1417 { 1418 if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv)) 1419 dev_priv->dpll_funcs = &hsw_dpll_funcs; 1420 else if (HAS_PCH_SPLIT(dev_priv)) 1421 dev_priv->dpll_funcs = &ilk_dpll_funcs; 1422 else if (IS_CHERRYVIEW(dev_priv)) 1423 dev_priv->dpll_funcs = &chv_dpll_funcs; 1424 else if (IS_VALLEYVIEW(dev_priv)) 1425 dev_priv->dpll_funcs = &vlv_dpll_funcs; 1426 else if (IS_G4X(dev_priv)) 1427 dev_priv->dpll_funcs = &g4x_dpll_funcs; 1428 else if (IS_PINEVIEW(dev_priv)) 1429 dev_priv->dpll_funcs = &pnv_dpll_funcs; 1430 else if (DISPLAY_VER(dev_priv) != 2) 1431 dev_priv->dpll_funcs = &i9xx_dpll_funcs; 1432 else 1433 dev_priv->dpll_funcs = &i8xx_dpll_funcs; 1434 } 1435 1436 static bool i9xx_has_pps(struct drm_i915_private *dev_priv) 1437 { 1438 if (IS_I830(dev_priv)) 1439 return false; 1440 1441 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 1442 } 1443 1444 void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) 1445 { 1446 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1447 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1448 u32 dpll = crtc_state->dpll_hw_state.dpll; 1449 enum pipe pipe = crtc->pipe; 1450 int i; 1451 1452 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1453 1454 /* PLL is protected by panel, make sure we can write it */ 1455 if (i9xx_has_pps(dev_priv)) 1456 assert_pps_unlocked(dev_priv, pipe); 1457 1458 intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0); 1459 intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1); 1460 1461 /* 1462 * Apparently we need to have VGA mode enabled prior to changing 1463 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 1464 * dividers, even though the register value does change. 1465 */ 1466 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 1467 intel_de_write(dev_priv, DPLL(pipe), dpll); 1468 1469 /* Wait for the clocks to stabilize. */ 1470 intel_de_posting_read(dev_priv, DPLL(pipe)); 1471 udelay(150); 1472 1473 if (DISPLAY_VER(dev_priv) >= 4) { 1474 intel_de_write(dev_priv, DPLL_MD(pipe), 1475 crtc_state->dpll_hw_state.dpll_md); 1476 } else { 1477 /* The pixel multiplier can only be updated once the 1478 * DPLL is enabled and the clocks are stable. 1479 * 1480 * So write it again. 1481 */ 1482 intel_de_write(dev_priv, DPLL(pipe), dpll); 1483 } 1484 1485 /* We do this three times for luck */ 1486 for (i = 0; i < 3; i++) { 1487 intel_de_write(dev_priv, DPLL(pipe), dpll); 1488 intel_de_posting_read(dev_priv, DPLL(pipe)); 1489 udelay(150); /* wait for warmup */ 1490 } 1491 } 1492 1493 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, 1494 enum pipe pipe) 1495 { 1496 u32 reg_val; 1497 1498 /* 1499 * PLLB opamp always calibrates to max value of 0x3f, force enable it 1500 * and set it to a reasonable value instead. 1501 */ 1502 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); 1503 reg_val &= 0xffffff00; 1504 reg_val |= 0x00000030; 1505 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); 1506 1507 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); 1508 reg_val &= 0x00ffffff; 1509 reg_val |= 0x8c000000; 1510 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 1511 1512 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); 1513 reg_val &= 0xffffff00; 1514 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); 1515 1516 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); 1517 reg_val &= 0x00ffffff; 1518 reg_val |= 0xb0000000; 1519 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 1520 } 1521 1522 static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) 1523 { 1524 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1525 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1526 enum pipe pipe = crtc->pipe; 1527 u32 mdiv; 1528 u32 bestn, bestm1, bestm2, bestp1, bestp2; 1529 u32 coreclk, reg_val; 1530 1531 vlv_dpio_get(dev_priv); 1532 1533 bestn = crtc_state->dpll.n; 1534 bestm1 = crtc_state->dpll.m1; 1535 bestm2 = crtc_state->dpll.m2; 1536 bestp1 = crtc_state->dpll.p1; 1537 bestp2 = crtc_state->dpll.p2; 1538 1539 /* See eDP HDMI DPIO driver vbios notes doc */ 1540 1541 /* PLL B needs special handling */ 1542 if (pipe == PIPE_B) 1543 vlv_pllb_recal_opamp(dev_priv, pipe); 1544 1545 /* Set up Tx target for periodic Rcomp update */ 1546 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); 1547 1548 /* Disable target IRef on PLL */ 1549 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); 1550 reg_val &= 0x00ffffff; 1551 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); 1552 1553 /* Disable fast lock */ 1554 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); 1555 1556 /* Set idtafcrecal before PLL is enabled */ 1557 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); 1558 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); 1559 mdiv |= ((bestn << DPIO_N_SHIFT)); 1560 mdiv |= (1 << DPIO_K_SHIFT); 1561 1562 /* 1563 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, 1564 * but we don't support that). 1565 * Note: don't use the DAC post divider as it seems unstable. 1566 */ 1567 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); 1568 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); 1569 1570 mdiv |= DPIO_ENABLE_CALIBRATION; 1571 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); 1572 1573 /* Set HBR and RBR LPF coefficients */ 1574 if (crtc_state->port_clock == 162000 || 1575 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) || 1576 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1577 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 1578 0x009f0003); 1579 else 1580 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 1581 0x00d0000f); 1582 1583 if (intel_crtc_has_dp_encoder(crtc_state)) { 1584 /* Use SSC source */ 1585 if (pipe == PIPE_A) 1586 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1587 0x0df40000); 1588 else 1589 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1590 0x0df70000); 1591 } else { /* HDMI or VGA */ 1592 /* Use bend source */ 1593 if (pipe == PIPE_A) 1594 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1595 0x0df70000); 1596 else 1597 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1598 0x0df40000); 1599 } 1600 1601 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); 1602 coreclk = (coreclk & 0x0000ff00) | 0x01c00000; 1603 if (intel_crtc_has_dp_encoder(crtc_state)) 1604 coreclk |= 0x01000000; 1605 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); 1606 1607 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); 1608 1609 vlv_dpio_put(dev_priv); 1610 } 1611 1612 static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state) 1613 { 1614 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1615 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1616 enum pipe pipe = crtc->pipe; 1617 1618 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); 1619 intel_de_posting_read(dev_priv, DPLL(pipe)); 1620 udelay(150); 1621 1622 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) 1623 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); 1624 } 1625 1626 void vlv_enable_pll(const struct intel_crtc_state *crtc_state) 1627 { 1628 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1629 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1630 enum pipe pipe = crtc->pipe; 1631 1632 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1633 1634 /* PLL is protected by panel, make sure we can write it */ 1635 assert_pps_unlocked(dev_priv, pipe); 1636 1637 /* Enable Refclk */ 1638 intel_de_write(dev_priv, DPLL(pipe), 1639 crtc_state->dpll_hw_state.dpll & 1640 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); 1641 1642 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { 1643 vlv_prepare_pll(crtc_state); 1644 _vlv_enable_pll(crtc_state); 1645 } 1646 1647 intel_de_write(dev_priv, DPLL_MD(pipe), 1648 crtc_state->dpll_hw_state.dpll_md); 1649 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); 1650 } 1651 1652 static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) 1653 { 1654 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1655 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1656 enum pipe pipe = crtc->pipe; 1657 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1658 u32 loopfilter, tribuf_calcntr; 1659 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; 1660 u32 dpio_val; 1661 int vco; 1662 1663 bestn = crtc_state->dpll.n; 1664 bestm2_frac = crtc_state->dpll.m2 & 0x3fffff; 1665 bestm1 = crtc_state->dpll.m1; 1666 bestm2 = crtc_state->dpll.m2 >> 22; 1667 bestp1 = crtc_state->dpll.p1; 1668 bestp2 = crtc_state->dpll.p2; 1669 vco = crtc_state->dpll.vco; 1670 dpio_val = 0; 1671 loopfilter = 0; 1672 1673 vlv_dpio_get(dev_priv); 1674 1675 /* p1 and p2 divider */ 1676 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), 1677 5 << DPIO_CHV_S1_DIV_SHIFT | 1678 bestp1 << DPIO_CHV_P1_DIV_SHIFT | 1679 bestp2 << DPIO_CHV_P2_DIV_SHIFT | 1680 1 << DPIO_CHV_K_DIV_SHIFT); 1681 1682 /* Feedback post-divider - m2 */ 1683 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); 1684 1685 /* Feedback refclk divider - n and m1 */ 1686 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), 1687 DPIO_CHV_M1_DIV_BY_2 | 1688 1 << DPIO_CHV_N_DIV_SHIFT); 1689 1690 /* M2 fraction division */ 1691 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); 1692 1693 /* M2 fraction division enable */ 1694 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 1695 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); 1696 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); 1697 if (bestm2_frac) 1698 dpio_val |= DPIO_CHV_FRAC_DIV_EN; 1699 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); 1700 1701 /* Program digital lock detect threshold */ 1702 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); 1703 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | 1704 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); 1705 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); 1706 if (!bestm2_frac) 1707 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; 1708 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); 1709 1710 /* Loop filter */ 1711 if (vco == 5400000) { 1712 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); 1713 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); 1714 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); 1715 tribuf_calcntr = 0x9; 1716 } else if (vco <= 6200000) { 1717 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); 1718 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); 1719 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1720 tribuf_calcntr = 0x9; 1721 } else if (vco <= 6480000) { 1722 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 1723 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 1724 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1725 tribuf_calcntr = 0x8; 1726 } else { 1727 /* Not supported. Apply the same limits as in the max case */ 1728 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 1729 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 1730 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1731 tribuf_calcntr = 0; 1732 } 1733 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); 1734 1735 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); 1736 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; 1737 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); 1738 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); 1739 1740 /* AFC Recal */ 1741 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), 1742 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | 1743 DPIO_AFC_RECAL); 1744 1745 vlv_dpio_put(dev_priv); 1746 } 1747 1748 static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) 1749 { 1750 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1751 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1752 enum pipe pipe = crtc->pipe; 1753 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1754 u32 tmp; 1755 1756 vlv_dpio_get(dev_priv); 1757 1758 /* Enable back the 10bit clock to display controller */ 1759 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); 1760 tmp |= DPIO_DCLKP_EN; 1761 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); 1762 1763 vlv_dpio_put(dev_priv); 1764 1765 /* 1766 * Need to wait > 100ns between dclkp clock enable bit and PLL enable. 1767 */ 1768 udelay(1); 1769 1770 /* Enable PLL */ 1771 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); 1772 1773 /* Check PLL is locked */ 1774 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) 1775 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); 1776 } 1777 1778 void chv_enable_pll(const struct intel_crtc_state *crtc_state) 1779 { 1780 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1781 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1782 enum pipe pipe = crtc->pipe; 1783 1784 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1785 1786 /* PLL is protected by panel, make sure we can write it */ 1787 assert_pps_unlocked(dev_priv, pipe); 1788 1789 /* Enable Refclk and SSC */ 1790 intel_de_write(dev_priv, DPLL(pipe), 1791 crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); 1792 1793 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { 1794 chv_prepare_pll(crtc_state); 1795 _chv_enable_pll(crtc_state); 1796 } 1797 1798 if (pipe != PIPE_A) { 1799 /* 1800 * WaPixelRepeatModeFixForC0:chv 1801 * 1802 * DPLLCMD is AWOL. Use chicken bits to propagate 1803 * the value from DPLLBMD to either pipe B or C. 1804 */ 1805 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); 1806 intel_de_write(dev_priv, DPLL_MD(PIPE_B), 1807 crtc_state->dpll_hw_state.dpll_md); 1808 intel_de_write(dev_priv, CBR4_VLV, 0); 1809 dev_priv->chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md; 1810 1811 /* 1812 * DPLLB VGA mode also seems to cause problems. 1813 * We should always have it disabled. 1814 */ 1815 drm_WARN_ON(&dev_priv->drm, 1816 (intel_de_read(dev_priv, DPLL(PIPE_B)) & 1817 DPLL_VGA_MODE_DIS) == 0); 1818 } else { 1819 intel_de_write(dev_priv, DPLL_MD(pipe), 1820 crtc_state->dpll_hw_state.dpll_md); 1821 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); 1822 } 1823 } 1824 1825 /** 1826 * vlv_force_pll_on - forcibly enable just the PLL 1827 * @dev_priv: i915 private structure 1828 * @pipe: pipe PLL to enable 1829 * @dpll: PLL configuration 1830 * 1831 * Enable the PLL for @pipe using the supplied @dpll config. To be used 1832 * in cases where we need the PLL enabled even when @pipe is not going to 1833 * be enabled. 1834 */ 1835 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, 1836 const struct dpll *dpll) 1837 { 1838 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 1839 struct intel_crtc_state *crtc_state; 1840 1841 crtc_state = intel_crtc_state_alloc(crtc); 1842 if (!crtc_state) 1843 return -ENOMEM; 1844 1845 crtc_state->cpu_transcoder = (enum transcoder)pipe; 1846 crtc_state->pixel_multiplier = 1; 1847 crtc_state->dpll = *dpll; 1848 crtc_state->output_types = BIT(INTEL_OUTPUT_EDP); 1849 1850 if (IS_CHERRYVIEW(dev_priv)) { 1851 chv_compute_dpll(crtc_state); 1852 chv_enable_pll(crtc_state); 1853 } else { 1854 vlv_compute_dpll(crtc_state); 1855 vlv_enable_pll(crtc_state); 1856 } 1857 1858 kfree(crtc_state); 1859 1860 return 0; 1861 } 1862 1863 void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 1864 { 1865 u32 val; 1866 1867 /* Make sure the pipe isn't still relying on us */ 1868 assert_transcoder_disabled(dev_priv, (enum transcoder)pipe); 1869 1870 val = DPLL_INTEGRATED_REF_CLK_VLV | 1871 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1872 if (pipe != PIPE_A) 1873 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1874 1875 intel_de_write(dev_priv, DPLL(pipe), val); 1876 intel_de_posting_read(dev_priv, DPLL(pipe)); 1877 } 1878 1879 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 1880 { 1881 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1882 u32 val; 1883 1884 /* Make sure the pipe isn't still relying on us */ 1885 assert_transcoder_disabled(dev_priv, (enum transcoder)pipe); 1886 1887 val = DPLL_SSC_REF_CLK_CHV | 1888 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1889 if (pipe != PIPE_A) 1890 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1891 1892 intel_de_write(dev_priv, DPLL(pipe), val); 1893 intel_de_posting_read(dev_priv, DPLL(pipe)); 1894 1895 vlv_dpio_get(dev_priv); 1896 1897 /* Disable 10bit clock to display controller */ 1898 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); 1899 val &= ~DPIO_DCLKP_EN; 1900 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); 1901 1902 vlv_dpio_put(dev_priv); 1903 } 1904 1905 void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) 1906 { 1907 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1908 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1909 enum pipe pipe = crtc->pipe; 1910 1911 /* Don't disable pipe or pipe PLLs if needed */ 1912 if (IS_I830(dev_priv)) 1913 return; 1914 1915 /* Make sure the pipe isn't still relying on us */ 1916 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1917 1918 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 1919 intel_de_posting_read(dev_priv, DPLL(pipe)); 1920 } 1921 1922 1923 /** 1924 * vlv_force_pll_off - forcibly disable just the PLL 1925 * @dev_priv: i915 private structure 1926 * @pipe: pipe PLL to disable 1927 * 1928 * Disable the PLL for @pipe. To be used in cases where we need 1929 * the PLL enabled even when @pipe is not going to be enabled. 1930 */ 1931 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) 1932 { 1933 if (IS_CHERRYVIEW(dev_priv)) 1934 chv_disable_pll(dev_priv, pipe); 1935 else 1936 vlv_disable_pll(dev_priv, pipe); 1937 } 1938 1939 /* Only for pre-ILK configs */ 1940 static void assert_pll(struct drm_i915_private *dev_priv, 1941 enum pipe pipe, bool state) 1942 { 1943 bool cur_state; 1944 1945 cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; 1946 I915_STATE_WARN(cur_state != state, 1947 "PLL state assertion failure (expected %s, current %s)\n", 1948 onoff(state), onoff(cur_state)); 1949 } 1950 1951 void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe) 1952 { 1953 assert_pll(i915, pipe, true); 1954 } 1955 1956 void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe) 1957 { 1958 assert_pll(i915, pipe, false); 1959 } 1960