1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/string_helpers.h> 8 9 #include "intel_crtc.h" 10 #include "intel_de.h" 11 #include "intel_display.h" 12 #include "intel_display_types.h" 13 #include "intel_dpll.h" 14 #include "intel_lvds.h" 15 #include "intel_panel.h" 16 #include "intel_pps.h" 17 #include "intel_snps_phy.h" 18 #include "vlv_sideband.h" 19 20 struct intel_dpll_funcs { 21 int (*crtc_compute_clock)(struct intel_crtc_state *crtc_state); 22 }; 23 24 struct intel_limit { 25 struct { 26 int min, max; 27 } dot, vco, n, m, m1, m2, p, p1; 28 29 struct { 30 int dot_limit; 31 int p2_slow, p2_fast; 32 } p2; 33 }; 34 static const struct intel_limit intel_limits_i8xx_dac = { 35 .dot = { .min = 25000, .max = 350000 }, 36 .vco = { .min = 908000, .max = 1512000 }, 37 .n = { .min = 2, .max = 16 }, 38 .m = { .min = 96, .max = 140 }, 39 .m1 = { .min = 18, .max = 26 }, 40 .m2 = { .min = 6, .max = 16 }, 41 .p = { .min = 4, .max = 128 }, 42 .p1 = { .min = 2, .max = 33 }, 43 .p2 = { .dot_limit = 165000, 44 .p2_slow = 4, .p2_fast = 2 }, 45 }; 46 47 static const struct intel_limit intel_limits_i8xx_dvo = { 48 .dot = { .min = 25000, .max = 350000 }, 49 .vco = { .min = 908000, .max = 1512000 }, 50 .n = { .min = 2, .max = 16 }, 51 .m = { .min = 96, .max = 140 }, 52 .m1 = { .min = 18, .max = 26 }, 53 .m2 = { .min = 6, .max = 16 }, 54 .p = { .min = 4, .max = 128 }, 55 .p1 = { .min = 2, .max = 33 }, 56 .p2 = { .dot_limit = 165000, 57 .p2_slow = 4, .p2_fast = 4 }, 58 }; 59 60 static const struct intel_limit intel_limits_i8xx_lvds = { 61 .dot = { .min = 25000, .max = 350000 }, 62 .vco = { .min = 908000, .max = 1512000 }, 63 .n = { .min = 2, .max = 16 }, 64 .m = { .min = 96, .max = 140 }, 65 .m1 = { .min = 18, .max = 26 }, 66 .m2 = { .min = 6, .max = 16 }, 67 .p = { .min = 4, .max = 128 }, 68 .p1 = { .min = 1, .max = 6 }, 69 .p2 = { .dot_limit = 165000, 70 .p2_slow = 14, .p2_fast = 7 }, 71 }; 72 73 static const struct intel_limit intel_limits_i9xx_sdvo = { 74 .dot = { .min = 20000, .max = 400000 }, 75 .vco = { .min = 1400000, .max = 2800000 }, 76 .n = { .min = 1, .max = 6 }, 77 .m = { .min = 70, .max = 120 }, 78 .m1 = { .min = 8, .max = 18 }, 79 .m2 = { .min = 3, .max = 7 }, 80 .p = { .min = 5, .max = 80 }, 81 .p1 = { .min = 1, .max = 8 }, 82 .p2 = { .dot_limit = 200000, 83 .p2_slow = 10, .p2_fast = 5 }, 84 }; 85 86 static const struct intel_limit intel_limits_i9xx_lvds = { 87 .dot = { .min = 20000, .max = 400000 }, 88 .vco = { .min = 1400000, .max = 2800000 }, 89 .n = { .min = 1, .max = 6 }, 90 .m = { .min = 70, .max = 120 }, 91 .m1 = { .min = 8, .max = 18 }, 92 .m2 = { .min = 3, .max = 7 }, 93 .p = { .min = 7, .max = 98 }, 94 .p1 = { .min = 1, .max = 8 }, 95 .p2 = { .dot_limit = 112000, 96 .p2_slow = 14, .p2_fast = 7 }, 97 }; 98 99 100 static const struct intel_limit intel_limits_g4x_sdvo = { 101 .dot = { .min = 25000, .max = 270000 }, 102 .vco = { .min = 1750000, .max = 3500000}, 103 .n = { .min = 1, .max = 4 }, 104 .m = { .min = 104, .max = 138 }, 105 .m1 = { .min = 17, .max = 23 }, 106 .m2 = { .min = 5, .max = 11 }, 107 .p = { .min = 10, .max = 30 }, 108 .p1 = { .min = 1, .max = 3}, 109 .p2 = { .dot_limit = 270000, 110 .p2_slow = 10, 111 .p2_fast = 10 112 }, 113 }; 114 115 static const struct intel_limit intel_limits_g4x_hdmi = { 116 .dot = { .min = 22000, .max = 400000 }, 117 .vco = { .min = 1750000, .max = 3500000}, 118 .n = { .min = 1, .max = 4 }, 119 .m = { .min = 104, .max = 138 }, 120 .m1 = { .min = 16, .max = 23 }, 121 .m2 = { .min = 5, .max = 11 }, 122 .p = { .min = 5, .max = 80 }, 123 .p1 = { .min = 1, .max = 8}, 124 .p2 = { .dot_limit = 165000, 125 .p2_slow = 10, .p2_fast = 5 }, 126 }; 127 128 static const struct intel_limit intel_limits_g4x_single_channel_lvds = { 129 .dot = { .min = 20000, .max = 115000 }, 130 .vco = { .min = 1750000, .max = 3500000 }, 131 .n = { .min = 1, .max = 3 }, 132 .m = { .min = 104, .max = 138 }, 133 .m1 = { .min = 17, .max = 23 }, 134 .m2 = { .min = 5, .max = 11 }, 135 .p = { .min = 28, .max = 112 }, 136 .p1 = { .min = 2, .max = 8 }, 137 .p2 = { .dot_limit = 0, 138 .p2_slow = 14, .p2_fast = 14 139 }, 140 }; 141 142 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { 143 .dot = { .min = 80000, .max = 224000 }, 144 .vco = { .min = 1750000, .max = 3500000 }, 145 .n = { .min = 1, .max = 3 }, 146 .m = { .min = 104, .max = 138 }, 147 .m1 = { .min = 17, .max = 23 }, 148 .m2 = { .min = 5, .max = 11 }, 149 .p = { .min = 14, .max = 42 }, 150 .p1 = { .min = 2, .max = 6 }, 151 .p2 = { .dot_limit = 0, 152 .p2_slow = 7, .p2_fast = 7 153 }, 154 }; 155 156 static const struct intel_limit pnv_limits_sdvo = { 157 .dot = { .min = 20000, .max = 400000}, 158 .vco = { .min = 1700000, .max = 3500000 }, 159 /* Pineview's Ncounter is a ring counter */ 160 .n = { .min = 3, .max = 6 }, 161 .m = { .min = 2, .max = 256 }, 162 /* Pineview only has one combined m divider, which we treat as m2. */ 163 .m1 = { .min = 0, .max = 0 }, 164 .m2 = { .min = 0, .max = 254 }, 165 .p = { .min = 5, .max = 80 }, 166 .p1 = { .min = 1, .max = 8 }, 167 .p2 = { .dot_limit = 200000, 168 .p2_slow = 10, .p2_fast = 5 }, 169 }; 170 171 static const struct intel_limit pnv_limits_lvds = { 172 .dot = { .min = 20000, .max = 400000 }, 173 .vco = { .min = 1700000, .max = 3500000 }, 174 .n = { .min = 3, .max = 6 }, 175 .m = { .min = 2, .max = 256 }, 176 .m1 = { .min = 0, .max = 0 }, 177 .m2 = { .min = 0, .max = 254 }, 178 .p = { .min = 7, .max = 112 }, 179 .p1 = { .min = 1, .max = 8 }, 180 .p2 = { .dot_limit = 112000, 181 .p2_slow = 14, .p2_fast = 14 }, 182 }; 183 184 /* Ironlake / Sandybridge 185 * 186 * We calculate clock using (register_value + 2) for N/M1/M2, so here 187 * the range value for them is (actual_value - 2). 188 */ 189 static const struct intel_limit ilk_limits_dac = { 190 .dot = { .min = 25000, .max = 350000 }, 191 .vco = { .min = 1760000, .max = 3510000 }, 192 .n = { .min = 1, .max = 5 }, 193 .m = { .min = 79, .max = 127 }, 194 .m1 = { .min = 12, .max = 22 }, 195 .m2 = { .min = 5, .max = 9 }, 196 .p = { .min = 5, .max = 80 }, 197 .p1 = { .min = 1, .max = 8 }, 198 .p2 = { .dot_limit = 225000, 199 .p2_slow = 10, .p2_fast = 5 }, 200 }; 201 202 static const struct intel_limit ilk_limits_single_lvds = { 203 .dot = { .min = 25000, .max = 350000 }, 204 .vco = { .min = 1760000, .max = 3510000 }, 205 .n = { .min = 1, .max = 3 }, 206 .m = { .min = 79, .max = 118 }, 207 .m1 = { .min = 12, .max = 22 }, 208 .m2 = { .min = 5, .max = 9 }, 209 .p = { .min = 28, .max = 112 }, 210 .p1 = { .min = 2, .max = 8 }, 211 .p2 = { .dot_limit = 225000, 212 .p2_slow = 14, .p2_fast = 14 }, 213 }; 214 215 static const struct intel_limit ilk_limits_dual_lvds = { 216 .dot = { .min = 25000, .max = 350000 }, 217 .vco = { .min = 1760000, .max = 3510000 }, 218 .n = { .min = 1, .max = 3 }, 219 .m = { .min = 79, .max = 127 }, 220 .m1 = { .min = 12, .max = 22 }, 221 .m2 = { .min = 5, .max = 9 }, 222 .p = { .min = 14, .max = 56 }, 223 .p1 = { .min = 2, .max = 8 }, 224 .p2 = { .dot_limit = 225000, 225 .p2_slow = 7, .p2_fast = 7 }, 226 }; 227 228 /* LVDS 100mhz refclk limits. */ 229 static const struct intel_limit ilk_limits_single_lvds_100m = { 230 .dot = { .min = 25000, .max = 350000 }, 231 .vco = { .min = 1760000, .max = 3510000 }, 232 .n = { .min = 1, .max = 2 }, 233 .m = { .min = 79, .max = 126 }, 234 .m1 = { .min = 12, .max = 22 }, 235 .m2 = { .min = 5, .max = 9 }, 236 .p = { .min = 28, .max = 112 }, 237 .p1 = { .min = 2, .max = 8 }, 238 .p2 = { .dot_limit = 225000, 239 .p2_slow = 14, .p2_fast = 14 }, 240 }; 241 242 static const struct intel_limit ilk_limits_dual_lvds_100m = { 243 .dot = { .min = 25000, .max = 350000 }, 244 .vco = { .min = 1760000, .max = 3510000 }, 245 .n = { .min = 1, .max = 3 }, 246 .m = { .min = 79, .max = 126 }, 247 .m1 = { .min = 12, .max = 22 }, 248 .m2 = { .min = 5, .max = 9 }, 249 .p = { .min = 14, .max = 42 }, 250 .p1 = { .min = 2, .max = 6 }, 251 .p2 = { .dot_limit = 225000, 252 .p2_slow = 7, .p2_fast = 7 }, 253 }; 254 255 static const struct intel_limit intel_limits_vlv = { 256 /* 257 * These are based on the data rate limits (measured in fast clocks) 258 * since those are the strictest limits we have. The fast 259 * clock and actual rate limits are more relaxed, so checking 260 * them would make no difference. 261 */ 262 .dot = { .min = 25000, .max = 270000 }, 263 .vco = { .min = 4000000, .max = 6000000 }, 264 .n = { .min = 1, .max = 7 }, 265 .m1 = { .min = 2, .max = 3 }, 266 .m2 = { .min = 11, .max = 156 }, 267 .p1 = { .min = 2, .max = 3 }, 268 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ 269 }; 270 271 static const struct intel_limit intel_limits_chv = { 272 /* 273 * These are based on the data rate limits (measured in fast clocks) 274 * since those are the strictest limits we have. The fast 275 * clock and actual rate limits are more relaxed, so checking 276 * them would make no difference. 277 */ 278 .dot = { .min = 25000, .max = 540000 }, 279 .vco = { .min = 4800000, .max = 6480000 }, 280 .n = { .min = 1, .max = 1 }, 281 .m1 = { .min = 2, .max = 2 }, 282 .m2 = { .min = 24 << 22, .max = 175 << 22 }, 283 .p1 = { .min = 2, .max = 4 }, 284 .p2 = { .p2_slow = 1, .p2_fast = 14 }, 285 }; 286 287 static const struct intel_limit intel_limits_bxt = { 288 .dot = { .min = 25000, .max = 594000 }, 289 .vco = { .min = 4800000, .max = 6700000 }, 290 .n = { .min = 1, .max = 1 }, 291 .m1 = { .min = 2, .max = 2 }, 292 /* FIXME: find real m2 limits */ 293 .m2 = { .min = 2 << 22, .max = 255 << 22 }, 294 .p1 = { .min = 2, .max = 4 }, 295 .p2 = { .p2_slow = 1, .p2_fast = 20 }, 296 }; 297 298 /* 299 * Platform specific helpers to calculate the port PLL loopback- (clock.m), 300 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast 301 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. 302 * The helpers' return value is the rate of the clock that is fed to the 303 * display engine's pipe which can be the above fast dot clock rate or a 304 * divided-down version of it. 305 */ 306 /* m1 is reserved as 0 in Pineview, n is a ring counter */ 307 int pnv_calc_dpll_params(int refclk, struct dpll *clock) 308 { 309 clock->m = clock->m2 + 2; 310 clock->p = clock->p1 * clock->p2; 311 if (WARN_ON(clock->n == 0 || clock->p == 0)) 312 return 0; 313 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 314 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 315 316 return clock->dot; 317 } 318 319 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) 320 { 321 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); 322 } 323 324 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) 325 { 326 clock->m = i9xx_dpll_compute_m(clock); 327 clock->p = clock->p1 * clock->p2; 328 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) 329 return 0; 330 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); 331 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 332 333 return clock->dot; 334 } 335 336 int vlv_calc_dpll_params(int refclk, struct dpll *clock) 337 { 338 clock->m = clock->m1 * clock->m2; 339 clock->p = clock->p1 * clock->p2 * 5; 340 if (WARN_ON(clock->n == 0 || clock->p == 0)) 341 return 0; 342 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 343 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 344 345 return clock->dot; 346 } 347 348 int chv_calc_dpll_params(int refclk, struct dpll *clock) 349 { 350 clock->m = clock->m1 * clock->m2; 351 clock->p = clock->p1 * clock->p2 * 5; 352 if (WARN_ON(clock->n == 0 || clock->p == 0)) 353 return 0; 354 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), 355 clock->n << 22); 356 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 357 358 return clock->dot; 359 } 360 361 /* 362 * Returns whether the given set of divisors are valid for a given refclk with 363 * the given connectors. 364 */ 365 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv, 366 const struct intel_limit *limit, 367 const struct dpll *clock) 368 { 369 if (clock->n < limit->n.min || limit->n.max < clock->n) 370 return false; 371 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 372 return false; 373 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 374 return false; 375 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 376 return false; 377 378 if (!IS_PINEVIEW(dev_priv) && !IS_LP(dev_priv)) 379 if (clock->m1 <= clock->m2) 380 return false; 381 382 if (!IS_LP(dev_priv)) { 383 if (clock->p < limit->p.min || limit->p.max < clock->p) 384 return false; 385 if (clock->m < limit->m.min || limit->m.max < clock->m) 386 return false; 387 } 388 389 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 390 return false; 391 /* XXX: We may need to be checking "Dot clock" depending on the multiplier, 392 * connector, etc., rather than just a single range. 393 */ 394 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 395 return false; 396 397 return true; 398 } 399 400 static int 401 i9xx_select_p2_div(const struct intel_limit *limit, 402 const struct intel_crtc_state *crtc_state, 403 int target) 404 { 405 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 406 407 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 408 /* 409 * For LVDS just rely on its current settings for dual-channel. 410 * We haven't figured out how to reliably set up different 411 * single/dual channel state, if we even can. 412 */ 413 if (intel_is_dual_link_lvds(dev_priv)) 414 return limit->p2.p2_fast; 415 else 416 return limit->p2.p2_slow; 417 } else { 418 if (target < limit->p2.dot_limit) 419 return limit->p2.p2_slow; 420 else 421 return limit->p2.p2_fast; 422 } 423 } 424 425 /* 426 * Returns a set of divisors for the desired target clock with the given 427 * refclk, or FALSE. 428 * 429 * Target and reference clocks are specified in kHz. 430 * 431 * If match_clock is provided, then best_clock P divider must match the P 432 * divider from @match_clock used for LVDS downclocking. 433 */ 434 static bool 435 i9xx_find_best_dpll(const struct intel_limit *limit, 436 struct intel_crtc_state *crtc_state, 437 int target, int refclk, 438 const struct dpll *match_clock, 439 struct dpll *best_clock) 440 { 441 struct drm_device *dev = crtc_state->uapi.crtc->dev; 442 struct dpll clock; 443 int err = target; 444 445 memset(best_clock, 0, sizeof(*best_clock)); 446 447 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 448 449 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 450 clock.m1++) { 451 for (clock.m2 = limit->m2.min; 452 clock.m2 <= limit->m2.max; clock.m2++) { 453 if (clock.m2 >= clock.m1) 454 break; 455 for (clock.n = limit->n.min; 456 clock.n <= limit->n.max; clock.n++) { 457 for (clock.p1 = limit->p1.min; 458 clock.p1 <= limit->p1.max; clock.p1++) { 459 int this_err; 460 461 i9xx_calc_dpll_params(refclk, &clock); 462 if (!intel_pll_is_valid(to_i915(dev), 463 limit, 464 &clock)) 465 continue; 466 if (match_clock && 467 clock.p != match_clock->p) 468 continue; 469 470 this_err = abs(clock.dot - target); 471 if (this_err < err) { 472 *best_clock = clock; 473 err = this_err; 474 } 475 } 476 } 477 } 478 } 479 480 return (err != target); 481 } 482 483 /* 484 * Returns a set of divisors for the desired target clock with the given 485 * refclk, or FALSE. 486 * 487 * Target and reference clocks are specified in kHz. 488 * 489 * If match_clock is provided, then best_clock P divider must match the P 490 * divider from @match_clock used for LVDS downclocking. 491 */ 492 static bool 493 pnv_find_best_dpll(const struct intel_limit *limit, 494 struct intel_crtc_state *crtc_state, 495 int target, int refclk, 496 const struct dpll *match_clock, 497 struct dpll *best_clock) 498 { 499 struct drm_device *dev = crtc_state->uapi.crtc->dev; 500 struct dpll clock; 501 int err = target; 502 503 memset(best_clock, 0, sizeof(*best_clock)); 504 505 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 506 507 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 508 clock.m1++) { 509 for (clock.m2 = limit->m2.min; 510 clock.m2 <= limit->m2.max; clock.m2++) { 511 for (clock.n = limit->n.min; 512 clock.n <= limit->n.max; clock.n++) { 513 for (clock.p1 = limit->p1.min; 514 clock.p1 <= limit->p1.max; clock.p1++) { 515 int this_err; 516 517 pnv_calc_dpll_params(refclk, &clock); 518 if (!intel_pll_is_valid(to_i915(dev), 519 limit, 520 &clock)) 521 continue; 522 if (match_clock && 523 clock.p != match_clock->p) 524 continue; 525 526 this_err = abs(clock.dot - target); 527 if (this_err < err) { 528 *best_clock = clock; 529 err = this_err; 530 } 531 } 532 } 533 } 534 } 535 536 return (err != target); 537 } 538 539 /* 540 * Returns a set of divisors for the desired target clock with the given 541 * refclk, or FALSE. 542 * 543 * Target and reference clocks are specified in kHz. 544 * 545 * If match_clock is provided, then best_clock P divider must match the P 546 * divider from @match_clock used for LVDS downclocking. 547 */ 548 static bool 549 g4x_find_best_dpll(const struct intel_limit *limit, 550 struct intel_crtc_state *crtc_state, 551 int target, int refclk, 552 const struct dpll *match_clock, 553 struct dpll *best_clock) 554 { 555 struct drm_device *dev = crtc_state->uapi.crtc->dev; 556 struct dpll clock; 557 int max_n; 558 bool found = false; 559 /* approximately equals target * 0.00585 */ 560 int err_most = (target >> 8) + (target >> 9); 561 562 memset(best_clock, 0, sizeof(*best_clock)); 563 564 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 565 566 max_n = limit->n.max; 567 /* based on hardware requirement, prefer smaller n to precision */ 568 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 569 /* based on hardware requirement, prefere larger m1,m2 */ 570 for (clock.m1 = limit->m1.max; 571 clock.m1 >= limit->m1.min; clock.m1--) { 572 for (clock.m2 = limit->m2.max; 573 clock.m2 >= limit->m2.min; clock.m2--) { 574 for (clock.p1 = limit->p1.max; 575 clock.p1 >= limit->p1.min; clock.p1--) { 576 int this_err; 577 578 i9xx_calc_dpll_params(refclk, &clock); 579 if (!intel_pll_is_valid(to_i915(dev), 580 limit, 581 &clock)) 582 continue; 583 584 this_err = abs(clock.dot - target); 585 if (this_err < err_most) { 586 *best_clock = clock; 587 err_most = this_err; 588 max_n = clock.n; 589 found = true; 590 } 591 } 592 } 593 } 594 } 595 return found; 596 } 597 598 /* 599 * Check if the calculated PLL configuration is more optimal compared to the 600 * best configuration and error found so far. Return the calculated error. 601 */ 602 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, 603 const struct dpll *calculated_clock, 604 const struct dpll *best_clock, 605 unsigned int best_error_ppm, 606 unsigned int *error_ppm) 607 { 608 /* 609 * For CHV ignore the error and consider only the P value. 610 * Prefer a bigger P value based on HW requirements. 611 */ 612 if (IS_CHERRYVIEW(to_i915(dev))) { 613 *error_ppm = 0; 614 615 return calculated_clock->p > best_clock->p; 616 } 617 618 if (drm_WARN_ON_ONCE(dev, !target_freq)) 619 return false; 620 621 *error_ppm = div_u64(1000000ULL * 622 abs(target_freq - calculated_clock->dot), 623 target_freq); 624 /* 625 * Prefer a better P value over a better (smaller) error if the error 626 * is small. Ensure this preference for future configurations too by 627 * setting the error to 0. 628 */ 629 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { 630 *error_ppm = 0; 631 632 return true; 633 } 634 635 return *error_ppm + 10 < best_error_ppm; 636 } 637 638 /* 639 * Returns a set of divisors for the desired target clock with the given 640 * refclk, or FALSE. 641 */ 642 static bool 643 vlv_find_best_dpll(const struct intel_limit *limit, 644 struct intel_crtc_state *crtc_state, 645 int target, int refclk, 646 const struct dpll *match_clock, 647 struct dpll *best_clock) 648 { 649 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 650 struct drm_device *dev = crtc->base.dev; 651 struct dpll clock; 652 unsigned int bestppm = 1000000; 653 /* min update 19.2 MHz */ 654 int max_n = min(limit->n.max, refclk / 19200); 655 bool found = false; 656 657 memset(best_clock, 0, sizeof(*best_clock)); 658 659 /* based on hardware requirement, prefer smaller n to precision */ 660 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 661 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 662 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; 663 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 664 clock.p = clock.p1 * clock.p2 * 5; 665 /* based on hardware requirement, prefer bigger m1,m2 values */ 666 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { 667 unsigned int ppm; 668 669 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, 670 refclk * clock.m1); 671 672 vlv_calc_dpll_params(refclk, &clock); 673 674 if (!intel_pll_is_valid(to_i915(dev), 675 limit, 676 &clock)) 677 continue; 678 679 if (!vlv_PLL_is_optimal(dev, target, 680 &clock, 681 best_clock, 682 bestppm, &ppm)) 683 continue; 684 685 *best_clock = clock; 686 bestppm = ppm; 687 found = true; 688 } 689 } 690 } 691 } 692 693 return found; 694 } 695 696 /* 697 * Returns a set of divisors for the desired target clock with the given 698 * refclk, or FALSE. 699 */ 700 static bool 701 chv_find_best_dpll(const struct intel_limit *limit, 702 struct intel_crtc_state *crtc_state, 703 int target, int refclk, 704 const struct dpll *match_clock, 705 struct dpll *best_clock) 706 { 707 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 708 struct drm_device *dev = crtc->base.dev; 709 unsigned int best_error_ppm; 710 struct dpll clock; 711 u64 m2; 712 int found = false; 713 714 memset(best_clock, 0, sizeof(*best_clock)); 715 best_error_ppm = 1000000; 716 717 /* 718 * Based on hardware doc, the n always set to 1, and m1 always 719 * set to 2. If requires to support 200Mhz refclk, we need to 720 * revisit this because n may not 1 anymore. 721 */ 722 clock.n = 1; 723 clock.m1 = 2; 724 725 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 726 for (clock.p2 = limit->p2.p2_fast; 727 clock.p2 >= limit->p2.p2_slow; 728 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 729 unsigned int error_ppm; 730 731 clock.p = clock.p1 * clock.p2 * 5; 732 733 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22, 734 refclk * clock.m1); 735 736 if (m2 > INT_MAX/clock.m1) 737 continue; 738 739 clock.m2 = m2; 740 741 chv_calc_dpll_params(refclk, &clock); 742 743 if (!intel_pll_is_valid(to_i915(dev), limit, &clock)) 744 continue; 745 746 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, 747 best_error_ppm, &error_ppm)) 748 continue; 749 750 *best_clock = clock; 751 best_error_ppm = error_ppm; 752 found = true; 753 } 754 } 755 756 return found; 757 } 758 759 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, 760 struct dpll *best_clock) 761 { 762 int refclk = 100000; 763 const struct intel_limit *limit = &intel_limits_bxt; 764 765 return chv_find_best_dpll(limit, crtc_state, 766 crtc_state->port_clock, refclk, 767 NULL, best_clock); 768 } 769 770 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) 771 { 772 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; 773 } 774 775 static u32 pnv_dpll_compute_fp(const struct dpll *dpll) 776 { 777 return (1 << dpll->n) << 16 | dpll->m2; 778 } 779 780 static void i9xx_update_pll_dividers(struct intel_crtc_state *crtc_state, 781 const struct dpll *clock, 782 const struct dpll *reduced_clock) 783 { 784 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 785 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 786 u32 fp, fp2; 787 788 if (IS_PINEVIEW(dev_priv)) { 789 fp = pnv_dpll_compute_fp(clock); 790 fp2 = pnv_dpll_compute_fp(reduced_clock); 791 } else { 792 fp = i9xx_dpll_compute_fp(clock); 793 fp2 = i9xx_dpll_compute_fp(reduced_clock); 794 } 795 796 crtc_state->dpll_hw_state.fp0 = fp; 797 crtc_state->dpll_hw_state.fp1 = fp2; 798 } 799 800 static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, 801 const struct dpll *clock, 802 const struct dpll *reduced_clock) 803 { 804 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 805 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 806 u32 dpll; 807 808 i9xx_update_pll_dividers(crtc_state, clock, reduced_clock); 809 810 dpll = DPLL_VGA_MODE_DIS; 811 812 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) 813 dpll |= DPLLB_MODE_LVDS; 814 else 815 dpll |= DPLLB_MODE_DAC_SERIAL; 816 817 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 818 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 819 dpll |= (crtc_state->pixel_multiplier - 1) 820 << SDVO_MULTIPLIER_SHIFT_HIRES; 821 } 822 823 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || 824 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 825 dpll |= DPLL_SDVO_HIGH_SPEED; 826 827 if (intel_crtc_has_dp_encoder(crtc_state)) 828 dpll |= DPLL_SDVO_HIGH_SPEED; 829 830 /* compute bitmask from p1 value */ 831 if (IS_G4X(dev_priv)) { 832 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 833 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 834 } else if (IS_PINEVIEW(dev_priv)) { 835 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; 836 WARN_ON(reduced_clock->p1 != clock->p1); 837 } else { 838 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 839 WARN_ON(reduced_clock->p1 != clock->p1); 840 } 841 842 switch (clock->p2) { 843 case 5: 844 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 845 break; 846 case 7: 847 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 848 break; 849 case 10: 850 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 851 break; 852 case 14: 853 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 854 break; 855 } 856 WARN_ON(reduced_clock->p2 != clock->p2); 857 858 if (DISPLAY_VER(dev_priv) >= 4) 859 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 860 861 if (crtc_state->sdvo_tv_clock) 862 dpll |= PLL_REF_INPUT_TVCLKINBC; 863 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 864 intel_panel_use_ssc(dev_priv)) 865 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 866 else 867 dpll |= PLL_REF_INPUT_DREFCLK; 868 869 dpll |= DPLL_VCO_ENABLE; 870 crtc_state->dpll_hw_state.dpll = dpll; 871 872 if (DISPLAY_VER(dev_priv) >= 4) { 873 u32 dpll_md = (crtc_state->pixel_multiplier - 1) 874 << DPLL_MD_UDI_MULTIPLIER_SHIFT; 875 crtc_state->dpll_hw_state.dpll_md = dpll_md; 876 } 877 } 878 879 static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state, 880 const struct dpll *clock, 881 const struct dpll *reduced_clock) 882 { 883 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 884 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 885 u32 dpll; 886 887 i9xx_update_pll_dividers(crtc_state, clock, reduced_clock); 888 889 dpll = DPLL_VGA_MODE_DIS; 890 891 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 892 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 893 } else { 894 if (clock->p1 == 2) 895 dpll |= PLL_P1_DIVIDE_BY_TWO; 896 else 897 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; 898 if (clock->p2 == 4) 899 dpll |= PLL_P2_DIVIDE_BY_4; 900 } 901 WARN_ON(reduced_clock->p1 != clock->p1); 902 WARN_ON(reduced_clock->p2 != clock->p2); 903 904 /* 905 * Bspec: 906 * "[Almador Errata}: For the correct operation of the muxed DVO pins 907 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, 908 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock 909 * Enable) must be set to “1” in both the DPLL A Control Register 910 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." 911 * 912 * For simplicity We simply keep both bits always enabled in 913 * both DPLLS. The spec says we should disable the DVO 2X clock 914 * when not needed, but this seems to work fine in practice. 915 */ 916 if (IS_I830(dev_priv) || 917 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) 918 dpll |= DPLL_DVO_2X_MODE; 919 920 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 921 intel_panel_use_ssc(dev_priv)) 922 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 923 else 924 dpll |= PLL_REF_INPUT_DREFCLK; 925 926 dpll |= DPLL_VCO_ENABLE; 927 crtc_state->dpll_hw_state.dpll = dpll; 928 } 929 930 static int hsw_crtc_compute_clock(struct intel_crtc_state *crtc_state) 931 { 932 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 933 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 934 struct intel_atomic_state *state = 935 to_intel_atomic_state(crtc_state->uapi.state); 936 struct intel_encoder *encoder = 937 intel_get_crtc_new_encoder(state, crtc_state); 938 939 if (IS_DG2(dev_priv)) 940 return intel_mpllb_calc_state(crtc_state, encoder); 941 942 if (DISPLAY_VER(dev_priv) < 11 && 943 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 944 return 0; 945 946 if (!intel_reserve_shared_dplls(state, crtc, encoder)) { 947 drm_dbg_kms(&dev_priv->drm, 948 "failed to find PLL for pipe %c\n", 949 pipe_name(crtc->pipe)); 950 return -EINVAL; 951 } 952 953 return 0; 954 } 955 956 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) 957 { 958 return dpll->m < factor * dpll->n; 959 } 960 961 static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state, 962 const struct dpll *clock, 963 const struct dpll *reduced_clock) 964 { 965 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 966 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 967 u32 fp, fp2; 968 int factor; 969 970 /* Enable autotuning of the PLL clock (if permissible) */ 971 factor = 21; 972 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 973 if ((intel_panel_use_ssc(dev_priv) && 974 dev_priv->vbt.lvds_ssc_freq == 100000) || 975 (HAS_PCH_IBX(dev_priv) && 976 intel_is_dual_link_lvds(dev_priv))) 977 factor = 25; 978 } else if (crtc_state->sdvo_tv_clock) { 979 factor = 20; 980 } 981 982 fp = i9xx_dpll_compute_fp(clock); 983 if (ilk_needs_fb_cb_tune(clock, factor)) 984 fp |= FP_CB_TUNE; 985 986 fp2 = i9xx_dpll_compute_fp(reduced_clock); 987 if (ilk_needs_fb_cb_tune(reduced_clock, factor)) 988 fp2 |= FP_CB_TUNE; 989 990 crtc_state->dpll_hw_state.fp0 = fp; 991 crtc_state->dpll_hw_state.fp1 = fp2; 992 } 993 994 static void ilk_compute_dpll(struct intel_crtc_state *crtc_state, 995 const struct dpll *clock, 996 const struct dpll *reduced_clock) 997 { 998 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 999 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1000 u32 dpll; 1001 1002 ilk_update_pll_dividers(crtc_state, clock, reduced_clock); 1003 1004 dpll = 0; 1005 1006 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) 1007 dpll |= DPLLB_MODE_LVDS; 1008 else 1009 dpll |= DPLLB_MODE_DAC_SERIAL; 1010 1011 dpll |= (crtc_state->pixel_multiplier - 1) 1012 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 1013 1014 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || 1015 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1016 dpll |= DPLL_SDVO_HIGH_SPEED; 1017 1018 if (intel_crtc_has_dp_encoder(crtc_state)) 1019 dpll |= DPLL_SDVO_HIGH_SPEED; 1020 1021 /* 1022 * The high speed IO clock is only really required for 1023 * SDVO/HDMI/DP, but we also enable it for CRT to make it 1024 * possible to share the DPLL between CRT and HDMI. Enabling 1025 * the clock needlessly does no real harm, except use up a 1026 * bit of power potentially. 1027 * 1028 * We'll limit this to IVB with 3 pipes, since it has only two 1029 * DPLLs and so DPLL sharing is the only way to get three pipes 1030 * driving PCH ports at the same time. On SNB we could do this, 1031 * and potentially avoid enabling the second DPLL, but it's not 1032 * clear if it''s a win or loss power wise. No point in doing 1033 * this on ILK at all since it has a fixed DPLL<->pipe mapping. 1034 */ 1035 if (INTEL_NUM_PIPES(dev_priv) == 3 && 1036 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1037 dpll |= DPLL_SDVO_HIGH_SPEED; 1038 1039 /* compute bitmask from p1 value */ 1040 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 1041 /* also FPA1 */ 1042 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 1043 1044 switch (clock->p2) { 1045 case 5: 1046 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 1047 break; 1048 case 7: 1049 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 1050 break; 1051 case 10: 1052 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 1053 break; 1054 case 14: 1055 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 1056 break; 1057 } 1058 WARN_ON(reduced_clock->p2 != clock->p2); 1059 1060 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 1061 intel_panel_use_ssc(dev_priv)) 1062 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 1063 else 1064 dpll |= PLL_REF_INPUT_DREFCLK; 1065 1066 dpll |= DPLL_VCO_ENABLE; 1067 1068 crtc_state->dpll_hw_state.dpll = dpll; 1069 } 1070 1071 static int ilk_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1072 { 1073 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1074 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1075 struct intel_atomic_state *state = 1076 to_intel_atomic_state(crtc_state->uapi.state); 1077 const struct intel_limit *limit; 1078 int refclk = 120000; 1079 1080 memset(&crtc_state->dpll_hw_state, 0, 1081 sizeof(crtc_state->dpll_hw_state)); 1082 1083 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 1084 if (!crtc_state->has_pch_encoder) 1085 return 0; 1086 1087 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1088 if (intel_panel_use_ssc(dev_priv)) { 1089 drm_dbg_kms(&dev_priv->drm, 1090 "using SSC reference clock of %d kHz\n", 1091 dev_priv->vbt.lvds_ssc_freq); 1092 refclk = dev_priv->vbt.lvds_ssc_freq; 1093 } 1094 1095 if (intel_is_dual_link_lvds(dev_priv)) { 1096 if (refclk == 100000) 1097 limit = &ilk_limits_dual_lvds_100m; 1098 else 1099 limit = &ilk_limits_dual_lvds; 1100 } else { 1101 if (refclk == 100000) 1102 limit = &ilk_limits_single_lvds_100m; 1103 else 1104 limit = &ilk_limits_single_lvds; 1105 } 1106 } else { 1107 limit = &ilk_limits_dac; 1108 } 1109 1110 if (!crtc_state->clock_set && 1111 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1112 refclk, NULL, &crtc_state->dpll)) { 1113 drm_err(&dev_priv->drm, 1114 "Couldn't find PLL settings for mode!\n"); 1115 return -EINVAL; 1116 } 1117 1118 ilk_compute_dpll(crtc_state, &crtc_state->dpll, 1119 &crtc_state->dpll); 1120 1121 if (!intel_reserve_shared_dplls(state, crtc, NULL)) { 1122 drm_dbg_kms(&dev_priv->drm, 1123 "failed to find PLL for pipe %c\n", 1124 pipe_name(crtc->pipe)); 1125 return -EINVAL; 1126 } 1127 1128 return 0; 1129 } 1130 1131 void vlv_compute_dpll(struct intel_crtc_state *crtc_state) 1132 { 1133 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1134 1135 crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | 1136 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1137 if (crtc->pipe != PIPE_A) 1138 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 1139 1140 /* DPLL not used with DSI, but still need the rest set up */ 1141 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1142 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | 1143 DPLL_EXT_BUFFER_ENABLE_VLV; 1144 1145 crtc_state->dpll_hw_state.dpll_md = 1146 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 1147 } 1148 1149 void chv_compute_dpll(struct intel_crtc_state *crtc_state) 1150 { 1151 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1152 1153 crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | 1154 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1155 if (crtc->pipe != PIPE_A) 1156 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 1157 1158 /* DPLL not used with DSI, but still need the rest set up */ 1159 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1160 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; 1161 1162 crtc_state->dpll_hw_state.dpll_md = 1163 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 1164 } 1165 1166 static int chv_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1167 { 1168 int refclk = 100000; 1169 const struct intel_limit *limit = &intel_limits_chv; 1170 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1171 1172 memset(&crtc_state->dpll_hw_state, 0, 1173 sizeof(crtc_state->dpll_hw_state)); 1174 1175 if (!crtc_state->clock_set && 1176 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1177 refclk, NULL, &crtc_state->dpll)) { 1178 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); 1179 return -EINVAL; 1180 } 1181 1182 chv_compute_dpll(crtc_state); 1183 1184 return 0; 1185 } 1186 1187 static int vlv_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1188 { 1189 int refclk = 100000; 1190 const struct intel_limit *limit = &intel_limits_vlv; 1191 struct drm_i915_private *i915 = to_i915(crtc_state->uapi.crtc->dev); 1192 1193 memset(&crtc_state->dpll_hw_state, 0, 1194 sizeof(crtc_state->dpll_hw_state)); 1195 1196 if (!crtc_state->clock_set && 1197 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1198 refclk, NULL, &crtc_state->dpll)) { 1199 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); 1200 return -EINVAL; 1201 } 1202 1203 vlv_compute_dpll(crtc_state); 1204 1205 return 0; 1206 } 1207 1208 static int g4x_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1209 { 1210 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1211 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1212 const struct intel_limit *limit; 1213 int refclk = 96000; 1214 1215 memset(&crtc_state->dpll_hw_state, 0, 1216 sizeof(crtc_state->dpll_hw_state)); 1217 1218 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1219 if (intel_panel_use_ssc(dev_priv)) { 1220 refclk = dev_priv->vbt.lvds_ssc_freq; 1221 drm_dbg_kms(&dev_priv->drm, 1222 "using SSC reference clock of %d kHz\n", 1223 refclk); 1224 } 1225 1226 if (intel_is_dual_link_lvds(dev_priv)) 1227 limit = &intel_limits_g4x_dual_channel_lvds; 1228 else 1229 limit = &intel_limits_g4x_single_channel_lvds; 1230 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || 1231 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1232 limit = &intel_limits_g4x_hdmi; 1233 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { 1234 limit = &intel_limits_g4x_sdvo; 1235 } else { 1236 /* The option is for other outputs */ 1237 limit = &intel_limits_i9xx_sdvo; 1238 } 1239 1240 if (!crtc_state->clock_set && 1241 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1242 refclk, NULL, &crtc_state->dpll)) { 1243 drm_err(&dev_priv->drm, 1244 "Couldn't find PLL settings for mode!\n"); 1245 return -EINVAL; 1246 } 1247 1248 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, 1249 &crtc_state->dpll); 1250 1251 return 0; 1252 } 1253 1254 static int pnv_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1255 { 1256 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1257 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1258 const struct intel_limit *limit; 1259 int refclk = 96000; 1260 1261 memset(&crtc_state->dpll_hw_state, 0, 1262 sizeof(crtc_state->dpll_hw_state)); 1263 1264 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1265 if (intel_panel_use_ssc(dev_priv)) { 1266 refclk = dev_priv->vbt.lvds_ssc_freq; 1267 drm_dbg_kms(&dev_priv->drm, 1268 "using SSC reference clock of %d kHz\n", 1269 refclk); 1270 } 1271 1272 limit = &pnv_limits_lvds; 1273 } else { 1274 limit = &pnv_limits_sdvo; 1275 } 1276 1277 if (!crtc_state->clock_set && 1278 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1279 refclk, NULL, &crtc_state->dpll)) { 1280 drm_err(&dev_priv->drm, 1281 "Couldn't find PLL settings for mode!\n"); 1282 return -EINVAL; 1283 } 1284 1285 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, 1286 &crtc_state->dpll); 1287 1288 return 0; 1289 } 1290 1291 static int i9xx_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1292 { 1293 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1294 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1295 const struct intel_limit *limit; 1296 int refclk = 96000; 1297 1298 memset(&crtc_state->dpll_hw_state, 0, 1299 sizeof(crtc_state->dpll_hw_state)); 1300 1301 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1302 if (intel_panel_use_ssc(dev_priv)) { 1303 refclk = dev_priv->vbt.lvds_ssc_freq; 1304 drm_dbg_kms(&dev_priv->drm, 1305 "using SSC reference clock of %d kHz\n", 1306 refclk); 1307 } 1308 1309 limit = &intel_limits_i9xx_lvds; 1310 } else { 1311 limit = &intel_limits_i9xx_sdvo; 1312 } 1313 1314 if (!crtc_state->clock_set && 1315 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1316 refclk, NULL, &crtc_state->dpll)) { 1317 drm_err(&dev_priv->drm, 1318 "Couldn't find PLL settings for mode!\n"); 1319 return -EINVAL; 1320 } 1321 1322 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, 1323 &crtc_state->dpll); 1324 1325 return 0; 1326 } 1327 1328 static int i8xx_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1329 { 1330 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1331 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1332 const struct intel_limit *limit; 1333 int refclk = 48000; 1334 1335 memset(&crtc_state->dpll_hw_state, 0, 1336 sizeof(crtc_state->dpll_hw_state)); 1337 1338 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1339 if (intel_panel_use_ssc(dev_priv)) { 1340 refclk = dev_priv->vbt.lvds_ssc_freq; 1341 drm_dbg_kms(&dev_priv->drm, 1342 "using SSC reference clock of %d kHz\n", 1343 refclk); 1344 } 1345 1346 limit = &intel_limits_i8xx_lvds; 1347 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { 1348 limit = &intel_limits_i8xx_dvo; 1349 } else { 1350 limit = &intel_limits_i8xx_dac; 1351 } 1352 1353 if (!crtc_state->clock_set && 1354 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1355 refclk, NULL, &crtc_state->dpll)) { 1356 drm_err(&dev_priv->drm, 1357 "Couldn't find PLL settings for mode!\n"); 1358 return -EINVAL; 1359 } 1360 1361 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, 1362 &crtc_state->dpll); 1363 1364 return 0; 1365 } 1366 1367 static const struct intel_dpll_funcs hsw_dpll_funcs = { 1368 .crtc_compute_clock = hsw_crtc_compute_clock, 1369 }; 1370 1371 static const struct intel_dpll_funcs ilk_dpll_funcs = { 1372 .crtc_compute_clock = ilk_crtc_compute_clock, 1373 }; 1374 1375 static const struct intel_dpll_funcs chv_dpll_funcs = { 1376 .crtc_compute_clock = chv_crtc_compute_clock, 1377 }; 1378 1379 static const struct intel_dpll_funcs vlv_dpll_funcs = { 1380 .crtc_compute_clock = vlv_crtc_compute_clock, 1381 }; 1382 1383 static const struct intel_dpll_funcs g4x_dpll_funcs = { 1384 .crtc_compute_clock = g4x_crtc_compute_clock, 1385 }; 1386 1387 static const struct intel_dpll_funcs pnv_dpll_funcs = { 1388 .crtc_compute_clock = pnv_crtc_compute_clock, 1389 }; 1390 1391 static const struct intel_dpll_funcs i9xx_dpll_funcs = { 1392 .crtc_compute_clock = i9xx_crtc_compute_clock, 1393 }; 1394 1395 static const struct intel_dpll_funcs i8xx_dpll_funcs = { 1396 .crtc_compute_clock = i8xx_crtc_compute_clock, 1397 }; 1398 1399 int intel_dpll_crtc_compute_clock(struct intel_crtc_state *crtc_state) 1400 { 1401 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1402 struct drm_i915_private *i915 = to_i915(crtc->base.dev); 1403 1404 return i915->dpll_funcs->crtc_compute_clock(crtc_state); 1405 } 1406 1407 void 1408 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv) 1409 { 1410 if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv)) 1411 dev_priv->dpll_funcs = &hsw_dpll_funcs; 1412 else if (HAS_PCH_SPLIT(dev_priv)) 1413 dev_priv->dpll_funcs = &ilk_dpll_funcs; 1414 else if (IS_CHERRYVIEW(dev_priv)) 1415 dev_priv->dpll_funcs = &chv_dpll_funcs; 1416 else if (IS_VALLEYVIEW(dev_priv)) 1417 dev_priv->dpll_funcs = &vlv_dpll_funcs; 1418 else if (IS_G4X(dev_priv)) 1419 dev_priv->dpll_funcs = &g4x_dpll_funcs; 1420 else if (IS_PINEVIEW(dev_priv)) 1421 dev_priv->dpll_funcs = &pnv_dpll_funcs; 1422 else if (DISPLAY_VER(dev_priv) != 2) 1423 dev_priv->dpll_funcs = &i9xx_dpll_funcs; 1424 else 1425 dev_priv->dpll_funcs = &i8xx_dpll_funcs; 1426 } 1427 1428 static bool i9xx_has_pps(struct drm_i915_private *dev_priv) 1429 { 1430 if (IS_I830(dev_priv)) 1431 return false; 1432 1433 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 1434 } 1435 1436 void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) 1437 { 1438 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1439 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1440 u32 dpll = crtc_state->dpll_hw_state.dpll; 1441 enum pipe pipe = crtc->pipe; 1442 int i; 1443 1444 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1445 1446 /* PLL is protected by panel, make sure we can write it */ 1447 if (i9xx_has_pps(dev_priv)) 1448 assert_pps_unlocked(dev_priv, pipe); 1449 1450 intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0); 1451 intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1); 1452 1453 /* 1454 * Apparently we need to have VGA mode enabled prior to changing 1455 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 1456 * dividers, even though the register value does change. 1457 */ 1458 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 1459 intel_de_write(dev_priv, DPLL(pipe), dpll); 1460 1461 /* Wait for the clocks to stabilize. */ 1462 intel_de_posting_read(dev_priv, DPLL(pipe)); 1463 udelay(150); 1464 1465 if (DISPLAY_VER(dev_priv) >= 4) { 1466 intel_de_write(dev_priv, DPLL_MD(pipe), 1467 crtc_state->dpll_hw_state.dpll_md); 1468 } else { 1469 /* The pixel multiplier can only be updated once the 1470 * DPLL is enabled and the clocks are stable. 1471 * 1472 * So write it again. 1473 */ 1474 intel_de_write(dev_priv, DPLL(pipe), dpll); 1475 } 1476 1477 /* We do this three times for luck */ 1478 for (i = 0; i < 3; i++) { 1479 intel_de_write(dev_priv, DPLL(pipe), dpll); 1480 intel_de_posting_read(dev_priv, DPLL(pipe)); 1481 udelay(150); /* wait for warmup */ 1482 } 1483 } 1484 1485 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, 1486 enum pipe pipe) 1487 { 1488 u32 reg_val; 1489 1490 /* 1491 * PLLB opamp always calibrates to max value of 0x3f, force enable it 1492 * and set it to a reasonable value instead. 1493 */ 1494 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); 1495 reg_val &= 0xffffff00; 1496 reg_val |= 0x00000030; 1497 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); 1498 1499 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); 1500 reg_val &= 0x00ffffff; 1501 reg_val |= 0x8c000000; 1502 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 1503 1504 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); 1505 reg_val &= 0xffffff00; 1506 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); 1507 1508 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); 1509 reg_val &= 0x00ffffff; 1510 reg_val |= 0xb0000000; 1511 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 1512 } 1513 1514 static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) 1515 { 1516 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1517 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1518 enum pipe pipe = crtc->pipe; 1519 u32 mdiv; 1520 u32 bestn, bestm1, bestm2, bestp1, bestp2; 1521 u32 coreclk, reg_val; 1522 1523 vlv_dpio_get(dev_priv); 1524 1525 bestn = crtc_state->dpll.n; 1526 bestm1 = crtc_state->dpll.m1; 1527 bestm2 = crtc_state->dpll.m2; 1528 bestp1 = crtc_state->dpll.p1; 1529 bestp2 = crtc_state->dpll.p2; 1530 1531 /* See eDP HDMI DPIO driver vbios notes doc */ 1532 1533 /* PLL B needs special handling */ 1534 if (pipe == PIPE_B) 1535 vlv_pllb_recal_opamp(dev_priv, pipe); 1536 1537 /* Set up Tx target for periodic Rcomp update */ 1538 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); 1539 1540 /* Disable target IRef on PLL */ 1541 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); 1542 reg_val &= 0x00ffffff; 1543 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); 1544 1545 /* Disable fast lock */ 1546 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); 1547 1548 /* Set idtafcrecal before PLL is enabled */ 1549 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); 1550 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); 1551 mdiv |= ((bestn << DPIO_N_SHIFT)); 1552 mdiv |= (1 << DPIO_K_SHIFT); 1553 1554 /* 1555 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, 1556 * but we don't support that). 1557 * Note: don't use the DAC post divider as it seems unstable. 1558 */ 1559 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); 1560 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); 1561 1562 mdiv |= DPIO_ENABLE_CALIBRATION; 1563 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); 1564 1565 /* Set HBR and RBR LPF coefficients */ 1566 if (crtc_state->port_clock == 162000 || 1567 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) || 1568 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1569 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 1570 0x009f0003); 1571 else 1572 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 1573 0x00d0000f); 1574 1575 if (intel_crtc_has_dp_encoder(crtc_state)) { 1576 /* Use SSC source */ 1577 if (pipe == PIPE_A) 1578 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1579 0x0df40000); 1580 else 1581 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1582 0x0df70000); 1583 } else { /* HDMI or VGA */ 1584 /* Use bend source */ 1585 if (pipe == PIPE_A) 1586 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1587 0x0df70000); 1588 else 1589 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1590 0x0df40000); 1591 } 1592 1593 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); 1594 coreclk = (coreclk & 0x0000ff00) | 0x01c00000; 1595 if (intel_crtc_has_dp_encoder(crtc_state)) 1596 coreclk |= 0x01000000; 1597 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); 1598 1599 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); 1600 1601 vlv_dpio_put(dev_priv); 1602 } 1603 1604 static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state) 1605 { 1606 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1607 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1608 enum pipe pipe = crtc->pipe; 1609 1610 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); 1611 intel_de_posting_read(dev_priv, DPLL(pipe)); 1612 udelay(150); 1613 1614 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) 1615 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); 1616 } 1617 1618 void vlv_enable_pll(const struct intel_crtc_state *crtc_state) 1619 { 1620 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1621 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1622 enum pipe pipe = crtc->pipe; 1623 1624 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1625 1626 /* PLL is protected by panel, make sure we can write it */ 1627 assert_pps_unlocked(dev_priv, pipe); 1628 1629 /* Enable Refclk */ 1630 intel_de_write(dev_priv, DPLL(pipe), 1631 crtc_state->dpll_hw_state.dpll & 1632 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); 1633 1634 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { 1635 vlv_prepare_pll(crtc_state); 1636 _vlv_enable_pll(crtc_state); 1637 } 1638 1639 intel_de_write(dev_priv, DPLL_MD(pipe), 1640 crtc_state->dpll_hw_state.dpll_md); 1641 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); 1642 } 1643 1644 static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) 1645 { 1646 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1647 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1648 enum pipe pipe = crtc->pipe; 1649 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1650 u32 loopfilter, tribuf_calcntr; 1651 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; 1652 u32 dpio_val; 1653 int vco; 1654 1655 bestn = crtc_state->dpll.n; 1656 bestm2_frac = crtc_state->dpll.m2 & 0x3fffff; 1657 bestm1 = crtc_state->dpll.m1; 1658 bestm2 = crtc_state->dpll.m2 >> 22; 1659 bestp1 = crtc_state->dpll.p1; 1660 bestp2 = crtc_state->dpll.p2; 1661 vco = crtc_state->dpll.vco; 1662 dpio_val = 0; 1663 loopfilter = 0; 1664 1665 vlv_dpio_get(dev_priv); 1666 1667 /* p1 and p2 divider */ 1668 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), 1669 5 << DPIO_CHV_S1_DIV_SHIFT | 1670 bestp1 << DPIO_CHV_P1_DIV_SHIFT | 1671 bestp2 << DPIO_CHV_P2_DIV_SHIFT | 1672 1 << DPIO_CHV_K_DIV_SHIFT); 1673 1674 /* Feedback post-divider - m2 */ 1675 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); 1676 1677 /* Feedback refclk divider - n and m1 */ 1678 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), 1679 DPIO_CHV_M1_DIV_BY_2 | 1680 1 << DPIO_CHV_N_DIV_SHIFT); 1681 1682 /* M2 fraction division */ 1683 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); 1684 1685 /* M2 fraction division enable */ 1686 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 1687 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); 1688 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); 1689 if (bestm2_frac) 1690 dpio_val |= DPIO_CHV_FRAC_DIV_EN; 1691 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); 1692 1693 /* Program digital lock detect threshold */ 1694 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); 1695 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | 1696 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); 1697 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); 1698 if (!bestm2_frac) 1699 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; 1700 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); 1701 1702 /* Loop filter */ 1703 if (vco == 5400000) { 1704 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); 1705 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); 1706 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); 1707 tribuf_calcntr = 0x9; 1708 } else if (vco <= 6200000) { 1709 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); 1710 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); 1711 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1712 tribuf_calcntr = 0x9; 1713 } else if (vco <= 6480000) { 1714 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 1715 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 1716 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1717 tribuf_calcntr = 0x8; 1718 } else { 1719 /* Not supported. Apply the same limits as in the max case */ 1720 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 1721 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 1722 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1723 tribuf_calcntr = 0; 1724 } 1725 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); 1726 1727 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); 1728 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; 1729 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); 1730 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); 1731 1732 /* AFC Recal */ 1733 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), 1734 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | 1735 DPIO_AFC_RECAL); 1736 1737 vlv_dpio_put(dev_priv); 1738 } 1739 1740 static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) 1741 { 1742 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1743 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1744 enum pipe pipe = crtc->pipe; 1745 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1746 u32 tmp; 1747 1748 vlv_dpio_get(dev_priv); 1749 1750 /* Enable back the 10bit clock to display controller */ 1751 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); 1752 tmp |= DPIO_DCLKP_EN; 1753 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); 1754 1755 vlv_dpio_put(dev_priv); 1756 1757 /* 1758 * Need to wait > 100ns between dclkp clock enable bit and PLL enable. 1759 */ 1760 udelay(1); 1761 1762 /* Enable PLL */ 1763 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); 1764 1765 /* Check PLL is locked */ 1766 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) 1767 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); 1768 } 1769 1770 void chv_enable_pll(const struct intel_crtc_state *crtc_state) 1771 { 1772 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1773 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1774 enum pipe pipe = crtc->pipe; 1775 1776 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1777 1778 /* PLL is protected by panel, make sure we can write it */ 1779 assert_pps_unlocked(dev_priv, pipe); 1780 1781 /* Enable Refclk and SSC */ 1782 intel_de_write(dev_priv, DPLL(pipe), 1783 crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); 1784 1785 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { 1786 chv_prepare_pll(crtc_state); 1787 _chv_enable_pll(crtc_state); 1788 } 1789 1790 if (pipe != PIPE_A) { 1791 /* 1792 * WaPixelRepeatModeFixForC0:chv 1793 * 1794 * DPLLCMD is AWOL. Use chicken bits to propagate 1795 * the value from DPLLBMD to either pipe B or C. 1796 */ 1797 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); 1798 intel_de_write(dev_priv, DPLL_MD(PIPE_B), 1799 crtc_state->dpll_hw_state.dpll_md); 1800 intel_de_write(dev_priv, CBR4_VLV, 0); 1801 dev_priv->chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md; 1802 1803 /* 1804 * DPLLB VGA mode also seems to cause problems. 1805 * We should always have it disabled. 1806 */ 1807 drm_WARN_ON(&dev_priv->drm, 1808 (intel_de_read(dev_priv, DPLL(PIPE_B)) & 1809 DPLL_VGA_MODE_DIS) == 0); 1810 } else { 1811 intel_de_write(dev_priv, DPLL_MD(pipe), 1812 crtc_state->dpll_hw_state.dpll_md); 1813 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); 1814 } 1815 } 1816 1817 /** 1818 * vlv_force_pll_on - forcibly enable just the PLL 1819 * @dev_priv: i915 private structure 1820 * @pipe: pipe PLL to enable 1821 * @dpll: PLL configuration 1822 * 1823 * Enable the PLL for @pipe using the supplied @dpll config. To be used 1824 * in cases where we need the PLL enabled even when @pipe is not going to 1825 * be enabled. 1826 */ 1827 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, 1828 const struct dpll *dpll) 1829 { 1830 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 1831 struct intel_crtc_state *crtc_state; 1832 1833 crtc_state = intel_crtc_state_alloc(crtc); 1834 if (!crtc_state) 1835 return -ENOMEM; 1836 1837 crtc_state->cpu_transcoder = (enum transcoder)pipe; 1838 crtc_state->pixel_multiplier = 1; 1839 crtc_state->dpll = *dpll; 1840 crtc_state->output_types = BIT(INTEL_OUTPUT_EDP); 1841 1842 if (IS_CHERRYVIEW(dev_priv)) { 1843 chv_compute_dpll(crtc_state); 1844 chv_enable_pll(crtc_state); 1845 } else { 1846 vlv_compute_dpll(crtc_state); 1847 vlv_enable_pll(crtc_state); 1848 } 1849 1850 kfree(crtc_state); 1851 1852 return 0; 1853 } 1854 1855 void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 1856 { 1857 u32 val; 1858 1859 /* Make sure the pipe isn't still relying on us */ 1860 assert_transcoder_disabled(dev_priv, (enum transcoder)pipe); 1861 1862 val = DPLL_INTEGRATED_REF_CLK_VLV | 1863 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1864 if (pipe != PIPE_A) 1865 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1866 1867 intel_de_write(dev_priv, DPLL(pipe), val); 1868 intel_de_posting_read(dev_priv, DPLL(pipe)); 1869 } 1870 1871 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 1872 { 1873 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1874 u32 val; 1875 1876 /* Make sure the pipe isn't still relying on us */ 1877 assert_transcoder_disabled(dev_priv, (enum transcoder)pipe); 1878 1879 val = DPLL_SSC_REF_CLK_CHV | 1880 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1881 if (pipe != PIPE_A) 1882 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1883 1884 intel_de_write(dev_priv, DPLL(pipe), val); 1885 intel_de_posting_read(dev_priv, DPLL(pipe)); 1886 1887 vlv_dpio_get(dev_priv); 1888 1889 /* Disable 10bit clock to display controller */ 1890 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); 1891 val &= ~DPIO_DCLKP_EN; 1892 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); 1893 1894 vlv_dpio_put(dev_priv); 1895 } 1896 1897 void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) 1898 { 1899 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1900 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1901 enum pipe pipe = crtc->pipe; 1902 1903 /* Don't disable pipe or pipe PLLs if needed */ 1904 if (IS_I830(dev_priv)) 1905 return; 1906 1907 /* Make sure the pipe isn't still relying on us */ 1908 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1909 1910 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 1911 intel_de_posting_read(dev_priv, DPLL(pipe)); 1912 } 1913 1914 1915 /** 1916 * vlv_force_pll_off - forcibly disable just the PLL 1917 * @dev_priv: i915 private structure 1918 * @pipe: pipe PLL to disable 1919 * 1920 * Disable the PLL for @pipe. To be used in cases where we need 1921 * the PLL enabled even when @pipe is not going to be enabled. 1922 */ 1923 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) 1924 { 1925 if (IS_CHERRYVIEW(dev_priv)) 1926 chv_disable_pll(dev_priv, pipe); 1927 else 1928 vlv_disable_pll(dev_priv, pipe); 1929 } 1930 1931 /* Only for pre-ILK configs */ 1932 static void assert_pll(struct drm_i915_private *dev_priv, 1933 enum pipe pipe, bool state) 1934 { 1935 bool cur_state; 1936 1937 cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; 1938 I915_STATE_WARN(cur_state != state, 1939 "PLL state assertion failure (expected %s, current %s)\n", 1940 str_on_off(state), str_on_off(cur_state)); 1941 } 1942 1943 void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe) 1944 { 1945 assert_pll(i915, pipe, true); 1946 } 1947 1948 void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe) 1949 { 1950 assert_pll(i915, pipe, false); 1951 } 1952