1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/string_helpers.h> 8 9 #include "intel_crtc.h" 10 #include "intel_de.h" 11 #include "intel_display.h" 12 #include "intel_display_types.h" 13 #include "intel_dpll.h" 14 #include "intel_lvds.h" 15 #include "intel_panel.h" 16 #include "intel_pps.h" 17 #include "intel_snps_phy.h" 18 #include "vlv_sideband.h" 19 20 struct intel_dpll_funcs { 21 int (*crtc_compute_clock)(struct intel_atomic_state *state, 22 struct intel_crtc *crtc); 23 int (*crtc_get_shared_dpll)(struct intel_atomic_state *state, 24 struct intel_crtc *crtc); 25 }; 26 27 struct intel_limit { 28 struct { 29 int min, max; 30 } dot, vco, n, m, m1, m2, p, p1; 31 32 struct { 33 int dot_limit; 34 int p2_slow, p2_fast; 35 } p2; 36 }; 37 static const struct intel_limit intel_limits_i8xx_dac = { 38 .dot = { .min = 25000, .max = 350000 }, 39 .vco = { .min = 908000, .max = 1512000 }, 40 .n = { .min = 2, .max = 16 }, 41 .m = { .min = 96, .max = 140 }, 42 .m1 = { .min = 18, .max = 26 }, 43 .m2 = { .min = 6, .max = 16 }, 44 .p = { .min = 4, .max = 128 }, 45 .p1 = { .min = 2, .max = 33 }, 46 .p2 = { .dot_limit = 165000, 47 .p2_slow = 4, .p2_fast = 2 }, 48 }; 49 50 static const struct intel_limit intel_limits_i8xx_dvo = { 51 .dot = { .min = 25000, .max = 350000 }, 52 .vco = { .min = 908000, .max = 1512000 }, 53 .n = { .min = 2, .max = 16 }, 54 .m = { .min = 96, .max = 140 }, 55 .m1 = { .min = 18, .max = 26 }, 56 .m2 = { .min = 6, .max = 16 }, 57 .p = { .min = 4, .max = 128 }, 58 .p1 = { .min = 2, .max = 33 }, 59 .p2 = { .dot_limit = 165000, 60 .p2_slow = 4, .p2_fast = 4 }, 61 }; 62 63 static const struct intel_limit intel_limits_i8xx_lvds = { 64 .dot = { .min = 25000, .max = 350000 }, 65 .vco = { .min = 908000, .max = 1512000 }, 66 .n = { .min = 2, .max = 16 }, 67 .m = { .min = 96, .max = 140 }, 68 .m1 = { .min = 18, .max = 26 }, 69 .m2 = { .min = 6, .max = 16 }, 70 .p = { .min = 4, .max = 128 }, 71 .p1 = { .min = 1, .max = 6 }, 72 .p2 = { .dot_limit = 165000, 73 .p2_slow = 14, .p2_fast = 7 }, 74 }; 75 76 static const struct intel_limit intel_limits_i9xx_sdvo = { 77 .dot = { .min = 20000, .max = 400000 }, 78 .vco = { .min = 1400000, .max = 2800000 }, 79 .n = { .min = 1, .max = 6 }, 80 .m = { .min = 70, .max = 120 }, 81 .m1 = { .min = 8, .max = 18 }, 82 .m2 = { .min = 3, .max = 7 }, 83 .p = { .min = 5, .max = 80 }, 84 .p1 = { .min = 1, .max = 8 }, 85 .p2 = { .dot_limit = 200000, 86 .p2_slow = 10, .p2_fast = 5 }, 87 }; 88 89 static const struct intel_limit intel_limits_i9xx_lvds = { 90 .dot = { .min = 20000, .max = 400000 }, 91 .vco = { .min = 1400000, .max = 2800000 }, 92 .n = { .min = 1, .max = 6 }, 93 .m = { .min = 70, .max = 120 }, 94 .m1 = { .min = 8, .max = 18 }, 95 .m2 = { .min = 3, .max = 7 }, 96 .p = { .min = 7, .max = 98 }, 97 .p1 = { .min = 1, .max = 8 }, 98 .p2 = { .dot_limit = 112000, 99 .p2_slow = 14, .p2_fast = 7 }, 100 }; 101 102 103 static const struct intel_limit intel_limits_g4x_sdvo = { 104 .dot = { .min = 25000, .max = 270000 }, 105 .vco = { .min = 1750000, .max = 3500000}, 106 .n = { .min = 1, .max = 4 }, 107 .m = { .min = 104, .max = 138 }, 108 .m1 = { .min = 17, .max = 23 }, 109 .m2 = { .min = 5, .max = 11 }, 110 .p = { .min = 10, .max = 30 }, 111 .p1 = { .min = 1, .max = 3}, 112 .p2 = { .dot_limit = 270000, 113 .p2_slow = 10, 114 .p2_fast = 10 115 }, 116 }; 117 118 static const struct intel_limit intel_limits_g4x_hdmi = { 119 .dot = { .min = 22000, .max = 400000 }, 120 .vco = { .min = 1750000, .max = 3500000}, 121 .n = { .min = 1, .max = 4 }, 122 .m = { .min = 104, .max = 138 }, 123 .m1 = { .min = 16, .max = 23 }, 124 .m2 = { .min = 5, .max = 11 }, 125 .p = { .min = 5, .max = 80 }, 126 .p1 = { .min = 1, .max = 8}, 127 .p2 = { .dot_limit = 165000, 128 .p2_slow = 10, .p2_fast = 5 }, 129 }; 130 131 static const struct intel_limit intel_limits_g4x_single_channel_lvds = { 132 .dot = { .min = 20000, .max = 115000 }, 133 .vco = { .min = 1750000, .max = 3500000 }, 134 .n = { .min = 1, .max = 3 }, 135 .m = { .min = 104, .max = 138 }, 136 .m1 = { .min = 17, .max = 23 }, 137 .m2 = { .min = 5, .max = 11 }, 138 .p = { .min = 28, .max = 112 }, 139 .p1 = { .min = 2, .max = 8 }, 140 .p2 = { .dot_limit = 0, 141 .p2_slow = 14, .p2_fast = 14 142 }, 143 }; 144 145 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { 146 .dot = { .min = 80000, .max = 224000 }, 147 .vco = { .min = 1750000, .max = 3500000 }, 148 .n = { .min = 1, .max = 3 }, 149 .m = { .min = 104, .max = 138 }, 150 .m1 = { .min = 17, .max = 23 }, 151 .m2 = { .min = 5, .max = 11 }, 152 .p = { .min = 14, .max = 42 }, 153 .p1 = { .min = 2, .max = 6 }, 154 .p2 = { .dot_limit = 0, 155 .p2_slow = 7, .p2_fast = 7 156 }, 157 }; 158 159 static const struct intel_limit pnv_limits_sdvo = { 160 .dot = { .min = 20000, .max = 400000}, 161 .vco = { .min = 1700000, .max = 3500000 }, 162 /* Pineview's Ncounter is a ring counter */ 163 .n = { .min = 3, .max = 6 }, 164 .m = { .min = 2, .max = 256 }, 165 /* Pineview only has one combined m divider, which we treat as m2. */ 166 .m1 = { .min = 0, .max = 0 }, 167 .m2 = { .min = 0, .max = 254 }, 168 .p = { .min = 5, .max = 80 }, 169 .p1 = { .min = 1, .max = 8 }, 170 .p2 = { .dot_limit = 200000, 171 .p2_slow = 10, .p2_fast = 5 }, 172 }; 173 174 static const struct intel_limit pnv_limits_lvds = { 175 .dot = { .min = 20000, .max = 400000 }, 176 .vco = { .min = 1700000, .max = 3500000 }, 177 .n = { .min = 3, .max = 6 }, 178 .m = { .min = 2, .max = 256 }, 179 .m1 = { .min = 0, .max = 0 }, 180 .m2 = { .min = 0, .max = 254 }, 181 .p = { .min = 7, .max = 112 }, 182 .p1 = { .min = 1, .max = 8 }, 183 .p2 = { .dot_limit = 112000, 184 .p2_slow = 14, .p2_fast = 14 }, 185 }; 186 187 /* Ironlake / Sandybridge 188 * 189 * We calculate clock using (register_value + 2) for N/M1/M2, so here 190 * the range value for them is (actual_value - 2). 191 */ 192 static const struct intel_limit ilk_limits_dac = { 193 .dot = { .min = 25000, .max = 350000 }, 194 .vco = { .min = 1760000, .max = 3510000 }, 195 .n = { .min = 1, .max = 5 }, 196 .m = { .min = 79, .max = 127 }, 197 .m1 = { .min = 12, .max = 22 }, 198 .m2 = { .min = 5, .max = 9 }, 199 .p = { .min = 5, .max = 80 }, 200 .p1 = { .min = 1, .max = 8 }, 201 .p2 = { .dot_limit = 225000, 202 .p2_slow = 10, .p2_fast = 5 }, 203 }; 204 205 static const struct intel_limit ilk_limits_single_lvds = { 206 .dot = { .min = 25000, .max = 350000 }, 207 .vco = { .min = 1760000, .max = 3510000 }, 208 .n = { .min = 1, .max = 3 }, 209 .m = { .min = 79, .max = 118 }, 210 .m1 = { .min = 12, .max = 22 }, 211 .m2 = { .min = 5, .max = 9 }, 212 .p = { .min = 28, .max = 112 }, 213 .p1 = { .min = 2, .max = 8 }, 214 .p2 = { .dot_limit = 225000, 215 .p2_slow = 14, .p2_fast = 14 }, 216 }; 217 218 static const struct intel_limit ilk_limits_dual_lvds = { 219 .dot = { .min = 25000, .max = 350000 }, 220 .vco = { .min = 1760000, .max = 3510000 }, 221 .n = { .min = 1, .max = 3 }, 222 .m = { .min = 79, .max = 127 }, 223 .m1 = { .min = 12, .max = 22 }, 224 .m2 = { .min = 5, .max = 9 }, 225 .p = { .min = 14, .max = 56 }, 226 .p1 = { .min = 2, .max = 8 }, 227 .p2 = { .dot_limit = 225000, 228 .p2_slow = 7, .p2_fast = 7 }, 229 }; 230 231 /* LVDS 100mhz refclk limits. */ 232 static const struct intel_limit ilk_limits_single_lvds_100m = { 233 .dot = { .min = 25000, .max = 350000 }, 234 .vco = { .min = 1760000, .max = 3510000 }, 235 .n = { .min = 1, .max = 2 }, 236 .m = { .min = 79, .max = 126 }, 237 .m1 = { .min = 12, .max = 22 }, 238 .m2 = { .min = 5, .max = 9 }, 239 .p = { .min = 28, .max = 112 }, 240 .p1 = { .min = 2, .max = 8 }, 241 .p2 = { .dot_limit = 225000, 242 .p2_slow = 14, .p2_fast = 14 }, 243 }; 244 245 static const struct intel_limit ilk_limits_dual_lvds_100m = { 246 .dot = { .min = 25000, .max = 350000 }, 247 .vco = { .min = 1760000, .max = 3510000 }, 248 .n = { .min = 1, .max = 3 }, 249 .m = { .min = 79, .max = 126 }, 250 .m1 = { .min = 12, .max = 22 }, 251 .m2 = { .min = 5, .max = 9 }, 252 .p = { .min = 14, .max = 42 }, 253 .p1 = { .min = 2, .max = 6 }, 254 .p2 = { .dot_limit = 225000, 255 .p2_slow = 7, .p2_fast = 7 }, 256 }; 257 258 static const struct intel_limit intel_limits_vlv = { 259 /* 260 * These are based on the data rate limits (measured in fast clocks) 261 * since those are the strictest limits we have. The fast 262 * clock and actual rate limits are more relaxed, so checking 263 * them would make no difference. 264 */ 265 .dot = { .min = 25000, .max = 270000 }, 266 .vco = { .min = 4000000, .max = 6000000 }, 267 .n = { .min = 1, .max = 7 }, 268 .m1 = { .min = 2, .max = 3 }, 269 .m2 = { .min = 11, .max = 156 }, 270 .p1 = { .min = 2, .max = 3 }, 271 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ 272 }; 273 274 static const struct intel_limit intel_limits_chv = { 275 /* 276 * These are based on the data rate limits (measured in fast clocks) 277 * since those are the strictest limits we have. The fast 278 * clock and actual rate limits are more relaxed, so checking 279 * them would make no difference. 280 */ 281 .dot = { .min = 25000, .max = 540000 }, 282 .vco = { .min = 4800000, .max = 6480000 }, 283 .n = { .min = 1, .max = 1 }, 284 .m1 = { .min = 2, .max = 2 }, 285 .m2 = { .min = 24 << 22, .max = 175 << 22 }, 286 .p1 = { .min = 2, .max = 4 }, 287 .p2 = { .p2_slow = 1, .p2_fast = 14 }, 288 }; 289 290 static const struct intel_limit intel_limits_bxt = { 291 .dot = { .min = 25000, .max = 594000 }, 292 .vco = { .min = 4800000, .max = 6700000 }, 293 .n = { .min = 1, .max = 1 }, 294 .m1 = { .min = 2, .max = 2 }, 295 /* FIXME: find real m2 limits */ 296 .m2 = { .min = 2 << 22, .max = 255 << 22 }, 297 .p1 = { .min = 2, .max = 4 }, 298 .p2 = { .p2_slow = 1, .p2_fast = 20 }, 299 }; 300 301 /* 302 * Platform specific helpers to calculate the port PLL loopback- (clock.m), 303 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast 304 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. 305 * The helpers' return value is the rate of the clock that is fed to the 306 * display engine's pipe which can be the above fast dot clock rate or a 307 * divided-down version of it. 308 */ 309 /* m1 is reserved as 0 in Pineview, n is a ring counter */ 310 int pnv_calc_dpll_params(int refclk, struct dpll *clock) 311 { 312 clock->m = clock->m2 + 2; 313 clock->p = clock->p1 * clock->p2; 314 if (WARN_ON(clock->n == 0 || clock->p == 0)) 315 return 0; 316 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 317 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 318 319 return clock->dot; 320 } 321 322 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) 323 { 324 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); 325 } 326 327 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) 328 { 329 clock->m = i9xx_dpll_compute_m(clock); 330 clock->p = clock->p1 * clock->p2; 331 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) 332 return 0; 333 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); 334 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 335 336 return clock->dot; 337 } 338 339 int vlv_calc_dpll_params(int refclk, struct dpll *clock) 340 { 341 clock->m = clock->m1 * clock->m2; 342 clock->p = clock->p1 * clock->p2 * 5; 343 if (WARN_ON(clock->n == 0 || clock->p == 0)) 344 return 0; 345 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 346 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 347 348 return clock->dot; 349 } 350 351 int chv_calc_dpll_params(int refclk, struct dpll *clock) 352 { 353 clock->m = clock->m1 * clock->m2; 354 clock->p = clock->p1 * clock->p2 * 5; 355 if (WARN_ON(clock->n == 0 || clock->p == 0)) 356 return 0; 357 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), 358 clock->n << 22); 359 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 360 361 return clock->dot; 362 } 363 364 /* 365 * Returns whether the given set of divisors are valid for a given refclk with 366 * the given connectors. 367 */ 368 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv, 369 const struct intel_limit *limit, 370 const struct dpll *clock) 371 { 372 if (clock->n < limit->n.min || limit->n.max < clock->n) 373 return false; 374 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 375 return false; 376 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 377 return false; 378 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 379 return false; 380 381 if (!IS_PINEVIEW(dev_priv) && !IS_LP(dev_priv)) 382 if (clock->m1 <= clock->m2) 383 return false; 384 385 if (!IS_LP(dev_priv)) { 386 if (clock->p < limit->p.min || limit->p.max < clock->p) 387 return false; 388 if (clock->m < limit->m.min || limit->m.max < clock->m) 389 return false; 390 } 391 392 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 393 return false; 394 /* XXX: We may need to be checking "Dot clock" depending on the multiplier, 395 * connector, etc., rather than just a single range. 396 */ 397 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 398 return false; 399 400 return true; 401 } 402 403 static int 404 i9xx_select_p2_div(const struct intel_limit *limit, 405 const struct intel_crtc_state *crtc_state, 406 int target) 407 { 408 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 409 410 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 411 /* 412 * For LVDS just rely on its current settings for dual-channel. 413 * We haven't figured out how to reliably set up different 414 * single/dual channel state, if we even can. 415 */ 416 if (intel_is_dual_link_lvds(dev_priv)) 417 return limit->p2.p2_fast; 418 else 419 return limit->p2.p2_slow; 420 } else { 421 if (target < limit->p2.dot_limit) 422 return limit->p2.p2_slow; 423 else 424 return limit->p2.p2_fast; 425 } 426 } 427 428 /* 429 * Returns a set of divisors for the desired target clock with the given 430 * refclk, or FALSE. 431 * 432 * Target and reference clocks are specified in kHz. 433 * 434 * If match_clock is provided, then best_clock P divider must match the P 435 * divider from @match_clock used for LVDS downclocking. 436 */ 437 static bool 438 i9xx_find_best_dpll(const struct intel_limit *limit, 439 struct intel_crtc_state *crtc_state, 440 int target, int refclk, 441 const struct dpll *match_clock, 442 struct dpll *best_clock) 443 { 444 struct drm_device *dev = crtc_state->uapi.crtc->dev; 445 struct dpll clock; 446 int err = target; 447 448 memset(best_clock, 0, sizeof(*best_clock)); 449 450 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 451 452 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 453 clock.m1++) { 454 for (clock.m2 = limit->m2.min; 455 clock.m2 <= limit->m2.max; clock.m2++) { 456 if (clock.m2 >= clock.m1) 457 break; 458 for (clock.n = limit->n.min; 459 clock.n <= limit->n.max; clock.n++) { 460 for (clock.p1 = limit->p1.min; 461 clock.p1 <= limit->p1.max; clock.p1++) { 462 int this_err; 463 464 i9xx_calc_dpll_params(refclk, &clock); 465 if (!intel_pll_is_valid(to_i915(dev), 466 limit, 467 &clock)) 468 continue; 469 if (match_clock && 470 clock.p != match_clock->p) 471 continue; 472 473 this_err = abs(clock.dot - target); 474 if (this_err < err) { 475 *best_clock = clock; 476 err = this_err; 477 } 478 } 479 } 480 } 481 } 482 483 return (err != target); 484 } 485 486 /* 487 * Returns a set of divisors for the desired target clock with the given 488 * refclk, or FALSE. 489 * 490 * Target and reference clocks are specified in kHz. 491 * 492 * If match_clock is provided, then best_clock P divider must match the P 493 * divider from @match_clock used for LVDS downclocking. 494 */ 495 static bool 496 pnv_find_best_dpll(const struct intel_limit *limit, 497 struct intel_crtc_state *crtc_state, 498 int target, int refclk, 499 const struct dpll *match_clock, 500 struct dpll *best_clock) 501 { 502 struct drm_device *dev = crtc_state->uapi.crtc->dev; 503 struct dpll clock; 504 int err = target; 505 506 memset(best_clock, 0, sizeof(*best_clock)); 507 508 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 509 510 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 511 clock.m1++) { 512 for (clock.m2 = limit->m2.min; 513 clock.m2 <= limit->m2.max; clock.m2++) { 514 for (clock.n = limit->n.min; 515 clock.n <= limit->n.max; clock.n++) { 516 for (clock.p1 = limit->p1.min; 517 clock.p1 <= limit->p1.max; clock.p1++) { 518 int this_err; 519 520 pnv_calc_dpll_params(refclk, &clock); 521 if (!intel_pll_is_valid(to_i915(dev), 522 limit, 523 &clock)) 524 continue; 525 if (match_clock && 526 clock.p != match_clock->p) 527 continue; 528 529 this_err = abs(clock.dot - target); 530 if (this_err < err) { 531 *best_clock = clock; 532 err = this_err; 533 } 534 } 535 } 536 } 537 } 538 539 return (err != target); 540 } 541 542 /* 543 * Returns a set of divisors for the desired target clock with the given 544 * refclk, or FALSE. 545 * 546 * Target and reference clocks are specified in kHz. 547 * 548 * If match_clock is provided, then best_clock P divider must match the P 549 * divider from @match_clock used for LVDS downclocking. 550 */ 551 static bool 552 g4x_find_best_dpll(const struct intel_limit *limit, 553 struct intel_crtc_state *crtc_state, 554 int target, int refclk, 555 const struct dpll *match_clock, 556 struct dpll *best_clock) 557 { 558 struct drm_device *dev = crtc_state->uapi.crtc->dev; 559 struct dpll clock; 560 int max_n; 561 bool found = false; 562 /* approximately equals target * 0.00585 */ 563 int err_most = (target >> 8) + (target >> 9); 564 565 memset(best_clock, 0, sizeof(*best_clock)); 566 567 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 568 569 max_n = limit->n.max; 570 /* based on hardware requirement, prefer smaller n to precision */ 571 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 572 /* based on hardware requirement, prefere larger m1,m2 */ 573 for (clock.m1 = limit->m1.max; 574 clock.m1 >= limit->m1.min; clock.m1--) { 575 for (clock.m2 = limit->m2.max; 576 clock.m2 >= limit->m2.min; clock.m2--) { 577 for (clock.p1 = limit->p1.max; 578 clock.p1 >= limit->p1.min; clock.p1--) { 579 int this_err; 580 581 i9xx_calc_dpll_params(refclk, &clock); 582 if (!intel_pll_is_valid(to_i915(dev), 583 limit, 584 &clock)) 585 continue; 586 587 this_err = abs(clock.dot - target); 588 if (this_err < err_most) { 589 *best_clock = clock; 590 err_most = this_err; 591 max_n = clock.n; 592 found = true; 593 } 594 } 595 } 596 } 597 } 598 return found; 599 } 600 601 /* 602 * Check if the calculated PLL configuration is more optimal compared to the 603 * best configuration and error found so far. Return the calculated error. 604 */ 605 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, 606 const struct dpll *calculated_clock, 607 const struct dpll *best_clock, 608 unsigned int best_error_ppm, 609 unsigned int *error_ppm) 610 { 611 /* 612 * For CHV ignore the error and consider only the P value. 613 * Prefer a bigger P value based on HW requirements. 614 */ 615 if (IS_CHERRYVIEW(to_i915(dev))) { 616 *error_ppm = 0; 617 618 return calculated_clock->p > best_clock->p; 619 } 620 621 if (drm_WARN_ON_ONCE(dev, !target_freq)) 622 return false; 623 624 *error_ppm = div_u64(1000000ULL * 625 abs(target_freq - calculated_clock->dot), 626 target_freq); 627 /* 628 * Prefer a better P value over a better (smaller) error if the error 629 * is small. Ensure this preference for future configurations too by 630 * setting the error to 0. 631 */ 632 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { 633 *error_ppm = 0; 634 635 return true; 636 } 637 638 return *error_ppm + 10 < best_error_ppm; 639 } 640 641 /* 642 * Returns a set of divisors for the desired target clock with the given 643 * refclk, or FALSE. 644 */ 645 static bool 646 vlv_find_best_dpll(const struct intel_limit *limit, 647 struct intel_crtc_state *crtc_state, 648 int target, int refclk, 649 const struct dpll *match_clock, 650 struct dpll *best_clock) 651 { 652 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 653 struct drm_device *dev = crtc->base.dev; 654 struct dpll clock; 655 unsigned int bestppm = 1000000; 656 /* min update 19.2 MHz */ 657 int max_n = min(limit->n.max, refclk / 19200); 658 bool found = false; 659 660 memset(best_clock, 0, sizeof(*best_clock)); 661 662 /* based on hardware requirement, prefer smaller n to precision */ 663 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 664 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 665 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; 666 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 667 clock.p = clock.p1 * clock.p2 * 5; 668 /* based on hardware requirement, prefer bigger m1,m2 values */ 669 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { 670 unsigned int ppm; 671 672 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, 673 refclk * clock.m1); 674 675 vlv_calc_dpll_params(refclk, &clock); 676 677 if (!intel_pll_is_valid(to_i915(dev), 678 limit, 679 &clock)) 680 continue; 681 682 if (!vlv_PLL_is_optimal(dev, target, 683 &clock, 684 best_clock, 685 bestppm, &ppm)) 686 continue; 687 688 *best_clock = clock; 689 bestppm = ppm; 690 found = true; 691 } 692 } 693 } 694 } 695 696 return found; 697 } 698 699 /* 700 * Returns a set of divisors for the desired target clock with the given 701 * refclk, or FALSE. 702 */ 703 static bool 704 chv_find_best_dpll(const struct intel_limit *limit, 705 struct intel_crtc_state *crtc_state, 706 int target, int refclk, 707 const struct dpll *match_clock, 708 struct dpll *best_clock) 709 { 710 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 711 struct drm_device *dev = crtc->base.dev; 712 unsigned int best_error_ppm; 713 struct dpll clock; 714 u64 m2; 715 int found = false; 716 717 memset(best_clock, 0, sizeof(*best_clock)); 718 best_error_ppm = 1000000; 719 720 /* 721 * Based on hardware doc, the n always set to 1, and m1 always 722 * set to 2. If requires to support 200Mhz refclk, we need to 723 * revisit this because n may not 1 anymore. 724 */ 725 clock.n = 1; 726 clock.m1 = 2; 727 728 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 729 for (clock.p2 = limit->p2.p2_fast; 730 clock.p2 >= limit->p2.p2_slow; 731 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 732 unsigned int error_ppm; 733 734 clock.p = clock.p1 * clock.p2 * 5; 735 736 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22, 737 refclk * clock.m1); 738 739 if (m2 > INT_MAX/clock.m1) 740 continue; 741 742 clock.m2 = m2; 743 744 chv_calc_dpll_params(refclk, &clock); 745 746 if (!intel_pll_is_valid(to_i915(dev), limit, &clock)) 747 continue; 748 749 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, 750 best_error_ppm, &error_ppm)) 751 continue; 752 753 *best_clock = clock; 754 best_error_ppm = error_ppm; 755 found = true; 756 } 757 } 758 759 return found; 760 } 761 762 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, 763 struct dpll *best_clock) 764 { 765 const struct intel_limit *limit = &intel_limits_bxt; 766 int refclk = 100000; 767 768 return chv_find_best_dpll(limit, crtc_state, 769 crtc_state->port_clock, refclk, 770 NULL, best_clock); 771 } 772 773 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) 774 { 775 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; 776 } 777 778 static u32 pnv_dpll_compute_fp(const struct dpll *dpll) 779 { 780 return (1 << dpll->n) << 16 | dpll->m2; 781 } 782 783 static void i9xx_update_pll_dividers(struct intel_crtc_state *crtc_state, 784 const struct dpll *clock, 785 const struct dpll *reduced_clock) 786 { 787 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 788 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 789 u32 fp, fp2; 790 791 if (IS_PINEVIEW(dev_priv)) { 792 fp = pnv_dpll_compute_fp(clock); 793 fp2 = pnv_dpll_compute_fp(reduced_clock); 794 } else { 795 fp = i9xx_dpll_compute_fp(clock); 796 fp2 = i9xx_dpll_compute_fp(reduced_clock); 797 } 798 799 crtc_state->dpll_hw_state.fp0 = fp; 800 crtc_state->dpll_hw_state.fp1 = fp2; 801 } 802 803 static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, 804 const struct dpll *clock, 805 const struct dpll *reduced_clock) 806 { 807 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 808 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 809 u32 dpll; 810 811 i9xx_update_pll_dividers(crtc_state, clock, reduced_clock); 812 813 dpll = DPLL_VGA_MODE_DIS; 814 815 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) 816 dpll |= DPLLB_MODE_LVDS; 817 else 818 dpll |= DPLLB_MODE_DAC_SERIAL; 819 820 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 821 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 822 dpll |= (crtc_state->pixel_multiplier - 1) 823 << SDVO_MULTIPLIER_SHIFT_HIRES; 824 } 825 826 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || 827 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 828 dpll |= DPLL_SDVO_HIGH_SPEED; 829 830 if (intel_crtc_has_dp_encoder(crtc_state)) 831 dpll |= DPLL_SDVO_HIGH_SPEED; 832 833 /* compute bitmask from p1 value */ 834 if (IS_G4X(dev_priv)) { 835 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 836 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 837 } else if (IS_PINEVIEW(dev_priv)) { 838 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; 839 WARN_ON(reduced_clock->p1 != clock->p1); 840 } else { 841 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 842 WARN_ON(reduced_clock->p1 != clock->p1); 843 } 844 845 switch (clock->p2) { 846 case 5: 847 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 848 break; 849 case 7: 850 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 851 break; 852 case 10: 853 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 854 break; 855 case 14: 856 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 857 break; 858 } 859 WARN_ON(reduced_clock->p2 != clock->p2); 860 861 if (DISPLAY_VER(dev_priv) >= 4) 862 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 863 864 if (crtc_state->sdvo_tv_clock) 865 dpll |= PLL_REF_INPUT_TVCLKINBC; 866 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 867 intel_panel_use_ssc(dev_priv)) 868 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 869 else 870 dpll |= PLL_REF_INPUT_DREFCLK; 871 872 dpll |= DPLL_VCO_ENABLE; 873 crtc_state->dpll_hw_state.dpll = dpll; 874 875 if (DISPLAY_VER(dev_priv) >= 4) { 876 u32 dpll_md = (crtc_state->pixel_multiplier - 1) 877 << DPLL_MD_UDI_MULTIPLIER_SHIFT; 878 crtc_state->dpll_hw_state.dpll_md = dpll_md; 879 } 880 } 881 882 static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state, 883 const struct dpll *clock, 884 const struct dpll *reduced_clock) 885 { 886 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 887 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 888 u32 dpll; 889 890 i9xx_update_pll_dividers(crtc_state, clock, reduced_clock); 891 892 dpll = DPLL_VGA_MODE_DIS; 893 894 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 895 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 896 } else { 897 if (clock->p1 == 2) 898 dpll |= PLL_P1_DIVIDE_BY_TWO; 899 else 900 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; 901 if (clock->p2 == 4) 902 dpll |= PLL_P2_DIVIDE_BY_4; 903 } 904 WARN_ON(reduced_clock->p1 != clock->p1); 905 WARN_ON(reduced_clock->p2 != clock->p2); 906 907 /* 908 * Bspec: 909 * "[Almador Errata}: For the correct operation of the muxed DVO pins 910 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, 911 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock 912 * Enable) must be set to “1” in both the DPLL A Control Register 913 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." 914 * 915 * For simplicity We simply keep both bits always enabled in 916 * both DPLLS. The spec says we should disable the DVO 2X clock 917 * when not needed, but this seems to work fine in practice. 918 */ 919 if (IS_I830(dev_priv) || 920 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) 921 dpll |= DPLL_DVO_2X_MODE; 922 923 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 924 intel_panel_use_ssc(dev_priv)) 925 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 926 else 927 dpll |= PLL_REF_INPUT_DREFCLK; 928 929 dpll |= DPLL_VCO_ENABLE; 930 crtc_state->dpll_hw_state.dpll = dpll; 931 } 932 933 static int hsw_crtc_compute_clock(struct intel_atomic_state *state, 934 struct intel_crtc *crtc) 935 { 936 return 0; 937 } 938 939 static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state, 940 struct intel_crtc *crtc) 941 { 942 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 943 struct intel_crtc_state *crtc_state = 944 intel_atomic_get_new_crtc_state(state, crtc); 945 struct intel_encoder *encoder = 946 intel_get_crtc_new_encoder(state, crtc_state); 947 int ret; 948 949 if (DISPLAY_VER(dev_priv) < 11 && 950 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 951 return 0; 952 953 ret = intel_reserve_shared_dplls(state, crtc, encoder); 954 if (ret) { 955 drm_dbg_kms(&dev_priv->drm, 956 "failed to find PLL for pipe %c\n", 957 pipe_name(crtc->pipe)); 958 return ret; 959 } 960 961 return 0; 962 } 963 964 static int dg2_crtc_compute_clock(struct intel_atomic_state *state, 965 struct intel_crtc *crtc) 966 { 967 struct intel_crtc_state *crtc_state = 968 intel_atomic_get_new_crtc_state(state, crtc); 969 struct intel_encoder *encoder = 970 intel_get_crtc_new_encoder(state, crtc_state); 971 972 return intel_mpllb_calc_state(crtc_state, encoder); 973 } 974 975 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) 976 { 977 return dpll->m < factor * dpll->n; 978 } 979 980 static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state, 981 const struct dpll *clock, 982 const struct dpll *reduced_clock) 983 { 984 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 985 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 986 u32 fp, fp2; 987 int factor; 988 989 /* Enable autotuning of the PLL clock (if permissible) */ 990 factor = 21; 991 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 992 if ((intel_panel_use_ssc(dev_priv) && 993 dev_priv->vbt.lvds_ssc_freq == 100000) || 994 (HAS_PCH_IBX(dev_priv) && 995 intel_is_dual_link_lvds(dev_priv))) 996 factor = 25; 997 } else if (crtc_state->sdvo_tv_clock) { 998 factor = 20; 999 } 1000 1001 fp = i9xx_dpll_compute_fp(clock); 1002 if (ilk_needs_fb_cb_tune(clock, factor)) 1003 fp |= FP_CB_TUNE; 1004 1005 fp2 = i9xx_dpll_compute_fp(reduced_clock); 1006 if (ilk_needs_fb_cb_tune(reduced_clock, factor)) 1007 fp2 |= FP_CB_TUNE; 1008 1009 crtc_state->dpll_hw_state.fp0 = fp; 1010 crtc_state->dpll_hw_state.fp1 = fp2; 1011 } 1012 1013 static void ilk_compute_dpll(struct intel_crtc_state *crtc_state, 1014 const struct dpll *clock, 1015 const struct dpll *reduced_clock) 1016 { 1017 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1018 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1019 u32 dpll; 1020 1021 ilk_update_pll_dividers(crtc_state, clock, reduced_clock); 1022 1023 dpll = 0; 1024 1025 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) 1026 dpll |= DPLLB_MODE_LVDS; 1027 else 1028 dpll |= DPLLB_MODE_DAC_SERIAL; 1029 1030 dpll |= (crtc_state->pixel_multiplier - 1) 1031 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 1032 1033 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || 1034 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1035 dpll |= DPLL_SDVO_HIGH_SPEED; 1036 1037 if (intel_crtc_has_dp_encoder(crtc_state)) 1038 dpll |= DPLL_SDVO_HIGH_SPEED; 1039 1040 /* 1041 * The high speed IO clock is only really required for 1042 * SDVO/HDMI/DP, but we also enable it for CRT to make it 1043 * possible to share the DPLL between CRT and HDMI. Enabling 1044 * the clock needlessly does no real harm, except use up a 1045 * bit of power potentially. 1046 * 1047 * We'll limit this to IVB with 3 pipes, since it has only two 1048 * DPLLs and so DPLL sharing is the only way to get three pipes 1049 * driving PCH ports at the same time. On SNB we could do this, 1050 * and potentially avoid enabling the second DPLL, but it's not 1051 * clear if it''s a win or loss power wise. No point in doing 1052 * this on ILK at all since it has a fixed DPLL<->pipe mapping. 1053 */ 1054 if (INTEL_NUM_PIPES(dev_priv) == 3 && 1055 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1056 dpll |= DPLL_SDVO_HIGH_SPEED; 1057 1058 /* compute bitmask from p1 value */ 1059 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 1060 /* also FPA1 */ 1061 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 1062 1063 switch (clock->p2) { 1064 case 5: 1065 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 1066 break; 1067 case 7: 1068 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 1069 break; 1070 case 10: 1071 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 1072 break; 1073 case 14: 1074 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 1075 break; 1076 } 1077 WARN_ON(reduced_clock->p2 != clock->p2); 1078 1079 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 1080 intel_panel_use_ssc(dev_priv)) 1081 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 1082 else 1083 dpll |= PLL_REF_INPUT_DREFCLK; 1084 1085 dpll |= DPLL_VCO_ENABLE; 1086 1087 crtc_state->dpll_hw_state.dpll = dpll; 1088 } 1089 1090 static int ilk_crtc_compute_clock(struct intel_atomic_state *state, 1091 struct intel_crtc *crtc) 1092 { 1093 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1094 struct intel_crtc_state *crtc_state = 1095 intel_atomic_get_new_crtc_state(state, crtc); 1096 const struct intel_limit *limit; 1097 int refclk = 120000; 1098 1099 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 1100 if (!crtc_state->has_pch_encoder) 1101 return 0; 1102 1103 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1104 if (intel_panel_use_ssc(dev_priv)) { 1105 drm_dbg_kms(&dev_priv->drm, 1106 "using SSC reference clock of %d kHz\n", 1107 dev_priv->vbt.lvds_ssc_freq); 1108 refclk = dev_priv->vbt.lvds_ssc_freq; 1109 } 1110 1111 if (intel_is_dual_link_lvds(dev_priv)) { 1112 if (refclk == 100000) 1113 limit = &ilk_limits_dual_lvds_100m; 1114 else 1115 limit = &ilk_limits_dual_lvds; 1116 } else { 1117 if (refclk == 100000) 1118 limit = &ilk_limits_single_lvds_100m; 1119 else 1120 limit = &ilk_limits_single_lvds; 1121 } 1122 } else { 1123 limit = &ilk_limits_dac; 1124 } 1125 1126 if (!crtc_state->clock_set && 1127 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1128 refclk, NULL, &crtc_state->dpll)) { 1129 drm_err(&dev_priv->drm, 1130 "Couldn't find PLL settings for mode!\n"); 1131 return -EINVAL; 1132 } 1133 1134 ilk_compute_dpll(crtc_state, &crtc_state->dpll, 1135 &crtc_state->dpll); 1136 1137 return 0; 1138 } 1139 1140 static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state, 1141 struct intel_crtc *crtc) 1142 { 1143 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1144 struct intel_crtc_state *crtc_state = 1145 intel_atomic_get_new_crtc_state(state, crtc); 1146 int ret; 1147 1148 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 1149 if (!crtc_state->has_pch_encoder) 1150 return 0; 1151 1152 ret = intel_reserve_shared_dplls(state, crtc, NULL); 1153 if (ret) { 1154 drm_dbg_kms(&dev_priv->drm, 1155 "failed to find PLL for pipe %c\n", 1156 pipe_name(crtc->pipe)); 1157 return ret; 1158 } 1159 1160 return 0; 1161 } 1162 1163 void vlv_compute_dpll(struct intel_crtc_state *crtc_state) 1164 { 1165 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1166 1167 crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | 1168 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1169 if (crtc->pipe != PIPE_A) 1170 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 1171 1172 /* DPLL not used with DSI, but still need the rest set up */ 1173 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1174 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | 1175 DPLL_EXT_BUFFER_ENABLE_VLV; 1176 1177 crtc_state->dpll_hw_state.dpll_md = 1178 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 1179 } 1180 1181 void chv_compute_dpll(struct intel_crtc_state *crtc_state) 1182 { 1183 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1184 1185 crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | 1186 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1187 if (crtc->pipe != PIPE_A) 1188 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 1189 1190 /* DPLL not used with DSI, but still need the rest set up */ 1191 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1192 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; 1193 1194 crtc_state->dpll_hw_state.dpll_md = 1195 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 1196 } 1197 1198 static int chv_crtc_compute_clock(struct intel_atomic_state *state, 1199 struct intel_crtc *crtc) 1200 { 1201 struct drm_i915_private *i915 = to_i915(state->base.dev); 1202 struct intel_crtc_state *crtc_state = 1203 intel_atomic_get_new_crtc_state(state, crtc); 1204 const struct intel_limit *limit = &intel_limits_chv; 1205 int refclk = 100000; 1206 1207 if (!crtc_state->clock_set && 1208 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1209 refclk, NULL, &crtc_state->dpll)) { 1210 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); 1211 return -EINVAL; 1212 } 1213 1214 chv_compute_dpll(crtc_state); 1215 1216 return 0; 1217 } 1218 1219 static int vlv_crtc_compute_clock(struct intel_atomic_state *state, 1220 struct intel_crtc *crtc) 1221 { 1222 struct drm_i915_private *i915 = to_i915(state->base.dev); 1223 struct intel_crtc_state *crtc_state = 1224 intel_atomic_get_new_crtc_state(state, crtc); 1225 const struct intel_limit *limit = &intel_limits_vlv; 1226 int refclk = 100000; 1227 1228 if (!crtc_state->clock_set && 1229 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1230 refclk, NULL, &crtc_state->dpll)) { 1231 drm_err(&i915->drm, "Couldn't find PLL settings for mode!\n"); 1232 return -EINVAL; 1233 } 1234 1235 vlv_compute_dpll(crtc_state); 1236 1237 return 0; 1238 } 1239 1240 static int g4x_crtc_compute_clock(struct intel_atomic_state *state, 1241 struct intel_crtc *crtc) 1242 { 1243 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1244 struct intel_crtc_state *crtc_state = 1245 intel_atomic_get_new_crtc_state(state, crtc); 1246 const struct intel_limit *limit; 1247 int refclk = 96000; 1248 1249 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1250 if (intel_panel_use_ssc(dev_priv)) { 1251 refclk = dev_priv->vbt.lvds_ssc_freq; 1252 drm_dbg_kms(&dev_priv->drm, 1253 "using SSC reference clock of %d kHz\n", 1254 refclk); 1255 } 1256 1257 if (intel_is_dual_link_lvds(dev_priv)) 1258 limit = &intel_limits_g4x_dual_channel_lvds; 1259 else 1260 limit = &intel_limits_g4x_single_channel_lvds; 1261 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || 1262 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1263 limit = &intel_limits_g4x_hdmi; 1264 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { 1265 limit = &intel_limits_g4x_sdvo; 1266 } else { 1267 /* The option is for other outputs */ 1268 limit = &intel_limits_i9xx_sdvo; 1269 } 1270 1271 if (!crtc_state->clock_set && 1272 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1273 refclk, NULL, &crtc_state->dpll)) { 1274 drm_err(&dev_priv->drm, 1275 "Couldn't find PLL settings for mode!\n"); 1276 return -EINVAL; 1277 } 1278 1279 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, 1280 &crtc_state->dpll); 1281 1282 return 0; 1283 } 1284 1285 static int pnv_crtc_compute_clock(struct intel_atomic_state *state, 1286 struct intel_crtc *crtc) 1287 { 1288 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1289 struct intel_crtc_state *crtc_state = 1290 intel_atomic_get_new_crtc_state(state, crtc); 1291 const struct intel_limit *limit; 1292 int refclk = 96000; 1293 1294 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1295 if (intel_panel_use_ssc(dev_priv)) { 1296 refclk = dev_priv->vbt.lvds_ssc_freq; 1297 drm_dbg_kms(&dev_priv->drm, 1298 "using SSC reference clock of %d kHz\n", 1299 refclk); 1300 } 1301 1302 limit = &pnv_limits_lvds; 1303 } else { 1304 limit = &pnv_limits_sdvo; 1305 } 1306 1307 if (!crtc_state->clock_set && 1308 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1309 refclk, NULL, &crtc_state->dpll)) { 1310 drm_err(&dev_priv->drm, 1311 "Couldn't find PLL settings for mode!\n"); 1312 return -EINVAL; 1313 } 1314 1315 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, 1316 &crtc_state->dpll); 1317 1318 return 0; 1319 } 1320 1321 static int i9xx_crtc_compute_clock(struct intel_atomic_state *state, 1322 struct intel_crtc *crtc) 1323 { 1324 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1325 struct intel_crtc_state *crtc_state = 1326 intel_atomic_get_new_crtc_state(state, crtc); 1327 const struct intel_limit *limit; 1328 int refclk = 96000; 1329 1330 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1331 if (intel_panel_use_ssc(dev_priv)) { 1332 refclk = dev_priv->vbt.lvds_ssc_freq; 1333 drm_dbg_kms(&dev_priv->drm, 1334 "using SSC reference clock of %d kHz\n", 1335 refclk); 1336 } 1337 1338 limit = &intel_limits_i9xx_lvds; 1339 } else { 1340 limit = &intel_limits_i9xx_sdvo; 1341 } 1342 1343 if (!crtc_state->clock_set && 1344 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1345 refclk, NULL, &crtc_state->dpll)) { 1346 drm_err(&dev_priv->drm, 1347 "Couldn't find PLL settings for mode!\n"); 1348 return -EINVAL; 1349 } 1350 1351 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, 1352 &crtc_state->dpll); 1353 1354 return 0; 1355 } 1356 1357 static int i8xx_crtc_compute_clock(struct intel_atomic_state *state, 1358 struct intel_crtc *crtc) 1359 { 1360 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1361 struct intel_crtc_state *crtc_state = 1362 intel_atomic_get_new_crtc_state(state, crtc); 1363 const struct intel_limit *limit; 1364 int refclk = 48000; 1365 1366 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1367 if (intel_panel_use_ssc(dev_priv)) { 1368 refclk = dev_priv->vbt.lvds_ssc_freq; 1369 drm_dbg_kms(&dev_priv->drm, 1370 "using SSC reference clock of %d kHz\n", 1371 refclk); 1372 } 1373 1374 limit = &intel_limits_i8xx_lvds; 1375 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { 1376 limit = &intel_limits_i8xx_dvo; 1377 } else { 1378 limit = &intel_limits_i8xx_dac; 1379 } 1380 1381 if (!crtc_state->clock_set && 1382 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1383 refclk, NULL, &crtc_state->dpll)) { 1384 drm_err(&dev_priv->drm, 1385 "Couldn't find PLL settings for mode!\n"); 1386 return -EINVAL; 1387 } 1388 1389 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, 1390 &crtc_state->dpll); 1391 1392 return 0; 1393 } 1394 1395 static const struct intel_dpll_funcs dg2_dpll_funcs = { 1396 .crtc_compute_clock = dg2_crtc_compute_clock, 1397 }; 1398 1399 static const struct intel_dpll_funcs hsw_dpll_funcs = { 1400 .crtc_compute_clock = hsw_crtc_compute_clock, 1401 .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll, 1402 }; 1403 1404 static const struct intel_dpll_funcs ilk_dpll_funcs = { 1405 .crtc_compute_clock = ilk_crtc_compute_clock, 1406 .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll, 1407 }; 1408 1409 static const struct intel_dpll_funcs chv_dpll_funcs = { 1410 .crtc_compute_clock = chv_crtc_compute_clock, 1411 }; 1412 1413 static const struct intel_dpll_funcs vlv_dpll_funcs = { 1414 .crtc_compute_clock = vlv_crtc_compute_clock, 1415 }; 1416 1417 static const struct intel_dpll_funcs g4x_dpll_funcs = { 1418 .crtc_compute_clock = g4x_crtc_compute_clock, 1419 }; 1420 1421 static const struct intel_dpll_funcs pnv_dpll_funcs = { 1422 .crtc_compute_clock = pnv_crtc_compute_clock, 1423 }; 1424 1425 static const struct intel_dpll_funcs i9xx_dpll_funcs = { 1426 .crtc_compute_clock = i9xx_crtc_compute_clock, 1427 }; 1428 1429 static const struct intel_dpll_funcs i8xx_dpll_funcs = { 1430 .crtc_compute_clock = i8xx_crtc_compute_clock, 1431 }; 1432 1433 int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, 1434 struct intel_crtc *crtc) 1435 { 1436 struct drm_i915_private *i915 = to_i915(state->base.dev); 1437 struct intel_crtc_state *crtc_state = 1438 intel_atomic_get_new_crtc_state(state, crtc); 1439 1440 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); 1441 1442 if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll)) 1443 return 0; 1444 1445 memset(&crtc_state->dpll_hw_state, 0, 1446 sizeof(crtc_state->dpll_hw_state)); 1447 1448 if (!crtc_state->hw.enable) 1449 return 0; 1450 1451 return i915->dpll_funcs->crtc_compute_clock(state, crtc); 1452 } 1453 1454 int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, 1455 struct intel_crtc *crtc) 1456 { 1457 struct drm_i915_private *i915 = to_i915(state->base.dev); 1458 struct intel_crtc_state *crtc_state = 1459 intel_atomic_get_new_crtc_state(state, crtc); 1460 1461 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); 1462 1463 if (drm_WARN_ON(&i915->drm, crtc_state->shared_dpll)) 1464 return 0; 1465 1466 if (!crtc_state->hw.enable) 1467 return 0; 1468 1469 if (!i915->dpll_funcs->crtc_get_shared_dpll) 1470 return 0; 1471 1472 return i915->dpll_funcs->crtc_get_shared_dpll(state, crtc); 1473 } 1474 1475 void 1476 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv) 1477 { 1478 if (IS_DG2(dev_priv)) 1479 dev_priv->dpll_funcs = &dg2_dpll_funcs; 1480 else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv)) 1481 dev_priv->dpll_funcs = &hsw_dpll_funcs; 1482 else if (HAS_PCH_SPLIT(dev_priv)) 1483 dev_priv->dpll_funcs = &ilk_dpll_funcs; 1484 else if (IS_CHERRYVIEW(dev_priv)) 1485 dev_priv->dpll_funcs = &chv_dpll_funcs; 1486 else if (IS_VALLEYVIEW(dev_priv)) 1487 dev_priv->dpll_funcs = &vlv_dpll_funcs; 1488 else if (IS_G4X(dev_priv)) 1489 dev_priv->dpll_funcs = &g4x_dpll_funcs; 1490 else if (IS_PINEVIEW(dev_priv)) 1491 dev_priv->dpll_funcs = &pnv_dpll_funcs; 1492 else if (DISPLAY_VER(dev_priv) != 2) 1493 dev_priv->dpll_funcs = &i9xx_dpll_funcs; 1494 else 1495 dev_priv->dpll_funcs = &i8xx_dpll_funcs; 1496 } 1497 1498 static bool i9xx_has_pps(struct drm_i915_private *dev_priv) 1499 { 1500 if (IS_I830(dev_priv)) 1501 return false; 1502 1503 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 1504 } 1505 1506 void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) 1507 { 1508 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1509 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1510 u32 dpll = crtc_state->dpll_hw_state.dpll; 1511 enum pipe pipe = crtc->pipe; 1512 int i; 1513 1514 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1515 1516 /* PLL is protected by panel, make sure we can write it */ 1517 if (i9xx_has_pps(dev_priv)) 1518 assert_pps_unlocked(dev_priv, pipe); 1519 1520 intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0); 1521 intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1); 1522 1523 /* 1524 * Apparently we need to have VGA mode enabled prior to changing 1525 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 1526 * dividers, even though the register value does change. 1527 */ 1528 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 1529 intel_de_write(dev_priv, DPLL(pipe), dpll); 1530 1531 /* Wait for the clocks to stabilize. */ 1532 intel_de_posting_read(dev_priv, DPLL(pipe)); 1533 udelay(150); 1534 1535 if (DISPLAY_VER(dev_priv) >= 4) { 1536 intel_de_write(dev_priv, DPLL_MD(pipe), 1537 crtc_state->dpll_hw_state.dpll_md); 1538 } else { 1539 /* The pixel multiplier can only be updated once the 1540 * DPLL is enabled and the clocks are stable. 1541 * 1542 * So write it again. 1543 */ 1544 intel_de_write(dev_priv, DPLL(pipe), dpll); 1545 } 1546 1547 /* We do this three times for luck */ 1548 for (i = 0; i < 3; i++) { 1549 intel_de_write(dev_priv, DPLL(pipe), dpll); 1550 intel_de_posting_read(dev_priv, DPLL(pipe)); 1551 udelay(150); /* wait for warmup */ 1552 } 1553 } 1554 1555 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, 1556 enum pipe pipe) 1557 { 1558 u32 reg_val; 1559 1560 /* 1561 * PLLB opamp always calibrates to max value of 0x3f, force enable it 1562 * and set it to a reasonable value instead. 1563 */ 1564 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); 1565 reg_val &= 0xffffff00; 1566 reg_val |= 0x00000030; 1567 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); 1568 1569 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); 1570 reg_val &= 0x00ffffff; 1571 reg_val |= 0x8c000000; 1572 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 1573 1574 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); 1575 reg_val &= 0xffffff00; 1576 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); 1577 1578 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); 1579 reg_val &= 0x00ffffff; 1580 reg_val |= 0xb0000000; 1581 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 1582 } 1583 1584 static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) 1585 { 1586 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1587 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1588 enum pipe pipe = crtc->pipe; 1589 u32 mdiv; 1590 u32 bestn, bestm1, bestm2, bestp1, bestp2; 1591 u32 coreclk, reg_val; 1592 1593 vlv_dpio_get(dev_priv); 1594 1595 bestn = crtc_state->dpll.n; 1596 bestm1 = crtc_state->dpll.m1; 1597 bestm2 = crtc_state->dpll.m2; 1598 bestp1 = crtc_state->dpll.p1; 1599 bestp2 = crtc_state->dpll.p2; 1600 1601 /* See eDP HDMI DPIO driver vbios notes doc */ 1602 1603 /* PLL B needs special handling */ 1604 if (pipe == PIPE_B) 1605 vlv_pllb_recal_opamp(dev_priv, pipe); 1606 1607 /* Set up Tx target for periodic Rcomp update */ 1608 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); 1609 1610 /* Disable target IRef on PLL */ 1611 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); 1612 reg_val &= 0x00ffffff; 1613 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); 1614 1615 /* Disable fast lock */ 1616 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); 1617 1618 /* Set idtafcrecal before PLL is enabled */ 1619 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); 1620 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); 1621 mdiv |= ((bestn << DPIO_N_SHIFT)); 1622 mdiv |= (1 << DPIO_K_SHIFT); 1623 1624 /* 1625 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, 1626 * but we don't support that). 1627 * Note: don't use the DAC post divider as it seems unstable. 1628 */ 1629 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); 1630 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); 1631 1632 mdiv |= DPIO_ENABLE_CALIBRATION; 1633 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); 1634 1635 /* Set HBR and RBR LPF coefficients */ 1636 if (crtc_state->port_clock == 162000 || 1637 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) || 1638 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1639 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 1640 0x009f0003); 1641 else 1642 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 1643 0x00d0000f); 1644 1645 if (intel_crtc_has_dp_encoder(crtc_state)) { 1646 /* Use SSC source */ 1647 if (pipe == PIPE_A) 1648 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1649 0x0df40000); 1650 else 1651 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1652 0x0df70000); 1653 } else { /* HDMI or VGA */ 1654 /* Use bend source */ 1655 if (pipe == PIPE_A) 1656 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1657 0x0df70000); 1658 else 1659 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1660 0x0df40000); 1661 } 1662 1663 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); 1664 coreclk = (coreclk & 0x0000ff00) | 0x01c00000; 1665 if (intel_crtc_has_dp_encoder(crtc_state)) 1666 coreclk |= 0x01000000; 1667 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); 1668 1669 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); 1670 1671 vlv_dpio_put(dev_priv); 1672 } 1673 1674 static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state) 1675 { 1676 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1677 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1678 enum pipe pipe = crtc->pipe; 1679 1680 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); 1681 intel_de_posting_read(dev_priv, DPLL(pipe)); 1682 udelay(150); 1683 1684 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) 1685 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); 1686 } 1687 1688 void vlv_enable_pll(const struct intel_crtc_state *crtc_state) 1689 { 1690 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1691 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1692 enum pipe pipe = crtc->pipe; 1693 1694 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1695 1696 /* PLL is protected by panel, make sure we can write it */ 1697 assert_pps_unlocked(dev_priv, pipe); 1698 1699 /* Enable Refclk */ 1700 intel_de_write(dev_priv, DPLL(pipe), 1701 crtc_state->dpll_hw_state.dpll & 1702 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); 1703 1704 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { 1705 vlv_prepare_pll(crtc_state); 1706 _vlv_enable_pll(crtc_state); 1707 } 1708 1709 intel_de_write(dev_priv, DPLL_MD(pipe), 1710 crtc_state->dpll_hw_state.dpll_md); 1711 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); 1712 } 1713 1714 static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) 1715 { 1716 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1717 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1718 enum pipe pipe = crtc->pipe; 1719 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1720 u32 loopfilter, tribuf_calcntr; 1721 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; 1722 u32 dpio_val; 1723 int vco; 1724 1725 bestn = crtc_state->dpll.n; 1726 bestm2_frac = crtc_state->dpll.m2 & 0x3fffff; 1727 bestm1 = crtc_state->dpll.m1; 1728 bestm2 = crtc_state->dpll.m2 >> 22; 1729 bestp1 = crtc_state->dpll.p1; 1730 bestp2 = crtc_state->dpll.p2; 1731 vco = crtc_state->dpll.vco; 1732 dpio_val = 0; 1733 loopfilter = 0; 1734 1735 vlv_dpio_get(dev_priv); 1736 1737 /* p1 and p2 divider */ 1738 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), 1739 5 << DPIO_CHV_S1_DIV_SHIFT | 1740 bestp1 << DPIO_CHV_P1_DIV_SHIFT | 1741 bestp2 << DPIO_CHV_P2_DIV_SHIFT | 1742 1 << DPIO_CHV_K_DIV_SHIFT); 1743 1744 /* Feedback post-divider - m2 */ 1745 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); 1746 1747 /* Feedback refclk divider - n and m1 */ 1748 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), 1749 DPIO_CHV_M1_DIV_BY_2 | 1750 1 << DPIO_CHV_N_DIV_SHIFT); 1751 1752 /* M2 fraction division */ 1753 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); 1754 1755 /* M2 fraction division enable */ 1756 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 1757 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); 1758 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); 1759 if (bestm2_frac) 1760 dpio_val |= DPIO_CHV_FRAC_DIV_EN; 1761 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); 1762 1763 /* Program digital lock detect threshold */ 1764 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); 1765 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | 1766 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); 1767 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); 1768 if (!bestm2_frac) 1769 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; 1770 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); 1771 1772 /* Loop filter */ 1773 if (vco == 5400000) { 1774 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); 1775 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); 1776 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); 1777 tribuf_calcntr = 0x9; 1778 } else if (vco <= 6200000) { 1779 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); 1780 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); 1781 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1782 tribuf_calcntr = 0x9; 1783 } else if (vco <= 6480000) { 1784 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 1785 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 1786 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1787 tribuf_calcntr = 0x8; 1788 } else { 1789 /* Not supported. Apply the same limits as in the max case */ 1790 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 1791 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 1792 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1793 tribuf_calcntr = 0; 1794 } 1795 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); 1796 1797 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); 1798 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; 1799 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); 1800 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); 1801 1802 /* AFC Recal */ 1803 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), 1804 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | 1805 DPIO_AFC_RECAL); 1806 1807 vlv_dpio_put(dev_priv); 1808 } 1809 1810 static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) 1811 { 1812 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1813 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1814 enum pipe pipe = crtc->pipe; 1815 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1816 u32 tmp; 1817 1818 vlv_dpio_get(dev_priv); 1819 1820 /* Enable back the 10bit clock to display controller */ 1821 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); 1822 tmp |= DPIO_DCLKP_EN; 1823 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); 1824 1825 vlv_dpio_put(dev_priv); 1826 1827 /* 1828 * Need to wait > 100ns between dclkp clock enable bit and PLL enable. 1829 */ 1830 udelay(1); 1831 1832 /* Enable PLL */ 1833 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); 1834 1835 /* Check PLL is locked */ 1836 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) 1837 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); 1838 } 1839 1840 void chv_enable_pll(const struct intel_crtc_state *crtc_state) 1841 { 1842 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1843 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1844 enum pipe pipe = crtc->pipe; 1845 1846 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1847 1848 /* PLL is protected by panel, make sure we can write it */ 1849 assert_pps_unlocked(dev_priv, pipe); 1850 1851 /* Enable Refclk and SSC */ 1852 intel_de_write(dev_priv, DPLL(pipe), 1853 crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); 1854 1855 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { 1856 chv_prepare_pll(crtc_state); 1857 _chv_enable_pll(crtc_state); 1858 } 1859 1860 if (pipe != PIPE_A) { 1861 /* 1862 * WaPixelRepeatModeFixForC0:chv 1863 * 1864 * DPLLCMD is AWOL. Use chicken bits to propagate 1865 * the value from DPLLBMD to either pipe B or C. 1866 */ 1867 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); 1868 intel_de_write(dev_priv, DPLL_MD(PIPE_B), 1869 crtc_state->dpll_hw_state.dpll_md); 1870 intel_de_write(dev_priv, CBR4_VLV, 0); 1871 dev_priv->chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md; 1872 1873 /* 1874 * DPLLB VGA mode also seems to cause problems. 1875 * We should always have it disabled. 1876 */ 1877 drm_WARN_ON(&dev_priv->drm, 1878 (intel_de_read(dev_priv, DPLL(PIPE_B)) & 1879 DPLL_VGA_MODE_DIS) == 0); 1880 } else { 1881 intel_de_write(dev_priv, DPLL_MD(pipe), 1882 crtc_state->dpll_hw_state.dpll_md); 1883 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); 1884 } 1885 } 1886 1887 /** 1888 * vlv_force_pll_on - forcibly enable just the PLL 1889 * @dev_priv: i915 private structure 1890 * @pipe: pipe PLL to enable 1891 * @dpll: PLL configuration 1892 * 1893 * Enable the PLL for @pipe using the supplied @dpll config. To be used 1894 * in cases where we need the PLL enabled even when @pipe is not going to 1895 * be enabled. 1896 */ 1897 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, 1898 const struct dpll *dpll) 1899 { 1900 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 1901 struct intel_crtc_state *crtc_state; 1902 1903 crtc_state = intel_crtc_state_alloc(crtc); 1904 if (!crtc_state) 1905 return -ENOMEM; 1906 1907 crtc_state->cpu_transcoder = (enum transcoder)pipe; 1908 crtc_state->pixel_multiplier = 1; 1909 crtc_state->dpll = *dpll; 1910 crtc_state->output_types = BIT(INTEL_OUTPUT_EDP); 1911 1912 if (IS_CHERRYVIEW(dev_priv)) { 1913 chv_compute_dpll(crtc_state); 1914 chv_enable_pll(crtc_state); 1915 } else { 1916 vlv_compute_dpll(crtc_state); 1917 vlv_enable_pll(crtc_state); 1918 } 1919 1920 kfree(crtc_state); 1921 1922 return 0; 1923 } 1924 1925 void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 1926 { 1927 u32 val; 1928 1929 /* Make sure the pipe isn't still relying on us */ 1930 assert_transcoder_disabled(dev_priv, (enum transcoder)pipe); 1931 1932 val = DPLL_INTEGRATED_REF_CLK_VLV | 1933 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1934 if (pipe != PIPE_A) 1935 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1936 1937 intel_de_write(dev_priv, DPLL(pipe), val); 1938 intel_de_posting_read(dev_priv, DPLL(pipe)); 1939 } 1940 1941 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 1942 { 1943 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1944 u32 val; 1945 1946 /* Make sure the pipe isn't still relying on us */ 1947 assert_transcoder_disabled(dev_priv, (enum transcoder)pipe); 1948 1949 val = DPLL_SSC_REF_CLK_CHV | 1950 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1951 if (pipe != PIPE_A) 1952 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1953 1954 intel_de_write(dev_priv, DPLL(pipe), val); 1955 intel_de_posting_read(dev_priv, DPLL(pipe)); 1956 1957 vlv_dpio_get(dev_priv); 1958 1959 /* Disable 10bit clock to display controller */ 1960 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); 1961 val &= ~DPIO_DCLKP_EN; 1962 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); 1963 1964 vlv_dpio_put(dev_priv); 1965 } 1966 1967 void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) 1968 { 1969 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1970 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1971 enum pipe pipe = crtc->pipe; 1972 1973 /* Don't disable pipe or pipe PLLs if needed */ 1974 if (IS_I830(dev_priv)) 1975 return; 1976 1977 /* Make sure the pipe isn't still relying on us */ 1978 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1979 1980 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 1981 intel_de_posting_read(dev_priv, DPLL(pipe)); 1982 } 1983 1984 1985 /** 1986 * vlv_force_pll_off - forcibly disable just the PLL 1987 * @dev_priv: i915 private structure 1988 * @pipe: pipe PLL to disable 1989 * 1990 * Disable the PLL for @pipe. To be used in cases where we need 1991 * the PLL enabled even when @pipe is not going to be enabled. 1992 */ 1993 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) 1994 { 1995 if (IS_CHERRYVIEW(dev_priv)) 1996 chv_disable_pll(dev_priv, pipe); 1997 else 1998 vlv_disable_pll(dev_priv, pipe); 1999 } 2000 2001 /* Only for pre-ILK configs */ 2002 static void assert_pll(struct drm_i915_private *dev_priv, 2003 enum pipe pipe, bool state) 2004 { 2005 bool cur_state; 2006 2007 cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; 2008 I915_STATE_WARN(cur_state != state, 2009 "PLL state assertion failure (expected %s, current %s)\n", 2010 str_on_off(state), str_on_off(cur_state)); 2011 } 2012 2013 void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe) 2014 { 2015 assert_pll(i915, pipe, true); 2016 } 2017 2018 void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe) 2019 { 2020 assert_pll(i915, pipe, false); 2021 } 2022