1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020 Intel Corporation 4 */ 5 6 #include <linux/kernel.h> 7 #include <linux/string_helpers.h> 8 9 #include "i915_reg.h" 10 #include "intel_crtc.h" 11 #include "intel_de.h" 12 #include "intel_display.h" 13 #include "intel_display_types.h" 14 #include "intel_dpio_phy.h" 15 #include "intel_dpll.h" 16 #include "intel_lvds.h" 17 #include "intel_panel.h" 18 #include "intel_pps.h" 19 #include "intel_snps_phy.h" 20 #include "vlv_sideband.h" 21 22 struct intel_dpll_funcs { 23 int (*crtc_compute_clock)(struct intel_atomic_state *state, 24 struct intel_crtc *crtc); 25 int (*crtc_get_shared_dpll)(struct intel_atomic_state *state, 26 struct intel_crtc *crtc); 27 }; 28 29 struct intel_limit { 30 struct { 31 int min, max; 32 } dot, vco, n, m, m1, m2, p, p1; 33 34 struct { 35 int dot_limit; 36 int p2_slow, p2_fast; 37 } p2; 38 }; 39 static const struct intel_limit intel_limits_i8xx_dac = { 40 .dot = { .min = 25000, .max = 350000 }, 41 .vco = { .min = 908000, .max = 1512000 }, 42 .n = { .min = 2, .max = 16 }, 43 .m = { .min = 96, .max = 140 }, 44 .m1 = { .min = 18, .max = 26 }, 45 .m2 = { .min = 6, .max = 16 }, 46 .p = { .min = 4, .max = 128 }, 47 .p1 = { .min = 2, .max = 33 }, 48 .p2 = { .dot_limit = 165000, 49 .p2_slow = 4, .p2_fast = 2 }, 50 }; 51 52 static const struct intel_limit intel_limits_i8xx_dvo = { 53 .dot = { .min = 25000, .max = 350000 }, 54 .vco = { .min = 908000, .max = 1512000 }, 55 .n = { .min = 2, .max = 16 }, 56 .m = { .min = 96, .max = 140 }, 57 .m1 = { .min = 18, .max = 26 }, 58 .m2 = { .min = 6, .max = 16 }, 59 .p = { .min = 4, .max = 128 }, 60 .p1 = { .min = 2, .max = 33 }, 61 .p2 = { .dot_limit = 165000, 62 .p2_slow = 4, .p2_fast = 4 }, 63 }; 64 65 static const struct intel_limit intel_limits_i8xx_lvds = { 66 .dot = { .min = 25000, .max = 350000 }, 67 .vco = { .min = 908000, .max = 1512000 }, 68 .n = { .min = 2, .max = 16 }, 69 .m = { .min = 96, .max = 140 }, 70 .m1 = { .min = 18, .max = 26 }, 71 .m2 = { .min = 6, .max = 16 }, 72 .p = { .min = 4, .max = 128 }, 73 .p1 = { .min = 1, .max = 6 }, 74 .p2 = { .dot_limit = 165000, 75 .p2_slow = 14, .p2_fast = 7 }, 76 }; 77 78 static const struct intel_limit intel_limits_i9xx_sdvo = { 79 .dot = { .min = 20000, .max = 400000 }, 80 .vco = { .min = 1400000, .max = 2800000 }, 81 .n = { .min = 1, .max = 6 }, 82 .m = { .min = 70, .max = 120 }, 83 .m1 = { .min = 8, .max = 18 }, 84 .m2 = { .min = 3, .max = 7 }, 85 .p = { .min = 5, .max = 80 }, 86 .p1 = { .min = 1, .max = 8 }, 87 .p2 = { .dot_limit = 200000, 88 .p2_slow = 10, .p2_fast = 5 }, 89 }; 90 91 static const struct intel_limit intel_limits_i9xx_lvds = { 92 .dot = { .min = 20000, .max = 400000 }, 93 .vco = { .min = 1400000, .max = 2800000 }, 94 .n = { .min = 1, .max = 6 }, 95 .m = { .min = 70, .max = 120 }, 96 .m1 = { .min = 8, .max = 18 }, 97 .m2 = { .min = 3, .max = 7 }, 98 .p = { .min = 7, .max = 98 }, 99 .p1 = { .min = 1, .max = 8 }, 100 .p2 = { .dot_limit = 112000, 101 .p2_slow = 14, .p2_fast = 7 }, 102 }; 103 104 105 static const struct intel_limit intel_limits_g4x_sdvo = { 106 .dot = { .min = 25000, .max = 270000 }, 107 .vco = { .min = 1750000, .max = 3500000}, 108 .n = { .min = 1, .max = 4 }, 109 .m = { .min = 104, .max = 138 }, 110 .m1 = { .min = 17, .max = 23 }, 111 .m2 = { .min = 5, .max = 11 }, 112 .p = { .min = 10, .max = 30 }, 113 .p1 = { .min = 1, .max = 3}, 114 .p2 = { .dot_limit = 270000, 115 .p2_slow = 10, 116 .p2_fast = 10 117 }, 118 }; 119 120 static const struct intel_limit intel_limits_g4x_hdmi = { 121 .dot = { .min = 22000, .max = 400000 }, 122 .vco = { .min = 1750000, .max = 3500000}, 123 .n = { .min = 1, .max = 4 }, 124 .m = { .min = 104, .max = 138 }, 125 .m1 = { .min = 16, .max = 23 }, 126 .m2 = { .min = 5, .max = 11 }, 127 .p = { .min = 5, .max = 80 }, 128 .p1 = { .min = 1, .max = 8}, 129 .p2 = { .dot_limit = 165000, 130 .p2_slow = 10, .p2_fast = 5 }, 131 }; 132 133 static const struct intel_limit intel_limits_g4x_single_channel_lvds = { 134 .dot = { .min = 20000, .max = 115000 }, 135 .vco = { .min = 1750000, .max = 3500000 }, 136 .n = { .min = 1, .max = 3 }, 137 .m = { .min = 104, .max = 138 }, 138 .m1 = { .min = 17, .max = 23 }, 139 .m2 = { .min = 5, .max = 11 }, 140 .p = { .min = 28, .max = 112 }, 141 .p1 = { .min = 2, .max = 8 }, 142 .p2 = { .dot_limit = 0, 143 .p2_slow = 14, .p2_fast = 14 144 }, 145 }; 146 147 static const struct intel_limit intel_limits_g4x_dual_channel_lvds = { 148 .dot = { .min = 80000, .max = 224000 }, 149 .vco = { .min = 1750000, .max = 3500000 }, 150 .n = { .min = 1, .max = 3 }, 151 .m = { .min = 104, .max = 138 }, 152 .m1 = { .min = 17, .max = 23 }, 153 .m2 = { .min = 5, .max = 11 }, 154 .p = { .min = 14, .max = 42 }, 155 .p1 = { .min = 2, .max = 6 }, 156 .p2 = { .dot_limit = 0, 157 .p2_slow = 7, .p2_fast = 7 158 }, 159 }; 160 161 static const struct intel_limit pnv_limits_sdvo = { 162 .dot = { .min = 20000, .max = 400000}, 163 .vco = { .min = 1700000, .max = 3500000 }, 164 /* Pineview's Ncounter is a ring counter */ 165 .n = { .min = 3, .max = 6 }, 166 .m = { .min = 2, .max = 256 }, 167 /* Pineview only has one combined m divider, which we treat as m2. */ 168 .m1 = { .min = 0, .max = 0 }, 169 .m2 = { .min = 0, .max = 254 }, 170 .p = { .min = 5, .max = 80 }, 171 .p1 = { .min = 1, .max = 8 }, 172 .p2 = { .dot_limit = 200000, 173 .p2_slow = 10, .p2_fast = 5 }, 174 }; 175 176 static const struct intel_limit pnv_limits_lvds = { 177 .dot = { .min = 20000, .max = 400000 }, 178 .vco = { .min = 1700000, .max = 3500000 }, 179 .n = { .min = 3, .max = 6 }, 180 .m = { .min = 2, .max = 256 }, 181 .m1 = { .min = 0, .max = 0 }, 182 .m2 = { .min = 0, .max = 254 }, 183 .p = { .min = 7, .max = 112 }, 184 .p1 = { .min = 1, .max = 8 }, 185 .p2 = { .dot_limit = 112000, 186 .p2_slow = 14, .p2_fast = 14 }, 187 }; 188 189 /* Ironlake / Sandybridge 190 * 191 * We calculate clock using (register_value + 2) for N/M1/M2, so here 192 * the range value for them is (actual_value - 2). 193 */ 194 static const struct intel_limit ilk_limits_dac = { 195 .dot = { .min = 25000, .max = 350000 }, 196 .vco = { .min = 1760000, .max = 3510000 }, 197 .n = { .min = 1, .max = 5 }, 198 .m = { .min = 79, .max = 127 }, 199 .m1 = { .min = 12, .max = 22 }, 200 .m2 = { .min = 5, .max = 9 }, 201 .p = { .min = 5, .max = 80 }, 202 .p1 = { .min = 1, .max = 8 }, 203 .p2 = { .dot_limit = 225000, 204 .p2_slow = 10, .p2_fast = 5 }, 205 }; 206 207 static const struct intel_limit ilk_limits_single_lvds = { 208 .dot = { .min = 25000, .max = 350000 }, 209 .vco = { .min = 1760000, .max = 3510000 }, 210 .n = { .min = 1, .max = 3 }, 211 .m = { .min = 79, .max = 118 }, 212 .m1 = { .min = 12, .max = 22 }, 213 .m2 = { .min = 5, .max = 9 }, 214 .p = { .min = 28, .max = 112 }, 215 .p1 = { .min = 2, .max = 8 }, 216 .p2 = { .dot_limit = 225000, 217 .p2_slow = 14, .p2_fast = 14 }, 218 }; 219 220 static const struct intel_limit ilk_limits_dual_lvds = { 221 .dot = { .min = 25000, .max = 350000 }, 222 .vco = { .min = 1760000, .max = 3510000 }, 223 .n = { .min = 1, .max = 3 }, 224 .m = { .min = 79, .max = 127 }, 225 .m1 = { .min = 12, .max = 22 }, 226 .m2 = { .min = 5, .max = 9 }, 227 .p = { .min = 14, .max = 56 }, 228 .p1 = { .min = 2, .max = 8 }, 229 .p2 = { .dot_limit = 225000, 230 .p2_slow = 7, .p2_fast = 7 }, 231 }; 232 233 /* LVDS 100mhz refclk limits. */ 234 static const struct intel_limit ilk_limits_single_lvds_100m = { 235 .dot = { .min = 25000, .max = 350000 }, 236 .vco = { .min = 1760000, .max = 3510000 }, 237 .n = { .min = 1, .max = 2 }, 238 .m = { .min = 79, .max = 126 }, 239 .m1 = { .min = 12, .max = 22 }, 240 .m2 = { .min = 5, .max = 9 }, 241 .p = { .min = 28, .max = 112 }, 242 .p1 = { .min = 2, .max = 8 }, 243 .p2 = { .dot_limit = 225000, 244 .p2_slow = 14, .p2_fast = 14 }, 245 }; 246 247 static const struct intel_limit ilk_limits_dual_lvds_100m = { 248 .dot = { .min = 25000, .max = 350000 }, 249 .vco = { .min = 1760000, .max = 3510000 }, 250 .n = { .min = 1, .max = 3 }, 251 .m = { .min = 79, .max = 126 }, 252 .m1 = { .min = 12, .max = 22 }, 253 .m2 = { .min = 5, .max = 9 }, 254 .p = { .min = 14, .max = 42 }, 255 .p1 = { .min = 2, .max = 6 }, 256 .p2 = { .dot_limit = 225000, 257 .p2_slow = 7, .p2_fast = 7 }, 258 }; 259 260 static const struct intel_limit intel_limits_vlv = { 261 /* 262 * These are based on the data rate limits (measured in fast clocks) 263 * since those are the strictest limits we have. The fast 264 * clock and actual rate limits are more relaxed, so checking 265 * them would make no difference. 266 */ 267 .dot = { .min = 25000, .max = 270000 }, 268 .vco = { .min = 4000000, .max = 6000000 }, 269 .n = { .min = 1, .max = 7 }, 270 .m1 = { .min = 2, .max = 3 }, 271 .m2 = { .min = 11, .max = 156 }, 272 .p1 = { .min = 2, .max = 3 }, 273 .p2 = { .p2_slow = 2, .p2_fast = 20 }, /* slow=min, fast=max */ 274 }; 275 276 static const struct intel_limit intel_limits_chv = { 277 /* 278 * These are based on the data rate limits (measured in fast clocks) 279 * since those are the strictest limits we have. The fast 280 * clock and actual rate limits are more relaxed, so checking 281 * them would make no difference. 282 */ 283 .dot = { .min = 25000, .max = 540000 }, 284 .vco = { .min = 4800000, .max = 6480000 }, 285 .n = { .min = 1, .max = 1 }, 286 .m1 = { .min = 2, .max = 2 }, 287 .m2 = { .min = 24 << 22, .max = 175 << 22 }, 288 .p1 = { .min = 2, .max = 4 }, 289 .p2 = { .p2_slow = 1, .p2_fast = 14 }, 290 }; 291 292 static const struct intel_limit intel_limits_bxt = { 293 .dot = { .min = 25000, .max = 594000 }, 294 .vco = { .min = 4800000, .max = 6700000 }, 295 .n = { .min = 1, .max = 1 }, 296 .m1 = { .min = 2, .max = 2 }, 297 /* FIXME: find real m2 limits */ 298 .m2 = { .min = 2 << 22, .max = 255 << 22 }, 299 .p1 = { .min = 2, .max = 4 }, 300 .p2 = { .p2_slow = 1, .p2_fast = 20 }, 301 }; 302 303 /* 304 * Platform specific helpers to calculate the port PLL loopback- (clock.m), 305 * and post-divider (clock.p) values, pre- (clock.vco) and post-divided fast 306 * (clock.dot) clock rates. This fast dot clock is fed to the port's IO logic. 307 * The helpers' return value is the rate of the clock that is fed to the 308 * display engine's pipe which can be the above fast dot clock rate or a 309 * divided-down version of it. 310 */ 311 /* m1 is reserved as 0 in Pineview, n is a ring counter */ 312 int pnv_calc_dpll_params(int refclk, struct dpll *clock) 313 { 314 clock->m = clock->m2 + 2; 315 clock->p = clock->p1 * clock->p2; 316 if (WARN_ON(clock->n == 0 || clock->p == 0)) 317 return 0; 318 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 319 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 320 321 return clock->dot; 322 } 323 324 static u32 i9xx_dpll_compute_m(const struct dpll *dpll) 325 { 326 return 5 * (dpll->m1 + 2) + (dpll->m2 + 2); 327 } 328 329 int i9xx_calc_dpll_params(int refclk, struct dpll *clock) 330 { 331 clock->m = i9xx_dpll_compute_m(clock); 332 clock->p = clock->p1 * clock->p2; 333 if (WARN_ON(clock->n + 2 == 0 || clock->p == 0)) 334 return 0; 335 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n + 2); 336 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 337 338 return clock->dot; 339 } 340 341 int vlv_calc_dpll_params(int refclk, struct dpll *clock) 342 { 343 clock->m = clock->m1 * clock->m2; 344 clock->p = clock->p1 * clock->p2 * 5; 345 if (WARN_ON(clock->n == 0 || clock->p == 0)) 346 return 0; 347 clock->vco = DIV_ROUND_CLOSEST(refclk * clock->m, clock->n); 348 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 349 350 return clock->dot; 351 } 352 353 int chv_calc_dpll_params(int refclk, struct dpll *clock) 354 { 355 clock->m = clock->m1 * clock->m2; 356 clock->p = clock->p1 * clock->p2 * 5; 357 if (WARN_ON(clock->n == 0 || clock->p == 0)) 358 return 0; 359 clock->vco = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(refclk, clock->m), 360 clock->n << 22); 361 clock->dot = DIV_ROUND_CLOSEST(clock->vco, clock->p); 362 363 return clock->dot; 364 } 365 366 /* 367 * Returns whether the given set of divisors are valid for a given refclk with 368 * the given connectors. 369 */ 370 static bool intel_pll_is_valid(struct drm_i915_private *dev_priv, 371 const struct intel_limit *limit, 372 const struct dpll *clock) 373 { 374 if (clock->n < limit->n.min || limit->n.max < clock->n) 375 return false; 376 if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1) 377 return false; 378 if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2) 379 return false; 380 if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1) 381 return false; 382 383 if (!IS_PINEVIEW(dev_priv) && !IS_LP(dev_priv)) 384 if (clock->m1 <= clock->m2) 385 return false; 386 387 if (!IS_LP(dev_priv)) { 388 if (clock->p < limit->p.min || limit->p.max < clock->p) 389 return false; 390 if (clock->m < limit->m.min || limit->m.max < clock->m) 391 return false; 392 } 393 394 if (clock->vco < limit->vco.min || limit->vco.max < clock->vco) 395 return false; 396 /* XXX: We may need to be checking "Dot clock" depending on the multiplier, 397 * connector, etc., rather than just a single range. 398 */ 399 if (clock->dot < limit->dot.min || limit->dot.max < clock->dot) 400 return false; 401 402 return true; 403 } 404 405 static int 406 i9xx_select_p2_div(const struct intel_limit *limit, 407 const struct intel_crtc_state *crtc_state, 408 int target) 409 { 410 struct drm_i915_private *dev_priv = to_i915(crtc_state->uapi.crtc->dev); 411 412 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 413 /* 414 * For LVDS just rely on its current settings for dual-channel. 415 * We haven't figured out how to reliably set up different 416 * single/dual channel state, if we even can. 417 */ 418 if (intel_is_dual_link_lvds(dev_priv)) 419 return limit->p2.p2_fast; 420 else 421 return limit->p2.p2_slow; 422 } else { 423 if (target < limit->p2.dot_limit) 424 return limit->p2.p2_slow; 425 else 426 return limit->p2.p2_fast; 427 } 428 } 429 430 /* 431 * Returns a set of divisors for the desired target clock with the given 432 * refclk, or FALSE. 433 * 434 * Target and reference clocks are specified in kHz. 435 * 436 * If match_clock is provided, then best_clock P divider must match the P 437 * divider from @match_clock used for LVDS downclocking. 438 */ 439 static bool 440 i9xx_find_best_dpll(const struct intel_limit *limit, 441 struct intel_crtc_state *crtc_state, 442 int target, int refclk, 443 const struct dpll *match_clock, 444 struct dpll *best_clock) 445 { 446 struct drm_device *dev = crtc_state->uapi.crtc->dev; 447 struct dpll clock; 448 int err = target; 449 450 memset(best_clock, 0, sizeof(*best_clock)); 451 452 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 453 454 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 455 clock.m1++) { 456 for (clock.m2 = limit->m2.min; 457 clock.m2 <= limit->m2.max; clock.m2++) { 458 if (clock.m2 >= clock.m1) 459 break; 460 for (clock.n = limit->n.min; 461 clock.n <= limit->n.max; clock.n++) { 462 for (clock.p1 = limit->p1.min; 463 clock.p1 <= limit->p1.max; clock.p1++) { 464 int this_err; 465 466 i9xx_calc_dpll_params(refclk, &clock); 467 if (!intel_pll_is_valid(to_i915(dev), 468 limit, 469 &clock)) 470 continue; 471 if (match_clock && 472 clock.p != match_clock->p) 473 continue; 474 475 this_err = abs(clock.dot - target); 476 if (this_err < err) { 477 *best_clock = clock; 478 err = this_err; 479 } 480 } 481 } 482 } 483 } 484 485 return (err != target); 486 } 487 488 /* 489 * Returns a set of divisors for the desired target clock with the given 490 * refclk, or FALSE. 491 * 492 * Target and reference clocks are specified in kHz. 493 * 494 * If match_clock is provided, then best_clock P divider must match the P 495 * divider from @match_clock used for LVDS downclocking. 496 */ 497 static bool 498 pnv_find_best_dpll(const struct intel_limit *limit, 499 struct intel_crtc_state *crtc_state, 500 int target, int refclk, 501 const struct dpll *match_clock, 502 struct dpll *best_clock) 503 { 504 struct drm_device *dev = crtc_state->uapi.crtc->dev; 505 struct dpll clock; 506 int err = target; 507 508 memset(best_clock, 0, sizeof(*best_clock)); 509 510 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 511 512 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; 513 clock.m1++) { 514 for (clock.m2 = limit->m2.min; 515 clock.m2 <= limit->m2.max; clock.m2++) { 516 for (clock.n = limit->n.min; 517 clock.n <= limit->n.max; clock.n++) { 518 for (clock.p1 = limit->p1.min; 519 clock.p1 <= limit->p1.max; clock.p1++) { 520 int this_err; 521 522 pnv_calc_dpll_params(refclk, &clock); 523 if (!intel_pll_is_valid(to_i915(dev), 524 limit, 525 &clock)) 526 continue; 527 if (match_clock && 528 clock.p != match_clock->p) 529 continue; 530 531 this_err = abs(clock.dot - target); 532 if (this_err < err) { 533 *best_clock = clock; 534 err = this_err; 535 } 536 } 537 } 538 } 539 } 540 541 return (err != target); 542 } 543 544 /* 545 * Returns a set of divisors for the desired target clock with the given 546 * refclk, or FALSE. 547 * 548 * Target and reference clocks are specified in kHz. 549 * 550 * If match_clock is provided, then best_clock P divider must match the P 551 * divider from @match_clock used for LVDS downclocking. 552 */ 553 static bool 554 g4x_find_best_dpll(const struct intel_limit *limit, 555 struct intel_crtc_state *crtc_state, 556 int target, int refclk, 557 const struct dpll *match_clock, 558 struct dpll *best_clock) 559 { 560 struct drm_device *dev = crtc_state->uapi.crtc->dev; 561 struct dpll clock; 562 int max_n; 563 bool found = false; 564 /* approximately equals target * 0.00585 */ 565 int err_most = (target >> 8) + (target >> 9); 566 567 memset(best_clock, 0, sizeof(*best_clock)); 568 569 clock.p2 = i9xx_select_p2_div(limit, crtc_state, target); 570 571 max_n = limit->n.max; 572 /* based on hardware requirement, prefer smaller n to precision */ 573 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 574 /* based on hardware requirement, prefere larger m1,m2 */ 575 for (clock.m1 = limit->m1.max; 576 clock.m1 >= limit->m1.min; clock.m1--) { 577 for (clock.m2 = limit->m2.max; 578 clock.m2 >= limit->m2.min; clock.m2--) { 579 for (clock.p1 = limit->p1.max; 580 clock.p1 >= limit->p1.min; clock.p1--) { 581 int this_err; 582 583 i9xx_calc_dpll_params(refclk, &clock); 584 if (!intel_pll_is_valid(to_i915(dev), 585 limit, 586 &clock)) 587 continue; 588 589 this_err = abs(clock.dot - target); 590 if (this_err < err_most) { 591 *best_clock = clock; 592 err_most = this_err; 593 max_n = clock.n; 594 found = true; 595 } 596 } 597 } 598 } 599 } 600 return found; 601 } 602 603 /* 604 * Check if the calculated PLL configuration is more optimal compared to the 605 * best configuration and error found so far. Return the calculated error. 606 */ 607 static bool vlv_PLL_is_optimal(struct drm_device *dev, int target_freq, 608 const struct dpll *calculated_clock, 609 const struct dpll *best_clock, 610 unsigned int best_error_ppm, 611 unsigned int *error_ppm) 612 { 613 /* 614 * For CHV ignore the error and consider only the P value. 615 * Prefer a bigger P value based on HW requirements. 616 */ 617 if (IS_CHERRYVIEW(to_i915(dev))) { 618 *error_ppm = 0; 619 620 return calculated_clock->p > best_clock->p; 621 } 622 623 if (drm_WARN_ON_ONCE(dev, !target_freq)) 624 return false; 625 626 *error_ppm = div_u64(1000000ULL * 627 abs(target_freq - calculated_clock->dot), 628 target_freq); 629 /* 630 * Prefer a better P value over a better (smaller) error if the error 631 * is small. Ensure this preference for future configurations too by 632 * setting the error to 0. 633 */ 634 if (*error_ppm < 100 && calculated_clock->p > best_clock->p) { 635 *error_ppm = 0; 636 637 return true; 638 } 639 640 return *error_ppm + 10 < best_error_ppm; 641 } 642 643 /* 644 * Returns a set of divisors for the desired target clock with the given 645 * refclk, or FALSE. 646 */ 647 static bool 648 vlv_find_best_dpll(const struct intel_limit *limit, 649 struct intel_crtc_state *crtc_state, 650 int target, int refclk, 651 const struct dpll *match_clock, 652 struct dpll *best_clock) 653 { 654 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 655 struct drm_device *dev = crtc->base.dev; 656 struct dpll clock; 657 unsigned int bestppm = 1000000; 658 /* min update 19.2 MHz */ 659 int max_n = min(limit->n.max, refclk / 19200); 660 bool found = false; 661 662 memset(best_clock, 0, sizeof(*best_clock)); 663 664 /* based on hardware requirement, prefer smaller n to precision */ 665 for (clock.n = limit->n.min; clock.n <= max_n; clock.n++) { 666 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 667 for (clock.p2 = limit->p2.p2_fast; clock.p2 >= limit->p2.p2_slow; 668 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 669 clock.p = clock.p1 * clock.p2 * 5; 670 /* based on hardware requirement, prefer bigger m1,m2 values */ 671 for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) { 672 unsigned int ppm; 673 674 clock.m2 = DIV_ROUND_CLOSEST(target * clock.p * clock.n, 675 refclk * clock.m1); 676 677 vlv_calc_dpll_params(refclk, &clock); 678 679 if (!intel_pll_is_valid(to_i915(dev), 680 limit, 681 &clock)) 682 continue; 683 684 if (!vlv_PLL_is_optimal(dev, target, 685 &clock, 686 best_clock, 687 bestppm, &ppm)) 688 continue; 689 690 *best_clock = clock; 691 bestppm = ppm; 692 found = true; 693 } 694 } 695 } 696 } 697 698 return found; 699 } 700 701 /* 702 * Returns a set of divisors for the desired target clock with the given 703 * refclk, or FALSE. 704 */ 705 static bool 706 chv_find_best_dpll(const struct intel_limit *limit, 707 struct intel_crtc_state *crtc_state, 708 int target, int refclk, 709 const struct dpll *match_clock, 710 struct dpll *best_clock) 711 { 712 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 713 struct drm_device *dev = crtc->base.dev; 714 unsigned int best_error_ppm; 715 struct dpll clock; 716 u64 m2; 717 int found = false; 718 719 memset(best_clock, 0, sizeof(*best_clock)); 720 best_error_ppm = 1000000; 721 722 /* 723 * Based on hardware doc, the n always set to 1, and m1 always 724 * set to 2. If requires to support 200Mhz refclk, we need to 725 * revisit this because n may not 1 anymore. 726 */ 727 clock.n = 1; 728 clock.m1 = 2; 729 730 for (clock.p1 = limit->p1.max; clock.p1 >= limit->p1.min; clock.p1--) { 731 for (clock.p2 = limit->p2.p2_fast; 732 clock.p2 >= limit->p2.p2_slow; 733 clock.p2 -= clock.p2 > 10 ? 2 : 1) { 734 unsigned int error_ppm; 735 736 clock.p = clock.p1 * clock.p2 * 5; 737 738 m2 = DIV_ROUND_CLOSEST_ULL(mul_u32_u32(target, clock.p * clock.n) << 22, 739 refclk * clock.m1); 740 741 if (m2 > INT_MAX/clock.m1) 742 continue; 743 744 clock.m2 = m2; 745 746 chv_calc_dpll_params(refclk, &clock); 747 748 if (!intel_pll_is_valid(to_i915(dev), limit, &clock)) 749 continue; 750 751 if (!vlv_PLL_is_optimal(dev, target, &clock, best_clock, 752 best_error_ppm, &error_ppm)) 753 continue; 754 755 *best_clock = clock; 756 best_error_ppm = error_ppm; 757 found = true; 758 } 759 } 760 761 return found; 762 } 763 764 bool bxt_find_best_dpll(struct intel_crtc_state *crtc_state, 765 struct dpll *best_clock) 766 { 767 const struct intel_limit *limit = &intel_limits_bxt; 768 int refclk = 100000; 769 770 return chv_find_best_dpll(limit, crtc_state, 771 crtc_state->port_clock, refclk, 772 NULL, best_clock); 773 } 774 775 u32 i9xx_dpll_compute_fp(const struct dpll *dpll) 776 { 777 return dpll->n << 16 | dpll->m1 << 8 | dpll->m2; 778 } 779 780 static u32 pnv_dpll_compute_fp(const struct dpll *dpll) 781 { 782 return (1 << dpll->n) << 16 | dpll->m2; 783 } 784 785 static void i9xx_update_pll_dividers(struct intel_crtc_state *crtc_state, 786 const struct dpll *clock, 787 const struct dpll *reduced_clock) 788 { 789 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 790 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 791 u32 fp, fp2; 792 793 if (IS_PINEVIEW(dev_priv)) { 794 fp = pnv_dpll_compute_fp(clock); 795 fp2 = pnv_dpll_compute_fp(reduced_clock); 796 } else { 797 fp = i9xx_dpll_compute_fp(clock); 798 fp2 = i9xx_dpll_compute_fp(reduced_clock); 799 } 800 801 crtc_state->dpll_hw_state.fp0 = fp; 802 crtc_state->dpll_hw_state.fp1 = fp2; 803 } 804 805 static void i9xx_compute_dpll(struct intel_crtc_state *crtc_state, 806 const struct dpll *clock, 807 const struct dpll *reduced_clock) 808 { 809 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 810 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 811 u32 dpll; 812 813 i9xx_update_pll_dividers(crtc_state, clock, reduced_clock); 814 815 dpll = DPLL_VGA_MODE_DIS; 816 817 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) 818 dpll |= DPLLB_MODE_LVDS; 819 else 820 dpll |= DPLLB_MODE_DAC_SERIAL; 821 822 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv) || 823 IS_G33(dev_priv) || IS_PINEVIEW(dev_priv)) { 824 dpll |= (crtc_state->pixel_multiplier - 1) 825 << SDVO_MULTIPLIER_SHIFT_HIRES; 826 } 827 828 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || 829 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 830 dpll |= DPLL_SDVO_HIGH_SPEED; 831 832 if (intel_crtc_has_dp_encoder(crtc_state)) 833 dpll |= DPLL_SDVO_HIGH_SPEED; 834 835 /* compute bitmask from p1 value */ 836 if (IS_G4X(dev_priv)) { 837 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 838 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 839 } else if (IS_PINEVIEW(dev_priv)) { 840 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT_PINEVIEW; 841 WARN_ON(reduced_clock->p1 != clock->p1); 842 } else { 843 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 844 WARN_ON(reduced_clock->p1 != clock->p1); 845 } 846 847 switch (clock->p2) { 848 case 5: 849 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 850 break; 851 case 7: 852 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 853 break; 854 case 10: 855 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 856 break; 857 case 14: 858 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 859 break; 860 } 861 WARN_ON(reduced_clock->p2 != clock->p2); 862 863 if (DISPLAY_VER(dev_priv) >= 4) 864 dpll |= (6 << PLL_LOAD_PULSE_PHASE_SHIFT); 865 866 if (crtc_state->sdvo_tv_clock) 867 dpll |= PLL_REF_INPUT_TVCLKINBC; 868 else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 869 intel_panel_use_ssc(dev_priv)) 870 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 871 else 872 dpll |= PLL_REF_INPUT_DREFCLK; 873 874 dpll |= DPLL_VCO_ENABLE; 875 crtc_state->dpll_hw_state.dpll = dpll; 876 877 if (DISPLAY_VER(dev_priv) >= 4) { 878 u32 dpll_md = (crtc_state->pixel_multiplier - 1) 879 << DPLL_MD_UDI_MULTIPLIER_SHIFT; 880 crtc_state->dpll_hw_state.dpll_md = dpll_md; 881 } 882 } 883 884 static void i8xx_compute_dpll(struct intel_crtc_state *crtc_state, 885 const struct dpll *clock, 886 const struct dpll *reduced_clock) 887 { 888 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 889 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 890 u32 dpll; 891 892 i9xx_update_pll_dividers(crtc_state, clock, reduced_clock); 893 894 dpll = DPLL_VGA_MODE_DIS; 895 896 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 897 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 898 } else { 899 if (clock->p1 == 2) 900 dpll |= PLL_P1_DIVIDE_BY_TWO; 901 else 902 dpll |= (clock->p1 - 2) << DPLL_FPA01_P1_POST_DIV_SHIFT; 903 if (clock->p2 == 4) 904 dpll |= PLL_P2_DIVIDE_BY_4; 905 } 906 WARN_ON(reduced_clock->p1 != clock->p1); 907 WARN_ON(reduced_clock->p2 != clock->p2); 908 909 /* 910 * Bspec: 911 * "[Almador Errata}: For the correct operation of the muxed DVO pins 912 * (GDEVSELB/I2Cdata, GIRDBY/I2CClk) and (GFRAMEB/DVI_Data, 913 * GTRDYB/DVI_Clk): Bit 31 (DPLL VCO Enable) and Bit 30 (2X Clock 914 * Enable) must be set to “1” in both the DPLL A Control Register 915 * (06014h-06017h) and DPLL B Control Register (06018h-0601Bh)." 916 * 917 * For simplicity We simply keep both bits always enabled in 918 * both DPLLS. The spec says we should disable the DVO 2X clock 919 * when not needed, but this seems to work fine in practice. 920 */ 921 if (IS_I830(dev_priv) || 922 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) 923 dpll |= DPLL_DVO_2X_MODE; 924 925 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 926 intel_panel_use_ssc(dev_priv)) 927 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 928 else 929 dpll |= PLL_REF_INPUT_DREFCLK; 930 931 dpll |= DPLL_VCO_ENABLE; 932 crtc_state->dpll_hw_state.dpll = dpll; 933 } 934 935 static int hsw_crtc_compute_clock(struct intel_atomic_state *state, 936 struct intel_crtc *crtc) 937 { 938 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 939 struct intel_crtc_state *crtc_state = 940 intel_atomic_get_new_crtc_state(state, crtc); 941 struct intel_encoder *encoder = 942 intel_get_crtc_new_encoder(state, crtc_state); 943 int ret; 944 945 if (DISPLAY_VER(dev_priv) < 11 && 946 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 947 return 0; 948 949 ret = intel_compute_shared_dplls(state, crtc, encoder); 950 if (ret) 951 return ret; 952 953 /* FIXME this is a mess */ 954 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 955 return 0; 956 957 /* CRT dotclock is determined via other means */ 958 if (!crtc_state->has_pch_encoder) 959 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 960 961 return 0; 962 } 963 964 static int hsw_crtc_get_shared_dpll(struct intel_atomic_state *state, 965 struct intel_crtc *crtc) 966 { 967 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 968 struct intel_crtc_state *crtc_state = 969 intel_atomic_get_new_crtc_state(state, crtc); 970 struct intel_encoder *encoder = 971 intel_get_crtc_new_encoder(state, crtc_state); 972 973 if (DISPLAY_VER(dev_priv) < 11 && 974 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 975 return 0; 976 977 return intel_reserve_shared_dplls(state, crtc, encoder); 978 } 979 980 static int dg2_crtc_compute_clock(struct intel_atomic_state *state, 981 struct intel_crtc *crtc) 982 { 983 struct intel_crtc_state *crtc_state = 984 intel_atomic_get_new_crtc_state(state, crtc); 985 struct intel_encoder *encoder = 986 intel_get_crtc_new_encoder(state, crtc_state); 987 int ret; 988 989 ret = intel_mpllb_calc_state(crtc_state, encoder); 990 if (ret) 991 return ret; 992 993 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 994 995 return 0; 996 } 997 998 static bool ilk_needs_fb_cb_tune(const struct dpll *dpll, int factor) 999 { 1000 return dpll->m < factor * dpll->n; 1001 } 1002 1003 static void ilk_update_pll_dividers(struct intel_crtc_state *crtc_state, 1004 const struct dpll *clock, 1005 const struct dpll *reduced_clock) 1006 { 1007 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1008 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1009 u32 fp, fp2; 1010 int factor; 1011 1012 /* Enable autotuning of the PLL clock (if permissible) */ 1013 factor = 21; 1014 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1015 if ((intel_panel_use_ssc(dev_priv) && 1016 dev_priv->display.vbt.lvds_ssc_freq == 100000) || 1017 (HAS_PCH_IBX(dev_priv) && 1018 intel_is_dual_link_lvds(dev_priv))) 1019 factor = 25; 1020 } else if (crtc_state->sdvo_tv_clock) { 1021 factor = 20; 1022 } 1023 1024 fp = i9xx_dpll_compute_fp(clock); 1025 if (ilk_needs_fb_cb_tune(clock, factor)) 1026 fp |= FP_CB_TUNE; 1027 1028 fp2 = i9xx_dpll_compute_fp(reduced_clock); 1029 if (ilk_needs_fb_cb_tune(reduced_clock, factor)) 1030 fp2 |= FP_CB_TUNE; 1031 1032 crtc_state->dpll_hw_state.fp0 = fp; 1033 crtc_state->dpll_hw_state.fp1 = fp2; 1034 } 1035 1036 static void ilk_compute_dpll(struct intel_crtc_state *crtc_state, 1037 const struct dpll *clock, 1038 const struct dpll *reduced_clock) 1039 { 1040 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1041 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1042 u32 dpll; 1043 1044 ilk_update_pll_dividers(crtc_state, clock, reduced_clock); 1045 1046 dpll = 0; 1047 1048 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) 1049 dpll |= DPLLB_MODE_LVDS; 1050 else 1051 dpll |= DPLLB_MODE_DAC_SERIAL; 1052 1053 dpll |= (crtc_state->pixel_multiplier - 1) 1054 << PLL_REF_SDVO_HDMI_MULTIPLIER_SHIFT; 1055 1056 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO) || 1057 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1058 dpll |= DPLL_SDVO_HIGH_SPEED; 1059 1060 if (intel_crtc_has_dp_encoder(crtc_state)) 1061 dpll |= DPLL_SDVO_HIGH_SPEED; 1062 1063 /* 1064 * The high speed IO clock is only really required for 1065 * SDVO/HDMI/DP, but we also enable it for CRT to make it 1066 * possible to share the DPLL between CRT and HDMI. Enabling 1067 * the clock needlessly does no real harm, except use up a 1068 * bit of power potentially. 1069 * 1070 * We'll limit this to IVB with 3 pipes, since it has only two 1071 * DPLLs and so DPLL sharing is the only way to get three pipes 1072 * driving PCH ports at the same time. On SNB we could do this, 1073 * and potentially avoid enabling the second DPLL, but it's not 1074 * clear if it''s a win or loss power wise. No point in doing 1075 * this on ILK at all since it has a fixed DPLL<->pipe mapping. 1076 */ 1077 if (INTEL_NUM_PIPES(dev_priv) == 3 && 1078 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) 1079 dpll |= DPLL_SDVO_HIGH_SPEED; 1080 1081 /* compute bitmask from p1 value */ 1082 dpll |= (1 << (clock->p1 - 1)) << DPLL_FPA01_P1_POST_DIV_SHIFT; 1083 /* also FPA1 */ 1084 dpll |= (1 << (reduced_clock->p1 - 1)) << DPLL_FPA1_P1_POST_DIV_SHIFT; 1085 1086 switch (clock->p2) { 1087 case 5: 1088 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_5; 1089 break; 1090 case 7: 1091 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_7; 1092 break; 1093 case 10: 1094 dpll |= DPLL_DAC_SERIAL_P2_CLOCK_DIV_10; 1095 break; 1096 case 14: 1097 dpll |= DPLLB_LVDS_P2_CLOCK_DIV_14; 1098 break; 1099 } 1100 WARN_ON(reduced_clock->p2 != clock->p2); 1101 1102 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS) && 1103 intel_panel_use_ssc(dev_priv)) 1104 dpll |= PLLB_REF_INPUT_SPREADSPECTRUMIN; 1105 else 1106 dpll |= PLL_REF_INPUT_DREFCLK; 1107 1108 dpll |= DPLL_VCO_ENABLE; 1109 1110 crtc_state->dpll_hw_state.dpll = dpll; 1111 } 1112 1113 static int ilk_crtc_compute_clock(struct intel_atomic_state *state, 1114 struct intel_crtc *crtc) 1115 { 1116 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1117 struct intel_crtc_state *crtc_state = 1118 intel_atomic_get_new_crtc_state(state, crtc); 1119 const struct intel_limit *limit; 1120 int refclk = 120000; 1121 int ret; 1122 1123 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 1124 if (!crtc_state->has_pch_encoder) 1125 return 0; 1126 1127 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1128 if (intel_panel_use_ssc(dev_priv)) { 1129 drm_dbg_kms(&dev_priv->drm, 1130 "using SSC reference clock of %d kHz\n", 1131 dev_priv->display.vbt.lvds_ssc_freq); 1132 refclk = dev_priv->display.vbt.lvds_ssc_freq; 1133 } 1134 1135 if (intel_is_dual_link_lvds(dev_priv)) { 1136 if (refclk == 100000) 1137 limit = &ilk_limits_dual_lvds_100m; 1138 else 1139 limit = &ilk_limits_dual_lvds; 1140 } else { 1141 if (refclk == 100000) 1142 limit = &ilk_limits_single_lvds_100m; 1143 else 1144 limit = &ilk_limits_single_lvds; 1145 } 1146 } else { 1147 limit = &ilk_limits_dac; 1148 } 1149 1150 if (!crtc_state->clock_set && 1151 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1152 refclk, NULL, &crtc_state->dpll)) 1153 return -EINVAL; 1154 1155 ilk_compute_dpll(crtc_state, &crtc_state->dpll, 1156 &crtc_state->dpll); 1157 1158 ret = intel_compute_shared_dplls(state, crtc, NULL); 1159 if (ret) 1160 return ret; 1161 1162 crtc_state->port_clock = crtc_state->dpll.dot; 1163 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1164 1165 return ret; 1166 } 1167 1168 static int ilk_crtc_get_shared_dpll(struct intel_atomic_state *state, 1169 struct intel_crtc *crtc) 1170 { 1171 struct intel_crtc_state *crtc_state = 1172 intel_atomic_get_new_crtc_state(state, crtc); 1173 1174 /* CPU eDP is the only output that doesn't need a PCH PLL of its own. */ 1175 if (!crtc_state->has_pch_encoder) 1176 return 0; 1177 1178 return intel_reserve_shared_dplls(state, crtc, NULL); 1179 } 1180 1181 void vlv_compute_dpll(struct intel_crtc_state *crtc_state) 1182 { 1183 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1184 1185 crtc_state->dpll_hw_state.dpll = DPLL_INTEGRATED_REF_CLK_VLV | 1186 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1187 if (crtc->pipe != PIPE_A) 1188 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 1189 1190 /* DPLL not used with DSI, but still need the rest set up */ 1191 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1192 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE | 1193 DPLL_EXT_BUFFER_ENABLE_VLV; 1194 1195 crtc_state->dpll_hw_state.dpll_md = 1196 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 1197 } 1198 1199 void chv_compute_dpll(struct intel_crtc_state *crtc_state) 1200 { 1201 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1202 1203 crtc_state->dpll_hw_state.dpll = DPLL_SSC_REF_CLK_CHV | 1204 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1205 if (crtc->pipe != PIPE_A) 1206 crtc_state->dpll_hw_state.dpll |= DPLL_INTEGRATED_CRI_CLK_VLV; 1207 1208 /* DPLL not used with DSI, but still need the rest set up */ 1209 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1210 crtc_state->dpll_hw_state.dpll |= DPLL_VCO_ENABLE; 1211 1212 crtc_state->dpll_hw_state.dpll_md = 1213 (crtc_state->pixel_multiplier - 1) << DPLL_MD_UDI_MULTIPLIER_SHIFT; 1214 } 1215 1216 static int chv_crtc_compute_clock(struct intel_atomic_state *state, 1217 struct intel_crtc *crtc) 1218 { 1219 struct intel_crtc_state *crtc_state = 1220 intel_atomic_get_new_crtc_state(state, crtc); 1221 const struct intel_limit *limit = &intel_limits_chv; 1222 int refclk = 100000; 1223 1224 if (!crtc_state->clock_set && 1225 !chv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1226 refclk, NULL, &crtc_state->dpll)) 1227 return -EINVAL; 1228 1229 chv_compute_dpll(crtc_state); 1230 1231 /* FIXME this is a mess */ 1232 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1233 return 0; 1234 1235 crtc_state->port_clock = crtc_state->dpll.dot; 1236 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1237 1238 return 0; 1239 } 1240 1241 static int vlv_crtc_compute_clock(struct intel_atomic_state *state, 1242 struct intel_crtc *crtc) 1243 { 1244 struct intel_crtc_state *crtc_state = 1245 intel_atomic_get_new_crtc_state(state, crtc); 1246 const struct intel_limit *limit = &intel_limits_vlv; 1247 int refclk = 100000; 1248 1249 if (!crtc_state->clock_set && 1250 !vlv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1251 refclk, NULL, &crtc_state->dpll)) { 1252 return -EINVAL; 1253 } 1254 1255 vlv_compute_dpll(crtc_state); 1256 1257 /* FIXME this is a mess */ 1258 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DSI)) 1259 return 0; 1260 1261 crtc_state->port_clock = crtc_state->dpll.dot; 1262 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1263 1264 return 0; 1265 } 1266 1267 static int g4x_crtc_compute_clock(struct intel_atomic_state *state, 1268 struct intel_crtc *crtc) 1269 { 1270 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1271 struct intel_crtc_state *crtc_state = 1272 intel_atomic_get_new_crtc_state(state, crtc); 1273 const struct intel_limit *limit; 1274 int refclk = 96000; 1275 1276 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1277 if (intel_panel_use_ssc(dev_priv)) { 1278 refclk = dev_priv->display.vbt.lvds_ssc_freq; 1279 drm_dbg_kms(&dev_priv->drm, 1280 "using SSC reference clock of %d kHz\n", 1281 refclk); 1282 } 1283 1284 if (intel_is_dual_link_lvds(dev_priv)) 1285 limit = &intel_limits_g4x_dual_channel_lvds; 1286 else 1287 limit = &intel_limits_g4x_single_channel_lvds; 1288 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI) || 1289 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG)) { 1290 limit = &intel_limits_g4x_hdmi; 1291 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_SDVO)) { 1292 limit = &intel_limits_g4x_sdvo; 1293 } else { 1294 /* The option is for other outputs */ 1295 limit = &intel_limits_i9xx_sdvo; 1296 } 1297 1298 if (!crtc_state->clock_set && 1299 !g4x_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1300 refclk, NULL, &crtc_state->dpll)) 1301 return -EINVAL; 1302 1303 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, 1304 &crtc_state->dpll); 1305 1306 crtc_state->port_clock = crtc_state->dpll.dot; 1307 /* FIXME this is a mess */ 1308 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_TVOUT)) 1309 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1310 1311 return 0; 1312 } 1313 1314 static int pnv_crtc_compute_clock(struct intel_atomic_state *state, 1315 struct intel_crtc *crtc) 1316 { 1317 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1318 struct intel_crtc_state *crtc_state = 1319 intel_atomic_get_new_crtc_state(state, crtc); 1320 const struct intel_limit *limit; 1321 int refclk = 96000; 1322 1323 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1324 if (intel_panel_use_ssc(dev_priv)) { 1325 refclk = dev_priv->display.vbt.lvds_ssc_freq; 1326 drm_dbg_kms(&dev_priv->drm, 1327 "using SSC reference clock of %d kHz\n", 1328 refclk); 1329 } 1330 1331 limit = &pnv_limits_lvds; 1332 } else { 1333 limit = &pnv_limits_sdvo; 1334 } 1335 1336 if (!crtc_state->clock_set && 1337 !pnv_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1338 refclk, NULL, &crtc_state->dpll)) 1339 return -EINVAL; 1340 1341 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, 1342 &crtc_state->dpll); 1343 1344 crtc_state->port_clock = crtc_state->dpll.dot; 1345 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1346 1347 return 0; 1348 } 1349 1350 static int i9xx_crtc_compute_clock(struct intel_atomic_state *state, 1351 struct intel_crtc *crtc) 1352 { 1353 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1354 struct intel_crtc_state *crtc_state = 1355 intel_atomic_get_new_crtc_state(state, crtc); 1356 const struct intel_limit *limit; 1357 int refclk = 96000; 1358 1359 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1360 if (intel_panel_use_ssc(dev_priv)) { 1361 refclk = dev_priv->display.vbt.lvds_ssc_freq; 1362 drm_dbg_kms(&dev_priv->drm, 1363 "using SSC reference clock of %d kHz\n", 1364 refclk); 1365 } 1366 1367 limit = &intel_limits_i9xx_lvds; 1368 } else { 1369 limit = &intel_limits_i9xx_sdvo; 1370 } 1371 1372 if (!crtc_state->clock_set && 1373 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1374 refclk, NULL, &crtc_state->dpll)) 1375 return -EINVAL; 1376 1377 i9xx_compute_dpll(crtc_state, &crtc_state->dpll, 1378 &crtc_state->dpll); 1379 1380 crtc_state->port_clock = crtc_state->dpll.dot; 1381 /* FIXME this is a mess */ 1382 if (!intel_crtc_has_type(crtc_state, INTEL_OUTPUT_TVOUT)) 1383 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1384 1385 return 0; 1386 } 1387 1388 static int i8xx_crtc_compute_clock(struct intel_atomic_state *state, 1389 struct intel_crtc *crtc) 1390 { 1391 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 1392 struct intel_crtc_state *crtc_state = 1393 intel_atomic_get_new_crtc_state(state, crtc); 1394 const struct intel_limit *limit; 1395 int refclk = 48000; 1396 1397 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_LVDS)) { 1398 if (intel_panel_use_ssc(dev_priv)) { 1399 refclk = dev_priv->display.vbt.lvds_ssc_freq; 1400 drm_dbg_kms(&dev_priv->drm, 1401 "using SSC reference clock of %d kHz\n", 1402 refclk); 1403 } 1404 1405 limit = &intel_limits_i8xx_lvds; 1406 } else if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DVO)) { 1407 limit = &intel_limits_i8xx_dvo; 1408 } else { 1409 limit = &intel_limits_i8xx_dac; 1410 } 1411 1412 if (!crtc_state->clock_set && 1413 !i9xx_find_best_dpll(limit, crtc_state, crtc_state->port_clock, 1414 refclk, NULL, &crtc_state->dpll)) 1415 return -EINVAL; 1416 1417 i8xx_compute_dpll(crtc_state, &crtc_state->dpll, 1418 &crtc_state->dpll); 1419 1420 crtc_state->port_clock = crtc_state->dpll.dot; 1421 crtc_state->hw.adjusted_mode.crtc_clock = intel_crtc_dotclock(crtc_state); 1422 1423 return 0; 1424 } 1425 1426 static const struct intel_dpll_funcs dg2_dpll_funcs = { 1427 .crtc_compute_clock = dg2_crtc_compute_clock, 1428 }; 1429 1430 static const struct intel_dpll_funcs hsw_dpll_funcs = { 1431 .crtc_compute_clock = hsw_crtc_compute_clock, 1432 .crtc_get_shared_dpll = hsw_crtc_get_shared_dpll, 1433 }; 1434 1435 static const struct intel_dpll_funcs ilk_dpll_funcs = { 1436 .crtc_compute_clock = ilk_crtc_compute_clock, 1437 .crtc_get_shared_dpll = ilk_crtc_get_shared_dpll, 1438 }; 1439 1440 static const struct intel_dpll_funcs chv_dpll_funcs = { 1441 .crtc_compute_clock = chv_crtc_compute_clock, 1442 }; 1443 1444 static const struct intel_dpll_funcs vlv_dpll_funcs = { 1445 .crtc_compute_clock = vlv_crtc_compute_clock, 1446 }; 1447 1448 static const struct intel_dpll_funcs g4x_dpll_funcs = { 1449 .crtc_compute_clock = g4x_crtc_compute_clock, 1450 }; 1451 1452 static const struct intel_dpll_funcs pnv_dpll_funcs = { 1453 .crtc_compute_clock = pnv_crtc_compute_clock, 1454 }; 1455 1456 static const struct intel_dpll_funcs i9xx_dpll_funcs = { 1457 .crtc_compute_clock = i9xx_crtc_compute_clock, 1458 }; 1459 1460 static const struct intel_dpll_funcs i8xx_dpll_funcs = { 1461 .crtc_compute_clock = i8xx_crtc_compute_clock, 1462 }; 1463 1464 int intel_dpll_crtc_compute_clock(struct intel_atomic_state *state, 1465 struct intel_crtc *crtc) 1466 { 1467 struct drm_i915_private *i915 = to_i915(state->base.dev); 1468 struct intel_crtc_state *crtc_state = 1469 intel_atomic_get_new_crtc_state(state, crtc); 1470 int ret; 1471 1472 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); 1473 1474 memset(&crtc_state->dpll_hw_state, 0, 1475 sizeof(crtc_state->dpll_hw_state)); 1476 1477 if (!crtc_state->hw.enable) 1478 return 0; 1479 1480 ret = i915->display.funcs.dpll->crtc_compute_clock(state, crtc); 1481 if (ret) { 1482 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't calculate DPLL settings\n", 1483 crtc->base.base.id, crtc->base.name); 1484 return ret; 1485 } 1486 1487 return 0; 1488 } 1489 1490 int intel_dpll_crtc_get_shared_dpll(struct intel_atomic_state *state, 1491 struct intel_crtc *crtc) 1492 { 1493 struct drm_i915_private *i915 = to_i915(state->base.dev); 1494 struct intel_crtc_state *crtc_state = 1495 intel_atomic_get_new_crtc_state(state, crtc); 1496 int ret; 1497 1498 drm_WARN_ON(&i915->drm, !intel_crtc_needs_modeset(crtc_state)); 1499 drm_WARN_ON(&i915->drm, !crtc_state->hw.enable && crtc_state->shared_dpll); 1500 1501 if (!crtc_state->hw.enable || crtc_state->shared_dpll) 1502 return 0; 1503 1504 if (!i915->display.funcs.dpll->crtc_get_shared_dpll) 1505 return 0; 1506 1507 ret = i915->display.funcs.dpll->crtc_get_shared_dpll(state, crtc); 1508 if (ret) { 1509 drm_dbg_kms(&i915->drm, "[CRTC:%d:%s] Couldn't get a shared DPLL\n", 1510 crtc->base.base.id, crtc->base.name); 1511 return ret; 1512 } 1513 1514 return 0; 1515 } 1516 1517 void 1518 intel_dpll_init_clock_hook(struct drm_i915_private *dev_priv) 1519 { 1520 if (IS_DG2(dev_priv)) 1521 dev_priv->display.funcs.dpll = &dg2_dpll_funcs; 1522 else if (DISPLAY_VER(dev_priv) >= 9 || HAS_DDI(dev_priv)) 1523 dev_priv->display.funcs.dpll = &hsw_dpll_funcs; 1524 else if (HAS_PCH_SPLIT(dev_priv)) 1525 dev_priv->display.funcs.dpll = &ilk_dpll_funcs; 1526 else if (IS_CHERRYVIEW(dev_priv)) 1527 dev_priv->display.funcs.dpll = &chv_dpll_funcs; 1528 else if (IS_VALLEYVIEW(dev_priv)) 1529 dev_priv->display.funcs.dpll = &vlv_dpll_funcs; 1530 else if (IS_G4X(dev_priv)) 1531 dev_priv->display.funcs.dpll = &g4x_dpll_funcs; 1532 else if (IS_PINEVIEW(dev_priv)) 1533 dev_priv->display.funcs.dpll = &pnv_dpll_funcs; 1534 else if (DISPLAY_VER(dev_priv) != 2) 1535 dev_priv->display.funcs.dpll = &i9xx_dpll_funcs; 1536 else 1537 dev_priv->display.funcs.dpll = &i8xx_dpll_funcs; 1538 } 1539 1540 static bool i9xx_has_pps(struct drm_i915_private *dev_priv) 1541 { 1542 if (IS_I830(dev_priv)) 1543 return false; 1544 1545 return IS_PINEVIEW(dev_priv) || IS_MOBILE(dev_priv); 1546 } 1547 1548 void i9xx_enable_pll(const struct intel_crtc_state *crtc_state) 1549 { 1550 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1551 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1552 u32 dpll = crtc_state->dpll_hw_state.dpll; 1553 enum pipe pipe = crtc->pipe; 1554 int i; 1555 1556 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1557 1558 /* PLL is protected by panel, make sure we can write it */ 1559 if (i9xx_has_pps(dev_priv)) 1560 assert_pps_unlocked(dev_priv, pipe); 1561 1562 intel_de_write(dev_priv, FP0(pipe), crtc_state->dpll_hw_state.fp0); 1563 intel_de_write(dev_priv, FP1(pipe), crtc_state->dpll_hw_state.fp1); 1564 1565 /* 1566 * Apparently we need to have VGA mode enabled prior to changing 1567 * the P1/P2 dividers. Otherwise the DPLL will keep using the old 1568 * dividers, even though the register value does change. 1569 */ 1570 intel_de_write(dev_priv, DPLL(pipe), dpll & ~DPLL_VGA_MODE_DIS); 1571 intel_de_write(dev_priv, DPLL(pipe), dpll); 1572 1573 /* Wait for the clocks to stabilize. */ 1574 intel_de_posting_read(dev_priv, DPLL(pipe)); 1575 udelay(150); 1576 1577 if (DISPLAY_VER(dev_priv) >= 4) { 1578 intel_de_write(dev_priv, DPLL_MD(pipe), 1579 crtc_state->dpll_hw_state.dpll_md); 1580 } else { 1581 /* The pixel multiplier can only be updated once the 1582 * DPLL is enabled and the clocks are stable. 1583 * 1584 * So write it again. 1585 */ 1586 intel_de_write(dev_priv, DPLL(pipe), dpll); 1587 } 1588 1589 /* We do this three times for luck */ 1590 for (i = 0; i < 3; i++) { 1591 intel_de_write(dev_priv, DPLL(pipe), dpll); 1592 intel_de_posting_read(dev_priv, DPLL(pipe)); 1593 udelay(150); /* wait for warmup */ 1594 } 1595 } 1596 1597 static void vlv_pllb_recal_opamp(struct drm_i915_private *dev_priv, 1598 enum pipe pipe) 1599 { 1600 u32 reg_val; 1601 1602 /* 1603 * PLLB opamp always calibrates to max value of 0x3f, force enable it 1604 * and set it to a reasonable value instead. 1605 */ 1606 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); 1607 reg_val &= 0xffffff00; 1608 reg_val |= 0x00000030; 1609 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); 1610 1611 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); 1612 reg_val &= 0x00ffffff; 1613 reg_val |= 0x8c000000; 1614 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 1615 1616 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW9(1)); 1617 reg_val &= 0xffffff00; 1618 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9(1), reg_val); 1619 1620 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_REF_DW13); 1621 reg_val &= 0x00ffffff; 1622 reg_val |= 0xb0000000; 1623 vlv_dpio_write(dev_priv, pipe, VLV_REF_DW13, reg_val); 1624 } 1625 1626 static void vlv_prepare_pll(const struct intel_crtc_state *crtc_state) 1627 { 1628 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1629 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1630 enum pipe pipe = crtc->pipe; 1631 u32 mdiv; 1632 u32 bestn, bestm1, bestm2, bestp1, bestp2; 1633 u32 coreclk, reg_val; 1634 1635 vlv_dpio_get(dev_priv); 1636 1637 bestn = crtc_state->dpll.n; 1638 bestm1 = crtc_state->dpll.m1; 1639 bestm2 = crtc_state->dpll.m2; 1640 bestp1 = crtc_state->dpll.p1; 1641 bestp2 = crtc_state->dpll.p2; 1642 1643 /* See eDP HDMI DPIO driver vbios notes doc */ 1644 1645 /* PLL B needs special handling */ 1646 if (pipe == PIPE_B) 1647 vlv_pllb_recal_opamp(dev_priv, pipe); 1648 1649 /* Set up Tx target for periodic Rcomp update */ 1650 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW9_BCAST, 0x0100000f); 1651 1652 /* Disable target IRef on PLL */ 1653 reg_val = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW8(pipe)); 1654 reg_val &= 0x00ffffff; 1655 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW8(pipe), reg_val); 1656 1657 /* Disable fast lock */ 1658 vlv_dpio_write(dev_priv, pipe, VLV_CMN_DW0, 0x610); 1659 1660 /* Set idtafcrecal before PLL is enabled */ 1661 mdiv = ((bestm1 << DPIO_M1DIV_SHIFT) | (bestm2 & DPIO_M2DIV_MASK)); 1662 mdiv |= ((bestp1 << DPIO_P1_SHIFT) | (bestp2 << DPIO_P2_SHIFT)); 1663 mdiv |= ((bestn << DPIO_N_SHIFT)); 1664 mdiv |= (1 << DPIO_K_SHIFT); 1665 1666 /* 1667 * Post divider depends on pixel clock rate, DAC vs digital (and LVDS, 1668 * but we don't support that). 1669 * Note: don't use the DAC post divider as it seems unstable. 1670 */ 1671 mdiv |= (DPIO_POST_DIV_HDMIDP << DPIO_POST_DIV_SHIFT); 1672 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); 1673 1674 mdiv |= DPIO_ENABLE_CALIBRATION; 1675 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW3(pipe), mdiv); 1676 1677 /* Set HBR and RBR LPF coefficients */ 1678 if (crtc_state->port_clock == 162000 || 1679 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_ANALOG) || 1680 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_HDMI)) 1681 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 1682 0x009f0003); 1683 else 1684 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW10(pipe), 1685 0x00d0000f); 1686 1687 if (intel_crtc_has_dp_encoder(crtc_state)) { 1688 /* Use SSC source */ 1689 if (pipe == PIPE_A) 1690 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1691 0x0df40000); 1692 else 1693 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1694 0x0df70000); 1695 } else { /* HDMI or VGA */ 1696 /* Use bend source */ 1697 if (pipe == PIPE_A) 1698 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1699 0x0df70000); 1700 else 1701 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW5(pipe), 1702 0x0df40000); 1703 } 1704 1705 coreclk = vlv_dpio_read(dev_priv, pipe, VLV_PLL_DW7(pipe)); 1706 coreclk = (coreclk & 0x0000ff00) | 0x01c00000; 1707 if (intel_crtc_has_dp_encoder(crtc_state)) 1708 coreclk |= 0x01000000; 1709 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW7(pipe), coreclk); 1710 1711 vlv_dpio_write(dev_priv, pipe, VLV_PLL_DW11(pipe), 0x87871000); 1712 1713 vlv_dpio_put(dev_priv); 1714 } 1715 1716 static void _vlv_enable_pll(const struct intel_crtc_state *crtc_state) 1717 { 1718 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1719 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1720 enum pipe pipe = crtc->pipe; 1721 1722 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); 1723 intel_de_posting_read(dev_priv, DPLL(pipe)); 1724 udelay(150); 1725 1726 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) 1727 drm_err(&dev_priv->drm, "DPLL %d failed to lock\n", pipe); 1728 } 1729 1730 void vlv_enable_pll(const struct intel_crtc_state *crtc_state) 1731 { 1732 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1733 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1734 enum pipe pipe = crtc->pipe; 1735 1736 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1737 1738 /* PLL is protected by panel, make sure we can write it */ 1739 assert_pps_unlocked(dev_priv, pipe); 1740 1741 /* Enable Refclk */ 1742 intel_de_write(dev_priv, DPLL(pipe), 1743 crtc_state->dpll_hw_state.dpll & 1744 ~(DPLL_VCO_ENABLE | DPLL_EXT_BUFFER_ENABLE_VLV)); 1745 1746 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { 1747 vlv_prepare_pll(crtc_state); 1748 _vlv_enable_pll(crtc_state); 1749 } 1750 1751 intel_de_write(dev_priv, DPLL_MD(pipe), 1752 crtc_state->dpll_hw_state.dpll_md); 1753 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); 1754 } 1755 1756 static void chv_prepare_pll(const struct intel_crtc_state *crtc_state) 1757 { 1758 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1759 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1760 enum pipe pipe = crtc->pipe; 1761 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1762 u32 loopfilter, tribuf_calcntr; 1763 u32 bestn, bestm1, bestm2, bestp1, bestp2, bestm2_frac; 1764 u32 dpio_val; 1765 int vco; 1766 1767 bestn = crtc_state->dpll.n; 1768 bestm2_frac = crtc_state->dpll.m2 & 0x3fffff; 1769 bestm1 = crtc_state->dpll.m1; 1770 bestm2 = crtc_state->dpll.m2 >> 22; 1771 bestp1 = crtc_state->dpll.p1; 1772 bestp2 = crtc_state->dpll.p2; 1773 vco = crtc_state->dpll.vco; 1774 dpio_val = 0; 1775 loopfilter = 0; 1776 1777 vlv_dpio_get(dev_priv); 1778 1779 /* p1 and p2 divider */ 1780 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW13(port), 1781 5 << DPIO_CHV_S1_DIV_SHIFT | 1782 bestp1 << DPIO_CHV_P1_DIV_SHIFT | 1783 bestp2 << DPIO_CHV_P2_DIV_SHIFT | 1784 1 << DPIO_CHV_K_DIV_SHIFT); 1785 1786 /* Feedback post-divider - m2 */ 1787 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW0(port), bestm2); 1788 1789 /* Feedback refclk divider - n and m1 */ 1790 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW1(port), 1791 DPIO_CHV_M1_DIV_BY_2 | 1792 1 << DPIO_CHV_N_DIV_SHIFT); 1793 1794 /* M2 fraction division */ 1795 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW2(port), bestm2_frac); 1796 1797 /* M2 fraction division enable */ 1798 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW3(port)); 1799 dpio_val &= ~(DPIO_CHV_FEEDFWD_GAIN_MASK | DPIO_CHV_FRAC_DIV_EN); 1800 dpio_val |= (2 << DPIO_CHV_FEEDFWD_GAIN_SHIFT); 1801 if (bestm2_frac) 1802 dpio_val |= DPIO_CHV_FRAC_DIV_EN; 1803 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW3(port), dpio_val); 1804 1805 /* Program digital lock detect threshold */ 1806 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW9(port)); 1807 dpio_val &= ~(DPIO_CHV_INT_LOCK_THRESHOLD_MASK | 1808 DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE); 1809 dpio_val |= (0x5 << DPIO_CHV_INT_LOCK_THRESHOLD_SHIFT); 1810 if (!bestm2_frac) 1811 dpio_val |= DPIO_CHV_INT_LOCK_THRESHOLD_SEL_COARSE; 1812 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW9(port), dpio_val); 1813 1814 /* Loop filter */ 1815 if (vco == 5400000) { 1816 loopfilter |= (0x3 << DPIO_CHV_PROP_COEFF_SHIFT); 1817 loopfilter |= (0x8 << DPIO_CHV_INT_COEFF_SHIFT); 1818 loopfilter |= (0x1 << DPIO_CHV_GAIN_CTRL_SHIFT); 1819 tribuf_calcntr = 0x9; 1820 } else if (vco <= 6200000) { 1821 loopfilter |= (0x5 << DPIO_CHV_PROP_COEFF_SHIFT); 1822 loopfilter |= (0xB << DPIO_CHV_INT_COEFF_SHIFT); 1823 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1824 tribuf_calcntr = 0x9; 1825 } else if (vco <= 6480000) { 1826 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 1827 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 1828 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1829 tribuf_calcntr = 0x8; 1830 } else { 1831 /* Not supported. Apply the same limits as in the max case */ 1832 loopfilter |= (0x4 << DPIO_CHV_PROP_COEFF_SHIFT); 1833 loopfilter |= (0x9 << DPIO_CHV_INT_COEFF_SHIFT); 1834 loopfilter |= (0x3 << DPIO_CHV_GAIN_CTRL_SHIFT); 1835 tribuf_calcntr = 0; 1836 } 1837 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW6(port), loopfilter); 1838 1839 dpio_val = vlv_dpio_read(dev_priv, pipe, CHV_PLL_DW8(port)); 1840 dpio_val &= ~DPIO_CHV_TDC_TARGET_CNT_MASK; 1841 dpio_val |= (tribuf_calcntr << DPIO_CHV_TDC_TARGET_CNT_SHIFT); 1842 vlv_dpio_write(dev_priv, pipe, CHV_PLL_DW8(port), dpio_val); 1843 1844 /* AFC Recal */ 1845 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), 1846 vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)) | 1847 DPIO_AFC_RECAL); 1848 1849 vlv_dpio_put(dev_priv); 1850 } 1851 1852 static void _chv_enable_pll(const struct intel_crtc_state *crtc_state) 1853 { 1854 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1855 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1856 enum pipe pipe = crtc->pipe; 1857 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1858 u32 tmp; 1859 1860 vlv_dpio_get(dev_priv); 1861 1862 /* Enable back the 10bit clock to display controller */ 1863 tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); 1864 tmp |= DPIO_DCLKP_EN; 1865 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), tmp); 1866 1867 vlv_dpio_put(dev_priv); 1868 1869 /* 1870 * Need to wait > 100ns between dclkp clock enable bit and PLL enable. 1871 */ 1872 udelay(1); 1873 1874 /* Enable PLL */ 1875 intel_de_write(dev_priv, DPLL(pipe), crtc_state->dpll_hw_state.dpll); 1876 1877 /* Check PLL is locked */ 1878 if (intel_de_wait_for_set(dev_priv, DPLL(pipe), DPLL_LOCK_VLV, 1)) 1879 drm_err(&dev_priv->drm, "PLL %d failed to lock\n", pipe); 1880 } 1881 1882 void chv_enable_pll(const struct intel_crtc_state *crtc_state) 1883 { 1884 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1885 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1886 enum pipe pipe = crtc->pipe; 1887 1888 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 1889 1890 /* PLL is protected by panel, make sure we can write it */ 1891 assert_pps_unlocked(dev_priv, pipe); 1892 1893 /* Enable Refclk and SSC */ 1894 intel_de_write(dev_priv, DPLL(pipe), 1895 crtc_state->dpll_hw_state.dpll & ~DPLL_VCO_ENABLE); 1896 1897 if (crtc_state->dpll_hw_state.dpll & DPLL_VCO_ENABLE) { 1898 chv_prepare_pll(crtc_state); 1899 _chv_enable_pll(crtc_state); 1900 } 1901 1902 if (pipe != PIPE_A) { 1903 /* 1904 * WaPixelRepeatModeFixForC0:chv 1905 * 1906 * DPLLCMD is AWOL. Use chicken bits to propagate 1907 * the value from DPLLBMD to either pipe B or C. 1908 */ 1909 intel_de_write(dev_priv, CBR4_VLV, CBR_DPLLBMD_PIPE(pipe)); 1910 intel_de_write(dev_priv, DPLL_MD(PIPE_B), 1911 crtc_state->dpll_hw_state.dpll_md); 1912 intel_de_write(dev_priv, CBR4_VLV, 0); 1913 dev_priv->chv_dpll_md[pipe] = crtc_state->dpll_hw_state.dpll_md; 1914 1915 /* 1916 * DPLLB VGA mode also seems to cause problems. 1917 * We should always have it disabled. 1918 */ 1919 drm_WARN_ON(&dev_priv->drm, 1920 (intel_de_read(dev_priv, DPLL(PIPE_B)) & 1921 DPLL_VGA_MODE_DIS) == 0); 1922 } else { 1923 intel_de_write(dev_priv, DPLL_MD(pipe), 1924 crtc_state->dpll_hw_state.dpll_md); 1925 intel_de_posting_read(dev_priv, DPLL_MD(pipe)); 1926 } 1927 } 1928 1929 /** 1930 * vlv_force_pll_on - forcibly enable just the PLL 1931 * @dev_priv: i915 private structure 1932 * @pipe: pipe PLL to enable 1933 * @dpll: PLL configuration 1934 * 1935 * Enable the PLL for @pipe using the supplied @dpll config. To be used 1936 * in cases where we need the PLL enabled even when @pipe is not going to 1937 * be enabled. 1938 */ 1939 int vlv_force_pll_on(struct drm_i915_private *dev_priv, enum pipe pipe, 1940 const struct dpll *dpll) 1941 { 1942 struct intel_crtc *crtc = intel_crtc_for_pipe(dev_priv, pipe); 1943 struct intel_crtc_state *crtc_state; 1944 1945 crtc_state = intel_crtc_state_alloc(crtc); 1946 if (!crtc_state) 1947 return -ENOMEM; 1948 1949 crtc_state->cpu_transcoder = (enum transcoder)pipe; 1950 crtc_state->pixel_multiplier = 1; 1951 crtc_state->dpll = *dpll; 1952 crtc_state->output_types = BIT(INTEL_OUTPUT_EDP); 1953 1954 if (IS_CHERRYVIEW(dev_priv)) { 1955 chv_compute_dpll(crtc_state); 1956 chv_enable_pll(crtc_state); 1957 } else { 1958 vlv_compute_dpll(crtc_state); 1959 vlv_enable_pll(crtc_state); 1960 } 1961 1962 kfree(crtc_state); 1963 1964 return 0; 1965 } 1966 1967 void vlv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 1968 { 1969 u32 val; 1970 1971 /* Make sure the pipe isn't still relying on us */ 1972 assert_transcoder_disabled(dev_priv, (enum transcoder)pipe); 1973 1974 val = DPLL_INTEGRATED_REF_CLK_VLV | 1975 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1976 if (pipe != PIPE_A) 1977 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1978 1979 intel_de_write(dev_priv, DPLL(pipe), val); 1980 intel_de_posting_read(dev_priv, DPLL(pipe)); 1981 } 1982 1983 void chv_disable_pll(struct drm_i915_private *dev_priv, enum pipe pipe) 1984 { 1985 enum dpio_channel port = vlv_pipe_to_channel(pipe); 1986 u32 val; 1987 1988 /* Make sure the pipe isn't still relying on us */ 1989 assert_transcoder_disabled(dev_priv, (enum transcoder)pipe); 1990 1991 val = DPLL_SSC_REF_CLK_CHV | 1992 DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS; 1993 if (pipe != PIPE_A) 1994 val |= DPLL_INTEGRATED_CRI_CLK_VLV; 1995 1996 intel_de_write(dev_priv, DPLL(pipe), val); 1997 intel_de_posting_read(dev_priv, DPLL(pipe)); 1998 1999 vlv_dpio_get(dev_priv); 2000 2001 /* Disable 10bit clock to display controller */ 2002 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW14(port)); 2003 val &= ~DPIO_DCLKP_EN; 2004 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW14(port), val); 2005 2006 vlv_dpio_put(dev_priv); 2007 } 2008 2009 void i9xx_disable_pll(const struct intel_crtc_state *crtc_state) 2010 { 2011 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 2012 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2013 enum pipe pipe = crtc->pipe; 2014 2015 /* Don't disable pipe or pipe PLLs if needed */ 2016 if (IS_I830(dev_priv)) 2017 return; 2018 2019 /* Make sure the pipe isn't still relying on us */ 2020 assert_transcoder_disabled(dev_priv, crtc_state->cpu_transcoder); 2021 2022 intel_de_write(dev_priv, DPLL(pipe), DPLL_VGA_MODE_DIS); 2023 intel_de_posting_read(dev_priv, DPLL(pipe)); 2024 } 2025 2026 2027 /** 2028 * vlv_force_pll_off - forcibly disable just the PLL 2029 * @dev_priv: i915 private structure 2030 * @pipe: pipe PLL to disable 2031 * 2032 * Disable the PLL for @pipe. To be used in cases where we need 2033 * the PLL enabled even when @pipe is not going to be enabled. 2034 */ 2035 void vlv_force_pll_off(struct drm_i915_private *dev_priv, enum pipe pipe) 2036 { 2037 if (IS_CHERRYVIEW(dev_priv)) 2038 chv_disable_pll(dev_priv, pipe); 2039 else 2040 vlv_disable_pll(dev_priv, pipe); 2041 } 2042 2043 /* Only for pre-ILK configs */ 2044 static void assert_pll(struct drm_i915_private *dev_priv, 2045 enum pipe pipe, bool state) 2046 { 2047 bool cur_state; 2048 2049 cur_state = intel_de_read(dev_priv, DPLL(pipe)) & DPLL_VCO_ENABLE; 2050 I915_STATE_WARN(cur_state != state, 2051 "PLL state assertion failure (expected %s, current %s)\n", 2052 str_on_off(state), str_on_off(cur_state)); 2053 } 2054 2055 void assert_pll_enabled(struct drm_i915_private *i915, enum pipe pipe) 2056 { 2057 assert_pll(i915, pipe, true); 2058 } 2059 2060 void assert_pll_disabled(struct drm_i915_private *i915, enum pipe pipe) 2061 { 2062 assert_pll(i915, pipe, false); 2063 } 2064