1 /* 2 * Copyright © 2014-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "intel_ddi.h" 25 #include "intel_ddi_buf_trans.h" 26 #include "intel_de.h" 27 #include "intel_display_types.h" 28 #include "intel_dp.h" 29 #include "intel_dpio_phy.h" 30 #include "vlv_sideband.h" 31 32 /** 33 * DOC: DPIO 34 * 35 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI 36 * ports. DPIO is the name given to such a display PHY. These PHYs 37 * don't follow the standard programming model using direct MMIO 38 * registers, and instead their registers must be accessed trough IOSF 39 * sideband. VLV has one such PHY for driving ports B and C, and CHV 40 * adds another PHY for driving port D. Each PHY responds to specific 41 * IOSF-SB port. 42 * 43 * Each display PHY is made up of one or two channels. Each channel 44 * houses a common lane part which contains the PLL and other common 45 * logic. CH0 common lane also contains the IOSF-SB logic for the 46 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock 47 * must be running when any DPIO registers are accessed. 48 * 49 * In addition to having their own registers, the PHYs are also 50 * controlled through some dedicated signals from the display 51 * controller. These include PLL reference clock enable, PLL enable, 52 * and CRI clock selection, for example. 53 * 54 * Eeach channel also has two splines (also called data lanes), and 55 * each spline is made up of one Physical Access Coding Sub-Layer 56 * (PCS) block and two TX lanes. So each channel has two PCS blocks 57 * and four TX lanes. The TX lanes are used as DP lanes or TMDS 58 * data/clock pairs depending on the output type. 59 * 60 * Additionally the PHY also contains an AUX lane with AUX blocks 61 * for each channel. This is used for DP AUX communication, but 62 * this fact isn't really relevant for the driver since AUX is 63 * controlled from the display controller side. No DPIO registers 64 * need to be accessed during AUX communication, 65 * 66 * Generally on VLV/CHV the common lane corresponds to the pipe and 67 * the spline (PCS/TX) corresponds to the port. 68 * 69 * For dual channel PHY (VLV/CHV): 70 * 71 * pipe A == CMN/PLL/REF CH0 72 * 73 * pipe B == CMN/PLL/REF CH1 74 * 75 * port B == PCS/TX CH0 76 * 77 * port C == PCS/TX CH1 78 * 79 * This is especially important when we cross the streams 80 * ie. drive port B with pipe B, or port C with pipe A. 81 * 82 * For single channel PHY (CHV): 83 * 84 * pipe C == CMN/PLL/REF CH0 85 * 86 * port D == PCS/TX CH0 87 * 88 * On BXT the entire PHY channel corresponds to the port. That means 89 * the PLL is also now associated with the port rather than the pipe, 90 * and so the clock needs to be routed to the appropriate transcoder. 91 * Port A PLL is directly connected to transcoder EDP and port B/C 92 * PLLs can be routed to any transcoder A/B/C. 93 * 94 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is 95 * digital port D (CHV) or port A (BXT). :: 96 * 97 * 98 * Dual channel PHY (VLV/CHV/BXT) 99 * --------------------------------- 100 * | CH0 | CH1 | 101 * | CMN/PLL/REF | CMN/PLL/REF | 102 * |---------------|---------------| Display PHY 103 * | PCS01 | PCS23 | PCS01 | PCS23 | 104 * |-------|-------|-------|-------| 105 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| 106 * --------------------------------- 107 * | DDI0 | DDI1 | DP/HDMI ports 108 * --------------------------------- 109 * 110 * Single channel PHY (CHV/BXT) 111 * ----------------- 112 * | CH0 | 113 * | CMN/PLL/REF | 114 * |---------------| Display PHY 115 * | PCS01 | PCS23 | 116 * |-------|-------| 117 * |TX0|TX1|TX2|TX3| 118 * ----------------- 119 * | DDI2 | DP/HDMI port 120 * ----------------- 121 */ 122 123 /** 124 * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy 125 */ 126 struct bxt_ddi_phy_info { 127 /** 128 * @dual_channel: true if this phy has a second channel. 129 */ 130 bool dual_channel; 131 132 /** 133 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor. 134 * Otherwise the GRC value will be copied from the phy indicated by 135 * this field. 136 */ 137 enum dpio_phy rcomp_phy; 138 139 /** 140 * @reset_delay: delay in us to wait before setting the common reset 141 * bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy. 142 */ 143 int reset_delay; 144 145 /** 146 * @pwron_mask: Mask with the appropriate bit set that would cause the 147 * punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON. 148 */ 149 u32 pwron_mask; 150 151 /** 152 * @channel: struct containing per channel information. 153 */ 154 struct { 155 /** 156 * @channel.port: which port maps to this channel. 157 */ 158 enum port port; 159 } channel[2]; 160 }; 161 162 static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = { 163 [DPIO_PHY0] = { 164 .dual_channel = true, 165 .rcomp_phy = DPIO_PHY1, 166 .pwron_mask = BIT(0), 167 168 .channel = { 169 [DPIO_CH0] = { .port = PORT_B }, 170 [DPIO_CH1] = { .port = PORT_C }, 171 } 172 }, 173 [DPIO_PHY1] = { 174 .dual_channel = false, 175 .rcomp_phy = -1, 176 .pwron_mask = BIT(1), 177 178 .channel = { 179 [DPIO_CH0] = { .port = PORT_A }, 180 } 181 }, 182 }; 183 184 static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = { 185 [DPIO_PHY0] = { 186 .dual_channel = false, 187 .rcomp_phy = DPIO_PHY1, 188 .pwron_mask = BIT(0), 189 .reset_delay = 20, 190 191 .channel = { 192 [DPIO_CH0] = { .port = PORT_B }, 193 } 194 }, 195 [DPIO_PHY1] = { 196 .dual_channel = false, 197 .rcomp_phy = -1, 198 .pwron_mask = BIT(3), 199 .reset_delay = 20, 200 201 .channel = { 202 [DPIO_CH0] = { .port = PORT_A }, 203 } 204 }, 205 [DPIO_PHY2] = { 206 .dual_channel = false, 207 .rcomp_phy = DPIO_PHY1, 208 .pwron_mask = BIT(1), 209 .reset_delay = 20, 210 211 .channel = { 212 [DPIO_CH0] = { .port = PORT_C }, 213 } 214 }, 215 }; 216 217 static const struct bxt_ddi_phy_info * 218 bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count) 219 { 220 if (IS_GEMINILAKE(dev_priv)) { 221 *count = ARRAY_SIZE(glk_ddi_phy_info); 222 return glk_ddi_phy_info; 223 } else { 224 *count = ARRAY_SIZE(bxt_ddi_phy_info); 225 return bxt_ddi_phy_info; 226 } 227 } 228 229 static const struct bxt_ddi_phy_info * 230 bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy) 231 { 232 int count; 233 const struct bxt_ddi_phy_info *phy_list = 234 bxt_get_phy_list(dev_priv, &count); 235 236 return &phy_list[phy]; 237 } 238 239 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, 240 enum dpio_phy *phy, enum dpio_channel *ch) 241 { 242 const struct bxt_ddi_phy_info *phy_info, *phys; 243 int i, count; 244 245 phys = bxt_get_phy_list(dev_priv, &count); 246 247 for (i = 0; i < count; i++) { 248 phy_info = &phys[i]; 249 250 if (port == phy_info->channel[DPIO_CH0].port) { 251 *phy = i; 252 *ch = DPIO_CH0; 253 return; 254 } 255 256 if (phy_info->dual_channel && 257 port == phy_info->channel[DPIO_CH1].port) { 258 *phy = i; 259 *ch = DPIO_CH1; 260 return; 261 } 262 } 263 264 drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c", 265 port_name(port)); 266 *phy = DPIO_PHY0; 267 *ch = DPIO_CH0; 268 } 269 270 void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder, 271 const struct intel_crtc_state *crtc_state) 272 { 273 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 274 int level = intel_ddi_level(encoder, crtc_state, 0); 275 const struct intel_ddi_buf_trans *trans; 276 enum dpio_channel ch; 277 enum dpio_phy phy; 278 int n_entries; 279 u32 val; 280 281 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 282 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 283 return; 284 285 bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch); 286 287 /* 288 * While we write to the group register to program all lanes at once we 289 * can read only lane registers and we pick lanes 0/1 for that. 290 */ 291 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); 292 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); 293 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val); 294 295 val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch)); 296 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); 297 val |= trans->entries[level].bxt.margin << MARGIN_000_SHIFT | 298 trans->entries[level].bxt.scale << UNIQ_TRANS_SCALE_SHIFT; 299 intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val); 300 301 val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch)); 302 val &= ~SCALE_DCOMP_METHOD; 303 if (trans->entries[level].bxt.enable) 304 val |= SCALE_DCOMP_METHOD; 305 306 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) 307 drm_err(&dev_priv->drm, 308 "Disabled scaling while ouniqetrangenmethod was set"); 309 310 intel_de_write(dev_priv, BXT_PORT_TX_DW3_GRP(phy, ch), val); 311 312 val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch)); 313 val &= ~DE_EMPHASIS; 314 val |= trans->entries[level].bxt.deemphasis << DEEMPH_SHIFT; 315 intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val); 316 317 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); 318 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; 319 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val); 320 } 321 322 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, 323 enum dpio_phy phy) 324 { 325 const struct bxt_ddi_phy_info *phy_info; 326 327 phy_info = bxt_get_phy_info(dev_priv, phy); 328 329 if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) 330 return false; 331 332 if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) & 333 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) { 334 drm_dbg(&dev_priv->drm, 335 "DDI PHY %d powered, but power hasn't settled\n", phy); 336 337 return false; 338 } 339 340 if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { 341 drm_dbg(&dev_priv->drm, 342 "DDI PHY %d powered, but still in reset\n", phy); 343 344 return false; 345 } 346 347 return true; 348 } 349 350 static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy) 351 { 352 u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy)); 353 354 return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; 355 } 356 357 static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv, 358 enum dpio_phy phy) 359 { 360 if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy), 361 GRC_DONE, 10)) 362 drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n", 363 phy); 364 } 365 366 static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, 367 enum dpio_phy phy) 368 { 369 const struct bxt_ddi_phy_info *phy_info; 370 u32 val; 371 372 phy_info = bxt_get_phy_info(dev_priv, phy); 373 374 if (bxt_ddi_phy_is_enabled(dev_priv, phy)) { 375 /* Still read out the GRC value for state verification */ 376 if (phy_info->rcomp_phy != -1) 377 dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy); 378 379 if (bxt_ddi_phy_verify_state(dev_priv, phy)) { 380 drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, " 381 "won't reprogram it\n", phy); 382 return; 383 } 384 385 drm_dbg(&dev_priv->drm, 386 "DDI PHY %d enabled with invalid state, " 387 "force reprogramming it\n", phy); 388 } 389 390 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); 391 val |= phy_info->pwron_mask; 392 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val); 393 394 /* 395 * The PHY registers start out inaccessible and respond to reads with 396 * all 1s. Eventually they become accessible as they power up, then 397 * the reserved bit will give the default 0. Poll on the reserved bit 398 * becoming 0 to find when the PHY is accessible. 399 * The flag should get set in 100us according to the HW team, but 400 * use 1ms due to occasional timeouts observed with that. 401 */ 402 if (intel_wait_for_register_fw(&dev_priv->uncore, 403 BXT_PORT_CL1CM_DW0(phy), 404 PHY_RESERVED | PHY_POWER_GOOD, 405 PHY_POWER_GOOD, 406 1)) 407 drm_err(&dev_priv->drm, "timeout during PHY%d power on\n", 408 phy); 409 410 /* Program PLL Rcomp code offset */ 411 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW9(phy)); 412 val &= ~IREF0RC_OFFSET_MASK; 413 val |= 0xE4 << IREF0RC_OFFSET_SHIFT; 414 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW9(phy), val); 415 416 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW10(phy)); 417 val &= ~IREF1RC_OFFSET_MASK; 418 val |= 0xE4 << IREF1RC_OFFSET_SHIFT; 419 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW10(phy), val); 420 421 /* Program power gating */ 422 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW28(phy)); 423 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | 424 SUS_CLK_CONFIG; 425 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW28(phy), val); 426 427 if (phy_info->dual_channel) { 428 val = intel_de_read(dev_priv, BXT_PORT_CL2CM_DW6(phy)); 429 val |= DW6_OLDO_DYN_PWR_DOWN_EN; 430 intel_de_write(dev_priv, BXT_PORT_CL2CM_DW6(phy), val); 431 } 432 433 if (phy_info->rcomp_phy != -1) { 434 u32 grc_code; 435 436 bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy); 437 438 /* 439 * PHY0 isn't connected to an RCOMP resistor so copy over 440 * the corresponding calibrated value from PHY1, and disable 441 * the automatic calibration on PHY0. 442 */ 443 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, 444 phy_info->rcomp_phy); 445 grc_code = val << GRC_CODE_FAST_SHIFT | 446 val << GRC_CODE_SLOW_SHIFT | 447 val; 448 intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code); 449 450 val = intel_de_read(dev_priv, BXT_PORT_REF_DW8(phy)); 451 val |= GRC_DIS | GRC_RDY_OVRD; 452 intel_de_write(dev_priv, BXT_PORT_REF_DW8(phy), val); 453 } 454 455 if (phy_info->reset_delay) 456 udelay(phy_info->reset_delay); 457 458 val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)); 459 val |= COMMON_RESET_DIS; 460 intel_de_write(dev_priv, BXT_PHY_CTL_FAMILY(phy), val); 461 } 462 463 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy) 464 { 465 const struct bxt_ddi_phy_info *phy_info; 466 u32 val; 467 468 phy_info = bxt_get_phy_info(dev_priv, phy); 469 470 val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)); 471 val &= ~COMMON_RESET_DIS; 472 intel_de_write(dev_priv, BXT_PHY_CTL_FAMILY(phy), val); 473 474 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); 475 val &= ~phy_info->pwron_mask; 476 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val); 477 } 478 479 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy) 480 { 481 const struct bxt_ddi_phy_info *phy_info = 482 bxt_get_phy_info(dev_priv, phy); 483 enum dpio_phy rcomp_phy = phy_info->rcomp_phy; 484 bool was_enabled; 485 486 lockdep_assert_held(&dev_priv->power_domains.lock); 487 488 was_enabled = true; 489 if (rcomp_phy != -1) 490 was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy); 491 492 /* 493 * We need to copy the GRC calibration value from rcomp_phy, 494 * so make sure it's powered up. 495 */ 496 if (!was_enabled) 497 _bxt_ddi_phy_init(dev_priv, rcomp_phy); 498 499 _bxt_ddi_phy_init(dev_priv, phy); 500 501 if (!was_enabled) 502 bxt_ddi_phy_uninit(dev_priv, rcomp_phy); 503 } 504 505 static bool __printf(6, 7) 506 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy, 507 i915_reg_t reg, u32 mask, u32 expected, 508 const char *reg_fmt, ...) 509 { 510 struct va_format vaf; 511 va_list args; 512 u32 val; 513 514 val = intel_de_read(dev_priv, reg); 515 if ((val & mask) == expected) 516 return true; 517 518 va_start(args, reg_fmt); 519 vaf.fmt = reg_fmt; 520 vaf.va = &args; 521 522 drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: " 523 "current %08x, expected %08x (mask %08x)\n", 524 phy, &vaf, reg.reg, val, (val & ~mask) | expected, 525 mask); 526 527 va_end(args); 528 529 return false; 530 } 531 532 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, 533 enum dpio_phy phy) 534 { 535 const struct bxt_ddi_phy_info *phy_info; 536 u32 mask; 537 bool ok; 538 539 phy_info = bxt_get_phy_info(dev_priv, phy); 540 541 #define _CHK(reg, mask, exp, fmt, ...) \ 542 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \ 543 ## __VA_ARGS__) 544 545 if (!bxt_ddi_phy_is_enabled(dev_priv, phy)) 546 return false; 547 548 ok = true; 549 550 /* PLL Rcomp code offset */ 551 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy), 552 IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT, 553 "BXT_PORT_CL1CM_DW9(%d)", phy); 554 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy), 555 IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT, 556 "BXT_PORT_CL1CM_DW10(%d)", phy); 557 558 /* Power gating */ 559 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG; 560 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask, 561 "BXT_PORT_CL1CM_DW28(%d)", phy); 562 563 if (phy_info->dual_channel) 564 ok &= _CHK(BXT_PORT_CL2CM_DW6(phy), 565 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN, 566 "BXT_PORT_CL2CM_DW6(%d)", phy); 567 568 if (phy_info->rcomp_phy != -1) { 569 u32 grc_code = dev_priv->bxt_phy_grc; 570 571 grc_code = grc_code << GRC_CODE_FAST_SHIFT | 572 grc_code << GRC_CODE_SLOW_SHIFT | 573 grc_code; 574 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK | 575 GRC_CODE_NOM_MASK; 576 ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code, 577 "BXT_PORT_REF_DW6(%d)", phy); 578 579 mask = GRC_DIS | GRC_RDY_OVRD; 580 ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask, 581 "BXT_PORT_REF_DW8(%d)", phy); 582 } 583 584 return ok; 585 #undef _CHK 586 } 587 588 u8 589 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count) 590 { 591 switch (lane_count) { 592 case 1: 593 return 0; 594 case 2: 595 return BIT(2) | BIT(0); 596 case 4: 597 return BIT(3) | BIT(2) | BIT(0); 598 default: 599 MISSING_CASE(lane_count); 600 601 return 0; 602 } 603 } 604 605 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, 606 u8 lane_lat_optim_mask) 607 { 608 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 609 enum port port = encoder->port; 610 enum dpio_phy phy; 611 enum dpio_channel ch; 612 int lane; 613 614 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); 615 616 for (lane = 0; lane < 4; lane++) { 617 u32 val = intel_de_read(dev_priv, 618 BXT_PORT_TX_DW14_LN(phy, ch, lane)); 619 620 /* 621 * Note that on CHV this flag is called UPAR, but has 622 * the same function. 623 */ 624 val &= ~LATENCY_OPTIM; 625 if (lane_lat_optim_mask & BIT(lane)) 626 val |= LATENCY_OPTIM; 627 628 intel_de_write(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane), 629 val); 630 } 631 } 632 633 u8 634 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder) 635 { 636 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 637 enum port port = encoder->port; 638 enum dpio_phy phy; 639 enum dpio_channel ch; 640 int lane; 641 u8 mask; 642 643 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); 644 645 mask = 0; 646 for (lane = 0; lane < 4; lane++) { 647 u32 val = intel_de_read(dev_priv, 648 BXT_PORT_TX_DW14_LN(phy, ch, lane)); 649 650 if (val & LATENCY_OPTIM) 651 mask |= BIT(lane); 652 } 653 654 return mask; 655 } 656 657 void chv_set_phy_signal_level(struct intel_encoder *encoder, 658 const struct intel_crtc_state *crtc_state, 659 u32 deemph_reg_value, u32 margin_reg_value, 660 bool uniq_trans_scale) 661 { 662 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 663 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 664 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 665 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 666 enum pipe pipe = crtc->pipe; 667 u32 val; 668 int i; 669 670 vlv_dpio_get(dev_priv); 671 672 /* Clear calc init */ 673 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 674 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 675 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 676 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 677 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 678 679 if (crtc_state->lane_count > 2) { 680 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 681 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 682 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 683 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 684 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 685 } 686 687 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); 688 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 689 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 690 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); 691 692 if (crtc_state->lane_count > 2) { 693 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); 694 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 695 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 696 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); 697 } 698 699 /* Program swing deemph */ 700 for (i = 0; i < crtc_state->lane_count; i++) { 701 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); 702 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 703 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; 704 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); 705 } 706 707 /* Program swing margin */ 708 for (i = 0; i < crtc_state->lane_count; i++) { 709 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 710 711 val &= ~DPIO_SWING_MARGIN000_MASK; 712 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; 713 714 /* 715 * Supposedly this value shouldn't matter when unique transition 716 * scale is disabled, but in fact it does matter. Let's just 717 * always program the same value and hope it's OK. 718 */ 719 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); 720 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; 721 722 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 723 } 724 725 /* 726 * The document said it needs to set bit 27 for ch0 and bit 26 727 * for ch1. Might be a typo in the doc. 728 * For now, for this unique transition scale selection, set bit 729 * 27 for ch0 and ch1. 730 */ 731 for (i = 0; i < crtc_state->lane_count; i++) { 732 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 733 if (uniq_trans_scale) 734 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; 735 else 736 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 737 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 738 } 739 740 /* Start swing calculation */ 741 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 742 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 743 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 744 745 if (crtc_state->lane_count > 2) { 746 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 747 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 748 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 749 } 750 751 vlv_dpio_put(dev_priv); 752 } 753 754 void chv_data_lane_soft_reset(struct intel_encoder *encoder, 755 const struct intel_crtc_state *crtc_state, 756 bool reset) 757 { 758 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 759 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); 760 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 761 enum pipe pipe = crtc->pipe; 762 u32 val; 763 764 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 765 if (reset) 766 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 767 else 768 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 769 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 770 771 if (crtc_state->lane_count > 2) { 772 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 773 if (reset) 774 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 775 else 776 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 777 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 778 } 779 780 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 781 val |= CHV_PCS_REQ_SOFTRESET_EN; 782 if (reset) 783 val &= ~DPIO_PCS_CLK_SOFT_RESET; 784 else 785 val |= DPIO_PCS_CLK_SOFT_RESET; 786 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 787 788 if (crtc_state->lane_count > 2) { 789 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 790 val |= CHV_PCS_REQ_SOFTRESET_EN; 791 if (reset) 792 val &= ~DPIO_PCS_CLK_SOFT_RESET; 793 else 794 val |= DPIO_PCS_CLK_SOFT_RESET; 795 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 796 } 797 } 798 799 void chv_phy_pre_pll_enable(struct intel_encoder *encoder, 800 const struct intel_crtc_state *crtc_state) 801 { 802 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 803 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 804 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 805 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 806 enum pipe pipe = crtc->pipe; 807 unsigned int lane_mask = 808 intel_dp_unused_lane_mask(crtc_state->lane_count); 809 u32 val; 810 811 /* 812 * Must trick the second common lane into life. 813 * Otherwise we can't even access the PLL. 814 */ 815 if (ch == DPIO_CH0 && pipe == PIPE_B) 816 dig_port->release_cl2_override = 817 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); 818 819 chv_phy_powergate_lanes(encoder, true, lane_mask); 820 821 vlv_dpio_get(dev_priv); 822 823 /* Assert data lane reset */ 824 chv_data_lane_soft_reset(encoder, crtc_state, true); 825 826 /* program left/right clock distribution */ 827 if (pipe != PIPE_B) { 828 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 829 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 830 if (ch == DPIO_CH0) 831 val |= CHV_BUFLEFTENA1_FORCE; 832 if (ch == DPIO_CH1) 833 val |= CHV_BUFRIGHTENA1_FORCE; 834 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 835 } else { 836 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 837 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 838 if (ch == DPIO_CH0) 839 val |= CHV_BUFLEFTENA2_FORCE; 840 if (ch == DPIO_CH1) 841 val |= CHV_BUFRIGHTENA2_FORCE; 842 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 843 } 844 845 /* program clock channel usage */ 846 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); 847 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 848 if (pipe != PIPE_B) 849 val &= ~CHV_PCS_USEDCLKCHANNEL; 850 else 851 val |= CHV_PCS_USEDCLKCHANNEL; 852 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); 853 854 if (crtc_state->lane_count > 2) { 855 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); 856 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 857 if (pipe != PIPE_B) 858 val &= ~CHV_PCS_USEDCLKCHANNEL; 859 else 860 val |= CHV_PCS_USEDCLKCHANNEL; 861 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); 862 } 863 864 /* 865 * This a a bit weird since generally CL 866 * matches the pipe, but here we need to 867 * pick the CL based on the port. 868 */ 869 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); 870 if (pipe != PIPE_B) 871 val &= ~CHV_CMN_USEDCLKCHANNEL; 872 else 873 val |= CHV_CMN_USEDCLKCHANNEL; 874 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); 875 876 vlv_dpio_put(dev_priv); 877 } 878 879 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, 880 const struct intel_crtc_state *crtc_state) 881 { 882 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 883 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 884 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 885 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 886 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 887 enum pipe pipe = crtc->pipe; 888 int data, i, stagger; 889 u32 val; 890 891 vlv_dpio_get(dev_priv); 892 893 /* allow hardware to manage TX FIFO reset source */ 894 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 895 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 896 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 897 898 if (crtc_state->lane_count > 2) { 899 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 900 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 901 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 902 } 903 904 /* Program Tx lane latency optimal setting*/ 905 for (i = 0; i < crtc_state->lane_count; i++) { 906 /* Set the upar bit */ 907 if (crtc_state->lane_count == 1) 908 data = 0x0; 909 else 910 data = (i == 1) ? 0x0 : 0x1; 911 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), 912 data << DPIO_UPAR_SHIFT); 913 } 914 915 /* Data lane stagger programming */ 916 if (crtc_state->port_clock > 270000) 917 stagger = 0x18; 918 else if (crtc_state->port_clock > 135000) 919 stagger = 0xd; 920 else if (crtc_state->port_clock > 67500) 921 stagger = 0x7; 922 else if (crtc_state->port_clock > 33750) 923 stagger = 0x4; 924 else 925 stagger = 0x2; 926 927 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 928 val |= DPIO_TX2_STAGGER_MASK(0x1f); 929 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 930 931 if (crtc_state->lane_count > 2) { 932 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 933 val |= DPIO_TX2_STAGGER_MASK(0x1f); 934 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 935 } 936 937 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), 938 DPIO_LANESTAGGER_STRAP(stagger) | 939 DPIO_LANESTAGGER_STRAP_OVRD | 940 DPIO_TX1_STAGGER_MASK(0x1f) | 941 DPIO_TX1_STAGGER_MULT(6) | 942 DPIO_TX2_STAGGER_MULT(0)); 943 944 if (crtc_state->lane_count > 2) { 945 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), 946 DPIO_LANESTAGGER_STRAP(stagger) | 947 DPIO_LANESTAGGER_STRAP_OVRD | 948 DPIO_TX1_STAGGER_MASK(0x1f) | 949 DPIO_TX1_STAGGER_MULT(7) | 950 DPIO_TX2_STAGGER_MULT(5)); 951 } 952 953 /* Deassert data lane reset */ 954 chv_data_lane_soft_reset(encoder, crtc_state, false); 955 956 vlv_dpio_put(dev_priv); 957 } 958 959 void chv_phy_release_cl2_override(struct intel_encoder *encoder) 960 { 961 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 962 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 963 964 if (dig_port->release_cl2_override) { 965 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); 966 dig_port->release_cl2_override = false; 967 } 968 } 969 970 void chv_phy_post_pll_disable(struct intel_encoder *encoder, 971 const struct intel_crtc_state *old_crtc_state) 972 { 973 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 974 enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe; 975 u32 val; 976 977 vlv_dpio_get(dev_priv); 978 979 /* disable left/right clock distribution */ 980 if (pipe != PIPE_B) { 981 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 982 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 983 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 984 } else { 985 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 986 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 987 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 988 } 989 990 vlv_dpio_put(dev_priv); 991 992 /* 993 * Leave the power down bit cleared for at least one 994 * lane so that chv_powergate_phy_ch() will power 995 * on something when the channel is otherwise unused. 996 * When the port is off and the override is removed 997 * the lanes power down anyway, so otherwise it doesn't 998 * really matter what the state of power down bits is 999 * after this. 1000 */ 1001 chv_phy_powergate_lanes(encoder, false, 0x0); 1002 } 1003 1004 void vlv_set_phy_signal_level(struct intel_encoder *encoder, 1005 const struct intel_crtc_state *crtc_state, 1006 u32 demph_reg_value, u32 preemph_reg_value, 1007 u32 uniqtranscale_reg_value, u32 tx3_demph) 1008 { 1009 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1010 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1011 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1012 enum dpio_channel port = vlv_dig_port_to_channel(dig_port); 1013 enum pipe pipe = crtc->pipe; 1014 1015 vlv_dpio_get(dev_priv); 1016 1017 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); 1018 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); 1019 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 1020 uniqtranscale_reg_value); 1021 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); 1022 1023 if (tx3_demph) 1024 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph); 1025 1026 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 1027 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); 1028 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 1029 1030 vlv_dpio_put(dev_priv); 1031 } 1032 1033 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, 1034 const struct intel_crtc_state *crtc_state) 1035 { 1036 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1037 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1038 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1039 enum dpio_channel port = vlv_dig_port_to_channel(dig_port); 1040 enum pipe pipe = crtc->pipe; 1041 1042 /* Program Tx lane resets to default */ 1043 vlv_dpio_get(dev_priv); 1044 1045 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 1046 DPIO_PCS_TX_LANE2_RESET | 1047 DPIO_PCS_TX_LANE1_RESET); 1048 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 1049 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1050 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1051 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1052 DPIO_PCS_CLK_SOFT_RESET); 1053 1054 /* Fix up inter-pair skew failure */ 1055 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 1056 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 1057 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 1058 1059 vlv_dpio_put(dev_priv); 1060 } 1061 1062 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, 1063 const struct intel_crtc_state *crtc_state) 1064 { 1065 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1066 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1067 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1068 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1069 enum dpio_channel port = vlv_dig_port_to_channel(dig_port); 1070 enum pipe pipe = crtc->pipe; 1071 u32 val; 1072 1073 vlv_dpio_get(dev_priv); 1074 1075 /* Enable clock channels for this port */ 1076 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 1077 val = 0; 1078 if (pipe) 1079 val |= (1<<21); 1080 else 1081 val &= ~(1<<21); 1082 val |= 0x001000c4; 1083 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 1084 1085 /* Program lane clock */ 1086 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 1087 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 1088 1089 vlv_dpio_put(dev_priv); 1090 } 1091 1092 void vlv_phy_reset_lanes(struct intel_encoder *encoder, 1093 const struct intel_crtc_state *old_crtc_state) 1094 { 1095 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1096 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1097 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1098 enum dpio_channel port = vlv_dig_port_to_channel(dig_port); 1099 enum pipe pipe = crtc->pipe; 1100 1101 vlv_dpio_get(dev_priv); 1102 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); 1103 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); 1104 vlv_dpio_put(dev_priv); 1105 } 1106