1 /*
2  * Copyright © 2014-2016 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  */
23 
24 #include "display/intel_dp.h"
25 
26 #include "intel_dpio_phy.h"
27 #include "intel_drv.h"
28 #include "intel_sideband.h"
29 
30 /**
31  * DOC: DPIO
32  *
33  * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
34  * ports. DPIO is the name given to such a display PHY. These PHYs
35  * don't follow the standard programming model using direct MMIO
36  * registers, and instead their registers must be accessed trough IOSF
37  * sideband. VLV has one such PHY for driving ports B and C, and CHV
38  * adds another PHY for driving port D. Each PHY responds to specific
39  * IOSF-SB port.
40  *
41  * Each display PHY is made up of one or two channels. Each channel
42  * houses a common lane part which contains the PLL and other common
43  * logic. CH0 common lane also contains the IOSF-SB logic for the
44  * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
45  * must be running when any DPIO registers are accessed.
46  *
47  * In addition to having their own registers, the PHYs are also
48  * controlled through some dedicated signals from the display
49  * controller. These include PLL reference clock enable, PLL enable,
50  * and CRI clock selection, for example.
51  *
52  * Eeach channel also has two splines (also called data lanes), and
53  * each spline is made up of one Physical Access Coding Sub-Layer
54  * (PCS) block and two TX lanes. So each channel has two PCS blocks
55  * and four TX lanes. The TX lanes are used as DP lanes or TMDS
56  * data/clock pairs depending on the output type.
57  *
58  * Additionally the PHY also contains an AUX lane with AUX blocks
59  * for each channel. This is used for DP AUX communication, but
60  * this fact isn't really relevant for the driver since AUX is
61  * controlled from the display controller side. No DPIO registers
62  * need to be accessed during AUX communication,
63  *
64  * Generally on VLV/CHV the common lane corresponds to the pipe and
65  * the spline (PCS/TX) corresponds to the port.
66  *
67  * For dual channel PHY (VLV/CHV):
68  *
69  *  pipe A == CMN/PLL/REF CH0
70  *
71  *  pipe B == CMN/PLL/REF CH1
72  *
73  *  port B == PCS/TX CH0
74  *
75  *  port C == PCS/TX CH1
76  *
77  * This is especially important when we cross the streams
78  * ie. drive port B with pipe B, or port C with pipe A.
79  *
80  * For single channel PHY (CHV):
81  *
82  *  pipe C == CMN/PLL/REF CH0
83  *
84  *  port D == PCS/TX CH0
85  *
86  * On BXT the entire PHY channel corresponds to the port. That means
87  * the PLL is also now associated with the port rather than the pipe,
88  * and so the clock needs to be routed to the appropriate transcoder.
89  * Port A PLL is directly connected to transcoder EDP and port B/C
90  * PLLs can be routed to any transcoder A/B/C.
91  *
92  * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
93  * digital port D (CHV) or port A (BXT). ::
94  *
95  *
96  *     Dual channel PHY (VLV/CHV/BXT)
97  *     ---------------------------------
98  *     |      CH0      |      CH1      |
99  *     |  CMN/PLL/REF  |  CMN/PLL/REF  |
100  *     |---------------|---------------| Display PHY
101  *     | PCS01 | PCS23 | PCS01 | PCS23 |
102  *     |-------|-------|-------|-------|
103  *     |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
104  *     ---------------------------------
105  *     |     DDI0      |     DDI1      | DP/HDMI ports
106  *     ---------------------------------
107  *
108  *     Single channel PHY (CHV/BXT)
109  *     -----------------
110  *     |      CH0      |
111  *     |  CMN/PLL/REF  |
112  *     |---------------| Display PHY
113  *     | PCS01 | PCS23 |
114  *     |-------|-------|
115  *     |TX0|TX1|TX2|TX3|
116  *     -----------------
117  *     |     DDI2      | DP/HDMI port
118  *     -----------------
119  */
120 
121 /**
122  * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
123  */
124 struct bxt_ddi_phy_info {
125 	/**
126 	 * @dual_channel: true if this phy has a second channel.
127 	 */
128 	bool dual_channel;
129 
130 	/**
131 	 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
132 	 * Otherwise the GRC value will be copied from the phy indicated by
133 	 * this field.
134 	 */
135 	enum dpio_phy rcomp_phy;
136 
137 	/**
138 	 * @reset_delay: delay in us to wait before setting the common reset
139 	 * bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy.
140 	 */
141 	int reset_delay;
142 
143 	/**
144 	 * @pwron_mask: Mask with the appropriate bit set that would cause the
145 	 * punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON.
146 	 */
147 	u32 pwron_mask;
148 
149 	/**
150 	 * @channel: struct containing per channel information.
151 	 */
152 	struct {
153 		/**
154 		 * @channel.port: which port maps to this channel.
155 		 */
156 		enum port port;
157 	} channel[2];
158 };
159 
160 static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
161 	[DPIO_PHY0] = {
162 		.dual_channel = true,
163 		.rcomp_phy = DPIO_PHY1,
164 		.pwron_mask = BIT(0),
165 
166 		.channel = {
167 			[DPIO_CH0] = { .port = PORT_B },
168 			[DPIO_CH1] = { .port = PORT_C },
169 		}
170 	},
171 	[DPIO_PHY1] = {
172 		.dual_channel = false,
173 		.rcomp_phy = -1,
174 		.pwron_mask = BIT(1),
175 
176 		.channel = {
177 			[DPIO_CH0] = { .port = PORT_A },
178 		}
179 	},
180 };
181 
182 static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = {
183 	[DPIO_PHY0] = {
184 		.dual_channel = false,
185 		.rcomp_phy = DPIO_PHY1,
186 		.pwron_mask = BIT(0),
187 		.reset_delay = 20,
188 
189 		.channel = {
190 			[DPIO_CH0] = { .port = PORT_B },
191 		}
192 	},
193 	[DPIO_PHY1] = {
194 		.dual_channel = false,
195 		.rcomp_phy = -1,
196 		.pwron_mask = BIT(3),
197 		.reset_delay = 20,
198 
199 		.channel = {
200 			[DPIO_CH0] = { .port = PORT_A },
201 		}
202 	},
203 	[DPIO_PHY2] = {
204 		.dual_channel = false,
205 		.rcomp_phy = DPIO_PHY1,
206 		.pwron_mask = BIT(1),
207 		.reset_delay = 20,
208 
209 		.channel = {
210 			[DPIO_CH0] = { .port = PORT_C },
211 		}
212 	},
213 };
214 
215 static const struct bxt_ddi_phy_info *
216 bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
217 {
218 	if (IS_GEMINILAKE(dev_priv)) {
219 		*count =  ARRAY_SIZE(glk_ddi_phy_info);
220 		return glk_ddi_phy_info;
221 	} else {
222 		*count =  ARRAY_SIZE(bxt_ddi_phy_info);
223 		return bxt_ddi_phy_info;
224 	}
225 }
226 
227 static const struct bxt_ddi_phy_info *
228 bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)
229 {
230 	int count;
231 	const struct bxt_ddi_phy_info *phy_list =
232 		bxt_get_phy_list(dev_priv, &count);
233 
234 	return &phy_list[phy];
235 }
236 
237 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
238 			     enum dpio_phy *phy, enum dpio_channel *ch)
239 {
240 	const struct bxt_ddi_phy_info *phy_info, *phys;
241 	int i, count;
242 
243 	phys = bxt_get_phy_list(dev_priv, &count);
244 
245 	for (i = 0; i < count; i++) {
246 		phy_info = &phys[i];
247 
248 		if (port == phy_info->channel[DPIO_CH0].port) {
249 			*phy = i;
250 			*ch = DPIO_CH0;
251 			return;
252 		}
253 
254 		if (phy_info->dual_channel &&
255 		    port == phy_info->channel[DPIO_CH1].port) {
256 			*phy = i;
257 			*ch = DPIO_CH1;
258 			return;
259 		}
260 	}
261 
262 	WARN(1, "PHY not found for PORT %c", port_name(port));
263 	*phy = DPIO_PHY0;
264 	*ch = DPIO_CH0;
265 }
266 
267 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv,
268 				  enum port port, u32 margin, u32 scale,
269 				  u32 enable, u32 deemphasis)
270 {
271 	u32 val;
272 	enum dpio_phy phy;
273 	enum dpio_channel ch;
274 
275 	bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
276 
277 	/*
278 	 * While we write to the group register to program all lanes at once we
279 	 * can read only lane registers and we pick lanes 0/1 for that.
280 	 */
281 	val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
282 	val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
283 	I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val);
284 
285 	val = I915_READ(BXT_PORT_TX_DW2_LN0(phy, ch));
286 	val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
287 	val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT;
288 	I915_WRITE(BXT_PORT_TX_DW2_GRP(phy, ch), val);
289 
290 	val = I915_READ(BXT_PORT_TX_DW3_LN0(phy, ch));
291 	val &= ~SCALE_DCOMP_METHOD;
292 	if (enable)
293 		val |= SCALE_DCOMP_METHOD;
294 
295 	if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
296 		DRM_ERROR("Disabled scaling while ouniqetrangenmethod was set");
297 
298 	I915_WRITE(BXT_PORT_TX_DW3_GRP(phy, ch), val);
299 
300 	val = I915_READ(BXT_PORT_TX_DW4_LN0(phy, ch));
301 	val &= ~DE_EMPHASIS;
302 	val |= deemphasis << DEEMPH_SHIFT;
303 	I915_WRITE(BXT_PORT_TX_DW4_GRP(phy, ch), val);
304 
305 	val = I915_READ(BXT_PORT_PCS_DW10_LN01(phy, ch));
306 	val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
307 	I915_WRITE(BXT_PORT_PCS_DW10_GRP(phy, ch), val);
308 }
309 
310 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
311 			    enum dpio_phy phy)
312 {
313 	const struct bxt_ddi_phy_info *phy_info;
314 
315 	phy_info = bxt_get_phy_info(dev_priv, phy);
316 
317 	if (!(I915_READ(BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
318 		return false;
319 
320 	if ((I915_READ(BXT_PORT_CL1CM_DW0(phy)) &
321 	     (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
322 		DRM_DEBUG_DRIVER("DDI PHY %d powered, but power hasn't settled\n",
323 				 phy);
324 
325 		return false;
326 	}
327 
328 	if (!(I915_READ(BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
329 		DRM_DEBUG_DRIVER("DDI PHY %d powered, but still in reset\n",
330 				 phy);
331 
332 		return false;
333 	}
334 
335 	return true;
336 }
337 
338 static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
339 {
340 	u32 val = I915_READ(BXT_PORT_REF_DW6(phy));
341 
342 	return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
343 }
344 
345 static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
346 				  enum dpio_phy phy)
347 {
348 	if (intel_wait_for_register(&dev_priv->uncore,
349 				    BXT_PORT_REF_DW3(phy),
350 				    GRC_DONE, GRC_DONE,
351 				    10))
352 		DRM_ERROR("timeout waiting for PHY%d GRC\n", phy);
353 }
354 
355 static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
356 			      enum dpio_phy phy)
357 {
358 	const struct bxt_ddi_phy_info *phy_info;
359 	u32 val;
360 
361 	phy_info = bxt_get_phy_info(dev_priv, phy);
362 
363 	if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
364 		/* Still read out the GRC value for state verification */
365 		if (phy_info->rcomp_phy != -1)
366 			dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
367 
368 		if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
369 			DRM_DEBUG_DRIVER("DDI PHY %d already enabled, "
370 					 "won't reprogram it\n", phy);
371 			return;
372 		}
373 
374 		DRM_DEBUG_DRIVER("DDI PHY %d enabled with invalid state, "
375 				 "force reprogramming it\n", phy);
376 	}
377 
378 	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
379 	val |= phy_info->pwron_mask;
380 	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
381 
382 	/*
383 	 * The PHY registers start out inaccessible and respond to reads with
384 	 * all 1s.  Eventually they become accessible as they power up, then
385 	 * the reserved bit will give the default 0.  Poll on the reserved bit
386 	 * becoming 0 to find when the PHY is accessible.
387 	 * The flag should get set in 100us according to the HW team, but
388 	 * use 1ms due to occasional timeouts observed with that.
389 	 */
390 	if (intel_wait_for_register_fw(&dev_priv->uncore,
391 				       BXT_PORT_CL1CM_DW0(phy),
392 				       PHY_RESERVED | PHY_POWER_GOOD,
393 				       PHY_POWER_GOOD,
394 				       1))
395 		DRM_ERROR("timeout during PHY%d power on\n", phy);
396 
397 	/* Program PLL Rcomp code offset */
398 	val = I915_READ(BXT_PORT_CL1CM_DW9(phy));
399 	val &= ~IREF0RC_OFFSET_MASK;
400 	val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
401 	I915_WRITE(BXT_PORT_CL1CM_DW9(phy), val);
402 
403 	val = I915_READ(BXT_PORT_CL1CM_DW10(phy));
404 	val &= ~IREF1RC_OFFSET_MASK;
405 	val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
406 	I915_WRITE(BXT_PORT_CL1CM_DW10(phy), val);
407 
408 	/* Program power gating */
409 	val = I915_READ(BXT_PORT_CL1CM_DW28(phy));
410 	val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
411 		SUS_CLK_CONFIG;
412 	I915_WRITE(BXT_PORT_CL1CM_DW28(phy), val);
413 
414 	if (phy_info->dual_channel) {
415 		val = I915_READ(BXT_PORT_CL2CM_DW6(phy));
416 		val |= DW6_OLDO_DYN_PWR_DOWN_EN;
417 		I915_WRITE(BXT_PORT_CL2CM_DW6(phy), val);
418 	}
419 
420 	if (phy_info->rcomp_phy != -1) {
421 		u32 grc_code;
422 
423 		bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
424 
425 		/*
426 		 * PHY0 isn't connected to an RCOMP resistor so copy over
427 		 * the corresponding calibrated value from PHY1, and disable
428 		 * the automatic calibration on PHY0.
429 		 */
430 		val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
431 							  phy_info->rcomp_phy);
432 		grc_code = val << GRC_CODE_FAST_SHIFT |
433 			   val << GRC_CODE_SLOW_SHIFT |
434 			   val;
435 		I915_WRITE(BXT_PORT_REF_DW6(phy), grc_code);
436 
437 		val = I915_READ(BXT_PORT_REF_DW8(phy));
438 		val |= GRC_DIS | GRC_RDY_OVRD;
439 		I915_WRITE(BXT_PORT_REF_DW8(phy), val);
440 	}
441 
442 	if (phy_info->reset_delay)
443 		udelay(phy_info->reset_delay);
444 
445 	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
446 	val |= COMMON_RESET_DIS;
447 	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
448 }
449 
450 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
451 {
452 	const struct bxt_ddi_phy_info *phy_info;
453 	u32 val;
454 
455 	phy_info = bxt_get_phy_info(dev_priv, phy);
456 
457 	val = I915_READ(BXT_PHY_CTL_FAMILY(phy));
458 	val &= ~COMMON_RESET_DIS;
459 	I915_WRITE(BXT_PHY_CTL_FAMILY(phy), val);
460 
461 	val = I915_READ(BXT_P_CR_GT_DISP_PWRON);
462 	val &= ~phy_info->pwron_mask;
463 	I915_WRITE(BXT_P_CR_GT_DISP_PWRON, val);
464 }
465 
466 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
467 {
468 	const struct bxt_ddi_phy_info *phy_info =
469 		bxt_get_phy_info(dev_priv, phy);
470 	enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
471 	bool was_enabled;
472 
473 	lockdep_assert_held(&dev_priv->power_domains.lock);
474 
475 	was_enabled = true;
476 	if (rcomp_phy != -1)
477 		was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy);
478 
479 	/*
480 	 * We need to copy the GRC calibration value from rcomp_phy,
481 	 * so make sure it's powered up.
482 	 */
483 	if (!was_enabled)
484 		_bxt_ddi_phy_init(dev_priv, rcomp_phy);
485 
486 	_bxt_ddi_phy_init(dev_priv, phy);
487 
488 	if (!was_enabled)
489 		bxt_ddi_phy_uninit(dev_priv, rcomp_phy);
490 }
491 
492 static bool __printf(6, 7)
493 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
494 		       i915_reg_t reg, u32 mask, u32 expected,
495 		       const char *reg_fmt, ...)
496 {
497 	struct va_format vaf;
498 	va_list args;
499 	u32 val;
500 
501 	val = I915_READ(reg);
502 	if ((val & mask) == expected)
503 		return true;
504 
505 	va_start(args, reg_fmt);
506 	vaf.fmt = reg_fmt;
507 	vaf.va = &args;
508 
509 	DRM_DEBUG_DRIVER("DDI PHY %d reg %pV [%08x] state mismatch: "
510 			 "current %08x, expected %08x (mask %08x)\n",
511 			 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
512 			 mask);
513 
514 	va_end(args);
515 
516 	return false;
517 }
518 
519 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
520 			      enum dpio_phy phy)
521 {
522 	const struct bxt_ddi_phy_info *phy_info;
523 	u32 mask;
524 	bool ok;
525 
526 	phy_info = bxt_get_phy_info(dev_priv, phy);
527 
528 #define _CHK(reg, mask, exp, fmt, ...)					\
529 	__phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt,	\
530 			       ## __VA_ARGS__)
531 
532 	if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
533 		return false;
534 
535 	ok = true;
536 
537 	/* PLL Rcomp code offset */
538 	ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
539 		    IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
540 		    "BXT_PORT_CL1CM_DW9(%d)", phy);
541 	ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
542 		    IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
543 		    "BXT_PORT_CL1CM_DW10(%d)", phy);
544 
545 	/* Power gating */
546 	mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
547 	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
548 		    "BXT_PORT_CL1CM_DW28(%d)", phy);
549 
550 	if (phy_info->dual_channel)
551 		ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
552 			   DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
553 			   "BXT_PORT_CL2CM_DW6(%d)", phy);
554 
555 	if (phy_info->rcomp_phy != -1) {
556 		u32 grc_code = dev_priv->bxt_phy_grc;
557 
558 		grc_code = grc_code << GRC_CODE_FAST_SHIFT |
559 			   grc_code << GRC_CODE_SLOW_SHIFT |
560 			   grc_code;
561 		mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
562 		       GRC_CODE_NOM_MASK;
563 		ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
564 			   "BXT_PORT_REF_DW6(%d)", phy);
565 
566 		mask = GRC_DIS | GRC_RDY_OVRD;
567 		ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
568 			    "BXT_PORT_REF_DW8(%d)", phy);
569 	}
570 
571 	return ok;
572 #undef _CHK
573 }
574 
575 u8
576 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count)
577 {
578 	switch (lane_count) {
579 	case 1:
580 		return 0;
581 	case 2:
582 		return BIT(2) | BIT(0);
583 	case 4:
584 		return BIT(3) | BIT(2) | BIT(0);
585 	default:
586 		MISSING_CASE(lane_count);
587 
588 		return 0;
589 	}
590 }
591 
592 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
593 				     u8 lane_lat_optim_mask)
594 {
595 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
596 	enum port port = encoder->port;
597 	enum dpio_phy phy;
598 	enum dpio_channel ch;
599 	int lane;
600 
601 	bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
602 
603 	for (lane = 0; lane < 4; lane++) {
604 		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
605 
606 		/*
607 		 * Note that on CHV this flag is called UPAR, but has
608 		 * the same function.
609 		 */
610 		val &= ~LATENCY_OPTIM;
611 		if (lane_lat_optim_mask & BIT(lane))
612 			val |= LATENCY_OPTIM;
613 
614 		I915_WRITE(BXT_PORT_TX_DW14_LN(phy, ch, lane), val);
615 	}
616 }
617 
618 u8
619 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
620 {
621 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
622 	enum port port = encoder->port;
623 	enum dpio_phy phy;
624 	enum dpio_channel ch;
625 	int lane;
626 	u8 mask;
627 
628 	bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
629 
630 	mask = 0;
631 	for (lane = 0; lane < 4; lane++) {
632 		u32 val = I915_READ(BXT_PORT_TX_DW14_LN(phy, ch, lane));
633 
634 		if (val & LATENCY_OPTIM)
635 			mask |= BIT(lane);
636 	}
637 
638 	return mask;
639 }
640 
641 
642 void chv_set_phy_signal_level(struct intel_encoder *encoder,
643 			      u32 deemph_reg_value, u32 margin_reg_value,
644 			      bool uniq_trans_scale)
645 {
646 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
647 	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
648 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
649 	enum dpio_channel ch = vlv_dport_to_channel(dport);
650 	enum pipe pipe = intel_crtc->pipe;
651 	u32 val;
652 	int i;
653 
654 	vlv_dpio_get(dev_priv);
655 
656 	/* Clear calc init */
657 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
658 	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
659 	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
660 	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
661 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
662 
663 	if (intel_crtc->config->lane_count > 2) {
664 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
665 		val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
666 		val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
667 		val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
668 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
669 	}
670 
671 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
672 	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
673 	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
674 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
675 
676 	if (intel_crtc->config->lane_count > 2) {
677 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
678 		val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
679 		val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
680 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
681 	}
682 
683 	/* Program swing deemph */
684 	for (i = 0; i < intel_crtc->config->lane_count; i++) {
685 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
686 		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
687 		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
688 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
689 	}
690 
691 	/* Program swing margin */
692 	for (i = 0; i < intel_crtc->config->lane_count; i++) {
693 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
694 
695 		val &= ~DPIO_SWING_MARGIN000_MASK;
696 		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
697 
698 		/*
699 		 * Supposedly this value shouldn't matter when unique transition
700 		 * scale is disabled, but in fact it does matter. Let's just
701 		 * always program the same value and hope it's OK.
702 		 */
703 		val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
704 		val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
705 
706 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
707 	}
708 
709 	/*
710 	 * The document said it needs to set bit 27 for ch0 and bit 26
711 	 * for ch1. Might be a typo in the doc.
712 	 * For now, for this unique transition scale selection, set bit
713 	 * 27 for ch0 and ch1.
714 	 */
715 	for (i = 0; i < intel_crtc->config->lane_count; i++) {
716 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
717 		if (uniq_trans_scale)
718 			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
719 		else
720 			val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
721 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
722 	}
723 
724 	/* Start swing calculation */
725 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
726 	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
727 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
728 
729 	if (intel_crtc->config->lane_count > 2) {
730 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
731 		val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
732 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
733 	}
734 
735 	vlv_dpio_put(dev_priv);
736 }
737 
738 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
739 			      const struct intel_crtc_state *crtc_state,
740 			      bool reset)
741 {
742 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
743 	enum dpio_channel ch = vlv_dport_to_channel(enc_to_dig_port(&encoder->base));
744 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
745 	enum pipe pipe = crtc->pipe;
746 	u32 val;
747 
748 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
749 	if (reset)
750 		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
751 	else
752 		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
753 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
754 
755 	if (crtc_state->lane_count > 2) {
756 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
757 		if (reset)
758 			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
759 		else
760 			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
761 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
762 	}
763 
764 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
765 	val |= CHV_PCS_REQ_SOFTRESET_EN;
766 	if (reset)
767 		val &= ~DPIO_PCS_CLK_SOFT_RESET;
768 	else
769 		val |= DPIO_PCS_CLK_SOFT_RESET;
770 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
771 
772 	if (crtc_state->lane_count > 2) {
773 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
774 		val |= CHV_PCS_REQ_SOFTRESET_EN;
775 		if (reset)
776 			val &= ~DPIO_PCS_CLK_SOFT_RESET;
777 		else
778 			val |= DPIO_PCS_CLK_SOFT_RESET;
779 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
780 	}
781 }
782 
783 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
784 			    const struct intel_crtc_state *crtc_state)
785 {
786 	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
787 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
788 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
789 	enum dpio_channel ch = vlv_dport_to_channel(dport);
790 	enum pipe pipe = crtc->pipe;
791 	unsigned int lane_mask =
792 		intel_dp_unused_lane_mask(crtc_state->lane_count);
793 	u32 val;
794 
795 	/*
796 	 * Must trick the second common lane into life.
797 	 * Otherwise we can't even access the PLL.
798 	 */
799 	if (ch == DPIO_CH0 && pipe == PIPE_B)
800 		dport->release_cl2_override =
801 			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
802 
803 	chv_phy_powergate_lanes(encoder, true, lane_mask);
804 
805 	vlv_dpio_get(dev_priv);
806 
807 	/* Assert data lane reset */
808 	chv_data_lane_soft_reset(encoder, crtc_state, true);
809 
810 	/* program left/right clock distribution */
811 	if (pipe != PIPE_B) {
812 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
813 		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
814 		if (ch == DPIO_CH0)
815 			val |= CHV_BUFLEFTENA1_FORCE;
816 		if (ch == DPIO_CH1)
817 			val |= CHV_BUFRIGHTENA1_FORCE;
818 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
819 	} else {
820 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
821 		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
822 		if (ch == DPIO_CH0)
823 			val |= CHV_BUFLEFTENA2_FORCE;
824 		if (ch == DPIO_CH1)
825 			val |= CHV_BUFRIGHTENA2_FORCE;
826 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
827 	}
828 
829 	/* program clock channel usage */
830 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
831 	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
832 	if (pipe != PIPE_B)
833 		val &= ~CHV_PCS_USEDCLKCHANNEL;
834 	else
835 		val |= CHV_PCS_USEDCLKCHANNEL;
836 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
837 
838 	if (crtc_state->lane_count > 2) {
839 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
840 		val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
841 		if (pipe != PIPE_B)
842 			val &= ~CHV_PCS_USEDCLKCHANNEL;
843 		else
844 			val |= CHV_PCS_USEDCLKCHANNEL;
845 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
846 	}
847 
848 	/*
849 	 * This a a bit weird since generally CL
850 	 * matches the pipe, but here we need to
851 	 * pick the CL based on the port.
852 	 */
853 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
854 	if (pipe != PIPE_B)
855 		val &= ~CHV_CMN_USEDCLKCHANNEL;
856 	else
857 		val |= CHV_CMN_USEDCLKCHANNEL;
858 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
859 
860 	vlv_dpio_put(dev_priv);
861 }
862 
863 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
864 				const struct intel_crtc_state *crtc_state)
865 {
866 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
867 	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
868 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
869 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
870 	enum dpio_channel ch = vlv_dport_to_channel(dport);
871 	enum pipe pipe = crtc->pipe;
872 	int data, i, stagger;
873 	u32 val;
874 
875 	vlv_dpio_get(dev_priv);
876 
877 	/* allow hardware to manage TX FIFO reset source */
878 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
879 	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
880 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
881 
882 	if (crtc_state->lane_count > 2) {
883 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
884 		val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
885 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
886 	}
887 
888 	/* Program Tx lane latency optimal setting*/
889 	for (i = 0; i < crtc_state->lane_count; i++) {
890 		/* Set the upar bit */
891 		if (crtc_state->lane_count == 1)
892 			data = 0x0;
893 		else
894 			data = (i == 1) ? 0x0 : 0x1;
895 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
896 				data << DPIO_UPAR_SHIFT);
897 	}
898 
899 	/* Data lane stagger programming */
900 	if (crtc_state->port_clock > 270000)
901 		stagger = 0x18;
902 	else if (crtc_state->port_clock > 135000)
903 		stagger = 0xd;
904 	else if (crtc_state->port_clock > 67500)
905 		stagger = 0x7;
906 	else if (crtc_state->port_clock > 33750)
907 		stagger = 0x4;
908 	else
909 		stagger = 0x2;
910 
911 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
912 	val |= DPIO_TX2_STAGGER_MASK(0x1f);
913 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
914 
915 	if (crtc_state->lane_count > 2) {
916 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
917 		val |= DPIO_TX2_STAGGER_MASK(0x1f);
918 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
919 	}
920 
921 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
922 		       DPIO_LANESTAGGER_STRAP(stagger) |
923 		       DPIO_LANESTAGGER_STRAP_OVRD |
924 		       DPIO_TX1_STAGGER_MASK(0x1f) |
925 		       DPIO_TX1_STAGGER_MULT(6) |
926 		       DPIO_TX2_STAGGER_MULT(0));
927 
928 	if (crtc_state->lane_count > 2) {
929 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
930 			       DPIO_LANESTAGGER_STRAP(stagger) |
931 			       DPIO_LANESTAGGER_STRAP_OVRD |
932 			       DPIO_TX1_STAGGER_MASK(0x1f) |
933 			       DPIO_TX1_STAGGER_MULT(7) |
934 			       DPIO_TX2_STAGGER_MULT(5));
935 	}
936 
937 	/* Deassert data lane reset */
938 	chv_data_lane_soft_reset(encoder, crtc_state, false);
939 
940 	vlv_dpio_put(dev_priv);
941 }
942 
943 void chv_phy_release_cl2_override(struct intel_encoder *encoder)
944 {
945 	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
946 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
947 
948 	if (dport->release_cl2_override) {
949 		chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
950 		dport->release_cl2_override = false;
951 	}
952 }
953 
954 void chv_phy_post_pll_disable(struct intel_encoder *encoder,
955 			      const struct intel_crtc_state *old_crtc_state)
956 {
957 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
958 	enum pipe pipe = to_intel_crtc(old_crtc_state->base.crtc)->pipe;
959 	u32 val;
960 
961 	vlv_dpio_get(dev_priv);
962 
963 	/* disable left/right clock distribution */
964 	if (pipe != PIPE_B) {
965 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
966 		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
967 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
968 	} else {
969 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
970 		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
971 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
972 	}
973 
974 	vlv_dpio_put(dev_priv);
975 
976 	/*
977 	 * Leave the power down bit cleared for at least one
978 	 * lane so that chv_powergate_phy_ch() will power
979 	 * on something when the channel is otherwise unused.
980 	 * When the port is off and the override is removed
981 	 * the lanes power down anyway, so otherwise it doesn't
982 	 * really matter what the state of power down bits is
983 	 * after this.
984 	 */
985 	chv_phy_powergate_lanes(encoder, false, 0x0);
986 }
987 
988 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
989 			      u32 demph_reg_value, u32 preemph_reg_value,
990 			      u32 uniqtranscale_reg_value, u32 tx3_demph)
991 {
992 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
993 	struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
994 	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
995 	enum dpio_channel port = vlv_dport_to_channel(dport);
996 	enum pipe pipe = intel_crtc->pipe;
997 
998 	vlv_dpio_get(dev_priv);
999 
1000 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
1001 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
1002 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
1003 			 uniqtranscale_reg_value);
1004 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
1005 
1006 	if (tx3_demph)
1007 		vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);
1008 
1009 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1010 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
1011 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1012 
1013 	vlv_dpio_put(dev_priv);
1014 }
1015 
1016 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
1017 			    const struct intel_crtc_state *crtc_state)
1018 {
1019 	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1020 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1021 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1022 	enum dpio_channel port = vlv_dport_to_channel(dport);
1023 	enum pipe pipe = crtc->pipe;
1024 
1025 	/* Program Tx lane resets to default */
1026 	vlv_dpio_get(dev_priv);
1027 
1028 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1029 			 DPIO_PCS_TX_LANE2_RESET |
1030 			 DPIO_PCS_TX_LANE1_RESET);
1031 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1032 			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1033 			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1034 			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1035 				 DPIO_PCS_CLK_SOFT_RESET);
1036 
1037 	/* Fix up inter-pair skew failure */
1038 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1039 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1040 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1041 
1042 	vlv_dpio_put(dev_priv);
1043 }
1044 
1045 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
1046 				const struct intel_crtc_state *crtc_state)
1047 {
1048 	struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base);
1049 	struct intel_digital_port *dport = dp_to_dig_port(intel_dp);
1050 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1051 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
1052 	enum dpio_channel port = vlv_dport_to_channel(dport);
1053 	enum pipe pipe = crtc->pipe;
1054 	u32 val;
1055 
1056 	vlv_dpio_get(dev_priv);
1057 
1058 	/* Enable clock channels for this port */
1059 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1060 	val = 0;
1061 	if (pipe)
1062 		val |= (1<<21);
1063 	else
1064 		val &= ~(1<<21);
1065 	val |= 0x001000c4;
1066 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1067 
1068 	/* Program lane clock */
1069 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1070 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1071 
1072 	vlv_dpio_put(dev_priv);
1073 }
1074 
1075 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
1076 			 const struct intel_crtc_state *old_crtc_state)
1077 {
1078 	struct intel_digital_port *dport = enc_to_dig_port(&encoder->base);
1079 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1080 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc);
1081 	enum dpio_channel port = vlv_dport_to_channel(dport);
1082 	enum pipe pipe = crtc->pipe;
1083 
1084 	vlv_dpio_get(dev_priv);
1085 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1086 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1087 	vlv_dpio_put(dev_priv);
1088 }
1089