1 /*
2  * Copyright © 2014-2016 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  */
23 
24 #include "intel_ddi.h"
25 #include "intel_ddi_buf_trans.h"
26 #include "intel_de.h"
27 #include "intel_display_power_well.h"
28 #include "intel_display_types.h"
29 #include "intel_dp.h"
30 #include "intel_dpio_phy.h"
31 #include "vlv_sideband.h"
32 
33 /**
34  * DOC: DPIO
35  *
36  * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
37  * ports. DPIO is the name given to such a display PHY. These PHYs
38  * don't follow the standard programming model using direct MMIO
39  * registers, and instead their registers must be accessed trough IOSF
40  * sideband. VLV has one such PHY for driving ports B and C, and CHV
41  * adds another PHY for driving port D. Each PHY responds to specific
42  * IOSF-SB port.
43  *
44  * Each display PHY is made up of one or two channels. Each channel
45  * houses a common lane part which contains the PLL and other common
46  * logic. CH0 common lane also contains the IOSF-SB logic for the
47  * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
48  * must be running when any DPIO registers are accessed.
49  *
50  * In addition to having their own registers, the PHYs are also
51  * controlled through some dedicated signals from the display
52  * controller. These include PLL reference clock enable, PLL enable,
53  * and CRI clock selection, for example.
54  *
55  * Eeach channel also has two splines (also called data lanes), and
56  * each spline is made up of one Physical Access Coding Sub-Layer
57  * (PCS) block and two TX lanes. So each channel has two PCS blocks
58  * and four TX lanes. The TX lanes are used as DP lanes or TMDS
59  * data/clock pairs depending on the output type.
60  *
61  * Additionally the PHY also contains an AUX lane with AUX blocks
62  * for each channel. This is used for DP AUX communication, but
63  * this fact isn't really relevant for the driver since AUX is
64  * controlled from the display controller side. No DPIO registers
65  * need to be accessed during AUX communication,
66  *
67  * Generally on VLV/CHV the common lane corresponds to the pipe and
68  * the spline (PCS/TX) corresponds to the port.
69  *
70  * For dual channel PHY (VLV/CHV):
71  *
72  *  pipe A == CMN/PLL/REF CH0
73  *
74  *  pipe B == CMN/PLL/REF CH1
75  *
76  *  port B == PCS/TX CH0
77  *
78  *  port C == PCS/TX CH1
79  *
80  * This is especially important when we cross the streams
81  * ie. drive port B with pipe B, or port C with pipe A.
82  *
83  * For single channel PHY (CHV):
84  *
85  *  pipe C == CMN/PLL/REF CH0
86  *
87  *  port D == PCS/TX CH0
88  *
89  * On BXT the entire PHY channel corresponds to the port. That means
90  * the PLL is also now associated with the port rather than the pipe,
91  * and so the clock needs to be routed to the appropriate transcoder.
92  * Port A PLL is directly connected to transcoder EDP and port B/C
93  * PLLs can be routed to any transcoder A/B/C.
94  *
95  * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
96  * digital port D (CHV) or port A (BXT). ::
97  *
98  *
99  *     Dual channel PHY (VLV/CHV/BXT)
100  *     ---------------------------------
101  *     |      CH0      |      CH1      |
102  *     |  CMN/PLL/REF  |  CMN/PLL/REF  |
103  *     |---------------|---------------| Display PHY
104  *     | PCS01 | PCS23 | PCS01 | PCS23 |
105  *     |-------|-------|-------|-------|
106  *     |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
107  *     ---------------------------------
108  *     |     DDI0      |     DDI1      | DP/HDMI ports
109  *     ---------------------------------
110  *
111  *     Single channel PHY (CHV/BXT)
112  *     -----------------
113  *     |      CH0      |
114  *     |  CMN/PLL/REF  |
115  *     |---------------| Display PHY
116  *     | PCS01 | PCS23 |
117  *     |-------|-------|
118  *     |TX0|TX1|TX2|TX3|
119  *     -----------------
120  *     |     DDI2      | DP/HDMI port
121  *     -----------------
122  */
123 
124 /**
125  * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
126  */
127 struct bxt_ddi_phy_info {
128 	/**
129 	 * @dual_channel: true if this phy has a second channel.
130 	 */
131 	bool dual_channel;
132 
133 	/**
134 	 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
135 	 * Otherwise the GRC value will be copied from the phy indicated by
136 	 * this field.
137 	 */
138 	enum dpio_phy rcomp_phy;
139 
140 	/**
141 	 * @reset_delay: delay in us to wait before setting the common reset
142 	 * bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy.
143 	 */
144 	int reset_delay;
145 
146 	/**
147 	 * @pwron_mask: Mask with the appropriate bit set that would cause the
148 	 * punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON.
149 	 */
150 	u32 pwron_mask;
151 
152 	/**
153 	 * @channel: struct containing per channel information.
154 	 */
155 	struct {
156 		/**
157 		 * @channel.port: which port maps to this channel.
158 		 */
159 		enum port port;
160 	} channel[2];
161 };
162 
163 static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
164 	[DPIO_PHY0] = {
165 		.dual_channel = true,
166 		.rcomp_phy = DPIO_PHY1,
167 		.pwron_mask = BIT(0),
168 
169 		.channel = {
170 			[DPIO_CH0] = { .port = PORT_B },
171 			[DPIO_CH1] = { .port = PORT_C },
172 		}
173 	},
174 	[DPIO_PHY1] = {
175 		.dual_channel = false,
176 		.rcomp_phy = -1,
177 		.pwron_mask = BIT(1),
178 
179 		.channel = {
180 			[DPIO_CH0] = { .port = PORT_A },
181 		}
182 	},
183 };
184 
185 static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = {
186 	[DPIO_PHY0] = {
187 		.dual_channel = false,
188 		.rcomp_phy = DPIO_PHY1,
189 		.pwron_mask = BIT(0),
190 		.reset_delay = 20,
191 
192 		.channel = {
193 			[DPIO_CH0] = { .port = PORT_B },
194 		}
195 	},
196 	[DPIO_PHY1] = {
197 		.dual_channel = false,
198 		.rcomp_phy = -1,
199 		.pwron_mask = BIT(3),
200 		.reset_delay = 20,
201 
202 		.channel = {
203 			[DPIO_CH0] = { .port = PORT_A },
204 		}
205 	},
206 	[DPIO_PHY2] = {
207 		.dual_channel = false,
208 		.rcomp_phy = DPIO_PHY1,
209 		.pwron_mask = BIT(1),
210 		.reset_delay = 20,
211 
212 		.channel = {
213 			[DPIO_CH0] = { .port = PORT_C },
214 		}
215 	},
216 };
217 
218 static const struct bxt_ddi_phy_info *
219 bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
220 {
221 	if (IS_GEMINILAKE(dev_priv)) {
222 		*count =  ARRAY_SIZE(glk_ddi_phy_info);
223 		return glk_ddi_phy_info;
224 	} else {
225 		*count =  ARRAY_SIZE(bxt_ddi_phy_info);
226 		return bxt_ddi_phy_info;
227 	}
228 }
229 
230 static const struct bxt_ddi_phy_info *
231 bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)
232 {
233 	int count;
234 	const struct bxt_ddi_phy_info *phy_list =
235 		bxt_get_phy_list(dev_priv, &count);
236 
237 	return &phy_list[phy];
238 }
239 
240 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
241 			     enum dpio_phy *phy, enum dpio_channel *ch)
242 {
243 	const struct bxt_ddi_phy_info *phy_info, *phys;
244 	int i, count;
245 
246 	phys = bxt_get_phy_list(dev_priv, &count);
247 
248 	for (i = 0; i < count; i++) {
249 		phy_info = &phys[i];
250 
251 		if (port == phy_info->channel[DPIO_CH0].port) {
252 			*phy = i;
253 			*ch = DPIO_CH0;
254 			return;
255 		}
256 
257 		if (phy_info->dual_channel &&
258 		    port == phy_info->channel[DPIO_CH1].port) {
259 			*phy = i;
260 			*ch = DPIO_CH1;
261 			return;
262 		}
263 	}
264 
265 	drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c",
266 		 port_name(port));
267 	*phy = DPIO_PHY0;
268 	*ch = DPIO_CH0;
269 }
270 
271 void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
272 				   const struct intel_crtc_state *crtc_state)
273 {
274 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
275 	int level = intel_ddi_level(encoder, crtc_state, 0);
276 	const struct intel_ddi_buf_trans *trans;
277 	enum dpio_channel ch;
278 	enum dpio_phy phy;
279 	int n_entries;
280 	u32 val;
281 
282 	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
283 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
284 		return;
285 
286 	bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch);
287 
288 	/*
289 	 * While we write to the group register to program all lanes at once we
290 	 * can read only lane registers and we pick lanes 0/1 for that.
291 	 */
292 	val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch));
293 	val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
294 	intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val);
295 
296 	val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch));
297 	val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
298 	val |= trans->entries[level].bxt.margin << MARGIN_000_SHIFT |
299 		trans->entries[level].bxt.scale << UNIQ_TRANS_SCALE_SHIFT;
300 	intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val);
301 
302 	val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch));
303 	val &= ~SCALE_DCOMP_METHOD;
304 	if (trans->entries[level].bxt.enable)
305 		val |= SCALE_DCOMP_METHOD;
306 
307 	if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
308 		drm_err(&dev_priv->drm,
309 			"Disabled scaling while ouniqetrangenmethod was set");
310 
311 	intel_de_write(dev_priv, BXT_PORT_TX_DW3_GRP(phy, ch), val);
312 
313 	val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch));
314 	val &= ~DE_EMPHASIS;
315 	val |= trans->entries[level].bxt.deemphasis << DEEMPH_SHIFT;
316 	intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val);
317 
318 	val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch));
319 	val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
320 	intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val);
321 }
322 
323 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
324 			    enum dpio_phy phy)
325 {
326 	const struct bxt_ddi_phy_info *phy_info;
327 
328 	phy_info = bxt_get_phy_info(dev_priv, phy);
329 
330 	if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
331 		return false;
332 
333 	if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) &
334 	     (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
335 		drm_dbg(&dev_priv->drm,
336 			"DDI PHY %d powered, but power hasn't settled\n", phy);
337 
338 		return false;
339 	}
340 
341 	if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
342 		drm_dbg(&dev_priv->drm,
343 			"DDI PHY %d powered, but still in reset\n", phy);
344 
345 		return false;
346 	}
347 
348 	return true;
349 }
350 
351 static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
352 {
353 	u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy));
354 
355 	return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
356 }
357 
358 static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
359 				  enum dpio_phy phy)
360 {
361 	if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy),
362 				  GRC_DONE, 10))
363 		drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n",
364 			phy);
365 }
366 
367 static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
368 			      enum dpio_phy phy)
369 {
370 	const struct bxt_ddi_phy_info *phy_info;
371 	u32 val;
372 
373 	phy_info = bxt_get_phy_info(dev_priv, phy);
374 
375 	if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
376 		/* Still read out the GRC value for state verification */
377 		if (phy_info->rcomp_phy != -1)
378 			dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy);
379 
380 		if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
381 			drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, "
382 				"won't reprogram it\n", phy);
383 			return;
384 		}
385 
386 		drm_dbg(&dev_priv->drm,
387 			"DDI PHY %d enabled with invalid state, "
388 			"force reprogramming it\n", phy);
389 	}
390 
391 	val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
392 	val |= phy_info->pwron_mask;
393 	intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val);
394 
395 	/*
396 	 * The PHY registers start out inaccessible and respond to reads with
397 	 * all 1s.  Eventually they become accessible as they power up, then
398 	 * the reserved bit will give the default 0.  Poll on the reserved bit
399 	 * becoming 0 to find when the PHY is accessible.
400 	 * The flag should get set in 100us according to the HW team, but
401 	 * use 1ms due to occasional timeouts observed with that.
402 	 */
403 	if (intel_wait_for_register_fw(&dev_priv->uncore,
404 				       BXT_PORT_CL1CM_DW0(phy),
405 				       PHY_RESERVED | PHY_POWER_GOOD,
406 				       PHY_POWER_GOOD,
407 				       1))
408 		drm_err(&dev_priv->drm, "timeout during PHY%d power on\n",
409 			phy);
410 
411 	/* Program PLL Rcomp code offset */
412 	val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW9(phy));
413 	val &= ~IREF0RC_OFFSET_MASK;
414 	val |= 0xE4 << IREF0RC_OFFSET_SHIFT;
415 	intel_de_write(dev_priv, BXT_PORT_CL1CM_DW9(phy), val);
416 
417 	val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW10(phy));
418 	val &= ~IREF1RC_OFFSET_MASK;
419 	val |= 0xE4 << IREF1RC_OFFSET_SHIFT;
420 	intel_de_write(dev_priv, BXT_PORT_CL1CM_DW10(phy), val);
421 
422 	/* Program power gating */
423 	val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW28(phy));
424 	val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN |
425 		SUS_CLK_CONFIG;
426 	intel_de_write(dev_priv, BXT_PORT_CL1CM_DW28(phy), val);
427 
428 	if (phy_info->dual_channel) {
429 		val = intel_de_read(dev_priv, BXT_PORT_CL2CM_DW6(phy));
430 		val |= DW6_OLDO_DYN_PWR_DOWN_EN;
431 		intel_de_write(dev_priv, BXT_PORT_CL2CM_DW6(phy), val);
432 	}
433 
434 	if (phy_info->rcomp_phy != -1) {
435 		u32 grc_code;
436 
437 		bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
438 
439 		/*
440 		 * PHY0 isn't connected to an RCOMP resistor so copy over
441 		 * the corresponding calibrated value from PHY1, and disable
442 		 * the automatic calibration on PHY0.
443 		 */
444 		val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv,
445 							  phy_info->rcomp_phy);
446 		grc_code = val << GRC_CODE_FAST_SHIFT |
447 			   val << GRC_CODE_SLOW_SHIFT |
448 			   val;
449 		intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code);
450 
451 		val = intel_de_read(dev_priv, BXT_PORT_REF_DW8(phy));
452 		val |= GRC_DIS | GRC_RDY_OVRD;
453 		intel_de_write(dev_priv, BXT_PORT_REF_DW8(phy), val);
454 	}
455 
456 	if (phy_info->reset_delay)
457 		udelay(phy_info->reset_delay);
458 
459 	val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy));
460 	val |= COMMON_RESET_DIS;
461 	intel_de_write(dev_priv, BXT_PHY_CTL_FAMILY(phy), val);
462 }
463 
464 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
465 {
466 	const struct bxt_ddi_phy_info *phy_info;
467 	u32 val;
468 
469 	phy_info = bxt_get_phy_info(dev_priv, phy);
470 
471 	val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy));
472 	val &= ~COMMON_RESET_DIS;
473 	intel_de_write(dev_priv, BXT_PHY_CTL_FAMILY(phy), val);
474 
475 	val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON);
476 	val &= ~phy_info->pwron_mask;
477 	intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val);
478 }
479 
480 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
481 {
482 	const struct bxt_ddi_phy_info *phy_info =
483 		bxt_get_phy_info(dev_priv, phy);
484 	enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
485 	bool was_enabled;
486 
487 	lockdep_assert_held(&dev_priv->display.power.domains.lock);
488 
489 	was_enabled = true;
490 	if (rcomp_phy != -1)
491 		was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy);
492 
493 	/*
494 	 * We need to copy the GRC calibration value from rcomp_phy,
495 	 * so make sure it's powered up.
496 	 */
497 	if (!was_enabled)
498 		_bxt_ddi_phy_init(dev_priv, rcomp_phy);
499 
500 	_bxt_ddi_phy_init(dev_priv, phy);
501 
502 	if (!was_enabled)
503 		bxt_ddi_phy_uninit(dev_priv, rcomp_phy);
504 }
505 
506 static bool __printf(6, 7)
507 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
508 		       i915_reg_t reg, u32 mask, u32 expected,
509 		       const char *reg_fmt, ...)
510 {
511 	struct va_format vaf;
512 	va_list args;
513 	u32 val;
514 
515 	val = intel_de_read(dev_priv, reg);
516 	if ((val & mask) == expected)
517 		return true;
518 
519 	va_start(args, reg_fmt);
520 	vaf.fmt = reg_fmt;
521 	vaf.va = &args;
522 
523 	drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: "
524 			 "current %08x, expected %08x (mask %08x)\n",
525 			 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
526 			 mask);
527 
528 	va_end(args);
529 
530 	return false;
531 }
532 
533 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
534 			      enum dpio_phy phy)
535 {
536 	const struct bxt_ddi_phy_info *phy_info;
537 	u32 mask;
538 	bool ok;
539 
540 	phy_info = bxt_get_phy_info(dev_priv, phy);
541 
542 #define _CHK(reg, mask, exp, fmt, ...)					\
543 	__phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt,	\
544 			       ## __VA_ARGS__)
545 
546 	if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
547 		return false;
548 
549 	ok = true;
550 
551 	/* PLL Rcomp code offset */
552 	ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
553 		    IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
554 		    "BXT_PORT_CL1CM_DW9(%d)", phy);
555 	ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
556 		    IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
557 		    "BXT_PORT_CL1CM_DW10(%d)", phy);
558 
559 	/* Power gating */
560 	mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
561 	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
562 		    "BXT_PORT_CL1CM_DW28(%d)", phy);
563 
564 	if (phy_info->dual_channel)
565 		ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
566 			   DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
567 			   "BXT_PORT_CL2CM_DW6(%d)", phy);
568 
569 	if (phy_info->rcomp_phy != -1) {
570 		u32 grc_code = dev_priv->bxt_phy_grc;
571 
572 		grc_code = grc_code << GRC_CODE_FAST_SHIFT |
573 			   grc_code << GRC_CODE_SLOW_SHIFT |
574 			   grc_code;
575 		mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
576 		       GRC_CODE_NOM_MASK;
577 		ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
578 			   "BXT_PORT_REF_DW6(%d)", phy);
579 
580 		mask = GRC_DIS | GRC_RDY_OVRD;
581 		ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
582 			    "BXT_PORT_REF_DW8(%d)", phy);
583 	}
584 
585 	return ok;
586 #undef _CHK
587 }
588 
589 u8
590 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count)
591 {
592 	switch (lane_count) {
593 	case 1:
594 		return 0;
595 	case 2:
596 		return BIT(2) | BIT(0);
597 	case 4:
598 		return BIT(3) | BIT(2) | BIT(0);
599 	default:
600 		MISSING_CASE(lane_count);
601 
602 		return 0;
603 	}
604 }
605 
606 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
607 				     u8 lane_lat_optim_mask)
608 {
609 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
610 	enum port port = encoder->port;
611 	enum dpio_phy phy;
612 	enum dpio_channel ch;
613 	int lane;
614 
615 	bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
616 
617 	for (lane = 0; lane < 4; lane++) {
618 		u32 val = intel_de_read(dev_priv,
619 					BXT_PORT_TX_DW14_LN(phy, ch, lane));
620 
621 		/*
622 		 * Note that on CHV this flag is called UPAR, but has
623 		 * the same function.
624 		 */
625 		val &= ~LATENCY_OPTIM;
626 		if (lane_lat_optim_mask & BIT(lane))
627 			val |= LATENCY_OPTIM;
628 
629 		intel_de_write(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane),
630 			       val);
631 	}
632 }
633 
634 u8
635 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
636 {
637 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
638 	enum port port = encoder->port;
639 	enum dpio_phy phy;
640 	enum dpio_channel ch;
641 	int lane;
642 	u8 mask;
643 
644 	bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
645 
646 	mask = 0;
647 	for (lane = 0; lane < 4; lane++) {
648 		u32 val = intel_de_read(dev_priv,
649 					BXT_PORT_TX_DW14_LN(phy, ch, lane));
650 
651 		if (val & LATENCY_OPTIM)
652 			mask |= BIT(lane);
653 	}
654 
655 	return mask;
656 }
657 
658 void chv_set_phy_signal_level(struct intel_encoder *encoder,
659 			      const struct intel_crtc_state *crtc_state,
660 			      u32 deemph_reg_value, u32 margin_reg_value,
661 			      bool uniq_trans_scale)
662 {
663 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
664 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
665 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
666 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
667 	enum pipe pipe = crtc->pipe;
668 	u32 val;
669 	int i;
670 
671 	vlv_dpio_get(dev_priv);
672 
673 	/* Clear calc init */
674 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
675 	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
676 	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
677 	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
678 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
679 
680 	if (crtc_state->lane_count > 2) {
681 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
682 		val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
683 		val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
684 		val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
685 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
686 	}
687 
688 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
689 	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
690 	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
691 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
692 
693 	if (crtc_state->lane_count > 2) {
694 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
695 		val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
696 		val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
697 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
698 	}
699 
700 	/* Program swing deemph */
701 	for (i = 0; i < crtc_state->lane_count; i++) {
702 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
703 		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
704 		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
705 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
706 	}
707 
708 	/* Program swing margin */
709 	for (i = 0; i < crtc_state->lane_count; i++) {
710 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
711 
712 		val &= ~DPIO_SWING_MARGIN000_MASK;
713 		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
714 
715 		/*
716 		 * Supposedly this value shouldn't matter when unique transition
717 		 * scale is disabled, but in fact it does matter. Let's just
718 		 * always program the same value and hope it's OK.
719 		 */
720 		val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
721 		val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
722 
723 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
724 	}
725 
726 	/*
727 	 * The document said it needs to set bit 27 for ch0 and bit 26
728 	 * for ch1. Might be a typo in the doc.
729 	 * For now, for this unique transition scale selection, set bit
730 	 * 27 for ch0 and ch1.
731 	 */
732 	for (i = 0; i < crtc_state->lane_count; i++) {
733 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
734 		if (uniq_trans_scale)
735 			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
736 		else
737 			val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
738 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
739 	}
740 
741 	/* Start swing calculation */
742 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
743 	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
744 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
745 
746 	if (crtc_state->lane_count > 2) {
747 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
748 		val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
749 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
750 	}
751 
752 	vlv_dpio_put(dev_priv);
753 }
754 
755 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
756 			      const struct intel_crtc_state *crtc_state,
757 			      bool reset)
758 {
759 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
760 	enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
761 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
762 	enum pipe pipe = crtc->pipe;
763 	u32 val;
764 
765 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
766 	if (reset)
767 		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
768 	else
769 		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
770 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
771 
772 	if (crtc_state->lane_count > 2) {
773 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
774 		if (reset)
775 			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
776 		else
777 			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
778 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
779 	}
780 
781 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
782 	val |= CHV_PCS_REQ_SOFTRESET_EN;
783 	if (reset)
784 		val &= ~DPIO_PCS_CLK_SOFT_RESET;
785 	else
786 		val |= DPIO_PCS_CLK_SOFT_RESET;
787 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
788 
789 	if (crtc_state->lane_count > 2) {
790 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
791 		val |= CHV_PCS_REQ_SOFTRESET_EN;
792 		if (reset)
793 			val &= ~DPIO_PCS_CLK_SOFT_RESET;
794 		else
795 			val |= DPIO_PCS_CLK_SOFT_RESET;
796 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
797 	}
798 }
799 
800 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
801 			    const struct intel_crtc_state *crtc_state)
802 {
803 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
804 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
805 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
806 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
807 	enum pipe pipe = crtc->pipe;
808 	unsigned int lane_mask =
809 		intel_dp_unused_lane_mask(crtc_state->lane_count);
810 	u32 val;
811 
812 	/*
813 	 * Must trick the second common lane into life.
814 	 * Otherwise we can't even access the PLL.
815 	 */
816 	if (ch == DPIO_CH0 && pipe == PIPE_B)
817 		dig_port->release_cl2_override =
818 			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
819 
820 	chv_phy_powergate_lanes(encoder, true, lane_mask);
821 
822 	vlv_dpio_get(dev_priv);
823 
824 	/* Assert data lane reset */
825 	chv_data_lane_soft_reset(encoder, crtc_state, true);
826 
827 	/* program left/right clock distribution */
828 	if (pipe != PIPE_B) {
829 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
830 		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
831 		if (ch == DPIO_CH0)
832 			val |= CHV_BUFLEFTENA1_FORCE;
833 		if (ch == DPIO_CH1)
834 			val |= CHV_BUFRIGHTENA1_FORCE;
835 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
836 	} else {
837 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
838 		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
839 		if (ch == DPIO_CH0)
840 			val |= CHV_BUFLEFTENA2_FORCE;
841 		if (ch == DPIO_CH1)
842 			val |= CHV_BUFRIGHTENA2_FORCE;
843 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
844 	}
845 
846 	/* program clock channel usage */
847 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
848 	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
849 	if (pipe != PIPE_B)
850 		val &= ~CHV_PCS_USEDCLKCHANNEL;
851 	else
852 		val |= CHV_PCS_USEDCLKCHANNEL;
853 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
854 
855 	if (crtc_state->lane_count > 2) {
856 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
857 		val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
858 		if (pipe != PIPE_B)
859 			val &= ~CHV_PCS_USEDCLKCHANNEL;
860 		else
861 			val |= CHV_PCS_USEDCLKCHANNEL;
862 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
863 	}
864 
865 	/*
866 	 * This a a bit weird since generally CL
867 	 * matches the pipe, but here we need to
868 	 * pick the CL based on the port.
869 	 */
870 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
871 	if (pipe != PIPE_B)
872 		val &= ~CHV_CMN_USEDCLKCHANNEL;
873 	else
874 		val |= CHV_CMN_USEDCLKCHANNEL;
875 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
876 
877 	vlv_dpio_put(dev_priv);
878 }
879 
880 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
881 				const struct intel_crtc_state *crtc_state)
882 {
883 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
884 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
885 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
886 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
887 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
888 	enum pipe pipe = crtc->pipe;
889 	int data, i, stagger;
890 	u32 val;
891 
892 	vlv_dpio_get(dev_priv);
893 
894 	/* allow hardware to manage TX FIFO reset source */
895 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
896 	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
897 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
898 
899 	if (crtc_state->lane_count > 2) {
900 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
901 		val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
902 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
903 	}
904 
905 	/* Program Tx lane latency optimal setting*/
906 	for (i = 0; i < crtc_state->lane_count; i++) {
907 		/* Set the upar bit */
908 		if (crtc_state->lane_count == 1)
909 			data = 0x0;
910 		else
911 			data = (i == 1) ? 0x0 : 0x1;
912 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
913 				data << DPIO_UPAR_SHIFT);
914 	}
915 
916 	/* Data lane stagger programming */
917 	if (crtc_state->port_clock > 270000)
918 		stagger = 0x18;
919 	else if (crtc_state->port_clock > 135000)
920 		stagger = 0xd;
921 	else if (crtc_state->port_clock > 67500)
922 		stagger = 0x7;
923 	else if (crtc_state->port_clock > 33750)
924 		stagger = 0x4;
925 	else
926 		stagger = 0x2;
927 
928 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
929 	val |= DPIO_TX2_STAGGER_MASK(0x1f);
930 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
931 
932 	if (crtc_state->lane_count > 2) {
933 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
934 		val |= DPIO_TX2_STAGGER_MASK(0x1f);
935 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
936 	}
937 
938 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
939 		       DPIO_LANESTAGGER_STRAP(stagger) |
940 		       DPIO_LANESTAGGER_STRAP_OVRD |
941 		       DPIO_TX1_STAGGER_MASK(0x1f) |
942 		       DPIO_TX1_STAGGER_MULT(6) |
943 		       DPIO_TX2_STAGGER_MULT(0));
944 
945 	if (crtc_state->lane_count > 2) {
946 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
947 			       DPIO_LANESTAGGER_STRAP(stagger) |
948 			       DPIO_LANESTAGGER_STRAP_OVRD |
949 			       DPIO_TX1_STAGGER_MASK(0x1f) |
950 			       DPIO_TX1_STAGGER_MULT(7) |
951 			       DPIO_TX2_STAGGER_MULT(5));
952 	}
953 
954 	/* Deassert data lane reset */
955 	chv_data_lane_soft_reset(encoder, crtc_state, false);
956 
957 	vlv_dpio_put(dev_priv);
958 }
959 
960 void chv_phy_release_cl2_override(struct intel_encoder *encoder)
961 {
962 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
963 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
964 
965 	if (dig_port->release_cl2_override) {
966 		chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
967 		dig_port->release_cl2_override = false;
968 	}
969 }
970 
971 void chv_phy_post_pll_disable(struct intel_encoder *encoder,
972 			      const struct intel_crtc_state *old_crtc_state)
973 {
974 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
975 	enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe;
976 	u32 val;
977 
978 	vlv_dpio_get(dev_priv);
979 
980 	/* disable left/right clock distribution */
981 	if (pipe != PIPE_B) {
982 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
983 		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
984 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
985 	} else {
986 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
987 		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
988 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
989 	}
990 
991 	vlv_dpio_put(dev_priv);
992 
993 	/*
994 	 * Leave the power down bit cleared for at least one
995 	 * lane so that chv_powergate_phy_ch() will power
996 	 * on something when the channel is otherwise unused.
997 	 * When the port is off and the override is removed
998 	 * the lanes power down anyway, so otherwise it doesn't
999 	 * really matter what the state of power down bits is
1000 	 * after this.
1001 	 */
1002 	chv_phy_powergate_lanes(encoder, false, 0x0);
1003 }
1004 
1005 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
1006 			      const struct intel_crtc_state *crtc_state,
1007 			      u32 demph_reg_value, u32 preemph_reg_value,
1008 			      u32 uniqtranscale_reg_value, u32 tx3_demph)
1009 {
1010 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1011 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1012 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1013 	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1014 	enum pipe pipe = crtc->pipe;
1015 
1016 	vlv_dpio_get(dev_priv);
1017 
1018 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
1019 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
1020 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
1021 			 uniqtranscale_reg_value);
1022 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
1023 
1024 	if (tx3_demph)
1025 		vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);
1026 
1027 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1028 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
1029 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1030 
1031 	vlv_dpio_put(dev_priv);
1032 }
1033 
1034 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
1035 			    const struct intel_crtc_state *crtc_state)
1036 {
1037 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1038 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1039 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1040 	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1041 	enum pipe pipe = crtc->pipe;
1042 
1043 	/* Program Tx lane resets to default */
1044 	vlv_dpio_get(dev_priv);
1045 
1046 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1047 			 DPIO_PCS_TX_LANE2_RESET |
1048 			 DPIO_PCS_TX_LANE1_RESET);
1049 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1050 			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1051 			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1052 			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1053 				 DPIO_PCS_CLK_SOFT_RESET);
1054 
1055 	/* Fix up inter-pair skew failure */
1056 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1057 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1058 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1059 
1060 	vlv_dpio_put(dev_priv);
1061 }
1062 
1063 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
1064 				const struct intel_crtc_state *crtc_state)
1065 {
1066 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1067 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1068 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1069 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1070 	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1071 	enum pipe pipe = crtc->pipe;
1072 	u32 val;
1073 
1074 	vlv_dpio_get(dev_priv);
1075 
1076 	/* Enable clock channels for this port */
1077 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1078 	val = 0;
1079 	if (pipe)
1080 		val |= (1<<21);
1081 	else
1082 		val &= ~(1<<21);
1083 	val |= 0x001000c4;
1084 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1085 
1086 	/* Program lane clock */
1087 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1088 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1089 
1090 	vlv_dpio_put(dev_priv);
1091 }
1092 
1093 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
1094 			 const struct intel_crtc_state *old_crtc_state)
1095 {
1096 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1097 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1098 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1099 	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1100 	enum pipe pipe = crtc->pipe;
1101 
1102 	vlv_dpio_get(dev_priv);
1103 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1104 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1105 	vlv_dpio_put(dev_priv);
1106 }
1107