1 /* 2 * Copyright © 2014-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "i915_reg.h" 25 #include "intel_ddi.h" 26 #include "intel_ddi_buf_trans.h" 27 #include "intel_de.h" 28 #include "intel_display_power_well.h" 29 #include "intel_display_types.h" 30 #include "intel_dp.h" 31 #include "intel_dpio_phy.h" 32 #include "vlv_sideband.h" 33 34 /** 35 * DOC: DPIO 36 * 37 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI 38 * ports. DPIO is the name given to such a display PHY. These PHYs 39 * don't follow the standard programming model using direct MMIO 40 * registers, and instead their registers must be accessed trough IOSF 41 * sideband. VLV has one such PHY for driving ports B and C, and CHV 42 * adds another PHY for driving port D. Each PHY responds to specific 43 * IOSF-SB port. 44 * 45 * Each display PHY is made up of one or two channels. Each channel 46 * houses a common lane part which contains the PLL and other common 47 * logic. CH0 common lane also contains the IOSF-SB logic for the 48 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock 49 * must be running when any DPIO registers are accessed. 50 * 51 * In addition to having their own registers, the PHYs are also 52 * controlled through some dedicated signals from the display 53 * controller. These include PLL reference clock enable, PLL enable, 54 * and CRI clock selection, for example. 55 * 56 * Eeach channel also has two splines (also called data lanes), and 57 * each spline is made up of one Physical Access Coding Sub-Layer 58 * (PCS) block and two TX lanes. So each channel has two PCS blocks 59 * and four TX lanes. The TX lanes are used as DP lanes or TMDS 60 * data/clock pairs depending on the output type. 61 * 62 * Additionally the PHY also contains an AUX lane with AUX blocks 63 * for each channel. This is used for DP AUX communication, but 64 * this fact isn't really relevant for the driver since AUX is 65 * controlled from the display controller side. No DPIO registers 66 * need to be accessed during AUX communication, 67 * 68 * Generally on VLV/CHV the common lane corresponds to the pipe and 69 * the spline (PCS/TX) corresponds to the port. 70 * 71 * For dual channel PHY (VLV/CHV): 72 * 73 * pipe A == CMN/PLL/REF CH0 74 * 75 * pipe B == CMN/PLL/REF CH1 76 * 77 * port B == PCS/TX CH0 78 * 79 * port C == PCS/TX CH1 80 * 81 * This is especially important when we cross the streams 82 * ie. drive port B with pipe B, or port C with pipe A. 83 * 84 * For single channel PHY (CHV): 85 * 86 * pipe C == CMN/PLL/REF CH0 87 * 88 * port D == PCS/TX CH0 89 * 90 * On BXT the entire PHY channel corresponds to the port. That means 91 * the PLL is also now associated with the port rather than the pipe, 92 * and so the clock needs to be routed to the appropriate transcoder. 93 * Port A PLL is directly connected to transcoder EDP and port B/C 94 * PLLs can be routed to any transcoder A/B/C. 95 * 96 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is 97 * digital port D (CHV) or port A (BXT). :: 98 * 99 * 100 * Dual channel PHY (VLV/CHV/BXT) 101 * --------------------------------- 102 * | CH0 | CH1 | 103 * | CMN/PLL/REF | CMN/PLL/REF | 104 * |---------------|---------------| Display PHY 105 * | PCS01 | PCS23 | PCS01 | PCS23 | 106 * |-------|-------|-------|-------| 107 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| 108 * --------------------------------- 109 * | DDI0 | DDI1 | DP/HDMI ports 110 * --------------------------------- 111 * 112 * Single channel PHY (CHV/BXT) 113 * ----------------- 114 * | CH0 | 115 * | CMN/PLL/REF | 116 * |---------------| Display PHY 117 * | PCS01 | PCS23 | 118 * |-------|-------| 119 * |TX0|TX1|TX2|TX3| 120 * ----------------- 121 * | DDI2 | DP/HDMI port 122 * ----------------- 123 */ 124 125 /** 126 * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy 127 */ 128 struct bxt_ddi_phy_info { 129 /** 130 * @dual_channel: true if this phy has a second channel. 131 */ 132 bool dual_channel; 133 134 /** 135 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor. 136 * Otherwise the GRC value will be copied from the phy indicated by 137 * this field. 138 */ 139 enum dpio_phy rcomp_phy; 140 141 /** 142 * @reset_delay: delay in us to wait before setting the common reset 143 * bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy. 144 */ 145 int reset_delay; 146 147 /** 148 * @pwron_mask: Mask with the appropriate bit set that would cause the 149 * punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON. 150 */ 151 u32 pwron_mask; 152 153 /** 154 * @channel: struct containing per channel information. 155 */ 156 struct { 157 /** 158 * @channel.port: which port maps to this channel. 159 */ 160 enum port port; 161 } channel[2]; 162 }; 163 164 static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = { 165 [DPIO_PHY0] = { 166 .dual_channel = true, 167 .rcomp_phy = DPIO_PHY1, 168 .pwron_mask = BIT(0), 169 170 .channel = { 171 [DPIO_CH0] = { .port = PORT_B }, 172 [DPIO_CH1] = { .port = PORT_C }, 173 } 174 }, 175 [DPIO_PHY1] = { 176 .dual_channel = false, 177 .rcomp_phy = -1, 178 .pwron_mask = BIT(1), 179 180 .channel = { 181 [DPIO_CH0] = { .port = PORT_A }, 182 } 183 }, 184 }; 185 186 static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = { 187 [DPIO_PHY0] = { 188 .dual_channel = false, 189 .rcomp_phy = DPIO_PHY1, 190 .pwron_mask = BIT(0), 191 .reset_delay = 20, 192 193 .channel = { 194 [DPIO_CH0] = { .port = PORT_B }, 195 } 196 }, 197 [DPIO_PHY1] = { 198 .dual_channel = false, 199 .rcomp_phy = -1, 200 .pwron_mask = BIT(3), 201 .reset_delay = 20, 202 203 .channel = { 204 [DPIO_CH0] = { .port = PORT_A }, 205 } 206 }, 207 [DPIO_PHY2] = { 208 .dual_channel = false, 209 .rcomp_phy = DPIO_PHY1, 210 .pwron_mask = BIT(1), 211 .reset_delay = 20, 212 213 .channel = { 214 [DPIO_CH0] = { .port = PORT_C }, 215 } 216 }, 217 }; 218 219 static const struct bxt_ddi_phy_info * 220 bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count) 221 { 222 if (IS_GEMINILAKE(dev_priv)) { 223 *count = ARRAY_SIZE(glk_ddi_phy_info); 224 return glk_ddi_phy_info; 225 } else { 226 *count = ARRAY_SIZE(bxt_ddi_phy_info); 227 return bxt_ddi_phy_info; 228 } 229 } 230 231 static const struct bxt_ddi_phy_info * 232 bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy) 233 { 234 int count; 235 const struct bxt_ddi_phy_info *phy_list = 236 bxt_get_phy_list(dev_priv, &count); 237 238 return &phy_list[phy]; 239 } 240 241 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, 242 enum dpio_phy *phy, enum dpio_channel *ch) 243 { 244 const struct bxt_ddi_phy_info *phy_info, *phys; 245 int i, count; 246 247 phys = bxt_get_phy_list(dev_priv, &count); 248 249 for (i = 0; i < count; i++) { 250 phy_info = &phys[i]; 251 252 if (port == phy_info->channel[DPIO_CH0].port) { 253 *phy = i; 254 *ch = DPIO_CH0; 255 return; 256 } 257 258 if (phy_info->dual_channel && 259 port == phy_info->channel[DPIO_CH1].port) { 260 *phy = i; 261 *ch = DPIO_CH1; 262 return; 263 } 264 } 265 266 drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c", 267 port_name(port)); 268 *phy = DPIO_PHY0; 269 *ch = DPIO_CH0; 270 } 271 272 void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder, 273 const struct intel_crtc_state *crtc_state) 274 { 275 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 276 int level = intel_ddi_level(encoder, crtc_state, 0); 277 const struct intel_ddi_buf_trans *trans; 278 enum dpio_channel ch; 279 enum dpio_phy phy; 280 int n_entries; 281 u32 val; 282 283 trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries); 284 if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans)) 285 return; 286 287 bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch); 288 289 /* 290 * While we write to the group register to program all lanes at once we 291 * can read only lane registers and we pick lanes 0/1 for that. 292 */ 293 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); 294 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); 295 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val); 296 297 val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch)); 298 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); 299 val |= trans->entries[level].bxt.margin << MARGIN_000_SHIFT | 300 trans->entries[level].bxt.scale << UNIQ_TRANS_SCALE_SHIFT; 301 intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val); 302 303 val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch)); 304 val &= ~SCALE_DCOMP_METHOD; 305 if (trans->entries[level].bxt.enable) 306 val |= SCALE_DCOMP_METHOD; 307 308 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) 309 drm_err(&dev_priv->drm, 310 "Disabled scaling while ouniqetrangenmethod was set"); 311 312 intel_de_write(dev_priv, BXT_PORT_TX_DW3_GRP(phy, ch), val); 313 314 val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch)); 315 val &= ~DE_EMPHASIS; 316 val |= trans->entries[level].bxt.deemphasis << DEEMPH_SHIFT; 317 intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val); 318 319 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); 320 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; 321 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val); 322 } 323 324 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, 325 enum dpio_phy phy) 326 { 327 const struct bxt_ddi_phy_info *phy_info; 328 329 phy_info = bxt_get_phy_info(dev_priv, phy); 330 331 if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) 332 return false; 333 334 if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) & 335 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) { 336 drm_dbg(&dev_priv->drm, 337 "DDI PHY %d powered, but power hasn't settled\n", phy); 338 339 return false; 340 } 341 342 if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { 343 drm_dbg(&dev_priv->drm, 344 "DDI PHY %d powered, but still in reset\n", phy); 345 346 return false; 347 } 348 349 return true; 350 } 351 352 static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy) 353 { 354 u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy)); 355 356 return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; 357 } 358 359 static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv, 360 enum dpio_phy phy) 361 { 362 if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy), 363 GRC_DONE, 10)) 364 drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n", 365 phy); 366 } 367 368 static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, 369 enum dpio_phy phy) 370 { 371 const struct bxt_ddi_phy_info *phy_info; 372 u32 val; 373 374 phy_info = bxt_get_phy_info(dev_priv, phy); 375 376 if (bxt_ddi_phy_is_enabled(dev_priv, phy)) { 377 /* Still read out the GRC value for state verification */ 378 if (phy_info->rcomp_phy != -1) 379 dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy); 380 381 if (bxt_ddi_phy_verify_state(dev_priv, phy)) { 382 drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, " 383 "won't reprogram it\n", phy); 384 return; 385 } 386 387 drm_dbg(&dev_priv->drm, 388 "DDI PHY %d enabled with invalid state, " 389 "force reprogramming it\n", phy); 390 } 391 392 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); 393 val |= phy_info->pwron_mask; 394 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val); 395 396 /* 397 * The PHY registers start out inaccessible and respond to reads with 398 * all 1s. Eventually they become accessible as they power up, then 399 * the reserved bit will give the default 0. Poll on the reserved bit 400 * becoming 0 to find when the PHY is accessible. 401 * The flag should get set in 100us according to the HW team, but 402 * use 1ms due to occasional timeouts observed with that. 403 */ 404 if (intel_wait_for_register_fw(&dev_priv->uncore, 405 BXT_PORT_CL1CM_DW0(phy), 406 PHY_RESERVED | PHY_POWER_GOOD, 407 PHY_POWER_GOOD, 408 1)) 409 drm_err(&dev_priv->drm, "timeout during PHY%d power on\n", 410 phy); 411 412 /* Program PLL Rcomp code offset */ 413 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW9(phy)); 414 val &= ~IREF0RC_OFFSET_MASK; 415 val |= 0xE4 << IREF0RC_OFFSET_SHIFT; 416 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW9(phy), val); 417 418 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW10(phy)); 419 val &= ~IREF1RC_OFFSET_MASK; 420 val |= 0xE4 << IREF1RC_OFFSET_SHIFT; 421 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW10(phy), val); 422 423 /* Program power gating */ 424 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW28(phy)); 425 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | 426 SUS_CLK_CONFIG; 427 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW28(phy), val); 428 429 if (phy_info->dual_channel) { 430 val = intel_de_read(dev_priv, BXT_PORT_CL2CM_DW6(phy)); 431 val |= DW6_OLDO_DYN_PWR_DOWN_EN; 432 intel_de_write(dev_priv, BXT_PORT_CL2CM_DW6(phy), val); 433 } 434 435 if (phy_info->rcomp_phy != -1) { 436 u32 grc_code; 437 438 bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy); 439 440 /* 441 * PHY0 isn't connected to an RCOMP resistor so copy over 442 * the corresponding calibrated value from PHY1, and disable 443 * the automatic calibration on PHY0. 444 */ 445 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, 446 phy_info->rcomp_phy); 447 grc_code = val << GRC_CODE_FAST_SHIFT | 448 val << GRC_CODE_SLOW_SHIFT | 449 val; 450 intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code); 451 452 val = intel_de_read(dev_priv, BXT_PORT_REF_DW8(phy)); 453 val |= GRC_DIS | GRC_RDY_OVRD; 454 intel_de_write(dev_priv, BXT_PORT_REF_DW8(phy), val); 455 } 456 457 if (phy_info->reset_delay) 458 udelay(phy_info->reset_delay); 459 460 val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)); 461 val |= COMMON_RESET_DIS; 462 intel_de_write(dev_priv, BXT_PHY_CTL_FAMILY(phy), val); 463 } 464 465 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy) 466 { 467 const struct bxt_ddi_phy_info *phy_info; 468 u32 val; 469 470 phy_info = bxt_get_phy_info(dev_priv, phy); 471 472 val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)); 473 val &= ~COMMON_RESET_DIS; 474 intel_de_write(dev_priv, BXT_PHY_CTL_FAMILY(phy), val); 475 476 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); 477 val &= ~phy_info->pwron_mask; 478 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val); 479 } 480 481 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy) 482 { 483 const struct bxt_ddi_phy_info *phy_info = 484 bxt_get_phy_info(dev_priv, phy); 485 enum dpio_phy rcomp_phy = phy_info->rcomp_phy; 486 bool was_enabled; 487 488 lockdep_assert_held(&dev_priv->display.power.domains.lock); 489 490 was_enabled = true; 491 if (rcomp_phy != -1) 492 was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy); 493 494 /* 495 * We need to copy the GRC calibration value from rcomp_phy, 496 * so make sure it's powered up. 497 */ 498 if (!was_enabled) 499 _bxt_ddi_phy_init(dev_priv, rcomp_phy); 500 501 _bxt_ddi_phy_init(dev_priv, phy); 502 503 if (!was_enabled) 504 bxt_ddi_phy_uninit(dev_priv, rcomp_phy); 505 } 506 507 static bool __printf(6, 7) 508 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy, 509 i915_reg_t reg, u32 mask, u32 expected, 510 const char *reg_fmt, ...) 511 { 512 struct va_format vaf; 513 va_list args; 514 u32 val; 515 516 val = intel_de_read(dev_priv, reg); 517 if ((val & mask) == expected) 518 return true; 519 520 va_start(args, reg_fmt); 521 vaf.fmt = reg_fmt; 522 vaf.va = &args; 523 524 drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: " 525 "current %08x, expected %08x (mask %08x)\n", 526 phy, &vaf, reg.reg, val, (val & ~mask) | expected, 527 mask); 528 529 va_end(args); 530 531 return false; 532 } 533 534 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, 535 enum dpio_phy phy) 536 { 537 const struct bxt_ddi_phy_info *phy_info; 538 u32 mask; 539 bool ok; 540 541 phy_info = bxt_get_phy_info(dev_priv, phy); 542 543 #define _CHK(reg, mask, exp, fmt, ...) \ 544 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \ 545 ## __VA_ARGS__) 546 547 if (!bxt_ddi_phy_is_enabled(dev_priv, phy)) 548 return false; 549 550 ok = true; 551 552 /* PLL Rcomp code offset */ 553 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy), 554 IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT, 555 "BXT_PORT_CL1CM_DW9(%d)", phy); 556 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy), 557 IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT, 558 "BXT_PORT_CL1CM_DW10(%d)", phy); 559 560 /* Power gating */ 561 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG; 562 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask, 563 "BXT_PORT_CL1CM_DW28(%d)", phy); 564 565 if (phy_info->dual_channel) 566 ok &= _CHK(BXT_PORT_CL2CM_DW6(phy), 567 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN, 568 "BXT_PORT_CL2CM_DW6(%d)", phy); 569 570 if (phy_info->rcomp_phy != -1) { 571 u32 grc_code = dev_priv->bxt_phy_grc; 572 573 grc_code = grc_code << GRC_CODE_FAST_SHIFT | 574 grc_code << GRC_CODE_SLOW_SHIFT | 575 grc_code; 576 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK | 577 GRC_CODE_NOM_MASK; 578 ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code, 579 "BXT_PORT_REF_DW6(%d)", phy); 580 581 mask = GRC_DIS | GRC_RDY_OVRD; 582 ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask, 583 "BXT_PORT_REF_DW8(%d)", phy); 584 } 585 586 return ok; 587 #undef _CHK 588 } 589 590 u8 591 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count) 592 { 593 switch (lane_count) { 594 case 1: 595 return 0; 596 case 2: 597 return BIT(2) | BIT(0); 598 case 4: 599 return BIT(3) | BIT(2) | BIT(0); 600 default: 601 MISSING_CASE(lane_count); 602 603 return 0; 604 } 605 } 606 607 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, 608 u8 lane_lat_optim_mask) 609 { 610 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 611 enum port port = encoder->port; 612 enum dpio_phy phy; 613 enum dpio_channel ch; 614 int lane; 615 616 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); 617 618 for (lane = 0; lane < 4; lane++) { 619 u32 val = intel_de_read(dev_priv, 620 BXT_PORT_TX_DW14_LN(phy, ch, lane)); 621 622 /* 623 * Note that on CHV this flag is called UPAR, but has 624 * the same function. 625 */ 626 val &= ~LATENCY_OPTIM; 627 if (lane_lat_optim_mask & BIT(lane)) 628 val |= LATENCY_OPTIM; 629 630 intel_de_write(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane), 631 val); 632 } 633 } 634 635 u8 636 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder) 637 { 638 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 639 enum port port = encoder->port; 640 enum dpio_phy phy; 641 enum dpio_channel ch; 642 int lane; 643 u8 mask; 644 645 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); 646 647 mask = 0; 648 for (lane = 0; lane < 4; lane++) { 649 u32 val = intel_de_read(dev_priv, 650 BXT_PORT_TX_DW14_LN(phy, ch, lane)); 651 652 if (val & LATENCY_OPTIM) 653 mask |= BIT(lane); 654 } 655 656 return mask; 657 } 658 659 enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port) 660 { 661 switch (dig_port->base.port) { 662 default: 663 MISSING_CASE(dig_port->base.port); 664 fallthrough; 665 case PORT_B: 666 case PORT_D: 667 return DPIO_CH0; 668 case PORT_C: 669 return DPIO_CH1; 670 } 671 } 672 673 enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port) 674 { 675 switch (dig_port->base.port) { 676 default: 677 MISSING_CASE(dig_port->base.port); 678 fallthrough; 679 case PORT_B: 680 case PORT_C: 681 return DPIO_PHY0; 682 case PORT_D: 683 return DPIO_PHY1; 684 } 685 } 686 687 enum dpio_channel vlv_pipe_to_channel(enum pipe pipe) 688 { 689 switch (pipe) { 690 default: 691 MISSING_CASE(pipe); 692 fallthrough; 693 case PIPE_A: 694 case PIPE_C: 695 return DPIO_CH0; 696 case PIPE_B: 697 return DPIO_CH1; 698 } 699 } 700 701 void chv_set_phy_signal_level(struct intel_encoder *encoder, 702 const struct intel_crtc_state *crtc_state, 703 u32 deemph_reg_value, u32 margin_reg_value, 704 bool uniq_trans_scale) 705 { 706 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 707 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 708 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 709 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 710 enum pipe pipe = crtc->pipe; 711 u32 val; 712 int i; 713 714 vlv_dpio_get(dev_priv); 715 716 /* Clear calc init */ 717 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 718 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 719 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 720 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 721 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 722 723 if (crtc_state->lane_count > 2) { 724 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 725 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 726 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 727 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 728 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 729 } 730 731 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); 732 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 733 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 734 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); 735 736 if (crtc_state->lane_count > 2) { 737 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); 738 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 739 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 740 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); 741 } 742 743 /* Program swing deemph */ 744 for (i = 0; i < crtc_state->lane_count; i++) { 745 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); 746 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 747 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; 748 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); 749 } 750 751 /* Program swing margin */ 752 for (i = 0; i < crtc_state->lane_count; i++) { 753 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 754 755 val &= ~DPIO_SWING_MARGIN000_MASK; 756 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; 757 758 /* 759 * Supposedly this value shouldn't matter when unique transition 760 * scale is disabled, but in fact it does matter. Let's just 761 * always program the same value and hope it's OK. 762 */ 763 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); 764 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; 765 766 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 767 } 768 769 /* 770 * The document said it needs to set bit 27 for ch0 and bit 26 771 * for ch1. Might be a typo in the doc. 772 * For now, for this unique transition scale selection, set bit 773 * 27 for ch0 and ch1. 774 */ 775 for (i = 0; i < crtc_state->lane_count; i++) { 776 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 777 if (uniq_trans_scale) 778 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; 779 else 780 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 781 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 782 } 783 784 /* Start swing calculation */ 785 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 786 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 787 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 788 789 if (crtc_state->lane_count > 2) { 790 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 791 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 792 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 793 } 794 795 vlv_dpio_put(dev_priv); 796 } 797 798 void chv_data_lane_soft_reset(struct intel_encoder *encoder, 799 const struct intel_crtc_state *crtc_state, 800 bool reset) 801 { 802 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 803 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); 804 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 805 enum pipe pipe = crtc->pipe; 806 u32 val; 807 808 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 809 if (reset) 810 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 811 else 812 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 813 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 814 815 if (crtc_state->lane_count > 2) { 816 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 817 if (reset) 818 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 819 else 820 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 821 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 822 } 823 824 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 825 val |= CHV_PCS_REQ_SOFTRESET_EN; 826 if (reset) 827 val &= ~DPIO_PCS_CLK_SOFT_RESET; 828 else 829 val |= DPIO_PCS_CLK_SOFT_RESET; 830 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 831 832 if (crtc_state->lane_count > 2) { 833 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 834 val |= CHV_PCS_REQ_SOFTRESET_EN; 835 if (reset) 836 val &= ~DPIO_PCS_CLK_SOFT_RESET; 837 else 838 val |= DPIO_PCS_CLK_SOFT_RESET; 839 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 840 } 841 } 842 843 void chv_phy_pre_pll_enable(struct intel_encoder *encoder, 844 const struct intel_crtc_state *crtc_state) 845 { 846 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 847 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 848 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 849 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 850 enum pipe pipe = crtc->pipe; 851 unsigned int lane_mask = 852 intel_dp_unused_lane_mask(crtc_state->lane_count); 853 u32 val; 854 855 /* 856 * Must trick the second common lane into life. 857 * Otherwise we can't even access the PLL. 858 */ 859 if (ch == DPIO_CH0 && pipe == PIPE_B) 860 dig_port->release_cl2_override = 861 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); 862 863 chv_phy_powergate_lanes(encoder, true, lane_mask); 864 865 vlv_dpio_get(dev_priv); 866 867 /* Assert data lane reset */ 868 chv_data_lane_soft_reset(encoder, crtc_state, true); 869 870 /* program left/right clock distribution */ 871 if (pipe != PIPE_B) { 872 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 873 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 874 if (ch == DPIO_CH0) 875 val |= CHV_BUFLEFTENA1_FORCE; 876 if (ch == DPIO_CH1) 877 val |= CHV_BUFRIGHTENA1_FORCE; 878 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 879 } else { 880 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 881 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 882 if (ch == DPIO_CH0) 883 val |= CHV_BUFLEFTENA2_FORCE; 884 if (ch == DPIO_CH1) 885 val |= CHV_BUFRIGHTENA2_FORCE; 886 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 887 } 888 889 /* program clock channel usage */ 890 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); 891 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 892 if (pipe != PIPE_B) 893 val &= ~CHV_PCS_USEDCLKCHANNEL; 894 else 895 val |= CHV_PCS_USEDCLKCHANNEL; 896 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); 897 898 if (crtc_state->lane_count > 2) { 899 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); 900 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 901 if (pipe != PIPE_B) 902 val &= ~CHV_PCS_USEDCLKCHANNEL; 903 else 904 val |= CHV_PCS_USEDCLKCHANNEL; 905 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); 906 } 907 908 /* 909 * This a a bit weird since generally CL 910 * matches the pipe, but here we need to 911 * pick the CL based on the port. 912 */ 913 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); 914 if (pipe != PIPE_B) 915 val &= ~CHV_CMN_USEDCLKCHANNEL; 916 else 917 val |= CHV_CMN_USEDCLKCHANNEL; 918 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); 919 920 vlv_dpio_put(dev_priv); 921 } 922 923 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, 924 const struct intel_crtc_state *crtc_state) 925 { 926 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 927 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 928 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 929 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 930 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 931 enum pipe pipe = crtc->pipe; 932 int data, i, stagger; 933 u32 val; 934 935 vlv_dpio_get(dev_priv); 936 937 /* allow hardware to manage TX FIFO reset source */ 938 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 939 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 940 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 941 942 if (crtc_state->lane_count > 2) { 943 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 944 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 945 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 946 } 947 948 /* Program Tx lane latency optimal setting*/ 949 for (i = 0; i < crtc_state->lane_count; i++) { 950 /* Set the upar bit */ 951 if (crtc_state->lane_count == 1) 952 data = 0x0; 953 else 954 data = (i == 1) ? 0x0 : 0x1; 955 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), 956 data << DPIO_UPAR_SHIFT); 957 } 958 959 /* Data lane stagger programming */ 960 if (crtc_state->port_clock > 270000) 961 stagger = 0x18; 962 else if (crtc_state->port_clock > 135000) 963 stagger = 0xd; 964 else if (crtc_state->port_clock > 67500) 965 stagger = 0x7; 966 else if (crtc_state->port_clock > 33750) 967 stagger = 0x4; 968 else 969 stagger = 0x2; 970 971 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 972 val |= DPIO_TX2_STAGGER_MASK(0x1f); 973 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 974 975 if (crtc_state->lane_count > 2) { 976 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 977 val |= DPIO_TX2_STAGGER_MASK(0x1f); 978 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 979 } 980 981 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), 982 DPIO_LANESTAGGER_STRAP(stagger) | 983 DPIO_LANESTAGGER_STRAP_OVRD | 984 DPIO_TX1_STAGGER_MASK(0x1f) | 985 DPIO_TX1_STAGGER_MULT(6) | 986 DPIO_TX2_STAGGER_MULT(0)); 987 988 if (crtc_state->lane_count > 2) { 989 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), 990 DPIO_LANESTAGGER_STRAP(stagger) | 991 DPIO_LANESTAGGER_STRAP_OVRD | 992 DPIO_TX1_STAGGER_MASK(0x1f) | 993 DPIO_TX1_STAGGER_MULT(7) | 994 DPIO_TX2_STAGGER_MULT(5)); 995 } 996 997 /* Deassert data lane reset */ 998 chv_data_lane_soft_reset(encoder, crtc_state, false); 999 1000 vlv_dpio_put(dev_priv); 1001 } 1002 1003 void chv_phy_release_cl2_override(struct intel_encoder *encoder) 1004 { 1005 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1006 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1007 1008 if (dig_port->release_cl2_override) { 1009 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); 1010 dig_port->release_cl2_override = false; 1011 } 1012 } 1013 1014 void chv_phy_post_pll_disable(struct intel_encoder *encoder, 1015 const struct intel_crtc_state *old_crtc_state) 1016 { 1017 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1018 enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe; 1019 u32 val; 1020 1021 vlv_dpio_get(dev_priv); 1022 1023 /* disable left/right clock distribution */ 1024 if (pipe != PIPE_B) { 1025 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 1026 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 1027 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 1028 } else { 1029 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 1030 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 1031 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 1032 } 1033 1034 vlv_dpio_put(dev_priv); 1035 1036 /* 1037 * Leave the power down bit cleared for at least one 1038 * lane so that chv_powergate_phy_ch() will power 1039 * on something when the channel is otherwise unused. 1040 * When the port is off and the override is removed 1041 * the lanes power down anyway, so otherwise it doesn't 1042 * really matter what the state of power down bits is 1043 * after this. 1044 */ 1045 chv_phy_powergate_lanes(encoder, false, 0x0); 1046 } 1047 1048 void vlv_set_phy_signal_level(struct intel_encoder *encoder, 1049 const struct intel_crtc_state *crtc_state, 1050 u32 demph_reg_value, u32 preemph_reg_value, 1051 u32 uniqtranscale_reg_value, u32 tx3_demph) 1052 { 1053 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1054 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1055 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1056 enum dpio_channel port = vlv_dig_port_to_channel(dig_port); 1057 enum pipe pipe = crtc->pipe; 1058 1059 vlv_dpio_get(dev_priv); 1060 1061 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); 1062 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); 1063 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 1064 uniqtranscale_reg_value); 1065 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); 1066 1067 if (tx3_demph) 1068 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph); 1069 1070 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 1071 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); 1072 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 1073 1074 vlv_dpio_put(dev_priv); 1075 } 1076 1077 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, 1078 const struct intel_crtc_state *crtc_state) 1079 { 1080 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1081 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1082 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1083 enum dpio_channel port = vlv_dig_port_to_channel(dig_port); 1084 enum pipe pipe = crtc->pipe; 1085 1086 /* Program Tx lane resets to default */ 1087 vlv_dpio_get(dev_priv); 1088 1089 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 1090 DPIO_PCS_TX_LANE2_RESET | 1091 DPIO_PCS_TX_LANE1_RESET); 1092 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 1093 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1094 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1095 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1096 DPIO_PCS_CLK_SOFT_RESET); 1097 1098 /* Fix up inter-pair skew failure */ 1099 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 1100 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 1101 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 1102 1103 vlv_dpio_put(dev_priv); 1104 } 1105 1106 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, 1107 const struct intel_crtc_state *crtc_state) 1108 { 1109 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1110 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1111 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1112 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1113 enum dpio_channel port = vlv_dig_port_to_channel(dig_port); 1114 enum pipe pipe = crtc->pipe; 1115 u32 val; 1116 1117 vlv_dpio_get(dev_priv); 1118 1119 /* Enable clock channels for this port */ 1120 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 1121 val = 0; 1122 if (pipe) 1123 val |= (1<<21); 1124 else 1125 val &= ~(1<<21); 1126 val |= 0x001000c4; 1127 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 1128 1129 /* Program lane clock */ 1130 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 1131 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 1132 1133 vlv_dpio_put(dev_priv); 1134 } 1135 1136 void vlv_phy_reset_lanes(struct intel_encoder *encoder, 1137 const struct intel_crtc_state *old_crtc_state) 1138 { 1139 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1140 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1141 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1142 enum dpio_channel port = vlv_dig_port_to_channel(dig_port); 1143 enum pipe pipe = crtc->pipe; 1144 1145 vlv_dpio_get(dev_priv); 1146 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); 1147 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); 1148 vlv_dpio_put(dev_priv); 1149 } 1150