1 /* 2 * Copyright © 2014-2016 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 21 * DEALINGS IN THE SOFTWARE. 22 */ 23 24 #include "display/intel_dp.h" 25 26 #include "intel_display_types.h" 27 #include "intel_dpio_phy.h" 28 #include "intel_sideband.h" 29 30 /** 31 * DOC: DPIO 32 * 33 * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI 34 * ports. DPIO is the name given to such a display PHY. These PHYs 35 * don't follow the standard programming model using direct MMIO 36 * registers, and instead their registers must be accessed trough IOSF 37 * sideband. VLV has one such PHY for driving ports B and C, and CHV 38 * adds another PHY for driving port D. Each PHY responds to specific 39 * IOSF-SB port. 40 * 41 * Each display PHY is made up of one or two channels. Each channel 42 * houses a common lane part which contains the PLL and other common 43 * logic. CH0 common lane also contains the IOSF-SB logic for the 44 * Common Register Interface (CRI) ie. the DPIO registers. CRI clock 45 * must be running when any DPIO registers are accessed. 46 * 47 * In addition to having their own registers, the PHYs are also 48 * controlled through some dedicated signals from the display 49 * controller. These include PLL reference clock enable, PLL enable, 50 * and CRI clock selection, for example. 51 * 52 * Eeach channel also has two splines (also called data lanes), and 53 * each spline is made up of one Physical Access Coding Sub-Layer 54 * (PCS) block and two TX lanes. So each channel has two PCS blocks 55 * and four TX lanes. The TX lanes are used as DP lanes or TMDS 56 * data/clock pairs depending on the output type. 57 * 58 * Additionally the PHY also contains an AUX lane with AUX blocks 59 * for each channel. This is used for DP AUX communication, but 60 * this fact isn't really relevant for the driver since AUX is 61 * controlled from the display controller side. No DPIO registers 62 * need to be accessed during AUX communication, 63 * 64 * Generally on VLV/CHV the common lane corresponds to the pipe and 65 * the spline (PCS/TX) corresponds to the port. 66 * 67 * For dual channel PHY (VLV/CHV): 68 * 69 * pipe A == CMN/PLL/REF CH0 70 * 71 * pipe B == CMN/PLL/REF CH1 72 * 73 * port B == PCS/TX CH0 74 * 75 * port C == PCS/TX CH1 76 * 77 * This is especially important when we cross the streams 78 * ie. drive port B with pipe B, or port C with pipe A. 79 * 80 * For single channel PHY (CHV): 81 * 82 * pipe C == CMN/PLL/REF CH0 83 * 84 * port D == PCS/TX CH0 85 * 86 * On BXT the entire PHY channel corresponds to the port. That means 87 * the PLL is also now associated with the port rather than the pipe, 88 * and so the clock needs to be routed to the appropriate transcoder. 89 * Port A PLL is directly connected to transcoder EDP and port B/C 90 * PLLs can be routed to any transcoder A/B/C. 91 * 92 * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is 93 * digital port D (CHV) or port A (BXT). :: 94 * 95 * 96 * Dual channel PHY (VLV/CHV/BXT) 97 * --------------------------------- 98 * | CH0 | CH1 | 99 * | CMN/PLL/REF | CMN/PLL/REF | 100 * |---------------|---------------| Display PHY 101 * | PCS01 | PCS23 | PCS01 | PCS23 | 102 * |-------|-------|-------|-------| 103 * |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3| 104 * --------------------------------- 105 * | DDI0 | DDI1 | DP/HDMI ports 106 * --------------------------------- 107 * 108 * Single channel PHY (CHV/BXT) 109 * ----------------- 110 * | CH0 | 111 * | CMN/PLL/REF | 112 * |---------------| Display PHY 113 * | PCS01 | PCS23 | 114 * |-------|-------| 115 * |TX0|TX1|TX2|TX3| 116 * ----------------- 117 * | DDI2 | DP/HDMI port 118 * ----------------- 119 */ 120 121 /** 122 * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy 123 */ 124 struct bxt_ddi_phy_info { 125 /** 126 * @dual_channel: true if this phy has a second channel. 127 */ 128 bool dual_channel; 129 130 /** 131 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor. 132 * Otherwise the GRC value will be copied from the phy indicated by 133 * this field. 134 */ 135 enum dpio_phy rcomp_phy; 136 137 /** 138 * @reset_delay: delay in us to wait before setting the common reset 139 * bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy. 140 */ 141 int reset_delay; 142 143 /** 144 * @pwron_mask: Mask with the appropriate bit set that would cause the 145 * punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON. 146 */ 147 u32 pwron_mask; 148 149 /** 150 * @channel: struct containing per channel information. 151 */ 152 struct { 153 /** 154 * @channel.port: which port maps to this channel. 155 */ 156 enum port port; 157 } channel[2]; 158 }; 159 160 static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = { 161 [DPIO_PHY0] = { 162 .dual_channel = true, 163 .rcomp_phy = DPIO_PHY1, 164 .pwron_mask = BIT(0), 165 166 .channel = { 167 [DPIO_CH0] = { .port = PORT_B }, 168 [DPIO_CH1] = { .port = PORT_C }, 169 } 170 }, 171 [DPIO_PHY1] = { 172 .dual_channel = false, 173 .rcomp_phy = -1, 174 .pwron_mask = BIT(1), 175 176 .channel = { 177 [DPIO_CH0] = { .port = PORT_A }, 178 } 179 }, 180 }; 181 182 static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = { 183 [DPIO_PHY0] = { 184 .dual_channel = false, 185 .rcomp_phy = DPIO_PHY1, 186 .pwron_mask = BIT(0), 187 .reset_delay = 20, 188 189 .channel = { 190 [DPIO_CH0] = { .port = PORT_B }, 191 } 192 }, 193 [DPIO_PHY1] = { 194 .dual_channel = false, 195 .rcomp_phy = -1, 196 .pwron_mask = BIT(3), 197 .reset_delay = 20, 198 199 .channel = { 200 [DPIO_CH0] = { .port = PORT_A }, 201 } 202 }, 203 [DPIO_PHY2] = { 204 .dual_channel = false, 205 .rcomp_phy = DPIO_PHY1, 206 .pwron_mask = BIT(1), 207 .reset_delay = 20, 208 209 .channel = { 210 [DPIO_CH0] = { .port = PORT_C }, 211 } 212 }, 213 }; 214 215 static const struct bxt_ddi_phy_info * 216 bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count) 217 { 218 if (IS_GEMINILAKE(dev_priv)) { 219 *count = ARRAY_SIZE(glk_ddi_phy_info); 220 return glk_ddi_phy_info; 221 } else { 222 *count = ARRAY_SIZE(bxt_ddi_phy_info); 223 return bxt_ddi_phy_info; 224 } 225 } 226 227 static const struct bxt_ddi_phy_info * 228 bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy) 229 { 230 int count; 231 const struct bxt_ddi_phy_info *phy_list = 232 bxt_get_phy_list(dev_priv, &count); 233 234 return &phy_list[phy]; 235 } 236 237 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port, 238 enum dpio_phy *phy, enum dpio_channel *ch) 239 { 240 const struct bxt_ddi_phy_info *phy_info, *phys; 241 int i, count; 242 243 phys = bxt_get_phy_list(dev_priv, &count); 244 245 for (i = 0; i < count; i++) { 246 phy_info = &phys[i]; 247 248 if (port == phy_info->channel[DPIO_CH0].port) { 249 *phy = i; 250 *ch = DPIO_CH0; 251 return; 252 } 253 254 if (phy_info->dual_channel && 255 port == phy_info->channel[DPIO_CH1].port) { 256 *phy = i; 257 *ch = DPIO_CH1; 258 return; 259 } 260 } 261 262 drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c", 263 port_name(port)); 264 *phy = DPIO_PHY0; 265 *ch = DPIO_CH0; 266 } 267 268 void bxt_ddi_phy_set_signal_level(struct drm_i915_private *dev_priv, 269 enum port port, u32 margin, u32 scale, 270 u32 enable, u32 deemphasis) 271 { 272 u32 val; 273 enum dpio_phy phy; 274 enum dpio_channel ch; 275 276 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); 277 278 /* 279 * While we write to the group register to program all lanes at once we 280 * can read only lane registers and we pick lanes 0/1 for that. 281 */ 282 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); 283 val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT); 284 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val); 285 286 val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch)); 287 val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE); 288 val |= margin << MARGIN_000_SHIFT | scale << UNIQ_TRANS_SCALE_SHIFT; 289 intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val); 290 291 val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch)); 292 val &= ~SCALE_DCOMP_METHOD; 293 if (enable) 294 val |= SCALE_DCOMP_METHOD; 295 296 if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD)) 297 drm_err(&dev_priv->drm, 298 "Disabled scaling while ouniqetrangenmethod was set"); 299 300 intel_de_write(dev_priv, BXT_PORT_TX_DW3_GRP(phy, ch), val); 301 302 val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch)); 303 val &= ~DE_EMPHASIS; 304 val |= deemphasis << DEEMPH_SHIFT; 305 intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val); 306 307 val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch)); 308 val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT; 309 intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val); 310 } 311 312 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv, 313 enum dpio_phy phy) 314 { 315 const struct bxt_ddi_phy_info *phy_info; 316 317 phy_info = bxt_get_phy_info(dev_priv, phy); 318 319 if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask)) 320 return false; 321 322 if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) & 323 (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) { 324 drm_dbg(&dev_priv->drm, 325 "DDI PHY %d powered, but power hasn't settled\n", phy); 326 327 return false; 328 } 329 330 if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) { 331 drm_dbg(&dev_priv->drm, 332 "DDI PHY %d powered, but still in reset\n", phy); 333 334 return false; 335 } 336 337 return true; 338 } 339 340 static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy) 341 { 342 u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy)); 343 344 return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT; 345 } 346 347 static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv, 348 enum dpio_phy phy) 349 { 350 if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy), 351 GRC_DONE, 10)) 352 drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n", 353 phy); 354 } 355 356 static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv, 357 enum dpio_phy phy) 358 { 359 const struct bxt_ddi_phy_info *phy_info; 360 u32 val; 361 362 phy_info = bxt_get_phy_info(dev_priv, phy); 363 364 if (bxt_ddi_phy_is_enabled(dev_priv, phy)) { 365 /* Still read out the GRC value for state verification */ 366 if (phy_info->rcomp_phy != -1) 367 dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, phy); 368 369 if (bxt_ddi_phy_verify_state(dev_priv, phy)) { 370 drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, " 371 "won't reprogram it\n", phy); 372 return; 373 } 374 375 drm_dbg(&dev_priv->drm, 376 "DDI PHY %d enabled with invalid state, " 377 "force reprogramming it\n", phy); 378 } 379 380 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); 381 val |= phy_info->pwron_mask; 382 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val); 383 384 /* 385 * The PHY registers start out inaccessible and respond to reads with 386 * all 1s. Eventually they become accessible as they power up, then 387 * the reserved bit will give the default 0. Poll on the reserved bit 388 * becoming 0 to find when the PHY is accessible. 389 * The flag should get set in 100us according to the HW team, but 390 * use 1ms due to occasional timeouts observed with that. 391 */ 392 if (intel_wait_for_register_fw(&dev_priv->uncore, 393 BXT_PORT_CL1CM_DW0(phy), 394 PHY_RESERVED | PHY_POWER_GOOD, 395 PHY_POWER_GOOD, 396 1)) 397 drm_err(&dev_priv->drm, "timeout during PHY%d power on\n", 398 phy); 399 400 /* Program PLL Rcomp code offset */ 401 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW9(phy)); 402 val &= ~IREF0RC_OFFSET_MASK; 403 val |= 0xE4 << IREF0RC_OFFSET_SHIFT; 404 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW9(phy), val); 405 406 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW10(phy)); 407 val &= ~IREF1RC_OFFSET_MASK; 408 val |= 0xE4 << IREF1RC_OFFSET_SHIFT; 409 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW10(phy), val); 410 411 /* Program power gating */ 412 val = intel_de_read(dev_priv, BXT_PORT_CL1CM_DW28(phy)); 413 val |= OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | 414 SUS_CLK_CONFIG; 415 intel_de_write(dev_priv, BXT_PORT_CL1CM_DW28(phy), val); 416 417 if (phy_info->dual_channel) { 418 val = intel_de_read(dev_priv, BXT_PORT_CL2CM_DW6(phy)); 419 val |= DW6_OLDO_DYN_PWR_DOWN_EN; 420 intel_de_write(dev_priv, BXT_PORT_CL2CM_DW6(phy), val); 421 } 422 423 if (phy_info->rcomp_phy != -1) { 424 u32 grc_code; 425 426 bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy); 427 428 /* 429 * PHY0 isn't connected to an RCOMP resistor so copy over 430 * the corresponding calibrated value from PHY1, and disable 431 * the automatic calibration on PHY0. 432 */ 433 val = dev_priv->bxt_phy_grc = bxt_get_grc(dev_priv, 434 phy_info->rcomp_phy); 435 grc_code = val << GRC_CODE_FAST_SHIFT | 436 val << GRC_CODE_SLOW_SHIFT | 437 val; 438 intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code); 439 440 val = intel_de_read(dev_priv, BXT_PORT_REF_DW8(phy)); 441 val |= GRC_DIS | GRC_RDY_OVRD; 442 intel_de_write(dev_priv, BXT_PORT_REF_DW8(phy), val); 443 } 444 445 if (phy_info->reset_delay) 446 udelay(phy_info->reset_delay); 447 448 val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)); 449 val |= COMMON_RESET_DIS; 450 intel_de_write(dev_priv, BXT_PHY_CTL_FAMILY(phy), val); 451 } 452 453 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy) 454 { 455 const struct bxt_ddi_phy_info *phy_info; 456 u32 val; 457 458 phy_info = bxt_get_phy_info(dev_priv, phy); 459 460 val = intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)); 461 val &= ~COMMON_RESET_DIS; 462 intel_de_write(dev_priv, BXT_PHY_CTL_FAMILY(phy), val); 463 464 val = intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON); 465 val &= ~phy_info->pwron_mask; 466 intel_de_write(dev_priv, BXT_P_CR_GT_DISP_PWRON, val); 467 } 468 469 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy) 470 { 471 const struct bxt_ddi_phy_info *phy_info = 472 bxt_get_phy_info(dev_priv, phy); 473 enum dpio_phy rcomp_phy = phy_info->rcomp_phy; 474 bool was_enabled; 475 476 lockdep_assert_held(&dev_priv->power_domains.lock); 477 478 was_enabled = true; 479 if (rcomp_phy != -1) 480 was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy); 481 482 /* 483 * We need to copy the GRC calibration value from rcomp_phy, 484 * so make sure it's powered up. 485 */ 486 if (!was_enabled) 487 _bxt_ddi_phy_init(dev_priv, rcomp_phy); 488 489 _bxt_ddi_phy_init(dev_priv, phy); 490 491 if (!was_enabled) 492 bxt_ddi_phy_uninit(dev_priv, rcomp_phy); 493 } 494 495 static bool __printf(6, 7) 496 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy, 497 i915_reg_t reg, u32 mask, u32 expected, 498 const char *reg_fmt, ...) 499 { 500 struct va_format vaf; 501 va_list args; 502 u32 val; 503 504 val = intel_de_read(dev_priv, reg); 505 if ((val & mask) == expected) 506 return true; 507 508 va_start(args, reg_fmt); 509 vaf.fmt = reg_fmt; 510 vaf.va = &args; 511 512 drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: " 513 "current %08x, expected %08x (mask %08x)\n", 514 phy, &vaf, reg.reg, val, (val & ~mask) | expected, 515 mask); 516 517 va_end(args); 518 519 return false; 520 } 521 522 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv, 523 enum dpio_phy phy) 524 { 525 const struct bxt_ddi_phy_info *phy_info; 526 u32 mask; 527 bool ok; 528 529 phy_info = bxt_get_phy_info(dev_priv, phy); 530 531 #define _CHK(reg, mask, exp, fmt, ...) \ 532 __phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt, \ 533 ## __VA_ARGS__) 534 535 if (!bxt_ddi_phy_is_enabled(dev_priv, phy)) 536 return false; 537 538 ok = true; 539 540 /* PLL Rcomp code offset */ 541 ok &= _CHK(BXT_PORT_CL1CM_DW9(phy), 542 IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT, 543 "BXT_PORT_CL1CM_DW9(%d)", phy); 544 ok &= _CHK(BXT_PORT_CL1CM_DW10(phy), 545 IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT, 546 "BXT_PORT_CL1CM_DW10(%d)", phy); 547 548 /* Power gating */ 549 mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG; 550 ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask, 551 "BXT_PORT_CL1CM_DW28(%d)", phy); 552 553 if (phy_info->dual_channel) 554 ok &= _CHK(BXT_PORT_CL2CM_DW6(phy), 555 DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN, 556 "BXT_PORT_CL2CM_DW6(%d)", phy); 557 558 if (phy_info->rcomp_phy != -1) { 559 u32 grc_code = dev_priv->bxt_phy_grc; 560 561 grc_code = grc_code << GRC_CODE_FAST_SHIFT | 562 grc_code << GRC_CODE_SLOW_SHIFT | 563 grc_code; 564 mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK | 565 GRC_CODE_NOM_MASK; 566 ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code, 567 "BXT_PORT_REF_DW6(%d)", phy); 568 569 mask = GRC_DIS | GRC_RDY_OVRD; 570 ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask, 571 "BXT_PORT_REF_DW8(%d)", phy); 572 } 573 574 return ok; 575 #undef _CHK 576 } 577 578 u8 579 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count) 580 { 581 switch (lane_count) { 582 case 1: 583 return 0; 584 case 2: 585 return BIT(2) | BIT(0); 586 case 4: 587 return BIT(3) | BIT(2) | BIT(0); 588 default: 589 MISSING_CASE(lane_count); 590 591 return 0; 592 } 593 } 594 595 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder, 596 u8 lane_lat_optim_mask) 597 { 598 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 599 enum port port = encoder->port; 600 enum dpio_phy phy; 601 enum dpio_channel ch; 602 int lane; 603 604 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); 605 606 for (lane = 0; lane < 4; lane++) { 607 u32 val = intel_de_read(dev_priv, 608 BXT_PORT_TX_DW14_LN(phy, ch, lane)); 609 610 /* 611 * Note that on CHV this flag is called UPAR, but has 612 * the same function. 613 */ 614 val &= ~LATENCY_OPTIM; 615 if (lane_lat_optim_mask & BIT(lane)) 616 val |= LATENCY_OPTIM; 617 618 intel_de_write(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane), 619 val); 620 } 621 } 622 623 u8 624 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder) 625 { 626 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 627 enum port port = encoder->port; 628 enum dpio_phy phy; 629 enum dpio_channel ch; 630 int lane; 631 u8 mask; 632 633 bxt_port_to_phy_channel(dev_priv, port, &phy, &ch); 634 635 mask = 0; 636 for (lane = 0; lane < 4; lane++) { 637 u32 val = intel_de_read(dev_priv, 638 BXT_PORT_TX_DW14_LN(phy, ch, lane)); 639 640 if (val & LATENCY_OPTIM) 641 mask |= BIT(lane); 642 } 643 644 return mask; 645 } 646 647 void chv_set_phy_signal_level(struct intel_encoder *encoder, 648 const struct intel_crtc_state *crtc_state, 649 u32 deemph_reg_value, u32 margin_reg_value, 650 bool uniq_trans_scale) 651 { 652 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 653 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 654 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 655 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 656 enum pipe pipe = crtc->pipe; 657 u32 val; 658 int i; 659 660 vlv_dpio_get(dev_priv); 661 662 /* Clear calc init */ 663 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 664 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 665 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 666 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 667 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 668 669 if (crtc_state->lane_count > 2) { 670 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 671 val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3); 672 val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK); 673 val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5; 674 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 675 } 676 677 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); 678 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 679 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 680 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); 681 682 if (crtc_state->lane_count > 2) { 683 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); 684 val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK); 685 val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000; 686 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); 687 } 688 689 /* Program swing deemph */ 690 for (i = 0; i < crtc_state->lane_count; i++) { 691 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); 692 val &= ~DPIO_SWING_DEEMPH9P5_MASK; 693 val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT; 694 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val); 695 } 696 697 /* Program swing margin */ 698 for (i = 0; i < crtc_state->lane_count; i++) { 699 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i)); 700 701 val &= ~DPIO_SWING_MARGIN000_MASK; 702 val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT; 703 704 /* 705 * Supposedly this value shouldn't matter when unique transition 706 * scale is disabled, but in fact it does matter. Let's just 707 * always program the same value and hope it's OK. 708 */ 709 val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT); 710 val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT; 711 712 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val); 713 } 714 715 /* 716 * The document said it needs to set bit 27 for ch0 and bit 26 717 * for ch1. Might be a typo in the doc. 718 * For now, for this unique transition scale selection, set bit 719 * 27 for ch0 and ch1. 720 */ 721 for (i = 0; i < crtc_state->lane_count; i++) { 722 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i)); 723 if (uniq_trans_scale) 724 val |= DPIO_TX_UNIQ_TRANS_SCALE_EN; 725 else 726 val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN; 727 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val); 728 } 729 730 /* Start swing calculation */ 731 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); 732 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 733 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); 734 735 if (crtc_state->lane_count > 2) { 736 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); 737 val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3; 738 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); 739 } 740 741 vlv_dpio_put(dev_priv); 742 } 743 744 void chv_data_lane_soft_reset(struct intel_encoder *encoder, 745 const struct intel_crtc_state *crtc_state, 746 bool reset) 747 { 748 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 749 enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder)); 750 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 751 enum pipe pipe = crtc->pipe; 752 u32 val; 753 754 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch)); 755 if (reset) 756 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 757 else 758 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 759 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val); 760 761 if (crtc_state->lane_count > 2) { 762 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch)); 763 if (reset) 764 val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET); 765 else 766 val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET; 767 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val); 768 } 769 770 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch)); 771 val |= CHV_PCS_REQ_SOFTRESET_EN; 772 if (reset) 773 val &= ~DPIO_PCS_CLK_SOFT_RESET; 774 else 775 val |= DPIO_PCS_CLK_SOFT_RESET; 776 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val); 777 778 if (crtc_state->lane_count > 2) { 779 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch)); 780 val |= CHV_PCS_REQ_SOFTRESET_EN; 781 if (reset) 782 val &= ~DPIO_PCS_CLK_SOFT_RESET; 783 else 784 val |= DPIO_PCS_CLK_SOFT_RESET; 785 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val); 786 } 787 } 788 789 void chv_phy_pre_pll_enable(struct intel_encoder *encoder, 790 const struct intel_crtc_state *crtc_state) 791 { 792 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 793 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 794 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 795 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 796 enum pipe pipe = crtc->pipe; 797 unsigned int lane_mask = 798 intel_dp_unused_lane_mask(crtc_state->lane_count); 799 u32 val; 800 801 /* 802 * Must trick the second common lane into life. 803 * Otherwise we can't even access the PLL. 804 */ 805 if (ch == DPIO_CH0 && pipe == PIPE_B) 806 dig_port->release_cl2_override = 807 !chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true); 808 809 chv_phy_powergate_lanes(encoder, true, lane_mask); 810 811 vlv_dpio_get(dev_priv); 812 813 /* Assert data lane reset */ 814 chv_data_lane_soft_reset(encoder, crtc_state, true); 815 816 /* program left/right clock distribution */ 817 if (pipe != PIPE_B) { 818 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 819 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 820 if (ch == DPIO_CH0) 821 val |= CHV_BUFLEFTENA1_FORCE; 822 if (ch == DPIO_CH1) 823 val |= CHV_BUFRIGHTENA1_FORCE; 824 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 825 } else { 826 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 827 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 828 if (ch == DPIO_CH0) 829 val |= CHV_BUFLEFTENA2_FORCE; 830 if (ch == DPIO_CH1) 831 val |= CHV_BUFRIGHTENA2_FORCE; 832 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 833 } 834 835 /* program clock channel usage */ 836 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch)); 837 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 838 if (pipe != PIPE_B) 839 val &= ~CHV_PCS_USEDCLKCHANNEL; 840 else 841 val |= CHV_PCS_USEDCLKCHANNEL; 842 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val); 843 844 if (crtc_state->lane_count > 2) { 845 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch)); 846 val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE; 847 if (pipe != PIPE_B) 848 val &= ~CHV_PCS_USEDCLKCHANNEL; 849 else 850 val |= CHV_PCS_USEDCLKCHANNEL; 851 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val); 852 } 853 854 /* 855 * This a a bit weird since generally CL 856 * matches the pipe, but here we need to 857 * pick the CL based on the port. 858 */ 859 val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch)); 860 if (pipe != PIPE_B) 861 val &= ~CHV_CMN_USEDCLKCHANNEL; 862 else 863 val |= CHV_CMN_USEDCLKCHANNEL; 864 vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val); 865 866 vlv_dpio_put(dev_priv); 867 } 868 869 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder, 870 const struct intel_crtc_state *crtc_state) 871 { 872 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 873 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 874 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 875 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 876 enum dpio_channel ch = vlv_dig_port_to_channel(dig_port); 877 enum pipe pipe = crtc->pipe; 878 int data, i, stagger; 879 u32 val; 880 881 vlv_dpio_get(dev_priv); 882 883 /* allow hardware to manage TX FIFO reset source */ 884 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 885 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 886 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 887 888 if (crtc_state->lane_count > 2) { 889 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 890 val &= ~DPIO_LANEDESKEW_STRAP_OVRD; 891 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 892 } 893 894 /* Program Tx lane latency optimal setting*/ 895 for (i = 0; i < crtc_state->lane_count; i++) { 896 /* Set the upar bit */ 897 if (crtc_state->lane_count == 1) 898 data = 0x0; 899 else 900 data = (i == 1) ? 0x0 : 0x1; 901 vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i), 902 data << DPIO_UPAR_SHIFT); 903 } 904 905 /* Data lane stagger programming */ 906 if (crtc_state->port_clock > 270000) 907 stagger = 0x18; 908 else if (crtc_state->port_clock > 135000) 909 stagger = 0xd; 910 else if (crtc_state->port_clock > 67500) 911 stagger = 0x7; 912 else if (crtc_state->port_clock > 33750) 913 stagger = 0x4; 914 else 915 stagger = 0x2; 916 917 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch)); 918 val |= DPIO_TX2_STAGGER_MASK(0x1f); 919 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val); 920 921 if (crtc_state->lane_count > 2) { 922 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch)); 923 val |= DPIO_TX2_STAGGER_MASK(0x1f); 924 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val); 925 } 926 927 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch), 928 DPIO_LANESTAGGER_STRAP(stagger) | 929 DPIO_LANESTAGGER_STRAP_OVRD | 930 DPIO_TX1_STAGGER_MASK(0x1f) | 931 DPIO_TX1_STAGGER_MULT(6) | 932 DPIO_TX2_STAGGER_MULT(0)); 933 934 if (crtc_state->lane_count > 2) { 935 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch), 936 DPIO_LANESTAGGER_STRAP(stagger) | 937 DPIO_LANESTAGGER_STRAP_OVRD | 938 DPIO_TX1_STAGGER_MASK(0x1f) | 939 DPIO_TX1_STAGGER_MULT(7) | 940 DPIO_TX2_STAGGER_MULT(5)); 941 } 942 943 /* Deassert data lane reset */ 944 chv_data_lane_soft_reset(encoder, crtc_state, false); 945 946 vlv_dpio_put(dev_priv); 947 } 948 949 void chv_phy_release_cl2_override(struct intel_encoder *encoder) 950 { 951 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 952 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 953 954 if (dig_port->release_cl2_override) { 955 chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false); 956 dig_port->release_cl2_override = false; 957 } 958 } 959 960 void chv_phy_post_pll_disable(struct intel_encoder *encoder, 961 const struct intel_crtc_state *old_crtc_state) 962 { 963 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 964 enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe; 965 u32 val; 966 967 vlv_dpio_get(dev_priv); 968 969 /* disable left/right clock distribution */ 970 if (pipe != PIPE_B) { 971 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0); 972 val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK); 973 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val); 974 } else { 975 val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1); 976 val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK); 977 vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val); 978 } 979 980 vlv_dpio_put(dev_priv); 981 982 /* 983 * Leave the power down bit cleared for at least one 984 * lane so that chv_powergate_phy_ch() will power 985 * on something when the channel is otherwise unused. 986 * When the port is off and the override is removed 987 * the lanes power down anyway, so otherwise it doesn't 988 * really matter what the state of power down bits is 989 * after this. 990 */ 991 chv_phy_powergate_lanes(encoder, false, 0x0); 992 } 993 994 void vlv_set_phy_signal_level(struct intel_encoder *encoder, 995 const struct intel_crtc_state *crtc_state, 996 u32 demph_reg_value, u32 preemph_reg_value, 997 u32 uniqtranscale_reg_value, u32 tx3_demph) 998 { 999 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1000 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1001 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1002 enum dpio_channel port = vlv_dig_port_to_channel(dig_port); 1003 enum pipe pipe = crtc->pipe; 1004 1005 vlv_dpio_get(dev_priv); 1006 1007 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000); 1008 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value); 1009 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port), 1010 uniqtranscale_reg_value); 1011 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040); 1012 1013 if (tx3_demph) 1014 vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph); 1015 1016 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000); 1017 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value); 1018 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN); 1019 1020 vlv_dpio_put(dev_priv); 1021 } 1022 1023 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder, 1024 const struct intel_crtc_state *crtc_state) 1025 { 1026 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1027 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1028 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1029 enum dpio_channel port = vlv_dig_port_to_channel(dig_port); 1030 enum pipe pipe = crtc->pipe; 1031 1032 /* Program Tx lane resets to default */ 1033 vlv_dpio_get(dev_priv); 1034 1035 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 1036 DPIO_PCS_TX_LANE2_RESET | 1037 DPIO_PCS_TX_LANE1_RESET); 1038 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 1039 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN | 1040 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN | 1041 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) | 1042 DPIO_PCS_CLK_SOFT_RESET); 1043 1044 /* Fix up inter-pair skew failure */ 1045 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00); 1046 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500); 1047 vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000); 1048 1049 vlv_dpio_put(dev_priv); 1050 } 1051 1052 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder, 1053 const struct intel_crtc_state *crtc_state) 1054 { 1055 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1056 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1057 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1058 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1059 enum dpio_channel port = vlv_dig_port_to_channel(dig_port); 1060 enum pipe pipe = crtc->pipe; 1061 u32 val; 1062 1063 vlv_dpio_get(dev_priv); 1064 1065 /* Enable clock channels for this port */ 1066 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port)); 1067 val = 0; 1068 if (pipe) 1069 val |= (1<<21); 1070 else 1071 val &= ~(1<<21); 1072 val |= 0x001000c4; 1073 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val); 1074 1075 /* Program lane clock */ 1076 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018); 1077 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888); 1078 1079 vlv_dpio_put(dev_priv); 1080 } 1081 1082 void vlv_phy_reset_lanes(struct intel_encoder *encoder, 1083 const struct intel_crtc_state *old_crtc_state) 1084 { 1085 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 1086 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1087 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc); 1088 enum dpio_channel port = vlv_dig_port_to_channel(dig_port); 1089 enum pipe pipe = crtc->pipe; 1090 1091 vlv_dpio_get(dev_priv); 1092 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000); 1093 vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060); 1094 vlv_dpio_put(dev_priv); 1095 } 1096