1 /*
2  * Copyright © 2014-2016 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
21  * DEALINGS IN THE SOFTWARE.
22  */
23 
24 #include "i915_reg.h"
25 #include "intel_ddi.h"
26 #include "intel_ddi_buf_trans.h"
27 #include "intel_de.h"
28 #include "intel_display_power_well.h"
29 #include "intel_display_types.h"
30 #include "intel_dp.h"
31 #include "intel_dpio_phy.h"
32 #include "vlv_sideband.h"
33 
34 /**
35  * DOC: DPIO
36  *
37  * VLV, CHV and BXT have slightly peculiar display PHYs for driving DP/HDMI
38  * ports. DPIO is the name given to such a display PHY. These PHYs
39  * don't follow the standard programming model using direct MMIO
40  * registers, and instead their registers must be accessed trough IOSF
41  * sideband. VLV has one such PHY for driving ports B and C, and CHV
42  * adds another PHY for driving port D. Each PHY responds to specific
43  * IOSF-SB port.
44  *
45  * Each display PHY is made up of one or two channels. Each channel
46  * houses a common lane part which contains the PLL and other common
47  * logic. CH0 common lane also contains the IOSF-SB logic for the
48  * Common Register Interface (CRI) ie. the DPIO registers. CRI clock
49  * must be running when any DPIO registers are accessed.
50  *
51  * In addition to having their own registers, the PHYs are also
52  * controlled through some dedicated signals from the display
53  * controller. These include PLL reference clock enable, PLL enable,
54  * and CRI clock selection, for example.
55  *
56  * Eeach channel also has two splines (also called data lanes), and
57  * each spline is made up of one Physical Access Coding Sub-Layer
58  * (PCS) block and two TX lanes. So each channel has two PCS blocks
59  * and four TX lanes. The TX lanes are used as DP lanes or TMDS
60  * data/clock pairs depending on the output type.
61  *
62  * Additionally the PHY also contains an AUX lane with AUX blocks
63  * for each channel. This is used for DP AUX communication, but
64  * this fact isn't really relevant for the driver since AUX is
65  * controlled from the display controller side. No DPIO registers
66  * need to be accessed during AUX communication,
67  *
68  * Generally on VLV/CHV the common lane corresponds to the pipe and
69  * the spline (PCS/TX) corresponds to the port.
70  *
71  * For dual channel PHY (VLV/CHV):
72  *
73  *  pipe A == CMN/PLL/REF CH0
74  *
75  *  pipe B == CMN/PLL/REF CH1
76  *
77  *  port B == PCS/TX CH0
78  *
79  *  port C == PCS/TX CH1
80  *
81  * This is especially important when we cross the streams
82  * ie. drive port B with pipe B, or port C with pipe A.
83  *
84  * For single channel PHY (CHV):
85  *
86  *  pipe C == CMN/PLL/REF CH0
87  *
88  *  port D == PCS/TX CH0
89  *
90  * On BXT the entire PHY channel corresponds to the port. That means
91  * the PLL is also now associated with the port rather than the pipe,
92  * and so the clock needs to be routed to the appropriate transcoder.
93  * Port A PLL is directly connected to transcoder EDP and port B/C
94  * PLLs can be routed to any transcoder A/B/C.
95  *
96  * Note: DDI0 is digital port B, DD1 is digital port C, and DDI2 is
97  * digital port D (CHV) or port A (BXT). ::
98  *
99  *
100  *     Dual channel PHY (VLV/CHV/BXT)
101  *     ---------------------------------
102  *     |      CH0      |      CH1      |
103  *     |  CMN/PLL/REF  |  CMN/PLL/REF  |
104  *     |---------------|---------------| Display PHY
105  *     | PCS01 | PCS23 | PCS01 | PCS23 |
106  *     |-------|-------|-------|-------|
107  *     |TX0|TX1|TX2|TX3|TX0|TX1|TX2|TX3|
108  *     ---------------------------------
109  *     |     DDI0      |     DDI1      | DP/HDMI ports
110  *     ---------------------------------
111  *
112  *     Single channel PHY (CHV/BXT)
113  *     -----------------
114  *     |      CH0      |
115  *     |  CMN/PLL/REF  |
116  *     |---------------| Display PHY
117  *     | PCS01 | PCS23 |
118  *     |-------|-------|
119  *     |TX0|TX1|TX2|TX3|
120  *     -----------------
121  *     |     DDI2      | DP/HDMI port
122  *     -----------------
123  */
124 
125 /**
126  * struct bxt_ddi_phy_info - Hold info for a broxton DDI phy
127  */
128 struct bxt_ddi_phy_info {
129 	/**
130 	 * @dual_channel: true if this phy has a second channel.
131 	 */
132 	bool dual_channel;
133 
134 	/**
135 	 * @rcomp_phy: If -1, indicates this phy has its own rcomp resistor.
136 	 * Otherwise the GRC value will be copied from the phy indicated by
137 	 * this field.
138 	 */
139 	enum dpio_phy rcomp_phy;
140 
141 	/**
142 	 * @reset_delay: delay in us to wait before setting the common reset
143 	 * bit in BXT_PHY_CTL_FAMILY, which effectively enables the phy.
144 	 */
145 	int reset_delay;
146 
147 	/**
148 	 * @pwron_mask: Mask with the appropriate bit set that would cause the
149 	 * punit to power this phy if written to BXT_P_CR_GT_DISP_PWRON.
150 	 */
151 	u32 pwron_mask;
152 
153 	/**
154 	 * @channel: struct containing per channel information.
155 	 */
156 	struct {
157 		/**
158 		 * @channel.port: which port maps to this channel.
159 		 */
160 		enum port port;
161 	} channel[2];
162 };
163 
164 static const struct bxt_ddi_phy_info bxt_ddi_phy_info[] = {
165 	[DPIO_PHY0] = {
166 		.dual_channel = true,
167 		.rcomp_phy = DPIO_PHY1,
168 		.pwron_mask = BIT(0),
169 
170 		.channel = {
171 			[DPIO_CH0] = { .port = PORT_B },
172 			[DPIO_CH1] = { .port = PORT_C },
173 		}
174 	},
175 	[DPIO_PHY1] = {
176 		.dual_channel = false,
177 		.rcomp_phy = -1,
178 		.pwron_mask = BIT(1),
179 
180 		.channel = {
181 			[DPIO_CH0] = { .port = PORT_A },
182 		}
183 	},
184 };
185 
186 static const struct bxt_ddi_phy_info glk_ddi_phy_info[] = {
187 	[DPIO_PHY0] = {
188 		.dual_channel = false,
189 		.rcomp_phy = DPIO_PHY1,
190 		.pwron_mask = BIT(0),
191 		.reset_delay = 20,
192 
193 		.channel = {
194 			[DPIO_CH0] = { .port = PORT_B },
195 		}
196 	},
197 	[DPIO_PHY1] = {
198 		.dual_channel = false,
199 		.rcomp_phy = -1,
200 		.pwron_mask = BIT(3),
201 		.reset_delay = 20,
202 
203 		.channel = {
204 			[DPIO_CH0] = { .port = PORT_A },
205 		}
206 	},
207 	[DPIO_PHY2] = {
208 		.dual_channel = false,
209 		.rcomp_phy = DPIO_PHY1,
210 		.pwron_mask = BIT(1),
211 		.reset_delay = 20,
212 
213 		.channel = {
214 			[DPIO_CH0] = { .port = PORT_C },
215 		}
216 	},
217 };
218 
219 static const struct bxt_ddi_phy_info *
220 bxt_get_phy_list(struct drm_i915_private *dev_priv, int *count)
221 {
222 	if (IS_GEMINILAKE(dev_priv)) {
223 		*count =  ARRAY_SIZE(glk_ddi_phy_info);
224 		return glk_ddi_phy_info;
225 	} else {
226 		*count =  ARRAY_SIZE(bxt_ddi_phy_info);
227 		return bxt_ddi_phy_info;
228 	}
229 }
230 
231 static const struct bxt_ddi_phy_info *
232 bxt_get_phy_info(struct drm_i915_private *dev_priv, enum dpio_phy phy)
233 {
234 	int count;
235 	const struct bxt_ddi_phy_info *phy_list =
236 		bxt_get_phy_list(dev_priv, &count);
237 
238 	return &phy_list[phy];
239 }
240 
241 void bxt_port_to_phy_channel(struct drm_i915_private *dev_priv, enum port port,
242 			     enum dpio_phy *phy, enum dpio_channel *ch)
243 {
244 	const struct bxt_ddi_phy_info *phy_info, *phys;
245 	int i, count;
246 
247 	phys = bxt_get_phy_list(dev_priv, &count);
248 
249 	for (i = 0; i < count; i++) {
250 		phy_info = &phys[i];
251 
252 		if (port == phy_info->channel[DPIO_CH0].port) {
253 			*phy = i;
254 			*ch = DPIO_CH0;
255 			return;
256 		}
257 
258 		if (phy_info->dual_channel &&
259 		    port == phy_info->channel[DPIO_CH1].port) {
260 			*phy = i;
261 			*ch = DPIO_CH1;
262 			return;
263 		}
264 	}
265 
266 	drm_WARN(&dev_priv->drm, 1, "PHY not found for PORT %c",
267 		 port_name(port));
268 	*phy = DPIO_PHY0;
269 	*ch = DPIO_CH0;
270 }
271 
272 void bxt_ddi_phy_set_signal_levels(struct intel_encoder *encoder,
273 				   const struct intel_crtc_state *crtc_state)
274 {
275 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
276 	int level = intel_ddi_level(encoder, crtc_state, 0);
277 	const struct intel_ddi_buf_trans *trans;
278 	enum dpio_channel ch;
279 	enum dpio_phy phy;
280 	int n_entries;
281 	u32 val;
282 
283 	trans = encoder->get_buf_trans(encoder, crtc_state, &n_entries);
284 	if (drm_WARN_ON_ONCE(&dev_priv->drm, !trans))
285 		return;
286 
287 	bxt_port_to_phy_channel(dev_priv, encoder->port, &phy, &ch);
288 
289 	/*
290 	 * While we write to the group register to program all lanes at once we
291 	 * can read only lane registers and we pick lanes 0/1 for that.
292 	 */
293 	val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch));
294 	val &= ~(TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT);
295 	intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val);
296 
297 	val = intel_de_read(dev_priv, BXT_PORT_TX_DW2_LN0(phy, ch));
298 	val &= ~(MARGIN_000 | UNIQ_TRANS_SCALE);
299 	val |= trans->entries[level].bxt.margin << MARGIN_000_SHIFT |
300 		trans->entries[level].bxt.scale << UNIQ_TRANS_SCALE_SHIFT;
301 	intel_de_write(dev_priv, BXT_PORT_TX_DW2_GRP(phy, ch), val);
302 
303 	val = intel_de_read(dev_priv, BXT_PORT_TX_DW3_LN0(phy, ch));
304 	val &= ~SCALE_DCOMP_METHOD;
305 	if (trans->entries[level].bxt.enable)
306 		val |= SCALE_DCOMP_METHOD;
307 
308 	if ((val & UNIQUE_TRANGE_EN_METHOD) && !(val & SCALE_DCOMP_METHOD))
309 		drm_err(&dev_priv->drm,
310 			"Disabled scaling while ouniqetrangenmethod was set");
311 
312 	intel_de_write(dev_priv, BXT_PORT_TX_DW3_GRP(phy, ch), val);
313 
314 	val = intel_de_read(dev_priv, BXT_PORT_TX_DW4_LN0(phy, ch));
315 	val &= ~DE_EMPHASIS;
316 	val |= trans->entries[level].bxt.deemphasis << DEEMPH_SHIFT;
317 	intel_de_write(dev_priv, BXT_PORT_TX_DW4_GRP(phy, ch), val);
318 
319 	val = intel_de_read(dev_priv, BXT_PORT_PCS_DW10_LN01(phy, ch));
320 	val |= TX2_SWING_CALC_INIT | TX1_SWING_CALC_INIT;
321 	intel_de_write(dev_priv, BXT_PORT_PCS_DW10_GRP(phy, ch), val);
322 }
323 
324 bool bxt_ddi_phy_is_enabled(struct drm_i915_private *dev_priv,
325 			    enum dpio_phy phy)
326 {
327 	const struct bxt_ddi_phy_info *phy_info;
328 
329 	phy_info = bxt_get_phy_info(dev_priv, phy);
330 
331 	if (!(intel_de_read(dev_priv, BXT_P_CR_GT_DISP_PWRON) & phy_info->pwron_mask))
332 		return false;
333 
334 	if ((intel_de_read(dev_priv, BXT_PORT_CL1CM_DW0(phy)) &
335 	     (PHY_POWER_GOOD | PHY_RESERVED)) != PHY_POWER_GOOD) {
336 		drm_dbg(&dev_priv->drm,
337 			"DDI PHY %d powered, but power hasn't settled\n", phy);
338 
339 		return false;
340 	}
341 
342 	if (!(intel_de_read(dev_priv, BXT_PHY_CTL_FAMILY(phy)) & COMMON_RESET_DIS)) {
343 		drm_dbg(&dev_priv->drm,
344 			"DDI PHY %d powered, but still in reset\n", phy);
345 
346 		return false;
347 	}
348 
349 	return true;
350 }
351 
352 static u32 bxt_get_grc(struct drm_i915_private *dev_priv, enum dpio_phy phy)
353 {
354 	u32 val = intel_de_read(dev_priv, BXT_PORT_REF_DW6(phy));
355 
356 	return (val & GRC_CODE_MASK) >> GRC_CODE_SHIFT;
357 }
358 
359 static void bxt_phy_wait_grc_done(struct drm_i915_private *dev_priv,
360 				  enum dpio_phy phy)
361 {
362 	if (intel_de_wait_for_set(dev_priv, BXT_PORT_REF_DW3(phy),
363 				  GRC_DONE, 10))
364 		drm_err(&dev_priv->drm, "timeout waiting for PHY%d GRC\n",
365 			phy);
366 }
367 
368 static void _bxt_ddi_phy_init(struct drm_i915_private *dev_priv,
369 			      enum dpio_phy phy)
370 {
371 	const struct bxt_ddi_phy_info *phy_info;
372 	u32 val;
373 
374 	phy_info = bxt_get_phy_info(dev_priv, phy);
375 
376 	if (bxt_ddi_phy_is_enabled(dev_priv, phy)) {
377 		/* Still read out the GRC value for state verification */
378 		if (phy_info->rcomp_phy != -1)
379 			dev_priv->display.state.bxt_phy_grc = bxt_get_grc(dev_priv, phy);
380 
381 		if (bxt_ddi_phy_verify_state(dev_priv, phy)) {
382 			drm_dbg(&dev_priv->drm, "DDI PHY %d already enabled, "
383 				"won't reprogram it\n", phy);
384 			return;
385 		}
386 
387 		drm_dbg(&dev_priv->drm,
388 			"DDI PHY %d enabled with invalid state, "
389 			"force reprogramming it\n", phy);
390 	}
391 
392 	intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, 0, phy_info->pwron_mask);
393 
394 	/*
395 	 * The PHY registers start out inaccessible and respond to reads with
396 	 * all 1s.  Eventually they become accessible as they power up, then
397 	 * the reserved bit will give the default 0.  Poll on the reserved bit
398 	 * becoming 0 to find when the PHY is accessible.
399 	 * The flag should get set in 100us according to the HW team, but
400 	 * use 1ms due to occasional timeouts observed with that.
401 	 */
402 	if (intel_wait_for_register_fw(&dev_priv->uncore,
403 				       BXT_PORT_CL1CM_DW0(phy),
404 				       PHY_RESERVED | PHY_POWER_GOOD,
405 				       PHY_POWER_GOOD,
406 				       1))
407 		drm_err(&dev_priv->drm, "timeout during PHY%d power on\n",
408 			phy);
409 
410 	/* Program PLL Rcomp code offset */
411 	intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW9(phy), IREF0RC_OFFSET_MASK,
412 		     0xE4 << IREF0RC_OFFSET_SHIFT);
413 
414 	intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW10(phy), IREF1RC_OFFSET_MASK,
415 		     0xE4 << IREF1RC_OFFSET_SHIFT);
416 
417 	/* Program power gating */
418 	intel_de_rmw(dev_priv, BXT_PORT_CL1CM_DW28(phy), 0,
419 		     OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG);
420 
421 	if (phy_info->dual_channel)
422 		intel_de_rmw(dev_priv, BXT_PORT_CL2CM_DW6(phy), 0,
423 			     DW6_OLDO_DYN_PWR_DOWN_EN);
424 
425 	if (phy_info->rcomp_phy != -1) {
426 		u32 grc_code;
427 
428 		bxt_phy_wait_grc_done(dev_priv, phy_info->rcomp_phy);
429 
430 		/*
431 		 * PHY0 isn't connected to an RCOMP resistor so copy over
432 		 * the corresponding calibrated value from PHY1, and disable
433 		 * the automatic calibration on PHY0.
434 		 */
435 		val = bxt_get_grc(dev_priv, phy_info->rcomp_phy);
436 		dev_priv->display.state.bxt_phy_grc = val;
437 
438 		grc_code = val << GRC_CODE_FAST_SHIFT |
439 			   val << GRC_CODE_SLOW_SHIFT |
440 			   val;
441 		intel_de_write(dev_priv, BXT_PORT_REF_DW6(phy), grc_code);
442 		intel_de_rmw(dev_priv, BXT_PORT_REF_DW8(phy),
443 			     0, GRC_DIS | GRC_RDY_OVRD);
444 	}
445 
446 	if (phy_info->reset_delay)
447 		udelay(phy_info->reset_delay);
448 
449 	intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), 0, COMMON_RESET_DIS);
450 }
451 
452 void bxt_ddi_phy_uninit(struct drm_i915_private *dev_priv, enum dpio_phy phy)
453 {
454 	const struct bxt_ddi_phy_info *phy_info;
455 
456 	phy_info = bxt_get_phy_info(dev_priv, phy);
457 
458 	intel_de_rmw(dev_priv, BXT_PHY_CTL_FAMILY(phy), COMMON_RESET_DIS, 0);
459 
460 	intel_de_rmw(dev_priv, BXT_P_CR_GT_DISP_PWRON, phy_info->pwron_mask, 0);
461 }
462 
463 void bxt_ddi_phy_init(struct drm_i915_private *dev_priv, enum dpio_phy phy)
464 {
465 	const struct bxt_ddi_phy_info *phy_info =
466 		bxt_get_phy_info(dev_priv, phy);
467 	enum dpio_phy rcomp_phy = phy_info->rcomp_phy;
468 	bool was_enabled;
469 
470 	lockdep_assert_held(&dev_priv->display.power.domains.lock);
471 
472 	was_enabled = true;
473 	if (rcomp_phy != -1)
474 		was_enabled = bxt_ddi_phy_is_enabled(dev_priv, rcomp_phy);
475 
476 	/*
477 	 * We need to copy the GRC calibration value from rcomp_phy,
478 	 * so make sure it's powered up.
479 	 */
480 	if (!was_enabled)
481 		_bxt_ddi_phy_init(dev_priv, rcomp_phy);
482 
483 	_bxt_ddi_phy_init(dev_priv, phy);
484 
485 	if (!was_enabled)
486 		bxt_ddi_phy_uninit(dev_priv, rcomp_phy);
487 }
488 
489 static bool __printf(6, 7)
490 __phy_reg_verify_state(struct drm_i915_private *dev_priv, enum dpio_phy phy,
491 		       i915_reg_t reg, u32 mask, u32 expected,
492 		       const char *reg_fmt, ...)
493 {
494 	struct va_format vaf;
495 	va_list args;
496 	u32 val;
497 
498 	val = intel_de_read(dev_priv, reg);
499 	if ((val & mask) == expected)
500 		return true;
501 
502 	va_start(args, reg_fmt);
503 	vaf.fmt = reg_fmt;
504 	vaf.va = &args;
505 
506 	drm_dbg(&dev_priv->drm, "DDI PHY %d reg %pV [%08x] state mismatch: "
507 			 "current %08x, expected %08x (mask %08x)\n",
508 			 phy, &vaf, reg.reg, val, (val & ~mask) | expected,
509 			 mask);
510 
511 	va_end(args);
512 
513 	return false;
514 }
515 
516 bool bxt_ddi_phy_verify_state(struct drm_i915_private *dev_priv,
517 			      enum dpio_phy phy)
518 {
519 	const struct bxt_ddi_phy_info *phy_info;
520 	u32 mask;
521 	bool ok;
522 
523 	phy_info = bxt_get_phy_info(dev_priv, phy);
524 
525 #define _CHK(reg, mask, exp, fmt, ...)					\
526 	__phy_reg_verify_state(dev_priv, phy, reg, mask, exp, fmt,	\
527 			       ## __VA_ARGS__)
528 
529 	if (!bxt_ddi_phy_is_enabled(dev_priv, phy))
530 		return false;
531 
532 	ok = true;
533 
534 	/* PLL Rcomp code offset */
535 	ok &= _CHK(BXT_PORT_CL1CM_DW9(phy),
536 		    IREF0RC_OFFSET_MASK, 0xe4 << IREF0RC_OFFSET_SHIFT,
537 		    "BXT_PORT_CL1CM_DW9(%d)", phy);
538 	ok &= _CHK(BXT_PORT_CL1CM_DW10(phy),
539 		    IREF1RC_OFFSET_MASK, 0xe4 << IREF1RC_OFFSET_SHIFT,
540 		    "BXT_PORT_CL1CM_DW10(%d)", phy);
541 
542 	/* Power gating */
543 	mask = OCL1_POWER_DOWN_EN | DW28_OLDO_DYN_PWR_DOWN_EN | SUS_CLK_CONFIG;
544 	ok &= _CHK(BXT_PORT_CL1CM_DW28(phy), mask, mask,
545 		    "BXT_PORT_CL1CM_DW28(%d)", phy);
546 
547 	if (phy_info->dual_channel)
548 		ok &= _CHK(BXT_PORT_CL2CM_DW6(phy),
549 			   DW6_OLDO_DYN_PWR_DOWN_EN, DW6_OLDO_DYN_PWR_DOWN_EN,
550 			   "BXT_PORT_CL2CM_DW6(%d)", phy);
551 
552 	if (phy_info->rcomp_phy != -1) {
553 		u32 grc_code = dev_priv->display.state.bxt_phy_grc;
554 
555 		grc_code = grc_code << GRC_CODE_FAST_SHIFT |
556 			   grc_code << GRC_CODE_SLOW_SHIFT |
557 			   grc_code;
558 		mask = GRC_CODE_FAST_MASK | GRC_CODE_SLOW_MASK |
559 		       GRC_CODE_NOM_MASK;
560 		ok &= _CHK(BXT_PORT_REF_DW6(phy), mask, grc_code,
561 			   "BXT_PORT_REF_DW6(%d)", phy);
562 
563 		mask = GRC_DIS | GRC_RDY_OVRD;
564 		ok &= _CHK(BXT_PORT_REF_DW8(phy), mask, mask,
565 			    "BXT_PORT_REF_DW8(%d)", phy);
566 	}
567 
568 	return ok;
569 #undef _CHK
570 }
571 
572 u8
573 bxt_ddi_phy_calc_lane_lat_optim_mask(u8 lane_count)
574 {
575 	switch (lane_count) {
576 	case 1:
577 		return 0;
578 	case 2:
579 		return BIT(2) | BIT(0);
580 	case 4:
581 		return BIT(3) | BIT(2) | BIT(0);
582 	default:
583 		MISSING_CASE(lane_count);
584 
585 		return 0;
586 	}
587 }
588 
589 void bxt_ddi_phy_set_lane_optim_mask(struct intel_encoder *encoder,
590 				     u8 lane_lat_optim_mask)
591 {
592 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
593 	enum port port = encoder->port;
594 	enum dpio_phy phy;
595 	enum dpio_channel ch;
596 	int lane;
597 
598 	bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
599 
600 	for (lane = 0; lane < 4; lane++) {
601 		u32 val = intel_de_read(dev_priv,
602 					BXT_PORT_TX_DW14_LN(phy, ch, lane));
603 
604 		/*
605 		 * Note that on CHV this flag is called UPAR, but has
606 		 * the same function.
607 		 */
608 		val &= ~LATENCY_OPTIM;
609 		if (lane_lat_optim_mask & BIT(lane))
610 			val |= LATENCY_OPTIM;
611 
612 		intel_de_write(dev_priv, BXT_PORT_TX_DW14_LN(phy, ch, lane),
613 			       val);
614 	}
615 }
616 
617 u8
618 bxt_ddi_phy_get_lane_lat_optim_mask(struct intel_encoder *encoder)
619 {
620 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
621 	enum port port = encoder->port;
622 	enum dpio_phy phy;
623 	enum dpio_channel ch;
624 	int lane;
625 	u8 mask;
626 
627 	bxt_port_to_phy_channel(dev_priv, port, &phy, &ch);
628 
629 	mask = 0;
630 	for (lane = 0; lane < 4; lane++) {
631 		u32 val = intel_de_read(dev_priv,
632 					BXT_PORT_TX_DW14_LN(phy, ch, lane));
633 
634 		if (val & LATENCY_OPTIM)
635 			mask |= BIT(lane);
636 	}
637 
638 	return mask;
639 }
640 
641 enum dpio_channel vlv_dig_port_to_channel(struct intel_digital_port *dig_port)
642 {
643 	switch (dig_port->base.port) {
644 	default:
645 		MISSING_CASE(dig_port->base.port);
646 		fallthrough;
647 	case PORT_B:
648 	case PORT_D:
649 		return DPIO_CH0;
650 	case PORT_C:
651 		return DPIO_CH1;
652 	}
653 }
654 
655 enum dpio_phy vlv_dig_port_to_phy(struct intel_digital_port *dig_port)
656 {
657 	switch (dig_port->base.port) {
658 	default:
659 		MISSING_CASE(dig_port->base.port);
660 		fallthrough;
661 	case PORT_B:
662 	case PORT_C:
663 		return DPIO_PHY0;
664 	case PORT_D:
665 		return DPIO_PHY1;
666 	}
667 }
668 
669 enum dpio_channel vlv_pipe_to_channel(enum pipe pipe)
670 {
671 	switch (pipe) {
672 	default:
673 		MISSING_CASE(pipe);
674 		fallthrough;
675 	case PIPE_A:
676 	case PIPE_C:
677 		return DPIO_CH0;
678 	case PIPE_B:
679 		return DPIO_CH1;
680 	}
681 }
682 
683 void chv_set_phy_signal_level(struct intel_encoder *encoder,
684 			      const struct intel_crtc_state *crtc_state,
685 			      u32 deemph_reg_value, u32 margin_reg_value,
686 			      bool uniq_trans_scale)
687 {
688 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
689 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
690 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
691 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
692 	enum pipe pipe = crtc->pipe;
693 	u32 val;
694 	int i;
695 
696 	vlv_dpio_get(dev_priv);
697 
698 	/* Clear calc init */
699 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
700 	val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
701 	val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
702 	val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
703 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
704 
705 	if (crtc_state->lane_count > 2) {
706 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
707 		val &= ~(DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3);
708 		val &= ~(DPIO_PCS_TX1DEEMP_MASK | DPIO_PCS_TX2DEEMP_MASK);
709 		val |= DPIO_PCS_TX1DEEMP_9P5 | DPIO_PCS_TX2DEEMP_9P5;
710 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
711 	}
712 
713 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch));
714 	val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
715 	val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
716 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val);
717 
718 	if (crtc_state->lane_count > 2) {
719 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch));
720 		val &= ~(DPIO_PCS_TX1MARGIN_MASK | DPIO_PCS_TX2MARGIN_MASK);
721 		val |= DPIO_PCS_TX1MARGIN_000 | DPIO_PCS_TX2MARGIN_000;
722 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val);
723 	}
724 
725 	/* Program swing deemph */
726 	for (i = 0; i < crtc_state->lane_count; i++) {
727 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i));
728 		val &= ~DPIO_SWING_DEEMPH9P5_MASK;
729 		val |= deemph_reg_value << DPIO_SWING_DEEMPH9P5_SHIFT;
730 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW4(ch, i), val);
731 	}
732 
733 	/* Program swing margin */
734 	for (i = 0; i < crtc_state->lane_count; i++) {
735 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW2(ch, i));
736 
737 		val &= ~DPIO_SWING_MARGIN000_MASK;
738 		val |= margin_reg_value << DPIO_SWING_MARGIN000_SHIFT;
739 
740 		/*
741 		 * Supposedly this value shouldn't matter when unique transition
742 		 * scale is disabled, but in fact it does matter. Let's just
743 		 * always program the same value and hope it's OK.
744 		 */
745 		val &= ~(0xff << DPIO_UNIQ_TRANS_SCALE_SHIFT);
746 		val |= 0x9a << DPIO_UNIQ_TRANS_SCALE_SHIFT;
747 
748 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW2(ch, i), val);
749 	}
750 
751 	/*
752 	 * The document said it needs to set bit 27 for ch0 and bit 26
753 	 * for ch1. Might be a typo in the doc.
754 	 * For now, for this unique transition scale selection, set bit
755 	 * 27 for ch0 and ch1.
756 	 */
757 	for (i = 0; i < crtc_state->lane_count; i++) {
758 		val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW3(ch, i));
759 		if (uniq_trans_scale)
760 			val |= DPIO_TX_UNIQ_TRANS_SCALE_EN;
761 		else
762 			val &= ~DPIO_TX_UNIQ_TRANS_SCALE_EN;
763 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW3(ch, i), val);
764 	}
765 
766 	/* Start swing calculation */
767 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch));
768 	val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
769 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val);
770 
771 	if (crtc_state->lane_count > 2) {
772 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch));
773 		val |= DPIO_PCS_SWING_CALC_TX0_TX2 | DPIO_PCS_SWING_CALC_TX1_TX3;
774 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val);
775 	}
776 
777 	vlv_dpio_put(dev_priv);
778 }
779 
780 void chv_data_lane_soft_reset(struct intel_encoder *encoder,
781 			      const struct intel_crtc_state *crtc_state,
782 			      bool reset)
783 {
784 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
785 	enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
786 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
787 	enum pipe pipe = crtc->pipe;
788 	u32 val;
789 
790 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW0(ch));
791 	if (reset)
792 		val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
793 	else
794 		val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
795 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW0(ch), val);
796 
797 	if (crtc_state->lane_count > 2) {
798 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW0(ch));
799 		if (reset)
800 			val &= ~(DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET);
801 		else
802 			val |= DPIO_PCS_TX_LANE2_RESET | DPIO_PCS_TX_LANE1_RESET;
803 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW0(ch), val);
804 	}
805 
806 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW1(ch));
807 	val |= CHV_PCS_REQ_SOFTRESET_EN;
808 	if (reset)
809 		val &= ~DPIO_PCS_CLK_SOFT_RESET;
810 	else
811 		val |= DPIO_PCS_CLK_SOFT_RESET;
812 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW1(ch), val);
813 
814 	if (crtc_state->lane_count > 2) {
815 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW1(ch));
816 		val |= CHV_PCS_REQ_SOFTRESET_EN;
817 		if (reset)
818 			val &= ~DPIO_PCS_CLK_SOFT_RESET;
819 		else
820 			val |= DPIO_PCS_CLK_SOFT_RESET;
821 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW1(ch), val);
822 	}
823 }
824 
825 void chv_phy_pre_pll_enable(struct intel_encoder *encoder,
826 			    const struct intel_crtc_state *crtc_state)
827 {
828 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
829 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
830 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
831 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
832 	enum pipe pipe = crtc->pipe;
833 	unsigned int lane_mask =
834 		intel_dp_unused_lane_mask(crtc_state->lane_count);
835 	u32 val;
836 
837 	/*
838 	 * Must trick the second common lane into life.
839 	 * Otherwise we can't even access the PLL.
840 	 */
841 	if (ch == DPIO_CH0 && pipe == PIPE_B)
842 		dig_port->release_cl2_override =
843 			!chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, true);
844 
845 	chv_phy_powergate_lanes(encoder, true, lane_mask);
846 
847 	vlv_dpio_get(dev_priv);
848 
849 	/* Assert data lane reset */
850 	chv_data_lane_soft_reset(encoder, crtc_state, true);
851 
852 	/* program left/right clock distribution */
853 	if (pipe != PIPE_B) {
854 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
855 		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
856 		if (ch == DPIO_CH0)
857 			val |= CHV_BUFLEFTENA1_FORCE;
858 		if (ch == DPIO_CH1)
859 			val |= CHV_BUFRIGHTENA1_FORCE;
860 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
861 	} else {
862 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
863 		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
864 		if (ch == DPIO_CH0)
865 			val |= CHV_BUFLEFTENA2_FORCE;
866 		if (ch == DPIO_CH1)
867 			val |= CHV_BUFRIGHTENA2_FORCE;
868 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
869 	}
870 
871 	/* program clock channel usage */
872 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(ch));
873 	val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
874 	if (pipe != PIPE_B)
875 		val &= ~CHV_PCS_USEDCLKCHANNEL;
876 	else
877 		val |= CHV_PCS_USEDCLKCHANNEL;
878 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW8(ch), val);
879 
880 	if (crtc_state->lane_count > 2) {
881 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW8(ch));
882 		val |= CHV_PCS_USEDCLKCHANNEL_OVRRIDE;
883 		if (pipe != PIPE_B)
884 			val &= ~CHV_PCS_USEDCLKCHANNEL;
885 		else
886 			val |= CHV_PCS_USEDCLKCHANNEL;
887 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW8(ch), val);
888 	}
889 
890 	/*
891 	 * This a a bit weird since generally CL
892 	 * matches the pipe, but here we need to
893 	 * pick the CL based on the port.
894 	 */
895 	val = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW19(ch));
896 	if (pipe != PIPE_B)
897 		val &= ~CHV_CMN_USEDCLKCHANNEL;
898 	else
899 		val |= CHV_CMN_USEDCLKCHANNEL;
900 	vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW19(ch), val);
901 
902 	vlv_dpio_put(dev_priv);
903 }
904 
905 void chv_phy_pre_encoder_enable(struct intel_encoder *encoder,
906 				const struct intel_crtc_state *crtc_state)
907 {
908 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
909 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
910 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
911 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
912 	enum dpio_channel ch = vlv_dig_port_to_channel(dig_port);
913 	enum pipe pipe = crtc->pipe;
914 	int data, i, stagger;
915 	u32 val;
916 
917 	vlv_dpio_get(dev_priv);
918 
919 	/* allow hardware to manage TX FIFO reset source */
920 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
921 	val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
922 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
923 
924 	if (crtc_state->lane_count > 2) {
925 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
926 		val &= ~DPIO_LANEDESKEW_STRAP_OVRD;
927 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
928 	}
929 
930 	/* Program Tx lane latency optimal setting*/
931 	for (i = 0; i < crtc_state->lane_count; i++) {
932 		/* Set the upar bit */
933 		if (crtc_state->lane_count == 1)
934 			data = 0x0;
935 		else
936 			data = (i == 1) ? 0x0 : 0x1;
937 		vlv_dpio_write(dev_priv, pipe, CHV_TX_DW14(ch, i),
938 				data << DPIO_UPAR_SHIFT);
939 	}
940 
941 	/* Data lane stagger programming */
942 	if (crtc_state->port_clock > 270000)
943 		stagger = 0x18;
944 	else if (crtc_state->port_clock > 135000)
945 		stagger = 0xd;
946 	else if (crtc_state->port_clock > 67500)
947 		stagger = 0x7;
948 	else if (crtc_state->port_clock > 33750)
949 		stagger = 0x4;
950 	else
951 		stagger = 0x2;
952 
953 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW11(ch));
954 	val |= DPIO_TX2_STAGGER_MASK(0x1f);
955 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW11(ch), val);
956 
957 	if (crtc_state->lane_count > 2) {
958 		val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW11(ch));
959 		val |= DPIO_TX2_STAGGER_MASK(0x1f);
960 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW11(ch), val);
961 	}
962 
963 	vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW12(ch),
964 		       DPIO_LANESTAGGER_STRAP(stagger) |
965 		       DPIO_LANESTAGGER_STRAP_OVRD |
966 		       DPIO_TX1_STAGGER_MASK(0x1f) |
967 		       DPIO_TX1_STAGGER_MULT(6) |
968 		       DPIO_TX2_STAGGER_MULT(0));
969 
970 	if (crtc_state->lane_count > 2) {
971 		vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW12(ch),
972 			       DPIO_LANESTAGGER_STRAP(stagger) |
973 			       DPIO_LANESTAGGER_STRAP_OVRD |
974 			       DPIO_TX1_STAGGER_MASK(0x1f) |
975 			       DPIO_TX1_STAGGER_MULT(7) |
976 			       DPIO_TX2_STAGGER_MULT(5));
977 	}
978 
979 	/* Deassert data lane reset */
980 	chv_data_lane_soft_reset(encoder, crtc_state, false);
981 
982 	vlv_dpio_put(dev_priv);
983 }
984 
985 void chv_phy_release_cl2_override(struct intel_encoder *encoder)
986 {
987 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
988 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
989 
990 	if (dig_port->release_cl2_override) {
991 		chv_phy_powergate_ch(dev_priv, DPIO_PHY0, DPIO_CH1, false);
992 		dig_port->release_cl2_override = false;
993 	}
994 }
995 
996 void chv_phy_post_pll_disable(struct intel_encoder *encoder,
997 			      const struct intel_crtc_state *old_crtc_state)
998 {
999 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1000 	enum pipe pipe = to_intel_crtc(old_crtc_state->uapi.crtc)->pipe;
1001 	u32 val;
1002 
1003 	vlv_dpio_get(dev_priv);
1004 
1005 	/* disable left/right clock distribution */
1006 	if (pipe != PIPE_B) {
1007 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW5_CH0);
1008 		val &= ~(CHV_BUFLEFTENA1_MASK | CHV_BUFRIGHTENA1_MASK);
1009 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW5_CH0, val);
1010 	} else {
1011 		val = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW1_CH1);
1012 		val &= ~(CHV_BUFLEFTENA2_MASK | CHV_BUFRIGHTENA2_MASK);
1013 		vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW1_CH1, val);
1014 	}
1015 
1016 	vlv_dpio_put(dev_priv);
1017 
1018 	/*
1019 	 * Leave the power down bit cleared for at least one
1020 	 * lane so that chv_powergate_phy_ch() will power
1021 	 * on something when the channel is otherwise unused.
1022 	 * When the port is off and the override is removed
1023 	 * the lanes power down anyway, so otherwise it doesn't
1024 	 * really matter what the state of power down bits is
1025 	 * after this.
1026 	 */
1027 	chv_phy_powergate_lanes(encoder, false, 0x0);
1028 }
1029 
1030 void vlv_set_phy_signal_level(struct intel_encoder *encoder,
1031 			      const struct intel_crtc_state *crtc_state,
1032 			      u32 demph_reg_value, u32 preemph_reg_value,
1033 			      u32 uniqtranscale_reg_value, u32 tx3_demph)
1034 {
1035 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1036 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1037 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1038 	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1039 	enum pipe pipe = crtc->pipe;
1040 
1041 	vlv_dpio_get(dev_priv);
1042 
1043 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), 0x00000000);
1044 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW4(port), demph_reg_value);
1045 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW2(port),
1046 			 uniqtranscale_reg_value);
1047 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW3(port), 0x0C782040);
1048 
1049 	if (tx3_demph)
1050 		vlv_dpio_write(dev_priv, pipe, VLV_TX3_DW4(port), tx3_demph);
1051 
1052 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW11(port), 0x00030000);
1053 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW9(port), preemph_reg_value);
1054 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW5(port), DPIO_TX_OCALINIT_EN);
1055 
1056 	vlv_dpio_put(dev_priv);
1057 }
1058 
1059 void vlv_phy_pre_pll_enable(struct intel_encoder *encoder,
1060 			    const struct intel_crtc_state *crtc_state)
1061 {
1062 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1063 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1064 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1065 	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1066 	enum pipe pipe = crtc->pipe;
1067 
1068 	/* Program Tx lane resets to default */
1069 	vlv_dpio_get(dev_priv);
1070 
1071 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port),
1072 			 DPIO_PCS_TX_LANE2_RESET |
1073 			 DPIO_PCS_TX_LANE1_RESET);
1074 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port),
1075 			 DPIO_PCS_CLK_CRI_RXEB_EIOS_EN |
1076 			 DPIO_PCS_CLK_CRI_RXDIGFILTSG_EN |
1077 			 (1<<DPIO_PCS_CLK_DATAWIDTH_SHIFT) |
1078 				 DPIO_PCS_CLK_SOFT_RESET);
1079 
1080 	/* Fix up inter-pair skew failure */
1081 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW12(port), 0x00750f00);
1082 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW11(port), 0x00001500);
1083 	vlv_dpio_write(dev_priv, pipe, VLV_TX_DW14(port), 0x40400000);
1084 
1085 	vlv_dpio_put(dev_priv);
1086 }
1087 
1088 void vlv_phy_pre_encoder_enable(struct intel_encoder *encoder,
1089 				const struct intel_crtc_state *crtc_state)
1090 {
1091 	struct intel_dp *intel_dp = enc_to_intel_dp(encoder);
1092 	struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
1093 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1094 	struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
1095 	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1096 	enum pipe pipe = crtc->pipe;
1097 	u32 val;
1098 
1099 	vlv_dpio_get(dev_priv);
1100 
1101 	/* Enable clock channels for this port */
1102 	val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW8(port));
1103 	val = 0;
1104 	if (pipe)
1105 		val |= (1<<21);
1106 	else
1107 		val &= ~(1<<21);
1108 	val |= 0x001000c4;
1109 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW8(port), val);
1110 
1111 	/* Program lane clock */
1112 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW14(port), 0x00760018);
1113 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW23(port), 0x00400888);
1114 
1115 	vlv_dpio_put(dev_priv);
1116 }
1117 
1118 void vlv_phy_reset_lanes(struct intel_encoder *encoder,
1119 			 const struct intel_crtc_state *old_crtc_state)
1120 {
1121 	struct intel_digital_port *dig_port = enc_to_dig_port(encoder);
1122 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
1123 	struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->uapi.crtc);
1124 	enum dpio_channel port = vlv_dig_port_to_channel(dig_port);
1125 	enum pipe pipe = crtc->pipe;
1126 
1127 	vlv_dpio_get(dev_priv);
1128 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW0(port), 0x00000000);
1129 	vlv_dpio_write(dev_priv, pipe, VLV_PCS_DW1(port), 0x00e00060);
1130 	vlv_dpio_put(dev_priv);
1131 }
1132