1 /* 2 * Copyright © 2008 Intel Corporation 3 * 2014 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 22 * IN THE SOFTWARE. 23 * 24 */ 25 26 #include <drm/drm_atomic.h> 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_edid.h> 29 #include <drm/drm_probe_helper.h> 30 31 #include "i915_drv.h" 32 #include "i915_reg.h" 33 #include "intel_atomic.h" 34 #include "intel_audio.h" 35 #include "intel_connector.h" 36 #include "intel_crtc.h" 37 #include "intel_ddi.h" 38 #include "intel_de.h" 39 #include "intel_display_types.h" 40 #include "intel_dp.h" 41 #include "intel_dp_hdcp.h" 42 #include "intel_dp_mst.h" 43 #include "intel_dpio_phy.h" 44 #include "intel_hdcp.h" 45 #include "intel_hotplug.h" 46 #include "skl_scaler.h" 47 48 static int intel_dp_mst_find_vcpi_slots_for_bpp(struct intel_encoder *encoder, 49 struct intel_crtc_state *crtc_state, 50 int max_bpp, 51 int min_bpp, 52 struct link_config_limits *limits, 53 struct drm_connector_state *conn_state, 54 int step, 55 bool dsc) 56 { 57 struct drm_atomic_state *state = crtc_state->uapi.state; 58 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 59 struct intel_dp *intel_dp = &intel_mst->primary->dp; 60 struct drm_dp_mst_topology_state *mst_state; 61 struct intel_connector *connector = 62 to_intel_connector(conn_state->connector); 63 struct drm_i915_private *i915 = to_i915(connector->base.dev); 64 const struct drm_display_mode *adjusted_mode = 65 &crtc_state->hw.adjusted_mode; 66 int bpp, slots = -EINVAL; 67 int ret = 0; 68 69 mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr); 70 if (IS_ERR(mst_state)) 71 return PTR_ERR(mst_state); 72 73 crtc_state->lane_count = limits->max_lane_count; 74 crtc_state->port_clock = limits->max_rate; 75 76 // TODO: Handle pbn_div changes by adding a new MST helper 77 if (!mst_state->pbn_div) { 78 mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr, 79 crtc_state->port_clock, 80 crtc_state->lane_count); 81 } 82 83 for (bpp = max_bpp; bpp >= min_bpp; bpp -= step) { 84 crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, 85 dsc ? bpp << 4 : bpp, 86 dsc); 87 88 drm_dbg_kms(&i915->drm, "Trying bpp %d\n", bpp); 89 90 slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr, 91 connector->port, 92 crtc_state->pbn); 93 if (slots == -EDEADLK) 94 return slots; 95 96 if (slots >= 0) { 97 ret = drm_dp_mst_atomic_check(state); 98 /* 99 * If we got slots >= 0 and we can fit those based on check 100 * then we can exit the loop. Otherwise keep trying. 101 */ 102 if (!ret) 103 break; 104 } 105 } 106 107 /* Despite slots are non-zero, we still failed the atomic check */ 108 if (ret && slots >= 0) 109 slots = ret; 110 111 if (slots < 0) { 112 drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n", 113 slots); 114 } else { 115 if (!dsc) 116 crtc_state->pipe_bpp = bpp; 117 else 118 crtc_state->dsc.compressed_bpp = bpp; 119 drm_dbg_kms(&i915->drm, "Got %d slots for pipe bpp %d dsc %d\n", slots, bpp, dsc); 120 } 121 122 return slots; 123 } 124 125 static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, 126 struct intel_crtc_state *crtc_state, 127 struct drm_connector_state *conn_state, 128 struct link_config_limits *limits) 129 { 130 const struct drm_display_mode *adjusted_mode = 131 &crtc_state->hw.adjusted_mode; 132 int slots = -EINVAL; 133 134 slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, limits->max_bpp, 135 limits->min_bpp, limits, 136 conn_state, 2 * 3, false); 137 138 if (slots < 0) 139 return slots; 140 141 intel_link_compute_m_n(crtc_state->pipe_bpp, 142 crtc_state->lane_count, 143 adjusted_mode->crtc_clock, 144 crtc_state->port_clock, 145 &crtc_state->dp_m_n, 146 crtc_state->fec_enable); 147 crtc_state->dp_m_n.tu = slots; 148 149 return 0; 150 } 151 152 static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, 153 struct intel_crtc_state *crtc_state, 154 struct drm_connector_state *conn_state, 155 struct link_config_limits *limits) 156 { 157 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 158 struct intel_dp *intel_dp = &intel_mst->primary->dp; 159 struct intel_connector *connector = 160 to_intel_connector(conn_state->connector); 161 struct drm_i915_private *i915 = to_i915(connector->base.dev); 162 const struct drm_display_mode *adjusted_mode = 163 &crtc_state->hw.adjusted_mode; 164 int slots = -EINVAL; 165 int i, num_bpc; 166 u8 dsc_bpc[3] = {0}; 167 int min_bpp, max_bpp, sink_min_bpp, sink_max_bpp; 168 u8 dsc_max_bpc; 169 bool need_timeslot_recalc = false; 170 u32 last_compressed_bpp; 171 172 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ 173 if (DISPLAY_VER(i915) >= 12) 174 dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc); 175 else 176 dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc); 177 178 max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp); 179 min_bpp = limits->min_bpp; 180 181 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, 182 dsc_bpc); 183 184 drm_dbg_kms(&i915->drm, "DSC Source supported min bpp %d max bpp %d\n", 185 min_bpp, max_bpp); 186 187 sink_max_bpp = dsc_bpc[0] * 3; 188 sink_min_bpp = sink_max_bpp; 189 190 for (i = 1; i < num_bpc; i++) { 191 if (sink_min_bpp > dsc_bpc[i] * 3) 192 sink_min_bpp = dsc_bpc[i] * 3; 193 if (sink_max_bpp < dsc_bpc[i] * 3) 194 sink_max_bpp = dsc_bpc[i] * 3; 195 } 196 197 drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n", 198 sink_min_bpp, sink_max_bpp); 199 200 if (min_bpp < sink_min_bpp) 201 min_bpp = sink_min_bpp; 202 203 if (max_bpp > sink_max_bpp) 204 max_bpp = sink_max_bpp; 205 206 slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, max_bpp, 207 min_bpp, limits, 208 conn_state, 2 * 3, true); 209 210 if (slots < 0) 211 return slots; 212 213 last_compressed_bpp = crtc_state->dsc.compressed_bpp; 214 215 crtc_state->dsc.compressed_bpp = intel_dp_dsc_nearest_valid_bpp(i915, 216 last_compressed_bpp, 217 crtc_state->pipe_bpp); 218 219 if (crtc_state->dsc.compressed_bpp != last_compressed_bpp) 220 need_timeslot_recalc = true; 221 222 /* 223 * Apparently some MST hubs dislike if vcpi slots are not matching precisely 224 * the actual compressed bpp we use. 225 */ 226 if (need_timeslot_recalc) { 227 slots = intel_dp_mst_find_vcpi_slots_for_bpp(encoder, crtc_state, 228 crtc_state->dsc.compressed_bpp, 229 crtc_state->dsc.compressed_bpp, 230 limits, conn_state, 2 * 3, true); 231 if (slots < 0) 232 return slots; 233 } 234 235 intel_link_compute_m_n(crtc_state->pipe_bpp, 236 crtc_state->lane_count, 237 adjusted_mode->crtc_clock, 238 crtc_state->port_clock, 239 &crtc_state->dp_m_n, 240 crtc_state->fec_enable); 241 crtc_state->dp_m_n.tu = slots; 242 243 return 0; 244 } 245 static int intel_dp_mst_update_slots(struct intel_encoder *encoder, 246 struct intel_crtc_state *crtc_state, 247 struct drm_connector_state *conn_state) 248 { 249 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 250 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 251 struct intel_dp *intel_dp = &intel_mst->primary->dp; 252 struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr; 253 struct drm_dp_mst_topology_state *topology_state; 254 u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ? 255 DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B; 256 257 topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr); 258 if (IS_ERR(topology_state)) { 259 drm_dbg_kms(&i915->drm, "slot update failed\n"); 260 return PTR_ERR(topology_state); 261 } 262 263 drm_dp_mst_update_slots(topology_state, link_coding_cap); 264 265 return 0; 266 } 267 268 static int intel_dp_mst_compute_config(struct intel_encoder *encoder, 269 struct intel_crtc_state *pipe_config, 270 struct drm_connector_state *conn_state) 271 { 272 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 273 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 274 struct intel_dp *intel_dp = &intel_mst->primary->dp; 275 struct intel_connector *connector = 276 to_intel_connector(conn_state->connector); 277 struct intel_digital_connector_state *intel_conn_state = 278 to_intel_digital_connector_state(conn_state); 279 const struct drm_display_mode *adjusted_mode = 280 &pipe_config->hw.adjusted_mode; 281 struct link_config_limits limits; 282 int ret; 283 284 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 285 return -EINVAL; 286 287 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 288 pipe_config->has_pch_encoder = false; 289 290 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 291 pipe_config->has_audio = connector->port->has_audio; 292 else 293 pipe_config->has_audio = 294 intel_conn_state->force_audio == HDMI_AUDIO_ON; 295 296 /* 297 * for MST we always configure max link bw - the spec doesn't 298 * seem to suggest we should do otherwise. 299 */ 300 limits.min_rate = 301 limits.max_rate = intel_dp_max_link_rate(intel_dp); 302 303 limits.min_lane_count = 304 limits.max_lane_count = intel_dp_max_lane_count(intel_dp); 305 306 limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format); 307 /* 308 * FIXME: If all the streams can't fit into the link with 309 * their current pipe_bpp we should reduce pipe_bpp across 310 * the board until things start to fit. Until then we 311 * limit to <= 8bpc since that's what was hardcoded for all 312 * MST streams previously. This hack should be removed once 313 * we have the proper retry logic in place. 314 */ 315 limits.max_bpp = min(pipe_config->pipe_bpp, 24); 316 317 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); 318 319 ret = intel_dp_mst_compute_link_config(encoder, pipe_config, 320 conn_state, &limits); 321 322 if (ret == -EDEADLK) 323 return ret; 324 325 /* enable compression if the mode doesn't fit available BW */ 326 drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); 327 if (ret || intel_dp->force_dsc_en) { 328 /* 329 * Try to get at least some timeslots and then see, if 330 * we can fit there with DSC. 331 */ 332 drm_dbg_kms(&dev_priv->drm, "Trying to find VCPI slots in DSC mode\n"); 333 334 ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config, 335 conn_state, &limits); 336 if (ret < 0) 337 return ret; 338 339 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, 340 conn_state, &limits, 341 pipe_config->dp_m_n.tu, false); 342 } 343 344 if (ret) 345 return ret; 346 347 ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state); 348 if (ret) 349 return ret; 350 351 pipe_config->limited_color_range = 352 intel_dp_limited_color_range(pipe_config, conn_state); 353 354 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 355 pipe_config->lane_lat_optim_mask = 356 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 357 358 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 359 360 return 0; 361 } 362 363 /* 364 * Iterate over all connectors and return a mask of 365 * all CPU transcoders streaming over the same DP link. 366 */ 367 static unsigned int 368 intel_dp_mst_transcoder_mask(struct intel_atomic_state *state, 369 struct intel_dp *mst_port) 370 { 371 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 372 const struct intel_digital_connector_state *conn_state; 373 struct intel_connector *connector; 374 u8 transcoders = 0; 375 int i; 376 377 if (DISPLAY_VER(dev_priv) < 12) 378 return 0; 379 380 for_each_new_intel_connector_in_state(state, connector, conn_state, i) { 381 const struct intel_crtc_state *crtc_state; 382 struct intel_crtc *crtc; 383 384 if (connector->mst_port != mst_port || !conn_state->base.crtc) 385 continue; 386 387 crtc = to_intel_crtc(conn_state->base.crtc); 388 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 389 390 if (!crtc_state->hw.active) 391 continue; 392 393 transcoders |= BIT(crtc_state->cpu_transcoder); 394 } 395 396 return transcoders; 397 } 398 399 static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder, 400 struct intel_crtc_state *crtc_state, 401 struct drm_connector_state *conn_state) 402 { 403 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state); 404 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 405 struct intel_dp *intel_dp = &intel_mst->primary->dp; 406 407 /* lowest numbered transcoder will be designated master */ 408 crtc_state->mst_master_transcoder = 409 ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1; 410 411 return 0; 412 } 413 414 /* 415 * If one of the connectors in a MST stream needs a modeset, mark all CRTCs 416 * that shares the same MST stream as mode changed, 417 * intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do 418 * a fastset when possible. 419 */ 420 static int 421 intel_dp_mst_atomic_master_trans_check(struct intel_connector *connector, 422 struct intel_atomic_state *state) 423 { 424 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 425 struct drm_connector_list_iter connector_list_iter; 426 struct intel_connector *connector_iter; 427 int ret = 0; 428 429 if (DISPLAY_VER(dev_priv) < 12) 430 return 0; 431 432 if (!intel_connector_needs_modeset(state, &connector->base)) 433 return 0; 434 435 drm_connector_list_iter_begin(&dev_priv->drm, &connector_list_iter); 436 for_each_intel_connector_iter(connector_iter, &connector_list_iter) { 437 struct intel_digital_connector_state *conn_iter_state; 438 struct intel_crtc_state *crtc_state; 439 struct intel_crtc *crtc; 440 441 if (connector_iter->mst_port != connector->mst_port || 442 connector_iter == connector) 443 continue; 444 445 conn_iter_state = intel_atomic_get_digital_connector_state(state, 446 connector_iter); 447 if (IS_ERR(conn_iter_state)) { 448 ret = PTR_ERR(conn_iter_state); 449 break; 450 } 451 452 if (!conn_iter_state->base.crtc) 453 continue; 454 455 crtc = to_intel_crtc(conn_iter_state->base.crtc); 456 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 457 if (IS_ERR(crtc_state)) { 458 ret = PTR_ERR(crtc_state); 459 break; 460 } 461 462 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 463 if (ret) 464 break; 465 crtc_state->uapi.mode_changed = true; 466 } 467 drm_connector_list_iter_end(&connector_list_iter); 468 469 return ret; 470 } 471 472 static int 473 intel_dp_mst_atomic_check(struct drm_connector *connector, 474 struct drm_atomic_state *_state) 475 { 476 struct intel_atomic_state *state = to_intel_atomic_state(_state); 477 struct intel_connector *intel_connector = 478 to_intel_connector(connector); 479 int ret; 480 481 ret = intel_digital_connector_atomic_check(connector, &state->base); 482 if (ret) 483 return ret; 484 485 ret = intel_dp_mst_atomic_master_trans_check(intel_connector, state); 486 if (ret) 487 return ret; 488 489 return drm_dp_atomic_release_time_slots(&state->base, 490 &intel_connector->mst_port->mst_mgr, 491 intel_connector->port); 492 } 493 494 static void clear_act_sent(struct intel_encoder *encoder, 495 const struct intel_crtc_state *crtc_state) 496 { 497 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 498 499 intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state), 500 DP_TP_STATUS_ACT_SENT); 501 } 502 503 static void wait_for_act_sent(struct intel_encoder *encoder, 504 const struct intel_crtc_state *crtc_state) 505 { 506 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 507 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 508 struct intel_dp *intel_dp = &intel_mst->primary->dp; 509 510 if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state), 511 DP_TP_STATUS_ACT_SENT, 1)) 512 drm_err(&i915->drm, "Timed out waiting for ACT sent\n"); 513 514 drm_dp_check_act_status(&intel_dp->mst_mgr); 515 } 516 517 static void intel_mst_disable_dp(struct intel_atomic_state *state, 518 struct intel_encoder *encoder, 519 const struct intel_crtc_state *old_crtc_state, 520 const struct drm_connector_state *old_conn_state) 521 { 522 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 523 struct intel_digital_port *dig_port = intel_mst->primary; 524 struct intel_dp *intel_dp = &dig_port->dp; 525 struct intel_connector *connector = 526 to_intel_connector(old_conn_state->connector); 527 struct drm_dp_mst_topology_state *mst_state = 528 drm_atomic_get_mst_topology_state(&state->base, &intel_dp->mst_mgr); 529 struct drm_i915_private *i915 = to_i915(connector->base.dev); 530 531 drm_dbg_kms(&i915->drm, "active links %d\n", 532 intel_dp->active_mst_links); 533 534 intel_hdcp_disable(intel_mst->connector); 535 536 drm_dp_remove_payload(&intel_dp->mst_mgr, mst_state, 537 drm_atomic_get_mst_payload_state(mst_state, connector->port)); 538 539 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 540 } 541 542 static void intel_mst_post_disable_dp(struct intel_atomic_state *state, 543 struct intel_encoder *encoder, 544 const struct intel_crtc_state *old_crtc_state, 545 const struct drm_connector_state *old_conn_state) 546 { 547 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 548 struct intel_digital_port *dig_port = intel_mst->primary; 549 struct intel_dp *intel_dp = &dig_port->dp; 550 struct intel_connector *connector = 551 to_intel_connector(old_conn_state->connector); 552 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 553 bool last_mst_stream; 554 555 intel_dp->active_mst_links--; 556 last_mst_stream = intel_dp->active_mst_links == 0; 557 drm_WARN_ON(&dev_priv->drm, 558 DISPLAY_VER(dev_priv) >= 12 && last_mst_stream && 559 !intel_dp_mst_is_master_trans(old_crtc_state)); 560 561 intel_crtc_vblank_off(old_crtc_state); 562 563 intel_disable_transcoder(old_crtc_state); 564 565 clear_act_sent(encoder, old_crtc_state); 566 567 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder), 568 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 569 570 wait_for_act_sent(encoder, old_crtc_state); 571 572 intel_ddi_disable_transcoder_func(old_crtc_state); 573 574 if (DISPLAY_VER(dev_priv) >= 9) 575 skl_scaler_disable(old_crtc_state); 576 else 577 ilk_pfit_disable(old_crtc_state); 578 579 /* 580 * Power down mst path before disabling the port, otherwise we end 581 * up getting interrupts from the sink upon detecting link loss. 582 */ 583 drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, 584 false); 585 586 /* 587 * BSpec 4287: disable DIP after the transcoder is disabled and before 588 * the transcoder clock select is set to none. 589 */ 590 if (last_mst_stream) 591 intel_dp_set_infoframes(&dig_port->base, false, 592 old_crtc_state, NULL); 593 /* 594 * From TGL spec: "If multi-stream slave transcoder: Configure 595 * Transcoder Clock Select to direct no clock to the transcoder" 596 * 597 * From older GENs spec: "Configure Transcoder Clock Select to direct 598 * no clock to the transcoder" 599 */ 600 if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream) 601 intel_ddi_disable_pipe_clock(old_crtc_state); 602 603 604 intel_mst->connector = NULL; 605 if (last_mst_stream) 606 dig_port->base.post_disable(state, &dig_port->base, 607 old_crtc_state, NULL); 608 609 drm_dbg_kms(&dev_priv->drm, "active links %d\n", 610 intel_dp->active_mst_links); 611 } 612 613 static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state, 614 struct intel_encoder *encoder, 615 const struct intel_crtc_state *pipe_config, 616 const struct drm_connector_state *conn_state) 617 { 618 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 619 struct intel_digital_port *dig_port = intel_mst->primary; 620 struct intel_dp *intel_dp = &dig_port->dp; 621 622 if (intel_dp->active_mst_links == 0) 623 dig_port->base.pre_pll_enable(state, &dig_port->base, 624 pipe_config, NULL); 625 } 626 627 static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, 628 struct intel_encoder *encoder, 629 const struct intel_crtc_state *pipe_config, 630 const struct drm_connector_state *conn_state) 631 { 632 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 633 struct intel_digital_port *dig_port = intel_mst->primary; 634 struct intel_dp *intel_dp = &dig_port->dp; 635 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 636 struct intel_connector *connector = 637 to_intel_connector(conn_state->connector); 638 struct drm_dp_mst_topology_state *mst_state = 639 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr); 640 int ret; 641 bool first_mst_stream; 642 643 /* MST encoders are bound to a crtc, not to a connector, 644 * force the mapping here for get_hw_state. 645 */ 646 connector->encoder = encoder; 647 intel_mst->connector = connector; 648 first_mst_stream = intel_dp->active_mst_links == 0; 649 drm_WARN_ON(&dev_priv->drm, 650 DISPLAY_VER(dev_priv) >= 12 && first_mst_stream && 651 !intel_dp_mst_is_master_trans(pipe_config)); 652 653 drm_dbg_kms(&dev_priv->drm, "active links %d\n", 654 intel_dp->active_mst_links); 655 656 if (first_mst_stream) 657 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 658 659 drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true); 660 661 if (first_mst_stream) 662 dig_port->base.pre_enable(state, &dig_port->base, 663 pipe_config, NULL); 664 665 intel_dp->active_mst_links++; 666 667 ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state, 668 drm_atomic_get_mst_payload_state(mst_state, connector->port)); 669 if (ret < 0) 670 drm_err(&dev_priv->drm, "Failed to create MST payload for %s: %d\n", 671 connector->base.name, ret); 672 673 /* 674 * Before Gen 12 this is not done as part of 675 * dig_port->base.pre_enable() and should be done here. For 676 * Gen 12+ the step in which this should be done is different for the 677 * first MST stream, so it's done on the DDI for the first stream and 678 * here for the following ones. 679 */ 680 if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream) 681 intel_ddi_enable_pipe_clock(encoder, pipe_config); 682 683 intel_ddi_set_dp_msa(pipe_config, conn_state); 684 } 685 686 static void intel_mst_enable_dp(struct intel_atomic_state *state, 687 struct intel_encoder *encoder, 688 const struct intel_crtc_state *pipe_config, 689 const struct drm_connector_state *conn_state) 690 { 691 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 692 struct intel_digital_port *dig_port = intel_mst->primary; 693 struct intel_dp *intel_dp = &dig_port->dp; 694 struct intel_connector *connector = to_intel_connector(conn_state->connector); 695 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 696 struct drm_dp_mst_topology_state *mst_state = 697 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr); 698 enum transcoder trans = pipe_config->cpu_transcoder; 699 700 drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder); 701 702 clear_act_sent(encoder, pipe_config); 703 704 if (intel_dp_is_uhbr(pipe_config)) { 705 const struct drm_display_mode *adjusted_mode = 706 &pipe_config->hw.adjusted_mode; 707 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 708 709 intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), 710 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 711 intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder), 712 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 713 } 714 715 intel_ddi_enable_transcoder_func(encoder, pipe_config); 716 717 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, 718 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 719 720 drm_dbg_kms(&dev_priv->drm, "active links %d\n", 721 intel_dp->active_mst_links); 722 723 wait_for_act_sent(encoder, pipe_config); 724 725 drm_dp_add_payload_part2(&intel_dp->mst_mgr, &state->base, 726 drm_atomic_get_mst_payload_state(mst_state, connector->port)); 727 728 if (DISPLAY_VER(dev_priv) >= 14 && pipe_config->fec_enable) 729 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(trans), 0, 730 FECSTALL_DIS_DPTSTREAM_DPTTG); 731 else if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable) 732 intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0, 733 FECSTALL_DIS_DPTSTREAM_DPTTG); 734 735 intel_enable_transcoder(pipe_config); 736 737 intel_crtc_vblank_on(pipe_config); 738 739 intel_audio_codec_enable(encoder, pipe_config, conn_state); 740 741 /* Enable hdcp if it's desired */ 742 if (conn_state->content_protection == 743 DRM_MODE_CONTENT_PROTECTION_DESIRED) 744 intel_hdcp_enable(to_intel_connector(conn_state->connector), 745 pipe_config, 746 (u8)conn_state->hdcp_content_type); 747 } 748 749 static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder, 750 enum pipe *pipe) 751 { 752 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 753 *pipe = intel_mst->pipe; 754 if (intel_mst->connector) 755 return true; 756 return false; 757 } 758 759 static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, 760 struct intel_crtc_state *pipe_config) 761 { 762 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 763 struct intel_digital_port *dig_port = intel_mst->primary; 764 765 dig_port->base.get_config(&dig_port->base, pipe_config); 766 } 767 768 static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder, 769 struct intel_crtc_state *crtc_state) 770 { 771 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 772 struct intel_digital_port *dig_port = intel_mst->primary; 773 774 return intel_dp_initial_fastset_check(&dig_port->base, crtc_state); 775 } 776 777 static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector) 778 { 779 struct intel_connector *intel_connector = to_intel_connector(connector); 780 struct intel_dp *intel_dp = intel_connector->mst_port; 781 struct edid *edid; 782 int ret; 783 784 if (drm_connector_is_unregistered(connector)) 785 return intel_connector_update_modes(connector, NULL); 786 787 edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port); 788 ret = intel_connector_update_modes(connector, edid); 789 kfree(edid); 790 791 return ret; 792 } 793 794 static int 795 intel_dp_mst_connector_late_register(struct drm_connector *connector) 796 { 797 struct intel_connector *intel_connector = to_intel_connector(connector); 798 int ret; 799 800 ret = drm_dp_mst_connector_late_register(connector, 801 intel_connector->port); 802 if (ret < 0) 803 return ret; 804 805 ret = intel_connector_register(connector); 806 if (ret < 0) 807 drm_dp_mst_connector_early_unregister(connector, 808 intel_connector->port); 809 810 return ret; 811 } 812 813 static void 814 intel_dp_mst_connector_early_unregister(struct drm_connector *connector) 815 { 816 struct intel_connector *intel_connector = to_intel_connector(connector); 817 818 intel_connector_unregister(connector); 819 drm_dp_mst_connector_early_unregister(connector, 820 intel_connector->port); 821 } 822 823 static const struct drm_connector_funcs intel_dp_mst_connector_funcs = { 824 .fill_modes = drm_helper_probe_single_connector_modes, 825 .atomic_get_property = intel_digital_connector_atomic_get_property, 826 .atomic_set_property = intel_digital_connector_atomic_set_property, 827 .late_register = intel_dp_mst_connector_late_register, 828 .early_unregister = intel_dp_mst_connector_early_unregister, 829 .destroy = intel_connector_destroy, 830 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 831 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 832 }; 833 834 static int intel_dp_mst_get_modes(struct drm_connector *connector) 835 { 836 return intel_dp_mst_get_ddc_modes(connector); 837 } 838 839 static int 840 intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, 841 struct drm_display_mode *mode, 842 struct drm_modeset_acquire_ctx *ctx, 843 enum drm_mode_status *status) 844 { 845 struct drm_i915_private *dev_priv = to_i915(connector->dev); 846 struct intel_connector *intel_connector = to_intel_connector(connector); 847 struct intel_dp *intel_dp = intel_connector->mst_port; 848 struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr; 849 struct drm_dp_mst_port *port = intel_connector->port; 850 const int min_bpp = 18; 851 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 852 int max_rate, mode_rate, max_lanes, max_link_clock; 853 int ret; 854 bool dsc = false, bigjoiner = false; 855 u16 dsc_max_output_bpp = 0; 856 u8 dsc_slice_count = 0; 857 int target_clock = mode->clock; 858 859 if (drm_connector_is_unregistered(connector)) { 860 *status = MODE_ERROR; 861 return 0; 862 } 863 864 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { 865 *status = MODE_NO_DBLESCAN; 866 return 0; 867 } 868 869 max_link_clock = intel_dp_max_link_rate(intel_dp); 870 max_lanes = intel_dp_max_lane_count(intel_dp); 871 872 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 873 mode_rate = intel_dp_link_required(mode->clock, min_bpp); 874 875 ret = drm_modeset_lock(&mgr->base.lock, ctx); 876 if (ret) 877 return ret; 878 879 if (mode_rate > max_rate || mode->clock > max_dotclk || 880 drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) { 881 *status = MODE_CLOCK_HIGH; 882 return 0; 883 } 884 885 if (mode->clock < 10000) { 886 *status = MODE_CLOCK_LOW; 887 return 0; 888 } 889 890 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 891 *status = MODE_H_ILLEGAL; 892 return 0; 893 } 894 895 if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) { 896 bigjoiner = true; 897 max_dotclk *= 2; 898 } 899 900 if (DISPLAY_VER(dev_priv) >= 10 && 901 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { 902 /* 903 * TBD pass the connector BPC, 904 * for now U8_MAX so that max BPC on that platform would be picked 905 */ 906 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); 907 908 if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { 909 dsc_max_output_bpp = 910 intel_dp_dsc_get_output_bpp(dev_priv, 911 max_link_clock, 912 max_lanes, 913 target_clock, 914 mode->hdisplay, 915 bigjoiner, 916 pipe_bpp, 64) >> 4; 917 dsc_slice_count = 918 intel_dp_dsc_get_slice_count(intel_dp, 919 target_clock, 920 mode->hdisplay, 921 bigjoiner); 922 } 923 924 dsc = dsc_max_output_bpp && dsc_slice_count; 925 } 926 927 /* 928 * Big joiner configuration needs DSC for TGL which is not true for 929 * XE_LPD where uncompressed joiner is supported. 930 */ 931 if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc) 932 return MODE_CLOCK_HIGH; 933 934 if (mode_rate > max_rate && !dsc) 935 return MODE_CLOCK_HIGH; 936 937 *status = intel_mode_valid_max_plane_size(dev_priv, mode, false); 938 return 0; 939 } 940 941 static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector, 942 struct drm_atomic_state *state) 943 { 944 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, 945 connector); 946 struct intel_connector *intel_connector = to_intel_connector(connector); 947 struct intel_dp *intel_dp = intel_connector->mst_port; 948 struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc); 949 950 return &intel_dp->mst_encoders[crtc->pipe]->base.base; 951 } 952 953 static int 954 intel_dp_mst_detect(struct drm_connector *connector, 955 struct drm_modeset_acquire_ctx *ctx, bool force) 956 { 957 struct drm_i915_private *i915 = to_i915(connector->dev); 958 struct intel_connector *intel_connector = to_intel_connector(connector); 959 struct intel_dp *intel_dp = intel_connector->mst_port; 960 961 if (!INTEL_DISPLAY_ENABLED(i915)) 962 return connector_status_disconnected; 963 964 if (drm_connector_is_unregistered(connector)) 965 return connector_status_disconnected; 966 967 return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr, 968 intel_connector->port); 969 } 970 971 static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = { 972 .get_modes = intel_dp_mst_get_modes, 973 .mode_valid_ctx = intel_dp_mst_mode_valid_ctx, 974 .atomic_best_encoder = intel_mst_atomic_best_encoder, 975 .atomic_check = intel_dp_mst_atomic_check, 976 .detect_ctx = intel_dp_mst_detect, 977 }; 978 979 static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder) 980 { 981 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(to_intel_encoder(encoder)); 982 983 drm_encoder_cleanup(encoder); 984 kfree(intel_mst); 985 } 986 987 static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = { 988 .destroy = intel_dp_mst_encoder_destroy, 989 }; 990 991 static bool intel_dp_mst_get_hw_state(struct intel_connector *connector) 992 { 993 if (intel_attached_encoder(connector) && connector->base.state->crtc) { 994 enum pipe pipe; 995 if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe)) 996 return false; 997 return true; 998 } 999 return false; 1000 } 1001 1002 static int intel_dp_mst_add_properties(struct intel_dp *intel_dp, 1003 struct drm_connector *connector, 1004 const char *pathprop) 1005 { 1006 struct drm_i915_private *i915 = to_i915(connector->dev); 1007 1008 drm_object_attach_property(&connector->base, 1009 i915->drm.mode_config.path_property, 0); 1010 drm_object_attach_property(&connector->base, 1011 i915->drm.mode_config.tile_property, 0); 1012 1013 intel_attach_force_audio_property(connector); 1014 intel_attach_broadcast_rgb_property(connector); 1015 1016 /* 1017 * Reuse the prop from the SST connector because we're 1018 * not allowed to create new props after device registration. 1019 */ 1020 connector->max_bpc_property = 1021 intel_dp->attached_connector->base.max_bpc_property; 1022 if (connector->max_bpc_property) 1023 drm_connector_attach_max_bpc_property(connector, 6, 12); 1024 1025 return drm_connector_set_path_property(connector, pathprop); 1026 } 1027 1028 static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, 1029 struct drm_dp_mst_port *port, 1030 const char *pathprop) 1031 { 1032 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); 1033 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1034 struct drm_device *dev = dig_port->base.base.dev; 1035 struct drm_i915_private *dev_priv = to_i915(dev); 1036 struct intel_connector *intel_connector; 1037 struct drm_connector *connector; 1038 enum pipe pipe; 1039 int ret; 1040 1041 intel_connector = intel_connector_alloc(); 1042 if (!intel_connector) 1043 return NULL; 1044 1045 intel_connector->get_hw_state = intel_dp_mst_get_hw_state; 1046 intel_connector->mst_port = intel_dp; 1047 intel_connector->port = port; 1048 drm_dp_mst_get_port_malloc(port); 1049 1050 connector = &intel_connector->base; 1051 ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs, 1052 DRM_MODE_CONNECTOR_DisplayPort); 1053 if (ret) { 1054 drm_dp_mst_put_port_malloc(port); 1055 intel_connector_free(intel_connector); 1056 return NULL; 1057 } 1058 1059 drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs); 1060 1061 for_each_pipe(dev_priv, pipe) { 1062 struct drm_encoder *enc = 1063 &intel_dp->mst_encoders[pipe]->base.base; 1064 1065 ret = drm_connector_attach_encoder(&intel_connector->base, enc); 1066 if (ret) 1067 goto err; 1068 } 1069 1070 ret = intel_dp_mst_add_properties(intel_dp, connector, pathprop); 1071 if (ret) 1072 goto err; 1073 1074 ret = intel_dp_hdcp_init(dig_port, intel_connector); 1075 if (ret) 1076 drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n", 1077 connector->name, connector->base.id); 1078 1079 return connector; 1080 1081 err: 1082 drm_connector_cleanup(connector); 1083 return NULL; 1084 } 1085 1086 static void 1087 intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr) 1088 { 1089 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); 1090 1091 intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); 1092 } 1093 1094 static const struct drm_dp_mst_topology_cbs mst_cbs = { 1095 .add_connector = intel_dp_add_mst_connector, 1096 .poll_hpd_irq = intel_dp_mst_poll_hpd_irq, 1097 }; 1098 1099 static struct intel_dp_mst_encoder * 1100 intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe) 1101 { 1102 struct intel_dp_mst_encoder *intel_mst; 1103 struct intel_encoder *intel_encoder; 1104 struct drm_device *dev = dig_port->base.base.dev; 1105 1106 intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL); 1107 1108 if (!intel_mst) 1109 return NULL; 1110 1111 intel_mst->pipe = pipe; 1112 intel_encoder = &intel_mst->base; 1113 intel_mst->primary = dig_port; 1114 1115 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs, 1116 DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe)); 1117 1118 intel_encoder->type = INTEL_OUTPUT_DP_MST; 1119 intel_encoder->power_domain = dig_port->base.power_domain; 1120 intel_encoder->port = dig_port->base.port; 1121 intel_encoder->cloneable = 0; 1122 /* 1123 * This is wrong, but broken userspace uses the intersection 1124 * of possible_crtcs of all the encoders of a given connector 1125 * to figure out which crtcs can drive said connector. What 1126 * should be used instead is the union of possible_crtcs. 1127 * To keep such userspace functioning we must misconfigure 1128 * this to make sure the intersection is not empty :( 1129 */ 1130 intel_encoder->pipe_mask = ~0; 1131 1132 intel_encoder->compute_config = intel_dp_mst_compute_config; 1133 intel_encoder->compute_config_late = intel_dp_mst_compute_config_late; 1134 intel_encoder->disable = intel_mst_disable_dp; 1135 intel_encoder->post_disable = intel_mst_post_disable_dp; 1136 intel_encoder->update_pipe = intel_ddi_update_pipe; 1137 intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp; 1138 intel_encoder->pre_enable = intel_mst_pre_enable_dp; 1139 intel_encoder->enable = intel_mst_enable_dp; 1140 intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state; 1141 intel_encoder->get_config = intel_dp_mst_enc_get_config; 1142 intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check; 1143 1144 return intel_mst; 1145 1146 } 1147 1148 static bool 1149 intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port) 1150 { 1151 struct intel_dp *intel_dp = &dig_port->dp; 1152 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 1153 enum pipe pipe; 1154 1155 for_each_pipe(dev_priv, pipe) 1156 intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe); 1157 return true; 1158 } 1159 1160 int 1161 intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port) 1162 { 1163 return dig_port->dp.active_mst_links; 1164 } 1165 1166 int 1167 intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id) 1168 { 1169 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 1170 struct intel_dp *intel_dp = &dig_port->dp; 1171 enum port port = dig_port->base.port; 1172 int ret; 1173 1174 if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp)) 1175 return 0; 1176 1177 if (DISPLAY_VER(i915) < 12 && port == PORT_A) 1178 return 0; 1179 1180 if (DISPLAY_VER(i915) < 11 && port == PORT_E) 1181 return 0; 1182 1183 intel_dp->mst_mgr.cbs = &mst_cbs; 1184 1185 /* create encoders */ 1186 intel_dp_create_fake_mst_encoders(dig_port); 1187 ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, 1188 &intel_dp->aux, 16, 3, conn_base_id); 1189 if (ret) { 1190 intel_dp->mst_mgr.cbs = NULL; 1191 return ret; 1192 } 1193 1194 return 0; 1195 } 1196 1197 bool intel_dp_mst_source_support(struct intel_dp *intel_dp) 1198 { 1199 return intel_dp->mst_mgr.cbs; 1200 } 1201 1202 void 1203 intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port) 1204 { 1205 struct intel_dp *intel_dp = &dig_port->dp; 1206 1207 if (!intel_dp_mst_source_support(intel_dp)) 1208 return; 1209 1210 drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr); 1211 /* encoders will get killed by normal cleanup */ 1212 1213 intel_dp->mst_mgr.cbs = NULL; 1214 } 1215 1216 bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state) 1217 { 1218 return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder; 1219 } 1220 1221 bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state) 1222 { 1223 return crtc_state->mst_master_transcoder != INVALID_TRANSCODER && 1224 crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder; 1225 } 1226