1 /* 2 * Copyright © 2008 Intel Corporation 3 * 2014 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 22 * IN THE SOFTWARE. 23 * 24 */ 25 26 #include <drm/drm_atomic.h> 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_edid.h> 29 #include <drm/drm_probe_helper.h> 30 31 #include "i915_drv.h" 32 #include "intel_atomic.h" 33 #include "intel_audio.h" 34 #include "intel_connector.h" 35 #include "intel_crtc.h" 36 #include "intel_ddi.h" 37 #include "intel_de.h" 38 #include "intel_display_types.h" 39 #include "intel_dp.h" 40 #include "intel_dp_hdcp.h" 41 #include "intel_dp_mst.h" 42 #include "intel_dpio_phy.h" 43 #include "intel_hdcp.h" 44 #include "intel_hotplug.h" 45 #include "skl_scaler.h" 46 47 static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, 48 struct intel_crtc_state *crtc_state, 49 struct drm_connector_state *conn_state, 50 struct link_config_limits *limits) 51 { 52 struct drm_atomic_state *state = crtc_state->uapi.state; 53 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 54 struct intel_dp *intel_dp = &intel_mst->primary->dp; 55 struct intel_connector *connector = 56 to_intel_connector(conn_state->connector); 57 struct drm_i915_private *i915 = to_i915(connector->base.dev); 58 const struct drm_display_mode *adjusted_mode = 59 &crtc_state->hw.adjusted_mode; 60 bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N); 61 int bpp, slots = -EINVAL; 62 63 crtc_state->lane_count = limits->max_lane_count; 64 crtc_state->port_clock = limits->max_clock; 65 66 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { 67 crtc_state->pipe_bpp = bpp; 68 69 crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, 70 crtc_state->pipe_bpp, 71 false); 72 73 slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, 74 connector->port, 75 crtc_state->pbn, 76 drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr, 77 crtc_state->port_clock, 78 crtc_state->lane_count)); 79 if (slots == -EDEADLK) 80 return slots; 81 if (slots >= 0) 82 break; 83 } 84 85 if (slots < 0) { 86 drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n", 87 slots); 88 return slots; 89 } 90 91 intel_link_compute_m_n(crtc_state->pipe_bpp, 92 crtc_state->lane_count, 93 adjusted_mode->crtc_clock, 94 crtc_state->port_clock, 95 &crtc_state->dp_m_n, 96 constant_n, crtc_state->fec_enable); 97 crtc_state->dp_m_n.tu = slots; 98 99 return 0; 100 } 101 102 static int intel_dp_mst_compute_config(struct intel_encoder *encoder, 103 struct intel_crtc_state *pipe_config, 104 struct drm_connector_state *conn_state) 105 { 106 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 107 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 108 struct intel_dp *intel_dp = &intel_mst->primary->dp; 109 struct intel_connector *connector = 110 to_intel_connector(conn_state->connector); 111 struct intel_digital_connector_state *intel_conn_state = 112 to_intel_digital_connector_state(conn_state); 113 const struct drm_display_mode *adjusted_mode = 114 &pipe_config->hw.adjusted_mode; 115 struct link_config_limits limits; 116 int ret; 117 118 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 119 return -EINVAL; 120 121 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 122 pipe_config->has_pch_encoder = false; 123 124 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 125 pipe_config->has_audio = connector->port->has_audio; 126 else 127 pipe_config->has_audio = 128 intel_conn_state->force_audio == HDMI_AUDIO_ON; 129 130 /* 131 * for MST we always configure max link bw - the spec doesn't 132 * seem to suggest we should do otherwise. 133 */ 134 limits.min_clock = 135 limits.max_clock = intel_dp_max_link_rate(intel_dp); 136 137 limits.min_lane_count = 138 limits.max_lane_count = intel_dp_max_lane_count(intel_dp); 139 140 limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format); 141 /* 142 * FIXME: If all the streams can't fit into the link with 143 * their current pipe_bpp we should reduce pipe_bpp across 144 * the board until things start to fit. Until then we 145 * limit to <= 8bpc since that's what was hardcoded for all 146 * MST streams previously. This hack should be removed once 147 * we have the proper retry logic in place. 148 */ 149 limits.max_bpp = min(pipe_config->pipe_bpp, 24); 150 151 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); 152 153 ret = intel_dp_mst_compute_link_config(encoder, pipe_config, 154 conn_state, &limits); 155 if (ret) 156 return ret; 157 158 pipe_config->limited_color_range = 159 intel_dp_limited_color_range(pipe_config, conn_state); 160 161 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 162 pipe_config->lane_lat_optim_mask = 163 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 164 165 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 166 167 return 0; 168 } 169 170 /* 171 * Iterate over all connectors and return a mask of 172 * all CPU transcoders streaming over the same DP link. 173 */ 174 static unsigned int 175 intel_dp_mst_transcoder_mask(struct intel_atomic_state *state, 176 struct intel_dp *mst_port) 177 { 178 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 179 const struct intel_digital_connector_state *conn_state; 180 struct intel_connector *connector; 181 u8 transcoders = 0; 182 int i; 183 184 if (DISPLAY_VER(dev_priv) < 12) 185 return 0; 186 187 for_each_new_intel_connector_in_state(state, connector, conn_state, i) { 188 const struct intel_crtc_state *crtc_state; 189 struct intel_crtc *crtc; 190 191 if (connector->mst_port != mst_port || !conn_state->base.crtc) 192 continue; 193 194 crtc = to_intel_crtc(conn_state->base.crtc); 195 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 196 197 if (!crtc_state->hw.active) 198 continue; 199 200 transcoders |= BIT(crtc_state->cpu_transcoder); 201 } 202 203 return transcoders; 204 } 205 206 static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder, 207 struct intel_crtc_state *crtc_state, 208 struct drm_connector_state *conn_state) 209 { 210 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state); 211 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 212 struct intel_dp *intel_dp = &intel_mst->primary->dp; 213 214 /* lowest numbered transcoder will be designated master */ 215 crtc_state->mst_master_transcoder = 216 ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1; 217 218 return 0; 219 } 220 221 /* 222 * If one of the connectors in a MST stream needs a modeset, mark all CRTCs 223 * that shares the same MST stream as mode changed, 224 * intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do 225 * a fastset when possible. 226 */ 227 static int 228 intel_dp_mst_atomic_master_trans_check(struct intel_connector *connector, 229 struct intel_atomic_state *state) 230 { 231 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 232 struct drm_connector_list_iter connector_list_iter; 233 struct intel_connector *connector_iter; 234 235 if (DISPLAY_VER(dev_priv) < 12) 236 return 0; 237 238 if (!intel_connector_needs_modeset(state, &connector->base)) 239 return 0; 240 241 drm_connector_list_iter_begin(&dev_priv->drm, &connector_list_iter); 242 for_each_intel_connector_iter(connector_iter, &connector_list_iter) { 243 struct intel_digital_connector_state *conn_iter_state; 244 struct intel_crtc_state *crtc_state; 245 struct intel_crtc *crtc; 246 int ret; 247 248 if (connector_iter->mst_port != connector->mst_port || 249 connector_iter == connector) 250 continue; 251 252 conn_iter_state = intel_atomic_get_digital_connector_state(state, 253 connector_iter); 254 if (IS_ERR(conn_iter_state)) { 255 drm_connector_list_iter_end(&connector_list_iter); 256 return PTR_ERR(conn_iter_state); 257 } 258 259 if (!conn_iter_state->base.crtc) 260 continue; 261 262 crtc = to_intel_crtc(conn_iter_state->base.crtc); 263 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 264 if (IS_ERR(crtc_state)) { 265 drm_connector_list_iter_end(&connector_list_iter); 266 return PTR_ERR(crtc_state); 267 } 268 269 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 270 if (ret) { 271 drm_connector_list_iter_end(&connector_list_iter); 272 return ret; 273 } 274 crtc_state->uapi.mode_changed = true; 275 } 276 drm_connector_list_iter_end(&connector_list_iter); 277 278 return 0; 279 } 280 281 static int 282 intel_dp_mst_atomic_check(struct drm_connector *connector, 283 struct drm_atomic_state *_state) 284 { 285 struct intel_atomic_state *state = to_intel_atomic_state(_state); 286 struct drm_connector_state *new_conn_state = 287 drm_atomic_get_new_connector_state(&state->base, connector); 288 struct drm_connector_state *old_conn_state = 289 drm_atomic_get_old_connector_state(&state->base, connector); 290 struct intel_connector *intel_connector = 291 to_intel_connector(connector); 292 struct drm_crtc *new_crtc = new_conn_state->crtc; 293 struct drm_dp_mst_topology_mgr *mgr; 294 int ret; 295 296 ret = intel_digital_connector_atomic_check(connector, &state->base); 297 if (ret) 298 return ret; 299 300 ret = intel_dp_mst_atomic_master_trans_check(intel_connector, state); 301 if (ret) 302 return ret; 303 304 if (!old_conn_state->crtc) 305 return 0; 306 307 /* We only want to free VCPI if this state disables the CRTC on this 308 * connector 309 */ 310 if (new_crtc) { 311 struct intel_crtc *crtc = to_intel_crtc(new_crtc); 312 struct intel_crtc_state *crtc_state = 313 intel_atomic_get_new_crtc_state(state, crtc); 314 315 if (!crtc_state || 316 !drm_atomic_crtc_needs_modeset(&crtc_state->uapi) || 317 crtc_state->uapi.enable) 318 return 0; 319 } 320 321 mgr = &enc_to_mst(to_intel_encoder(old_conn_state->best_encoder))->primary->dp.mst_mgr; 322 ret = drm_dp_atomic_release_vcpi_slots(&state->base, mgr, 323 intel_connector->port); 324 325 return ret; 326 } 327 328 static void clear_act_sent(struct intel_encoder *encoder, 329 const struct intel_crtc_state *crtc_state) 330 { 331 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 332 333 intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state), 334 DP_TP_STATUS_ACT_SENT); 335 } 336 337 static void wait_for_act_sent(struct intel_encoder *encoder, 338 const struct intel_crtc_state *crtc_state) 339 { 340 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 341 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 342 struct intel_dp *intel_dp = &intel_mst->primary->dp; 343 344 if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state), 345 DP_TP_STATUS_ACT_SENT, 1)) 346 drm_err(&i915->drm, "Timed out waiting for ACT sent\n"); 347 348 drm_dp_check_act_status(&intel_dp->mst_mgr); 349 } 350 351 static void intel_mst_pre_disable_dp(struct intel_atomic_state *state, 352 struct intel_encoder *encoder, 353 const struct intel_crtc_state *old_crtc_state, 354 const struct drm_connector_state *old_conn_state) 355 { 356 if (old_crtc_state->has_audio) 357 intel_audio_codec_disable(encoder, old_crtc_state, 358 old_conn_state); 359 } 360 361 static void intel_mst_disable_dp(struct intel_atomic_state *state, 362 struct intel_encoder *encoder, 363 const struct intel_crtc_state *old_crtc_state, 364 const struct drm_connector_state *old_conn_state) 365 { 366 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 367 struct intel_digital_port *dig_port = intel_mst->primary; 368 struct intel_dp *intel_dp = &dig_port->dp; 369 struct intel_connector *connector = 370 to_intel_connector(old_conn_state->connector); 371 struct drm_i915_private *i915 = to_i915(connector->base.dev); 372 int ret; 373 374 drm_dbg_kms(&i915->drm, "active links %d\n", 375 intel_dp->active_mst_links); 376 377 intel_hdcp_disable(intel_mst->connector); 378 379 drm_dp_mst_reset_vcpi_slots(&intel_dp->mst_mgr, connector->port); 380 381 ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); 382 if (ret) { 383 drm_dbg_kms(&i915->drm, "failed to update payload %d\n", ret); 384 } 385 } 386 387 static void intel_mst_post_disable_dp(struct intel_atomic_state *state, 388 struct intel_encoder *encoder, 389 const struct intel_crtc_state *old_crtc_state, 390 const struct drm_connector_state *old_conn_state) 391 { 392 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 393 struct intel_digital_port *dig_port = intel_mst->primary; 394 struct intel_dp *intel_dp = &dig_port->dp; 395 struct intel_connector *connector = 396 to_intel_connector(old_conn_state->connector); 397 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 398 bool last_mst_stream; 399 u32 val; 400 401 intel_dp->active_mst_links--; 402 last_mst_stream = intel_dp->active_mst_links == 0; 403 drm_WARN_ON(&dev_priv->drm, 404 DISPLAY_VER(dev_priv) >= 12 && last_mst_stream && 405 !intel_dp_mst_is_master_trans(old_crtc_state)); 406 407 intel_crtc_vblank_off(old_crtc_state); 408 409 intel_disable_pipe(old_crtc_state); 410 411 drm_dp_update_payload_part2(&intel_dp->mst_mgr); 412 413 clear_act_sent(encoder, old_crtc_state); 414 415 val = intel_de_read(dev_priv, 416 TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder)); 417 val &= ~TRANS_DDI_DP_VC_PAYLOAD_ALLOC; 418 intel_de_write(dev_priv, 419 TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder), 420 val); 421 422 wait_for_act_sent(encoder, old_crtc_state); 423 424 drm_dp_mst_deallocate_vcpi(&intel_dp->mst_mgr, connector->port); 425 426 intel_ddi_disable_transcoder_func(old_crtc_state); 427 428 if (DISPLAY_VER(dev_priv) >= 9) 429 skl_scaler_disable(old_crtc_state); 430 else 431 ilk_pfit_disable(old_crtc_state); 432 433 /* 434 * Power down mst path before disabling the port, otherwise we end 435 * up getting interrupts from the sink upon detecting link loss. 436 */ 437 drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, 438 false); 439 440 /* 441 * BSpec 4287: disable DIP after the transcoder is disabled and before 442 * the transcoder clock select is set to none. 443 */ 444 if (last_mst_stream) 445 intel_dp_set_infoframes(&dig_port->base, false, 446 old_crtc_state, NULL); 447 /* 448 * From TGL spec: "If multi-stream slave transcoder: Configure 449 * Transcoder Clock Select to direct no clock to the transcoder" 450 * 451 * From older GENs spec: "Configure Transcoder Clock Select to direct 452 * no clock to the transcoder" 453 */ 454 if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream) 455 intel_ddi_disable_pipe_clock(old_crtc_state); 456 457 458 intel_mst->connector = NULL; 459 if (last_mst_stream) 460 dig_port->base.post_disable(state, &dig_port->base, 461 old_crtc_state, NULL); 462 463 drm_dbg_kms(&dev_priv->drm, "active links %d\n", 464 intel_dp->active_mst_links); 465 } 466 467 static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state, 468 struct intel_encoder *encoder, 469 const struct intel_crtc_state *pipe_config, 470 const struct drm_connector_state *conn_state) 471 { 472 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 473 struct intel_digital_port *dig_port = intel_mst->primary; 474 struct intel_dp *intel_dp = &dig_port->dp; 475 476 if (intel_dp->active_mst_links == 0) 477 dig_port->base.pre_pll_enable(state, &dig_port->base, 478 pipe_config, NULL); 479 } 480 481 static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, 482 struct intel_encoder *encoder, 483 const struct intel_crtc_state *pipe_config, 484 const struct drm_connector_state *conn_state) 485 { 486 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 487 struct intel_digital_port *dig_port = intel_mst->primary; 488 struct intel_dp *intel_dp = &dig_port->dp; 489 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 490 struct intel_connector *connector = 491 to_intel_connector(conn_state->connector); 492 int ret; 493 bool first_mst_stream; 494 495 /* MST encoders are bound to a crtc, not to a connector, 496 * force the mapping here for get_hw_state. 497 */ 498 connector->encoder = encoder; 499 intel_mst->connector = connector; 500 first_mst_stream = intel_dp->active_mst_links == 0; 501 drm_WARN_ON(&dev_priv->drm, 502 DISPLAY_VER(dev_priv) >= 12 && first_mst_stream && 503 !intel_dp_mst_is_master_trans(pipe_config)); 504 505 drm_dbg_kms(&dev_priv->drm, "active links %d\n", 506 intel_dp->active_mst_links); 507 508 if (first_mst_stream) 509 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 510 511 drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true); 512 513 if (first_mst_stream) 514 dig_port->base.pre_enable(state, &dig_port->base, 515 pipe_config, NULL); 516 517 ret = drm_dp_mst_allocate_vcpi(&intel_dp->mst_mgr, 518 connector->port, 519 pipe_config->pbn, 520 pipe_config->dp_m_n.tu); 521 if (!ret) 522 drm_err(&dev_priv->drm, "failed to allocate vcpi\n"); 523 524 intel_dp->active_mst_links++; 525 526 ret = drm_dp_update_payload_part1(&intel_dp->mst_mgr); 527 528 /* 529 * Before Gen 12 this is not done as part of 530 * dig_port->base.pre_enable() and should be done here. For 531 * Gen 12+ the step in which this should be done is different for the 532 * first MST stream, so it's done on the DDI for the first stream and 533 * here for the following ones. 534 */ 535 if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream) 536 intel_ddi_enable_pipe_clock(encoder, pipe_config); 537 538 intel_ddi_set_dp_msa(pipe_config, conn_state); 539 540 intel_dp_set_m_n(pipe_config, M1_N1); 541 } 542 543 static void intel_mst_enable_dp(struct intel_atomic_state *state, 544 struct intel_encoder *encoder, 545 const struct intel_crtc_state *pipe_config, 546 const struct drm_connector_state *conn_state) 547 { 548 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 549 struct intel_digital_port *dig_port = intel_mst->primary; 550 struct intel_dp *intel_dp = &dig_port->dp; 551 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 552 enum transcoder trans = pipe_config->cpu_transcoder; 553 554 drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder); 555 556 clear_act_sent(encoder, pipe_config); 557 558 intel_ddi_enable_transcoder_func(encoder, pipe_config); 559 560 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, 561 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 562 563 drm_dbg_kms(&dev_priv->drm, "active links %d\n", 564 intel_dp->active_mst_links); 565 566 wait_for_act_sent(encoder, pipe_config); 567 568 drm_dp_update_payload_part2(&intel_dp->mst_mgr); 569 570 if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable) 571 intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0, 572 FECSTALL_DIS_DPTSTREAM_DPTTG); 573 574 intel_enable_pipe(pipe_config); 575 576 intel_crtc_vblank_on(pipe_config); 577 578 if (pipe_config->has_audio) 579 intel_audio_codec_enable(encoder, pipe_config, conn_state); 580 581 /* Enable hdcp if it's desired */ 582 if (conn_state->content_protection == 583 DRM_MODE_CONTENT_PROTECTION_DESIRED) 584 intel_hdcp_enable(to_intel_connector(conn_state->connector), 585 pipe_config, 586 (u8)conn_state->hdcp_content_type); 587 } 588 589 static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder, 590 enum pipe *pipe) 591 { 592 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 593 *pipe = intel_mst->pipe; 594 if (intel_mst->connector) 595 return true; 596 return false; 597 } 598 599 static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, 600 struct intel_crtc_state *pipe_config) 601 { 602 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 603 struct intel_digital_port *dig_port = intel_mst->primary; 604 605 dig_port->base.get_config(&dig_port->base, pipe_config); 606 } 607 608 static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder, 609 struct intel_crtc_state *crtc_state) 610 { 611 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 612 struct intel_digital_port *dig_port = intel_mst->primary; 613 614 return intel_dp_initial_fastset_check(&dig_port->base, crtc_state); 615 } 616 617 static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector) 618 { 619 struct intel_connector *intel_connector = to_intel_connector(connector); 620 struct intel_dp *intel_dp = intel_connector->mst_port; 621 struct edid *edid; 622 int ret; 623 624 if (drm_connector_is_unregistered(connector)) 625 return intel_connector_update_modes(connector, NULL); 626 627 edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port); 628 ret = intel_connector_update_modes(connector, edid); 629 kfree(edid); 630 631 return ret; 632 } 633 634 static int 635 intel_dp_mst_connector_late_register(struct drm_connector *connector) 636 { 637 struct intel_connector *intel_connector = to_intel_connector(connector); 638 int ret; 639 640 ret = drm_dp_mst_connector_late_register(connector, 641 intel_connector->port); 642 if (ret < 0) 643 return ret; 644 645 ret = intel_connector_register(connector); 646 if (ret < 0) 647 drm_dp_mst_connector_early_unregister(connector, 648 intel_connector->port); 649 650 return ret; 651 } 652 653 static void 654 intel_dp_mst_connector_early_unregister(struct drm_connector *connector) 655 { 656 struct intel_connector *intel_connector = to_intel_connector(connector); 657 658 intel_connector_unregister(connector); 659 drm_dp_mst_connector_early_unregister(connector, 660 intel_connector->port); 661 } 662 663 static const struct drm_connector_funcs intel_dp_mst_connector_funcs = { 664 .fill_modes = drm_helper_probe_single_connector_modes, 665 .atomic_get_property = intel_digital_connector_atomic_get_property, 666 .atomic_set_property = intel_digital_connector_atomic_set_property, 667 .late_register = intel_dp_mst_connector_late_register, 668 .early_unregister = intel_dp_mst_connector_early_unregister, 669 .destroy = intel_connector_destroy, 670 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 671 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 672 }; 673 674 static int intel_dp_mst_get_modes(struct drm_connector *connector) 675 { 676 return intel_dp_mst_get_ddc_modes(connector); 677 } 678 679 static int 680 intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, 681 struct drm_display_mode *mode, 682 struct drm_modeset_acquire_ctx *ctx, 683 enum drm_mode_status *status) 684 { 685 struct drm_i915_private *dev_priv = to_i915(connector->dev); 686 struct intel_connector *intel_connector = to_intel_connector(connector); 687 struct intel_dp *intel_dp = intel_connector->mst_port; 688 struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr; 689 struct drm_dp_mst_port *port = intel_connector->port; 690 const int min_bpp = 18; 691 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 692 int max_rate, mode_rate, max_lanes, max_link_clock; 693 int ret; 694 695 if (drm_connector_is_unregistered(connector)) { 696 *status = MODE_ERROR; 697 return 0; 698 } 699 700 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { 701 *status = MODE_NO_DBLESCAN; 702 return 0; 703 } 704 705 max_link_clock = intel_dp_max_link_rate(intel_dp); 706 max_lanes = intel_dp_max_lane_count(intel_dp); 707 708 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 709 mode_rate = intel_dp_link_required(mode->clock, min_bpp); 710 711 ret = drm_modeset_lock(&mgr->base.lock, ctx); 712 if (ret) 713 return ret; 714 715 if (mode_rate > max_rate || mode->clock > max_dotclk || 716 drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) { 717 *status = MODE_CLOCK_HIGH; 718 return 0; 719 } 720 721 if (mode->clock < 10000) { 722 *status = MODE_CLOCK_LOW; 723 return 0; 724 } 725 726 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 727 *status = MODE_H_ILLEGAL; 728 return 0; 729 } 730 731 *status = intel_mode_valid_max_plane_size(dev_priv, mode, false); 732 return 0; 733 } 734 735 static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector, 736 struct drm_atomic_state *state) 737 { 738 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, 739 connector); 740 struct intel_connector *intel_connector = to_intel_connector(connector); 741 struct intel_dp *intel_dp = intel_connector->mst_port; 742 struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc); 743 744 return &intel_dp->mst_encoders[crtc->pipe]->base.base; 745 } 746 747 static int 748 intel_dp_mst_detect(struct drm_connector *connector, 749 struct drm_modeset_acquire_ctx *ctx, bool force) 750 { 751 struct drm_i915_private *i915 = to_i915(connector->dev); 752 struct intel_connector *intel_connector = to_intel_connector(connector); 753 struct intel_dp *intel_dp = intel_connector->mst_port; 754 755 if (!INTEL_DISPLAY_ENABLED(i915)) 756 return connector_status_disconnected; 757 758 if (drm_connector_is_unregistered(connector)) 759 return connector_status_disconnected; 760 761 return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr, 762 intel_connector->port); 763 } 764 765 static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = { 766 .get_modes = intel_dp_mst_get_modes, 767 .mode_valid_ctx = intel_dp_mst_mode_valid_ctx, 768 .atomic_best_encoder = intel_mst_atomic_best_encoder, 769 .atomic_check = intel_dp_mst_atomic_check, 770 .detect_ctx = intel_dp_mst_detect, 771 }; 772 773 static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder) 774 { 775 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(to_intel_encoder(encoder)); 776 777 drm_encoder_cleanup(encoder); 778 kfree(intel_mst); 779 } 780 781 static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = { 782 .destroy = intel_dp_mst_encoder_destroy, 783 }; 784 785 static bool intel_dp_mst_get_hw_state(struct intel_connector *connector) 786 { 787 if (intel_attached_encoder(connector) && connector->base.state->crtc) { 788 enum pipe pipe; 789 if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe)) 790 return false; 791 return true; 792 } 793 return false; 794 } 795 796 static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, struct drm_dp_mst_port *port, const char *pathprop) 797 { 798 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); 799 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 800 struct drm_device *dev = dig_port->base.base.dev; 801 struct drm_i915_private *dev_priv = to_i915(dev); 802 struct intel_connector *intel_connector; 803 struct drm_connector *connector; 804 enum pipe pipe; 805 int ret; 806 807 intel_connector = intel_connector_alloc(); 808 if (!intel_connector) 809 return NULL; 810 811 intel_connector->get_hw_state = intel_dp_mst_get_hw_state; 812 intel_connector->mst_port = intel_dp; 813 intel_connector->port = port; 814 drm_dp_mst_get_port_malloc(port); 815 816 connector = &intel_connector->base; 817 ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs, 818 DRM_MODE_CONNECTOR_DisplayPort); 819 if (ret) { 820 intel_connector_free(intel_connector); 821 return NULL; 822 } 823 824 drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs); 825 826 for_each_pipe(dev_priv, pipe) { 827 struct drm_encoder *enc = 828 &intel_dp->mst_encoders[pipe]->base.base; 829 830 ret = drm_connector_attach_encoder(&intel_connector->base, enc); 831 if (ret) 832 goto err; 833 } 834 835 drm_object_attach_property(&connector->base, dev->mode_config.path_property, 0); 836 drm_object_attach_property(&connector->base, dev->mode_config.tile_property, 0); 837 838 ret = drm_connector_set_path_property(connector, pathprop); 839 if (ret) 840 goto err; 841 842 intel_attach_force_audio_property(connector); 843 intel_attach_broadcast_rgb_property(connector); 844 845 ret = intel_dp_hdcp_init(dig_port, intel_connector); 846 if (ret) 847 drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n", 848 connector->name, connector->base.id); 849 /* 850 * Reuse the prop from the SST connector because we're 851 * not allowed to create new props after device registration. 852 */ 853 connector->max_bpc_property = 854 intel_dp->attached_connector->base.max_bpc_property; 855 if (connector->max_bpc_property) 856 drm_connector_attach_max_bpc_property(connector, 6, 12); 857 858 return connector; 859 860 err: 861 drm_connector_cleanup(connector); 862 return NULL; 863 } 864 865 static void 866 intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr) 867 { 868 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); 869 870 intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); 871 } 872 873 static const struct drm_dp_mst_topology_cbs mst_cbs = { 874 .add_connector = intel_dp_add_mst_connector, 875 .poll_hpd_irq = intel_dp_mst_poll_hpd_irq, 876 }; 877 878 static struct intel_dp_mst_encoder * 879 intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe) 880 { 881 struct intel_dp_mst_encoder *intel_mst; 882 struct intel_encoder *intel_encoder; 883 struct drm_device *dev = dig_port->base.base.dev; 884 885 intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL); 886 887 if (!intel_mst) 888 return NULL; 889 890 intel_mst->pipe = pipe; 891 intel_encoder = &intel_mst->base; 892 intel_mst->primary = dig_port; 893 894 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs, 895 DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe)); 896 897 intel_encoder->type = INTEL_OUTPUT_DP_MST; 898 intel_encoder->power_domain = dig_port->base.power_domain; 899 intel_encoder->port = dig_port->base.port; 900 intel_encoder->cloneable = 0; 901 /* 902 * This is wrong, but broken userspace uses the intersection 903 * of possible_crtcs of all the encoders of a given connector 904 * to figure out which crtcs can drive said connector. What 905 * should be used instead is the union of possible_crtcs. 906 * To keep such userspace functioning we must misconfigure 907 * this to make sure the intersection is not empty :( 908 */ 909 intel_encoder->pipe_mask = ~0; 910 911 intel_encoder->compute_config = intel_dp_mst_compute_config; 912 intel_encoder->compute_config_late = intel_dp_mst_compute_config_late; 913 intel_encoder->pre_disable = intel_mst_pre_disable_dp; 914 intel_encoder->disable = intel_mst_disable_dp; 915 intel_encoder->post_disable = intel_mst_post_disable_dp; 916 intel_encoder->update_pipe = intel_ddi_update_pipe; 917 intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp; 918 intel_encoder->pre_enable = intel_mst_pre_enable_dp; 919 intel_encoder->enable = intel_mst_enable_dp; 920 intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state; 921 intel_encoder->get_config = intel_dp_mst_enc_get_config; 922 intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check; 923 924 return intel_mst; 925 926 } 927 928 static bool 929 intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port) 930 { 931 struct intel_dp *intel_dp = &dig_port->dp; 932 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 933 enum pipe pipe; 934 935 for_each_pipe(dev_priv, pipe) 936 intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe); 937 return true; 938 } 939 940 int 941 intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port) 942 { 943 return dig_port->dp.active_mst_links; 944 } 945 946 int 947 intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id) 948 { 949 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 950 struct intel_dp *intel_dp = &dig_port->dp; 951 enum port port = dig_port->base.port; 952 int ret; 953 int max_source_rate = 954 intel_dp->source_rates[intel_dp->num_source_rates - 1]; 955 956 if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp)) 957 return 0; 958 959 if (DISPLAY_VER(i915) < 12 && port == PORT_A) 960 return 0; 961 962 if (DISPLAY_VER(i915) < 11 && port == PORT_E) 963 return 0; 964 965 intel_dp->mst_mgr.cbs = &mst_cbs; 966 967 /* create encoders */ 968 intel_dp_create_fake_mst_encoders(dig_port); 969 ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, 970 &intel_dp->aux, 16, 3, 971 dig_port->max_lanes, 972 max_source_rate, 973 conn_base_id); 974 if (ret) 975 return ret; 976 977 intel_dp->can_mst = true; 978 979 return 0; 980 } 981 982 void 983 intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port) 984 { 985 struct intel_dp *intel_dp = &dig_port->dp; 986 987 if (!intel_dp->can_mst) 988 return; 989 990 drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr); 991 /* encoders will get killed by normal cleanup */ 992 } 993 994 bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state) 995 { 996 return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder; 997 } 998 999 bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state) 1000 { 1001 return crtc_state->mst_master_transcoder != INVALID_TRANSCODER && 1002 crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder; 1003 } 1004