1 /* 2 * Copyright © 2008 Intel Corporation 3 * 2014 Red Hat Inc. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the next 13 * paragraph) shall be included in all copies or substantial portions of the 14 * Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 22 * IN THE SOFTWARE. 23 * 24 */ 25 26 #include <drm/drm_atomic.h> 27 #include <drm/drm_atomic_helper.h> 28 #include <drm/drm_edid.h> 29 #include <drm/drm_probe_helper.h> 30 31 #include "i915_drv.h" 32 #include "i915_reg.h" 33 #include "intel_atomic.h" 34 #include "intel_audio.h" 35 #include "intel_connector.h" 36 #include "intel_crtc.h" 37 #include "intel_ddi.h" 38 #include "intel_de.h" 39 #include "intel_display_types.h" 40 #include "intel_dp.h" 41 #include "intel_dp_hdcp.h" 42 #include "intel_dp_mst.h" 43 #include "intel_dpio_phy.h" 44 #include "intel_hdcp.h" 45 #include "intel_hotplug.h" 46 #include "skl_scaler.h" 47 48 static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, 49 struct intel_crtc_state *crtc_state, 50 struct drm_connector_state *conn_state, 51 struct link_config_limits *limits) 52 { 53 struct drm_atomic_state *state = crtc_state->uapi.state; 54 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 55 struct intel_dp *intel_dp = &intel_mst->primary->dp; 56 struct drm_dp_mst_topology_state *mst_state; 57 struct intel_connector *connector = 58 to_intel_connector(conn_state->connector); 59 struct drm_i915_private *i915 = to_i915(connector->base.dev); 60 const struct drm_display_mode *adjusted_mode = 61 &crtc_state->hw.adjusted_mode; 62 int bpp, slots = -EINVAL; 63 64 mst_state = drm_atomic_get_mst_topology_state(state, &intel_dp->mst_mgr); 65 if (IS_ERR(mst_state)) 66 return PTR_ERR(mst_state); 67 68 crtc_state->lane_count = limits->max_lane_count; 69 crtc_state->port_clock = limits->max_rate; 70 71 // TODO: Handle pbn_div changes by adding a new MST helper 72 if (!mst_state->pbn_div) { 73 mst_state->pbn_div = drm_dp_get_vc_payload_bw(&intel_dp->mst_mgr, 74 limits->max_rate, 75 limits->max_lane_count); 76 } 77 78 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { 79 crtc_state->pipe_bpp = bpp; 80 81 crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, 82 crtc_state->pipe_bpp, 83 false); 84 slots = drm_dp_atomic_find_time_slots(state, &intel_dp->mst_mgr, 85 connector->port, crtc_state->pbn); 86 if (slots == -EDEADLK) 87 return slots; 88 if (slots >= 0) 89 break; 90 } 91 92 if (slots < 0) { 93 drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n", 94 slots); 95 return slots; 96 } 97 98 intel_link_compute_m_n(crtc_state->pipe_bpp, 99 crtc_state->lane_count, 100 adjusted_mode->crtc_clock, 101 crtc_state->port_clock, 102 &crtc_state->dp_m_n, 103 crtc_state->fec_enable); 104 crtc_state->dp_m_n.tu = slots; 105 106 return 0; 107 } 108 109 static int intel_dp_mst_update_slots(struct intel_encoder *encoder, 110 struct intel_crtc_state *crtc_state, 111 struct drm_connector_state *conn_state) 112 { 113 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 114 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 115 struct intel_dp *intel_dp = &intel_mst->primary->dp; 116 struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr; 117 struct drm_dp_mst_topology_state *topology_state; 118 u8 link_coding_cap = intel_dp_is_uhbr(crtc_state) ? 119 DP_CAP_ANSI_128B132B : DP_CAP_ANSI_8B10B; 120 121 topology_state = drm_atomic_get_mst_topology_state(conn_state->state, mgr); 122 if (IS_ERR(topology_state)) { 123 drm_dbg_kms(&i915->drm, "slot update failed\n"); 124 return PTR_ERR(topology_state); 125 } 126 127 drm_dp_mst_update_slots(topology_state, link_coding_cap); 128 129 return 0; 130 } 131 132 static int intel_dp_mst_compute_config(struct intel_encoder *encoder, 133 struct intel_crtc_state *pipe_config, 134 struct drm_connector_state *conn_state) 135 { 136 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 137 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 138 struct intel_dp *intel_dp = &intel_mst->primary->dp; 139 struct intel_connector *connector = 140 to_intel_connector(conn_state->connector); 141 struct intel_digital_connector_state *intel_conn_state = 142 to_intel_digital_connector_state(conn_state); 143 const struct drm_display_mode *adjusted_mode = 144 &pipe_config->hw.adjusted_mode; 145 struct link_config_limits limits; 146 int ret; 147 148 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 149 return -EINVAL; 150 151 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 152 pipe_config->has_pch_encoder = false; 153 154 if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 155 pipe_config->has_audio = connector->port->has_audio; 156 else 157 pipe_config->has_audio = 158 intel_conn_state->force_audio == HDMI_AUDIO_ON; 159 160 /* 161 * for MST we always configure max link bw - the spec doesn't 162 * seem to suggest we should do otherwise. 163 */ 164 limits.min_rate = 165 limits.max_rate = intel_dp_max_link_rate(intel_dp); 166 167 limits.min_lane_count = 168 limits.max_lane_count = intel_dp_max_lane_count(intel_dp); 169 170 limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format); 171 /* 172 * FIXME: If all the streams can't fit into the link with 173 * their current pipe_bpp we should reduce pipe_bpp across 174 * the board until things start to fit. Until then we 175 * limit to <= 8bpc since that's what was hardcoded for all 176 * MST streams previously. This hack should be removed once 177 * we have the proper retry logic in place. 178 */ 179 limits.max_bpp = min(pipe_config->pipe_bpp, 24); 180 181 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); 182 183 ret = intel_dp_mst_compute_link_config(encoder, pipe_config, 184 conn_state, &limits); 185 if (ret) 186 return ret; 187 188 ret = intel_dp_mst_update_slots(encoder, pipe_config, conn_state); 189 if (ret) 190 return ret; 191 192 pipe_config->limited_color_range = 193 intel_dp_limited_color_range(pipe_config, conn_state); 194 195 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 196 pipe_config->lane_lat_optim_mask = 197 bxt_ddi_phy_calc_lane_lat_optim_mask(pipe_config->lane_count); 198 199 intel_ddi_compute_min_voltage_level(dev_priv, pipe_config); 200 201 return 0; 202 } 203 204 /* 205 * Iterate over all connectors and return a mask of 206 * all CPU transcoders streaming over the same DP link. 207 */ 208 static unsigned int 209 intel_dp_mst_transcoder_mask(struct intel_atomic_state *state, 210 struct intel_dp *mst_port) 211 { 212 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 213 const struct intel_digital_connector_state *conn_state; 214 struct intel_connector *connector; 215 u8 transcoders = 0; 216 int i; 217 218 if (DISPLAY_VER(dev_priv) < 12) 219 return 0; 220 221 for_each_new_intel_connector_in_state(state, connector, conn_state, i) { 222 const struct intel_crtc_state *crtc_state; 223 struct intel_crtc *crtc; 224 225 if (connector->mst_port != mst_port || !conn_state->base.crtc) 226 continue; 227 228 crtc = to_intel_crtc(conn_state->base.crtc); 229 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 230 231 if (!crtc_state->hw.active) 232 continue; 233 234 transcoders |= BIT(crtc_state->cpu_transcoder); 235 } 236 237 return transcoders; 238 } 239 240 static int intel_dp_mst_compute_config_late(struct intel_encoder *encoder, 241 struct intel_crtc_state *crtc_state, 242 struct drm_connector_state *conn_state) 243 { 244 struct intel_atomic_state *state = to_intel_atomic_state(conn_state->state); 245 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 246 struct intel_dp *intel_dp = &intel_mst->primary->dp; 247 248 /* lowest numbered transcoder will be designated master */ 249 crtc_state->mst_master_transcoder = 250 ffs(intel_dp_mst_transcoder_mask(state, intel_dp)) - 1; 251 252 return 0; 253 } 254 255 /* 256 * If one of the connectors in a MST stream needs a modeset, mark all CRTCs 257 * that shares the same MST stream as mode changed, 258 * intel_modeset_pipe_config()+intel_crtc_check_fastset() will take care to do 259 * a fastset when possible. 260 */ 261 static int 262 intel_dp_mst_atomic_master_trans_check(struct intel_connector *connector, 263 struct intel_atomic_state *state) 264 { 265 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 266 struct drm_connector_list_iter connector_list_iter; 267 struct intel_connector *connector_iter; 268 int ret = 0; 269 270 if (DISPLAY_VER(dev_priv) < 12) 271 return 0; 272 273 if (!intel_connector_needs_modeset(state, &connector->base)) 274 return 0; 275 276 drm_connector_list_iter_begin(&dev_priv->drm, &connector_list_iter); 277 for_each_intel_connector_iter(connector_iter, &connector_list_iter) { 278 struct intel_digital_connector_state *conn_iter_state; 279 struct intel_crtc_state *crtc_state; 280 struct intel_crtc *crtc; 281 282 if (connector_iter->mst_port != connector->mst_port || 283 connector_iter == connector) 284 continue; 285 286 conn_iter_state = intel_atomic_get_digital_connector_state(state, 287 connector_iter); 288 if (IS_ERR(conn_iter_state)) { 289 ret = PTR_ERR(conn_iter_state); 290 break; 291 } 292 293 if (!conn_iter_state->base.crtc) 294 continue; 295 296 crtc = to_intel_crtc(conn_iter_state->base.crtc); 297 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 298 if (IS_ERR(crtc_state)) { 299 ret = PTR_ERR(crtc_state); 300 break; 301 } 302 303 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 304 if (ret) 305 break; 306 crtc_state->uapi.mode_changed = true; 307 } 308 drm_connector_list_iter_end(&connector_list_iter); 309 310 return ret; 311 } 312 313 static int 314 intel_dp_mst_atomic_check(struct drm_connector *connector, 315 struct drm_atomic_state *_state) 316 { 317 struct intel_atomic_state *state = to_intel_atomic_state(_state); 318 struct intel_connector *intel_connector = 319 to_intel_connector(connector); 320 int ret; 321 322 ret = intel_digital_connector_atomic_check(connector, &state->base); 323 if (ret) 324 return ret; 325 326 ret = intel_dp_mst_atomic_master_trans_check(intel_connector, state); 327 if (ret) 328 return ret; 329 330 return drm_dp_atomic_release_time_slots(&state->base, 331 &intel_connector->mst_port->mst_mgr, 332 intel_connector->port); 333 } 334 335 static void clear_act_sent(struct intel_encoder *encoder, 336 const struct intel_crtc_state *crtc_state) 337 { 338 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 339 340 intel_de_write(i915, dp_tp_status_reg(encoder, crtc_state), 341 DP_TP_STATUS_ACT_SENT); 342 } 343 344 static void wait_for_act_sent(struct intel_encoder *encoder, 345 const struct intel_crtc_state *crtc_state) 346 { 347 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 348 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 349 struct intel_dp *intel_dp = &intel_mst->primary->dp; 350 351 if (intel_de_wait_for_set(i915, dp_tp_status_reg(encoder, crtc_state), 352 DP_TP_STATUS_ACT_SENT, 1)) 353 drm_err(&i915->drm, "Timed out waiting for ACT sent\n"); 354 355 drm_dp_check_act_status(&intel_dp->mst_mgr); 356 } 357 358 static void intel_mst_disable_dp(struct intel_atomic_state *state, 359 struct intel_encoder *encoder, 360 const struct intel_crtc_state *old_crtc_state, 361 const struct drm_connector_state *old_conn_state) 362 { 363 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 364 struct intel_digital_port *dig_port = intel_mst->primary; 365 struct intel_dp *intel_dp = &dig_port->dp; 366 struct intel_connector *connector = 367 to_intel_connector(old_conn_state->connector); 368 struct drm_dp_mst_topology_state *mst_state = 369 drm_atomic_get_mst_topology_state(&state->base, &intel_dp->mst_mgr); 370 struct drm_i915_private *i915 = to_i915(connector->base.dev); 371 372 drm_dbg_kms(&i915->drm, "active links %d\n", 373 intel_dp->active_mst_links); 374 375 intel_hdcp_disable(intel_mst->connector); 376 377 drm_dp_remove_payload(&intel_dp->mst_mgr, mst_state, 378 drm_atomic_get_mst_payload_state(mst_state, connector->port)); 379 380 intel_audio_codec_disable(encoder, old_crtc_state, old_conn_state); 381 } 382 383 static void intel_mst_post_disable_dp(struct intel_atomic_state *state, 384 struct intel_encoder *encoder, 385 const struct intel_crtc_state *old_crtc_state, 386 const struct drm_connector_state *old_conn_state) 387 { 388 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 389 struct intel_digital_port *dig_port = intel_mst->primary; 390 struct intel_dp *intel_dp = &dig_port->dp; 391 struct intel_connector *connector = 392 to_intel_connector(old_conn_state->connector); 393 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 394 bool last_mst_stream; 395 396 intel_dp->active_mst_links--; 397 last_mst_stream = intel_dp->active_mst_links == 0; 398 drm_WARN_ON(&dev_priv->drm, 399 DISPLAY_VER(dev_priv) >= 12 && last_mst_stream && 400 !intel_dp_mst_is_master_trans(old_crtc_state)); 401 402 intel_crtc_vblank_off(old_crtc_state); 403 404 intel_disable_transcoder(old_crtc_state); 405 406 clear_act_sent(encoder, old_crtc_state); 407 408 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(old_crtc_state->cpu_transcoder), 409 TRANS_DDI_DP_VC_PAYLOAD_ALLOC, 0); 410 411 wait_for_act_sent(encoder, old_crtc_state); 412 413 intel_ddi_disable_transcoder_func(old_crtc_state); 414 415 if (DISPLAY_VER(dev_priv) >= 9) 416 skl_scaler_disable(old_crtc_state); 417 else 418 ilk_pfit_disable(old_crtc_state); 419 420 /* 421 * Power down mst path before disabling the port, otherwise we end 422 * up getting interrupts from the sink upon detecting link loss. 423 */ 424 drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, 425 false); 426 427 /* 428 * BSpec 4287: disable DIP after the transcoder is disabled and before 429 * the transcoder clock select is set to none. 430 */ 431 if (last_mst_stream) 432 intel_dp_set_infoframes(&dig_port->base, false, 433 old_crtc_state, NULL); 434 /* 435 * From TGL spec: "If multi-stream slave transcoder: Configure 436 * Transcoder Clock Select to direct no clock to the transcoder" 437 * 438 * From older GENs spec: "Configure Transcoder Clock Select to direct 439 * no clock to the transcoder" 440 */ 441 if (DISPLAY_VER(dev_priv) < 12 || !last_mst_stream) 442 intel_ddi_disable_pipe_clock(old_crtc_state); 443 444 445 intel_mst->connector = NULL; 446 if (last_mst_stream) 447 dig_port->base.post_disable(state, &dig_port->base, 448 old_crtc_state, NULL); 449 450 drm_dbg_kms(&dev_priv->drm, "active links %d\n", 451 intel_dp->active_mst_links); 452 } 453 454 static void intel_mst_pre_pll_enable_dp(struct intel_atomic_state *state, 455 struct intel_encoder *encoder, 456 const struct intel_crtc_state *pipe_config, 457 const struct drm_connector_state *conn_state) 458 { 459 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 460 struct intel_digital_port *dig_port = intel_mst->primary; 461 struct intel_dp *intel_dp = &dig_port->dp; 462 463 if (intel_dp->active_mst_links == 0) 464 dig_port->base.pre_pll_enable(state, &dig_port->base, 465 pipe_config, NULL); 466 } 467 468 static void intel_mst_pre_enable_dp(struct intel_atomic_state *state, 469 struct intel_encoder *encoder, 470 const struct intel_crtc_state *pipe_config, 471 const struct drm_connector_state *conn_state) 472 { 473 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 474 struct intel_digital_port *dig_port = intel_mst->primary; 475 struct intel_dp *intel_dp = &dig_port->dp; 476 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 477 struct intel_connector *connector = 478 to_intel_connector(conn_state->connector); 479 struct drm_dp_mst_topology_state *mst_state = 480 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr); 481 int ret; 482 bool first_mst_stream; 483 484 /* MST encoders are bound to a crtc, not to a connector, 485 * force the mapping here for get_hw_state. 486 */ 487 connector->encoder = encoder; 488 intel_mst->connector = connector; 489 first_mst_stream = intel_dp->active_mst_links == 0; 490 drm_WARN_ON(&dev_priv->drm, 491 DISPLAY_VER(dev_priv) >= 12 && first_mst_stream && 492 !intel_dp_mst_is_master_trans(pipe_config)); 493 494 drm_dbg_kms(&dev_priv->drm, "active links %d\n", 495 intel_dp->active_mst_links); 496 497 if (first_mst_stream) 498 intel_dp_set_power(intel_dp, DP_SET_POWER_D0); 499 500 drm_dp_send_power_updown_phy(&intel_dp->mst_mgr, connector->port, true); 501 502 if (first_mst_stream) 503 dig_port->base.pre_enable(state, &dig_port->base, 504 pipe_config, NULL); 505 506 intel_dp->active_mst_links++; 507 508 ret = drm_dp_add_payload_part1(&intel_dp->mst_mgr, mst_state, 509 drm_atomic_get_mst_payload_state(mst_state, connector->port)); 510 if (ret < 0) 511 drm_err(&dev_priv->drm, "Failed to create MST payload for %s: %d\n", 512 connector->base.name, ret); 513 514 /* 515 * Before Gen 12 this is not done as part of 516 * dig_port->base.pre_enable() and should be done here. For 517 * Gen 12+ the step in which this should be done is different for the 518 * first MST stream, so it's done on the DDI for the first stream and 519 * here for the following ones. 520 */ 521 if (DISPLAY_VER(dev_priv) < 12 || !first_mst_stream) 522 intel_ddi_enable_pipe_clock(encoder, pipe_config); 523 524 intel_ddi_set_dp_msa(pipe_config, conn_state); 525 } 526 527 static void intel_mst_enable_dp(struct intel_atomic_state *state, 528 struct intel_encoder *encoder, 529 const struct intel_crtc_state *pipe_config, 530 const struct drm_connector_state *conn_state) 531 { 532 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 533 struct intel_digital_port *dig_port = intel_mst->primary; 534 struct intel_dp *intel_dp = &dig_port->dp; 535 struct intel_connector *connector = to_intel_connector(conn_state->connector); 536 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 537 struct drm_dp_mst_topology_state *mst_state = 538 drm_atomic_get_new_mst_topology_state(&state->base, &intel_dp->mst_mgr); 539 enum transcoder trans = pipe_config->cpu_transcoder; 540 541 drm_WARN_ON(&dev_priv->drm, pipe_config->has_pch_encoder); 542 543 clear_act_sent(encoder, pipe_config); 544 545 if (intel_dp_is_uhbr(pipe_config)) { 546 const struct drm_display_mode *adjusted_mode = 547 &pipe_config->hw.adjusted_mode; 548 u64 crtc_clock_hz = KHz(adjusted_mode->crtc_clock); 549 550 intel_de_write(dev_priv, TRANS_DP2_VFREQHIGH(pipe_config->cpu_transcoder), 551 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz >> 24)); 552 intel_de_write(dev_priv, TRANS_DP2_VFREQLOW(pipe_config->cpu_transcoder), 553 TRANS_DP2_VFREQ_PIXEL_CLOCK(crtc_clock_hz & 0xffffff)); 554 } 555 556 intel_ddi_enable_transcoder_func(encoder, pipe_config); 557 558 intel_de_rmw(dev_priv, TRANS_DDI_FUNC_CTL(trans), 0, 559 TRANS_DDI_DP_VC_PAYLOAD_ALLOC); 560 561 drm_dbg_kms(&dev_priv->drm, "active links %d\n", 562 intel_dp->active_mst_links); 563 564 wait_for_act_sent(encoder, pipe_config); 565 566 drm_dp_add_payload_part2(&intel_dp->mst_mgr, &state->base, 567 drm_atomic_get_mst_payload_state(mst_state, connector->port)); 568 569 if (DISPLAY_VER(dev_priv) >= 14 && pipe_config->fec_enable) 570 intel_de_rmw(dev_priv, MTL_CHICKEN_TRANS(trans), 0, 571 FECSTALL_DIS_DPTSTREAM_DPTTG); 572 else if (DISPLAY_VER(dev_priv) >= 12 && pipe_config->fec_enable) 573 intel_de_rmw(dev_priv, CHICKEN_TRANS(trans), 0, 574 FECSTALL_DIS_DPTSTREAM_DPTTG); 575 576 intel_enable_transcoder(pipe_config); 577 578 intel_crtc_vblank_on(pipe_config); 579 580 intel_audio_codec_enable(encoder, pipe_config, conn_state); 581 582 /* Enable hdcp if it's desired */ 583 if (conn_state->content_protection == 584 DRM_MODE_CONTENT_PROTECTION_DESIRED) 585 intel_hdcp_enable(to_intel_connector(conn_state->connector), 586 pipe_config, 587 (u8)conn_state->hdcp_content_type); 588 } 589 590 static bool intel_dp_mst_enc_get_hw_state(struct intel_encoder *encoder, 591 enum pipe *pipe) 592 { 593 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 594 *pipe = intel_mst->pipe; 595 if (intel_mst->connector) 596 return true; 597 return false; 598 } 599 600 static void intel_dp_mst_enc_get_config(struct intel_encoder *encoder, 601 struct intel_crtc_state *pipe_config) 602 { 603 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 604 struct intel_digital_port *dig_port = intel_mst->primary; 605 606 dig_port->base.get_config(&dig_port->base, pipe_config); 607 } 608 609 static bool intel_dp_mst_initial_fastset_check(struct intel_encoder *encoder, 610 struct intel_crtc_state *crtc_state) 611 { 612 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); 613 struct intel_digital_port *dig_port = intel_mst->primary; 614 615 return intel_dp_initial_fastset_check(&dig_port->base, crtc_state); 616 } 617 618 static int intel_dp_mst_get_ddc_modes(struct drm_connector *connector) 619 { 620 struct intel_connector *intel_connector = to_intel_connector(connector); 621 struct intel_dp *intel_dp = intel_connector->mst_port; 622 struct edid *edid; 623 int ret; 624 625 if (drm_connector_is_unregistered(connector)) 626 return intel_connector_update_modes(connector, NULL); 627 628 edid = drm_dp_mst_get_edid(connector, &intel_dp->mst_mgr, intel_connector->port); 629 ret = intel_connector_update_modes(connector, edid); 630 kfree(edid); 631 632 return ret; 633 } 634 635 static int 636 intel_dp_mst_connector_late_register(struct drm_connector *connector) 637 { 638 struct intel_connector *intel_connector = to_intel_connector(connector); 639 int ret; 640 641 ret = drm_dp_mst_connector_late_register(connector, 642 intel_connector->port); 643 if (ret < 0) 644 return ret; 645 646 ret = intel_connector_register(connector); 647 if (ret < 0) 648 drm_dp_mst_connector_early_unregister(connector, 649 intel_connector->port); 650 651 return ret; 652 } 653 654 static void 655 intel_dp_mst_connector_early_unregister(struct drm_connector *connector) 656 { 657 struct intel_connector *intel_connector = to_intel_connector(connector); 658 659 intel_connector_unregister(connector); 660 drm_dp_mst_connector_early_unregister(connector, 661 intel_connector->port); 662 } 663 664 static const struct drm_connector_funcs intel_dp_mst_connector_funcs = { 665 .fill_modes = drm_helper_probe_single_connector_modes, 666 .atomic_get_property = intel_digital_connector_atomic_get_property, 667 .atomic_set_property = intel_digital_connector_atomic_set_property, 668 .late_register = intel_dp_mst_connector_late_register, 669 .early_unregister = intel_dp_mst_connector_early_unregister, 670 .destroy = intel_connector_destroy, 671 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 672 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 673 }; 674 675 static int intel_dp_mst_get_modes(struct drm_connector *connector) 676 { 677 return intel_dp_mst_get_ddc_modes(connector); 678 } 679 680 static int 681 intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, 682 struct drm_display_mode *mode, 683 struct drm_modeset_acquire_ctx *ctx, 684 enum drm_mode_status *status) 685 { 686 struct drm_i915_private *dev_priv = to_i915(connector->dev); 687 struct intel_connector *intel_connector = to_intel_connector(connector); 688 struct intel_dp *intel_dp = intel_connector->mst_port; 689 struct drm_dp_mst_topology_mgr *mgr = &intel_dp->mst_mgr; 690 struct drm_dp_mst_port *port = intel_connector->port; 691 const int min_bpp = 18; 692 int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; 693 int max_rate, mode_rate, max_lanes, max_link_clock; 694 int ret; 695 696 if (drm_connector_is_unregistered(connector)) { 697 *status = MODE_ERROR; 698 return 0; 699 } 700 701 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) { 702 *status = MODE_NO_DBLESCAN; 703 return 0; 704 } 705 706 max_link_clock = intel_dp_max_link_rate(intel_dp); 707 max_lanes = intel_dp_max_lane_count(intel_dp); 708 709 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 710 mode_rate = intel_dp_link_required(mode->clock, min_bpp); 711 712 ret = drm_modeset_lock(&mgr->base.lock, ctx); 713 if (ret) 714 return ret; 715 716 if (mode_rate > max_rate || mode->clock > max_dotclk || 717 drm_dp_calc_pbn_mode(mode->clock, min_bpp, false) > port->full_pbn) { 718 *status = MODE_CLOCK_HIGH; 719 return 0; 720 } 721 722 if (mode->clock < 10000) { 723 *status = MODE_CLOCK_LOW; 724 return 0; 725 } 726 727 if (mode->flags & DRM_MODE_FLAG_DBLCLK) { 728 *status = MODE_H_ILLEGAL; 729 return 0; 730 } 731 732 *status = intel_mode_valid_max_plane_size(dev_priv, mode, false); 733 return 0; 734 } 735 736 static struct drm_encoder *intel_mst_atomic_best_encoder(struct drm_connector *connector, 737 struct drm_atomic_state *state) 738 { 739 struct drm_connector_state *connector_state = drm_atomic_get_new_connector_state(state, 740 connector); 741 struct intel_connector *intel_connector = to_intel_connector(connector); 742 struct intel_dp *intel_dp = intel_connector->mst_port; 743 struct intel_crtc *crtc = to_intel_crtc(connector_state->crtc); 744 745 return &intel_dp->mst_encoders[crtc->pipe]->base.base; 746 } 747 748 static int 749 intel_dp_mst_detect(struct drm_connector *connector, 750 struct drm_modeset_acquire_ctx *ctx, bool force) 751 { 752 struct drm_i915_private *i915 = to_i915(connector->dev); 753 struct intel_connector *intel_connector = to_intel_connector(connector); 754 struct intel_dp *intel_dp = intel_connector->mst_port; 755 756 if (!INTEL_DISPLAY_ENABLED(i915)) 757 return connector_status_disconnected; 758 759 if (drm_connector_is_unregistered(connector)) 760 return connector_status_disconnected; 761 762 return drm_dp_mst_detect_port(connector, ctx, &intel_dp->mst_mgr, 763 intel_connector->port); 764 } 765 766 static const struct drm_connector_helper_funcs intel_dp_mst_connector_helper_funcs = { 767 .get_modes = intel_dp_mst_get_modes, 768 .mode_valid_ctx = intel_dp_mst_mode_valid_ctx, 769 .atomic_best_encoder = intel_mst_atomic_best_encoder, 770 .atomic_check = intel_dp_mst_atomic_check, 771 .detect_ctx = intel_dp_mst_detect, 772 }; 773 774 static void intel_dp_mst_encoder_destroy(struct drm_encoder *encoder) 775 { 776 struct intel_dp_mst_encoder *intel_mst = enc_to_mst(to_intel_encoder(encoder)); 777 778 drm_encoder_cleanup(encoder); 779 kfree(intel_mst); 780 } 781 782 static const struct drm_encoder_funcs intel_dp_mst_enc_funcs = { 783 .destroy = intel_dp_mst_encoder_destroy, 784 }; 785 786 static bool intel_dp_mst_get_hw_state(struct intel_connector *connector) 787 { 788 if (intel_attached_encoder(connector) && connector->base.state->crtc) { 789 enum pipe pipe; 790 if (!intel_attached_encoder(connector)->get_hw_state(intel_attached_encoder(connector), &pipe)) 791 return false; 792 return true; 793 } 794 return false; 795 } 796 797 static int intel_dp_mst_add_properties(struct intel_dp *intel_dp, 798 struct drm_connector *connector, 799 const char *pathprop) 800 { 801 struct drm_i915_private *i915 = to_i915(connector->dev); 802 803 drm_object_attach_property(&connector->base, 804 i915->drm.mode_config.path_property, 0); 805 drm_object_attach_property(&connector->base, 806 i915->drm.mode_config.tile_property, 0); 807 808 intel_attach_force_audio_property(connector); 809 intel_attach_broadcast_rgb_property(connector); 810 811 /* 812 * Reuse the prop from the SST connector because we're 813 * not allowed to create new props after device registration. 814 */ 815 connector->max_bpc_property = 816 intel_dp->attached_connector->base.max_bpc_property; 817 if (connector->max_bpc_property) 818 drm_connector_attach_max_bpc_property(connector, 6, 12); 819 820 return drm_connector_set_path_property(connector, pathprop); 821 } 822 823 static struct drm_connector *intel_dp_add_mst_connector(struct drm_dp_mst_topology_mgr *mgr, 824 struct drm_dp_mst_port *port, 825 const char *pathprop) 826 { 827 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); 828 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 829 struct drm_device *dev = dig_port->base.base.dev; 830 struct drm_i915_private *dev_priv = to_i915(dev); 831 struct intel_connector *intel_connector; 832 struct drm_connector *connector; 833 enum pipe pipe; 834 int ret; 835 836 intel_connector = intel_connector_alloc(); 837 if (!intel_connector) 838 return NULL; 839 840 intel_connector->get_hw_state = intel_dp_mst_get_hw_state; 841 intel_connector->mst_port = intel_dp; 842 intel_connector->port = port; 843 drm_dp_mst_get_port_malloc(port); 844 845 connector = &intel_connector->base; 846 ret = drm_connector_init(dev, connector, &intel_dp_mst_connector_funcs, 847 DRM_MODE_CONNECTOR_DisplayPort); 848 if (ret) { 849 drm_dp_mst_put_port_malloc(port); 850 intel_connector_free(intel_connector); 851 return NULL; 852 } 853 854 drm_connector_helper_add(connector, &intel_dp_mst_connector_helper_funcs); 855 856 for_each_pipe(dev_priv, pipe) { 857 struct drm_encoder *enc = 858 &intel_dp->mst_encoders[pipe]->base.base; 859 860 ret = drm_connector_attach_encoder(&intel_connector->base, enc); 861 if (ret) 862 goto err; 863 } 864 865 ret = intel_dp_mst_add_properties(intel_dp, connector, pathprop); 866 if (ret) 867 goto err; 868 869 ret = intel_dp_hdcp_init(dig_port, intel_connector); 870 if (ret) 871 drm_dbg_kms(&dev_priv->drm, "[%s:%d] HDCP MST init failed, skipping.\n", 872 connector->name, connector->base.id); 873 874 return connector; 875 876 err: 877 drm_connector_cleanup(connector); 878 return NULL; 879 } 880 881 static void 882 intel_dp_mst_poll_hpd_irq(struct drm_dp_mst_topology_mgr *mgr) 883 { 884 struct intel_dp *intel_dp = container_of(mgr, struct intel_dp, mst_mgr); 885 886 intel_hpd_trigger_irq(dp_to_dig_port(intel_dp)); 887 } 888 889 static const struct drm_dp_mst_topology_cbs mst_cbs = { 890 .add_connector = intel_dp_add_mst_connector, 891 .poll_hpd_irq = intel_dp_mst_poll_hpd_irq, 892 }; 893 894 static struct intel_dp_mst_encoder * 895 intel_dp_create_fake_mst_encoder(struct intel_digital_port *dig_port, enum pipe pipe) 896 { 897 struct intel_dp_mst_encoder *intel_mst; 898 struct intel_encoder *intel_encoder; 899 struct drm_device *dev = dig_port->base.base.dev; 900 901 intel_mst = kzalloc(sizeof(*intel_mst), GFP_KERNEL); 902 903 if (!intel_mst) 904 return NULL; 905 906 intel_mst->pipe = pipe; 907 intel_encoder = &intel_mst->base; 908 intel_mst->primary = dig_port; 909 910 drm_encoder_init(dev, &intel_encoder->base, &intel_dp_mst_enc_funcs, 911 DRM_MODE_ENCODER_DPMST, "DP-MST %c", pipe_name(pipe)); 912 913 intel_encoder->type = INTEL_OUTPUT_DP_MST; 914 intel_encoder->power_domain = dig_port->base.power_domain; 915 intel_encoder->port = dig_port->base.port; 916 intel_encoder->cloneable = 0; 917 /* 918 * This is wrong, but broken userspace uses the intersection 919 * of possible_crtcs of all the encoders of a given connector 920 * to figure out which crtcs can drive said connector. What 921 * should be used instead is the union of possible_crtcs. 922 * To keep such userspace functioning we must misconfigure 923 * this to make sure the intersection is not empty :( 924 */ 925 intel_encoder->pipe_mask = ~0; 926 927 intel_encoder->compute_config = intel_dp_mst_compute_config; 928 intel_encoder->compute_config_late = intel_dp_mst_compute_config_late; 929 intel_encoder->disable = intel_mst_disable_dp; 930 intel_encoder->post_disable = intel_mst_post_disable_dp; 931 intel_encoder->update_pipe = intel_ddi_update_pipe; 932 intel_encoder->pre_pll_enable = intel_mst_pre_pll_enable_dp; 933 intel_encoder->pre_enable = intel_mst_pre_enable_dp; 934 intel_encoder->enable = intel_mst_enable_dp; 935 intel_encoder->get_hw_state = intel_dp_mst_enc_get_hw_state; 936 intel_encoder->get_config = intel_dp_mst_enc_get_config; 937 intel_encoder->initial_fastset_check = intel_dp_mst_initial_fastset_check; 938 939 return intel_mst; 940 941 } 942 943 static bool 944 intel_dp_create_fake_mst_encoders(struct intel_digital_port *dig_port) 945 { 946 struct intel_dp *intel_dp = &dig_port->dp; 947 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 948 enum pipe pipe; 949 950 for_each_pipe(dev_priv, pipe) 951 intel_dp->mst_encoders[pipe] = intel_dp_create_fake_mst_encoder(dig_port, pipe); 952 return true; 953 } 954 955 int 956 intel_dp_mst_encoder_active_links(struct intel_digital_port *dig_port) 957 { 958 return dig_port->dp.active_mst_links; 959 } 960 961 int 962 intel_dp_mst_encoder_init(struct intel_digital_port *dig_port, int conn_base_id) 963 { 964 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 965 struct intel_dp *intel_dp = &dig_port->dp; 966 enum port port = dig_port->base.port; 967 int ret; 968 969 if (!HAS_DP_MST(i915) || intel_dp_is_edp(intel_dp)) 970 return 0; 971 972 if (DISPLAY_VER(i915) < 12 && port == PORT_A) 973 return 0; 974 975 if (DISPLAY_VER(i915) < 11 && port == PORT_E) 976 return 0; 977 978 intel_dp->mst_mgr.cbs = &mst_cbs; 979 980 /* create encoders */ 981 intel_dp_create_fake_mst_encoders(dig_port); 982 ret = drm_dp_mst_topology_mgr_init(&intel_dp->mst_mgr, &i915->drm, 983 &intel_dp->aux, 16, 3, conn_base_id); 984 if (ret) { 985 intel_dp->mst_mgr.cbs = NULL; 986 return ret; 987 } 988 989 return 0; 990 } 991 992 bool intel_dp_mst_source_support(struct intel_dp *intel_dp) 993 { 994 return intel_dp->mst_mgr.cbs; 995 } 996 997 void 998 intel_dp_mst_encoder_cleanup(struct intel_digital_port *dig_port) 999 { 1000 struct intel_dp *intel_dp = &dig_port->dp; 1001 1002 if (!intel_dp_mst_source_support(intel_dp)) 1003 return; 1004 1005 drm_dp_mst_topology_mgr_destroy(&intel_dp->mst_mgr); 1006 /* encoders will get killed by normal cleanup */ 1007 1008 intel_dp->mst_mgr.cbs = NULL; 1009 } 1010 1011 bool intel_dp_mst_is_master_trans(const struct intel_crtc_state *crtc_state) 1012 { 1013 return crtc_state->mst_master_transcoder == crtc_state->cpu_transcoder; 1014 } 1015 1016 bool intel_dp_mst_is_slave_trans(const struct intel_crtc_state *crtc_state) 1017 { 1018 return crtc_state->mst_master_transcoder != INVALID_TRANSCODER && 1019 crtc_state->mst_master_transcoder != crtc_state->cpu_transcoder; 1020 } 1021