1 /*
2  * Copyright © 2008-2015 Intel Corporation
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21  * IN THE SOFTWARE.
22  */
23 
24 #include "intel_display_types.h"
25 #include "intel_dp.h"
26 #include "intel_dp_link_training.h"
27 
28 static void
29 intel_dp_dump_link_status(struct drm_device *drm,
30 			  const u8 link_status[DP_LINK_STATUS_SIZE])
31 {
32 	drm_dbg_kms(drm,
33 		    "ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n",
34 		    link_status[0], link_status[1], link_status[2],
35 		    link_status[3], link_status[4], link_status[5]);
36 }
37 
38 static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp)
39 {
40 	memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps));
41 }
42 
43 static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp)
44 {
45 	intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT -
46 				    DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0;
47 }
48 
49 static const char *intel_dp_phy_name(enum drm_dp_phy dp_phy,
50 				     char *buf, size_t buf_size)
51 {
52 	if (dp_phy == DP_PHY_DPRX)
53 		snprintf(buf, buf_size, "DPRX");
54 	else
55 		snprintf(buf, buf_size, "LTTPR %d", dp_phy - DP_PHY_LTTPR1 + 1);
56 
57 	return buf;
58 }
59 
60 static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp,
61 				   enum drm_dp_phy dp_phy)
62 {
63 	return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1];
64 }
65 
66 static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp,
67 					 enum drm_dp_phy dp_phy)
68 {
69 	u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
70 	char phy_name[10];
71 
72 	intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name));
73 
74 	if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) {
75 		drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
76 			    "failed to read the PHY caps for %s\n",
77 			    phy_name);
78 		return;
79 	}
80 
81 	drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
82 		    "%s PHY capabilities: %*ph\n",
83 		    phy_name,
84 		    (int)sizeof(intel_dp->lttpr_phy_caps[0]),
85 		    phy_caps);
86 }
87 
88 static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp)
89 {
90 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
91 
92 	if (intel_dp_is_edp(intel_dp))
93 		return false;
94 
95 	/*
96 	 * Detecting LTTPRs must be avoided on platforms with an AUX timeout
97 	 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1).
98 	 */
99 	if (DISPLAY_VER(i915) < 10 || IS_GEMINILAKE(i915))
100 		return false;
101 
102 	if (drm_dp_read_lttpr_common_caps(&intel_dp->aux,
103 					  intel_dp->lttpr_common_caps) < 0)
104 		goto reset_caps;
105 
106 	drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
107 		    "LTTPR common capabilities: %*ph\n",
108 		    (int)sizeof(intel_dp->lttpr_common_caps),
109 		    intel_dp->lttpr_common_caps);
110 
111 	/* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */
112 	if (intel_dp->lttpr_common_caps[0] < 0x14)
113 		goto reset_caps;
114 
115 	return true;
116 
117 reset_caps:
118 	intel_dp_reset_lttpr_common_caps(intel_dp);
119 	return false;
120 }
121 
122 static bool
123 intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable)
124 {
125 	u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT :
126 			  DP_PHY_REPEATER_MODE_NON_TRANSPARENT;
127 
128 	return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1;
129 }
130 
131 /**
132  * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode
133  * @intel_dp: Intel DP struct
134  *
135  * Read the LTTPR common and DPRX capabilities and switch to non-transparent
136  * link training mode if any is detected and read the PHY capabilities for all
137  * detected LTTPRs. In case of an LTTPR detection error or if the number of
138  * LTTPRs is more than is supported (8), fall back to the no-LTTPR,
139  * transparent mode link training mode.
140  *
141  * Returns:
142  *   >0  if LTTPRs were detected and the non-transparent LT mode was set. The
143  *       DPRX capabilities are read out.
144  *    0  if no LTTPRs or more than 8 LTTPRs were detected or in case of a
145  *       detection failure and the transparent LT mode was set. The DPRX
146  *       capabilities are read out.
147  *   <0  Reading out the DPRX capabilities failed.
148  */
149 int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp)
150 {
151 	int lttpr_count;
152 	bool ret;
153 	int i;
154 
155 	ret = intel_dp_read_lttpr_common_caps(intel_dp);
156 
157 	/* The DPTX shall read the DPRX caps after LTTPR detection. */
158 	if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) {
159 		intel_dp_reset_lttpr_common_caps(intel_dp);
160 		return -EIO;
161 	}
162 
163 	if (!ret)
164 		return 0;
165 
166 	/*
167 	 * The 0xF0000-0xF02FF range is only valid if the DPCD revision is
168 	 * at least 1.4.
169 	 */
170 	if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) {
171 		intel_dp_reset_lttpr_common_caps(intel_dp);
172 		return 0;
173 	}
174 
175 	lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
176 	/*
177 	 * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are
178 	 * detected as this breaks link training at least on the Dell WD19TB
179 	 * dock.
180 	 */
181 	if (lttpr_count == 0)
182 		return 0;
183 
184 	/*
185 	 * See DP Standard v2.0 3.6.6.1. about the explicit disabling of
186 	 * non-transparent mode and the disable->enable non-transparent mode
187 	 * sequence.
188 	 */
189 	intel_dp_set_lttpr_transparent_mode(intel_dp, true);
190 
191 	/*
192 	 * In case of unsupported number of LTTPRs or failing to switch to
193 	 * non-transparent mode fall-back to transparent link training mode,
194 	 * still taking into account any LTTPR common lane- rate/count limits.
195 	 */
196 	if (lttpr_count < 0)
197 		return 0;
198 
199 	if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) {
200 		drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
201 			    "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n");
202 
203 		intel_dp_set_lttpr_transparent_mode(intel_dp, true);
204 		intel_dp_reset_lttpr_count(intel_dp);
205 
206 		return 0;
207 	}
208 
209 	for (i = 0; i < lttpr_count; i++)
210 		intel_dp_read_lttpr_phy_caps(intel_dp, DP_PHY_LTTPR(i));
211 
212 	return lttpr_count;
213 }
214 EXPORT_SYMBOL(intel_dp_init_lttpr_and_dprx_caps);
215 
216 static u8 dp_voltage_max(u8 preemph)
217 {
218 	switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) {
219 	case DP_TRAIN_PRE_EMPH_LEVEL_0:
220 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
221 	case DP_TRAIN_PRE_EMPH_LEVEL_1:
222 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
223 	case DP_TRAIN_PRE_EMPH_LEVEL_2:
224 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_1;
225 	case DP_TRAIN_PRE_EMPH_LEVEL_3:
226 	default:
227 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_0;
228 	}
229 }
230 
231 static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp,
232 				     enum drm_dp_phy dp_phy)
233 {
234 	const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
235 
236 	if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps))
237 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_3;
238 	else
239 		return DP_TRAIN_VOLTAGE_SWING_LEVEL_2;
240 }
241 
242 static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp,
243 				     enum drm_dp_phy dp_phy)
244 {
245 	const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
246 
247 	if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps))
248 		return DP_TRAIN_PRE_EMPH_LEVEL_3;
249 	else
250 		return DP_TRAIN_PRE_EMPH_LEVEL_2;
251 }
252 
253 static bool
254 intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp,
255 				     enum drm_dp_phy dp_phy)
256 {
257 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
258 	int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps);
259 
260 	drm_WARN_ON_ONCE(&i915->drm, lttpr_count <= 0 && dp_phy != DP_PHY_DPRX);
261 
262 	return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1);
263 }
264 
265 static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp,
266 				   const struct intel_crtc_state *crtc_state,
267 				   enum drm_dp_phy dp_phy)
268 {
269 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
270 	u8 voltage_max;
271 
272 	/*
273 	 * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from
274 	 * the DPRX_PHY we train.
275 	 */
276 	if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
277 		voltage_max = intel_dp->voltage_max(intel_dp, crtc_state);
278 	else
279 		voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1);
280 
281 	drm_WARN_ON_ONCE(&i915->drm,
282 			 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 &&
283 			 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3);
284 
285 	return voltage_max;
286 }
287 
288 static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp,
289 				   enum drm_dp_phy dp_phy)
290 {
291 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
292 	u8 preemph_max;
293 
294 	/*
295 	 * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from
296 	 * the DPRX_PHY we train.
297 	 */
298 	if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
299 		preemph_max = intel_dp->preemph_max(intel_dp);
300 	else
301 		preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1);
302 
303 	drm_WARN_ON_ONCE(&i915->drm,
304 			 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 &&
305 			 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3);
306 
307 	return preemph_max;
308 }
309 
310 void
311 intel_dp_get_adjust_train(struct intel_dp *intel_dp,
312 			  const struct intel_crtc_state *crtc_state,
313 			  enum drm_dp_phy dp_phy,
314 			  const u8 link_status[DP_LINK_STATUS_SIZE])
315 {
316 	u8 v = 0;
317 	u8 p = 0;
318 	int lane;
319 	u8 voltage_max;
320 	u8 preemph_max;
321 
322 	for (lane = 0; lane < crtc_state->lane_count; lane++) {
323 		v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane));
324 		p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane));
325 	}
326 
327 	preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy);
328 	if (p >= preemph_max)
329 		p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED;
330 
331 	v = min(v, dp_voltage_max(p));
332 
333 	voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy);
334 	if (v >= voltage_max)
335 		v = voltage_max | DP_TRAIN_MAX_SWING_REACHED;
336 
337 	for (lane = 0; lane < 4; lane++)
338 		intel_dp->train_set[lane] = v | p;
339 }
340 
341 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp,
342 					     enum drm_dp_phy dp_phy)
343 {
344 	return dp_phy == DP_PHY_DPRX ?
345 		DP_TRAINING_PATTERN_SET :
346 		DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy);
347 }
348 
349 static bool
350 intel_dp_set_link_train(struct intel_dp *intel_dp,
351 			const struct intel_crtc_state *crtc_state,
352 			enum drm_dp_phy dp_phy,
353 			u8 dp_train_pat)
354 {
355 	int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
356 	u8 buf[sizeof(intel_dp->train_set) + 1];
357 	int len;
358 
359 	intel_dp_program_link_training_pattern(intel_dp, crtc_state,
360 					       dp_train_pat);
361 
362 	buf[0] = dp_train_pat;
363 	/* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */
364 	memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count);
365 	len = crtc_state->lane_count + 1;
366 
367 	return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len;
368 }
369 
370 static char dp_training_pattern_name(u8 train_pat)
371 {
372 	switch (train_pat) {
373 	case DP_TRAINING_PATTERN_1:
374 	case DP_TRAINING_PATTERN_2:
375 	case DP_TRAINING_PATTERN_3:
376 		return '0' + train_pat;
377 	case DP_TRAINING_PATTERN_4:
378 		return '4';
379 	default:
380 		MISSING_CASE(train_pat);
381 		return '?';
382 	}
383 }
384 
385 void
386 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp,
387 				       const struct intel_crtc_state *crtc_state,
388 				       u8 dp_train_pat)
389 {
390 	struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base;
391 	struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
392 	u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat);
393 
394 	if (train_pat != DP_TRAINING_PATTERN_DISABLE)
395 		drm_dbg_kms(&dev_priv->drm,
396 			    "[ENCODER:%d:%s] Using DP training pattern TPS%c\n",
397 			    encoder->base.base.id, encoder->base.name,
398 			    dp_training_pattern_name(train_pat));
399 
400 	intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat);
401 }
402 
403 void intel_dp_set_signal_levels(struct intel_dp *intel_dp,
404 				const struct intel_crtc_state *crtc_state,
405 				enum drm_dp_phy dp_phy)
406 {
407 	struct drm_i915_private *dev_priv = dp_to_i915(intel_dp);
408 	u8 train_set = intel_dp->train_set[0];
409 	char phy_name[10];
410 
411 	drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n",
412 		    train_set & DP_TRAIN_VOLTAGE_SWING_MASK,
413 		    train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "",
414 		    (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >>
415 		    DP_TRAIN_PRE_EMPHASIS_SHIFT,
416 		    train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ?
417 		    " (max)" : "",
418 		    intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
419 
420 	if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy))
421 		intel_dp->set_signal_levels(intel_dp, crtc_state);
422 }
423 
424 static bool
425 intel_dp_reset_link_train(struct intel_dp *intel_dp,
426 			  const struct intel_crtc_state *crtc_state,
427 			  enum drm_dp_phy dp_phy,
428 			  u8 dp_train_pat)
429 {
430 	memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set));
431 	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
432 	return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat);
433 }
434 
435 static bool
436 intel_dp_update_link_train(struct intel_dp *intel_dp,
437 			   const struct intel_crtc_state *crtc_state,
438 			   enum drm_dp_phy dp_phy)
439 {
440 	int reg = dp_phy == DP_PHY_DPRX ?
441 			    DP_TRAINING_LANE0_SET :
442 			    DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy);
443 	int ret;
444 
445 	intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy);
446 
447 	ret = drm_dp_dpcd_write(&intel_dp->aux, reg,
448 				intel_dp->train_set, crtc_state->lane_count);
449 
450 	return ret == crtc_state->lane_count;
451 }
452 
453 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp,
454 					     const struct intel_crtc_state *crtc_state)
455 {
456 	int lane;
457 
458 	for (lane = 0; lane < crtc_state->lane_count; lane++)
459 		if ((intel_dp->train_set[lane] &
460 		     DP_TRAIN_MAX_SWING_REACHED) == 0)
461 			return false;
462 
463 	return true;
464 }
465 
466 /*
467  * Prepare link training by configuring the link parameters. On DDI platforms
468  * also enable the port here.
469  */
470 static bool
471 intel_dp_prepare_link_train(struct intel_dp *intel_dp,
472 			    const struct intel_crtc_state *crtc_state)
473 {
474 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
475 	u8 link_config[2];
476 	u8 link_bw, rate_select;
477 
478 	if (intel_dp->prepare_link_retrain)
479 		intel_dp->prepare_link_retrain(intel_dp, crtc_state);
480 
481 	intel_dp_compute_rate(intel_dp, crtc_state->port_clock,
482 			      &link_bw, &rate_select);
483 
484 	if (link_bw)
485 		drm_dbg_kms(&i915->drm,
486 			    "Using LINK_BW_SET value %02x\n", link_bw);
487 	else
488 		drm_dbg_kms(&i915->drm,
489 			    "Using LINK_RATE_SET value %02x\n", rate_select);
490 
491 	/* Write the link configuration data */
492 	link_config[0] = link_bw;
493 	link_config[1] = crtc_state->lane_count;
494 	if (drm_dp_enhanced_frame_cap(intel_dp->dpcd))
495 		link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN;
496 	drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2);
497 
498 	/* eDP 1.4 rate select method. */
499 	if (!link_bw)
500 		drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET,
501 				  &rate_select, 1);
502 
503 	link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0;
504 	link_config[1] = DP_SET_ANSI_8B10B;
505 	drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2);
506 
507 	intel_dp->DP |= DP_PORT_EN;
508 
509 	return true;
510 }
511 
512 static void intel_dp_link_training_clock_recovery_delay(struct intel_dp *intel_dp,
513 							enum drm_dp_phy dp_phy)
514 {
515 	if (dp_phy == DP_PHY_DPRX)
516 		drm_dp_link_train_clock_recovery_delay(&intel_dp->aux, intel_dp->dpcd);
517 	else
518 		drm_dp_lttpr_link_train_clock_recovery_delay();
519 }
520 
521 /*
522  * Perform the link training clock recovery phase on the given DP PHY using
523  * training pattern 1.
524  */
525 static bool
526 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp,
527 				      const struct intel_crtc_state *crtc_state,
528 				      enum drm_dp_phy dp_phy)
529 {
530 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
531 	u8 voltage;
532 	int voltage_tries, cr_tries, max_cr_tries;
533 	bool max_vswing_reached = false;
534 
535 	/* clock recovery */
536 	if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy,
537 				       DP_TRAINING_PATTERN_1 |
538 				       DP_LINK_SCRAMBLING_DISABLE)) {
539 		drm_err(&i915->drm, "failed to enable link training\n");
540 		return false;
541 	}
542 
543 	/*
544 	 * The DP 1.4 spec defines the max clock recovery retries value
545 	 * as 10 but for pre-DP 1.4 devices we set a very tolerant
546 	 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x
547 	 * x 5 identical voltage retries). Since the previous specs didn't
548 	 * define a limit and created the possibility of an infinite loop
549 	 * we want to prevent any sync from triggering that corner case.
550 	 */
551 	if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14)
552 		max_cr_tries = 10;
553 	else
554 		max_cr_tries = 80;
555 
556 	voltage_tries = 1;
557 	for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) {
558 		u8 link_status[DP_LINK_STATUS_SIZE];
559 
560 		intel_dp_link_training_clock_recovery_delay(intel_dp, dp_phy);
561 
562 		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
563 						     link_status) < 0) {
564 			drm_err(&i915->drm, "failed to get link status\n");
565 			return false;
566 		}
567 
568 		if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) {
569 			drm_dbg_kms(&i915->drm, "clock recovery OK\n");
570 			return true;
571 		}
572 
573 		if (voltage_tries == 5) {
574 			drm_dbg_kms(&i915->drm,
575 				    "Same voltage tried 5 times\n");
576 			return false;
577 		}
578 
579 		if (max_vswing_reached) {
580 			drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n");
581 			return false;
582 		}
583 
584 		voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK;
585 
586 		/* Update training set as requested by target */
587 		intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
588 					  link_status);
589 		if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
590 			drm_err(&i915->drm,
591 				"failed to update link training\n");
592 			return false;
593 		}
594 
595 		if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) ==
596 		    voltage)
597 			++voltage_tries;
598 		else
599 			voltage_tries = 1;
600 
601 		if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state))
602 			max_vswing_reached = true;
603 
604 	}
605 	drm_err(&i915->drm,
606 		"Failed clock recovery %d times, giving up!\n", max_cr_tries);
607 	return false;
608 }
609 
610 /*
611  * Pick training pattern for channel equalization. Training pattern 4 for HBR3
612  * or for 1.4 devices that support it, training Pattern 3 for HBR2
613  * or 1.2 devices that support it, Training Pattern 2 otherwise.
614  */
615 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp,
616 				     const struct intel_crtc_state *crtc_state,
617 				     enum drm_dp_phy dp_phy)
618 {
619 	bool source_tps3, sink_tps3, source_tps4, sink_tps4;
620 
621 	/*
622 	 * Intel platforms that support HBR3 also support TPS4. It is mandatory
623 	 * for all downstream devices that support HBR3. There are no known eDP
624 	 * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1
625 	 * specification.
626 	 * LTTPRs must support TPS4.
627 	 */
628 	source_tps4 = intel_dp_source_supports_hbr3(intel_dp);
629 	sink_tps4 = dp_phy != DP_PHY_DPRX ||
630 		    drm_dp_tps4_supported(intel_dp->dpcd);
631 	if (source_tps4 && sink_tps4) {
632 		return DP_TRAINING_PATTERN_4;
633 	} else if (crtc_state->port_clock == 810000) {
634 		if (!source_tps4)
635 			drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
636 				    "8.1 Gbps link rate without source HBR3/TPS4 support\n");
637 		if (!sink_tps4)
638 			drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
639 				    "8.1 Gbps link rate without sink TPS4 support\n");
640 	}
641 	/*
642 	 * Intel platforms that support HBR2 also support TPS3. TPS3 support is
643 	 * also mandatory for downstream devices that support HBR2. However, not
644 	 * all sinks follow the spec.
645 	 */
646 	source_tps3 = intel_dp_source_supports_hbr2(intel_dp);
647 	sink_tps3 = dp_phy != DP_PHY_DPRX ||
648 		    drm_dp_tps3_supported(intel_dp->dpcd);
649 	if (source_tps3 && sink_tps3) {
650 		return  DP_TRAINING_PATTERN_3;
651 	} else if (crtc_state->port_clock >= 540000) {
652 		if (!source_tps3)
653 			drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
654 				    ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n");
655 		if (!sink_tps3)
656 			drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
657 				    ">=5.4/6.48 Gbps link rate without sink TPS3 support\n");
658 	}
659 
660 	return DP_TRAINING_PATTERN_2;
661 }
662 
663 static void
664 intel_dp_link_training_channel_equalization_delay(struct intel_dp *intel_dp,
665 						  enum drm_dp_phy dp_phy)
666 {
667 	if (dp_phy == DP_PHY_DPRX) {
668 		drm_dp_link_train_channel_eq_delay(&intel_dp->aux, intel_dp->dpcd);
669 	} else {
670 		const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy);
671 
672 		drm_dp_lttpr_link_train_channel_eq_delay(&intel_dp->aux, phy_caps);
673 	}
674 }
675 
676 /*
677  * Perform the link training channel equalization phase on the given DP PHY
678  * using one of training pattern 2, 3 or 4 depending on the source and
679  * sink capabilities.
680  */
681 static bool
682 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp,
683 					    const struct intel_crtc_state *crtc_state,
684 					    enum drm_dp_phy dp_phy)
685 {
686 	struct drm_i915_private *i915 = dp_to_i915(intel_dp);
687 	int tries;
688 	u32 training_pattern;
689 	u8 link_status[DP_LINK_STATUS_SIZE];
690 	bool channel_eq = false;
691 
692 	training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy);
693 	/* Scrambling is disabled for TPS2/3 and enabled for TPS4 */
694 	if (training_pattern != DP_TRAINING_PATTERN_4)
695 		training_pattern |= DP_LINK_SCRAMBLING_DISABLE;
696 
697 	/* channel equalization */
698 	if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy,
699 				     training_pattern)) {
700 		drm_err(&i915->drm, "failed to start channel equalization\n");
701 		return false;
702 	}
703 
704 	for (tries = 0; tries < 5; tries++) {
705 		intel_dp_link_training_channel_equalization_delay(intel_dp,
706 								  dp_phy);
707 		if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy,
708 						     link_status) < 0) {
709 			drm_err(&i915->drm,
710 				"failed to get link status\n");
711 			break;
712 		}
713 
714 		/* Make sure clock is still ok */
715 		if (!drm_dp_clock_recovery_ok(link_status,
716 					      crtc_state->lane_count)) {
717 			intel_dp_dump_link_status(&i915->drm, link_status);
718 			drm_dbg_kms(&i915->drm,
719 				    "Clock recovery check failed, cannot "
720 				    "continue channel equalization\n");
721 			break;
722 		}
723 
724 		if (drm_dp_channel_eq_ok(link_status,
725 					 crtc_state->lane_count)) {
726 			channel_eq = true;
727 			drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training "
728 				    "successful\n");
729 			break;
730 		}
731 
732 		/* Update training set as requested by target */
733 		intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy,
734 					  link_status);
735 		if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) {
736 			drm_err(&i915->drm,
737 				"failed to update link training\n");
738 			break;
739 		}
740 	}
741 
742 	/* Try 5 times, else fail and try at lower BW */
743 	if (tries == 5) {
744 		intel_dp_dump_link_status(&i915->drm, link_status);
745 		drm_dbg_kms(&i915->drm,
746 			    "Channel equalization failed 5 times\n");
747 	}
748 
749 	return channel_eq;
750 }
751 
752 static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp,
753 						   enum drm_dp_phy dp_phy)
754 {
755 	int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy);
756 	u8 val = DP_TRAINING_PATTERN_DISABLE;
757 
758 	return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1;
759 }
760 
761 /**
762  * intel_dp_stop_link_train - stop link training
763  * @intel_dp: DP struct
764  * @crtc_state: state for CRTC attached to the encoder
765  *
766  * Stop the link training of the @intel_dp port, disabling the training
767  * pattern in the sink's DPCD, and disabling the test pattern symbol
768  * generation on the port.
769  *
770  * What symbols are output on the port after this point is
771  * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern
772  * with the pipe being disabled, on older platforms it's HW specific if/how an
773  * idle pattern is generated, as the pipe is already enabled here for those.
774  *
775  * This function must be called after intel_dp_start_link_train().
776  */
777 void intel_dp_stop_link_train(struct intel_dp *intel_dp,
778 			      const struct intel_crtc_state *crtc_state)
779 {
780 	intel_dp->link_trained = true;
781 
782 	intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX);
783 	intel_dp_program_link_training_pattern(intel_dp, crtc_state,
784 					       DP_TRAINING_PATTERN_DISABLE);
785 }
786 
787 static bool
788 intel_dp_link_train_phy(struct intel_dp *intel_dp,
789 			const struct intel_crtc_state *crtc_state,
790 			enum drm_dp_phy dp_phy)
791 {
792 	struct intel_connector *intel_connector = intel_dp->attached_connector;
793 	char phy_name[10];
794 	bool ret = false;
795 
796 	if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy))
797 		goto out;
798 
799 	if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy))
800 		goto out;
801 
802 	ret = true;
803 
804 out:
805 	drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
806 		    "[CONNECTOR:%d:%s] Link Training %s at link rate = %d, lane count = %d, at %s\n",
807 		    intel_connector->base.base.id,
808 		    intel_connector->base.name,
809 		    ret ? "passed" : "failed",
810 		    crtc_state->port_clock, crtc_state->lane_count,
811 		    intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)));
812 
813 	return ret;
814 }
815 
816 static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp,
817 						     const struct intel_crtc_state *crtc_state)
818 {
819 	struct intel_connector *intel_connector = intel_dp->attached_connector;
820 
821 	if (intel_dp->hobl_active) {
822 		drm_dbg_kms(&dp_to_i915(intel_dp)->drm,
823 			    "Link Training failed with HOBL active, not enabling it from now on");
824 		intel_dp->hobl_failed = true;
825 	} else if (intel_dp_get_link_train_fallback_values(intel_dp,
826 							   crtc_state->port_clock,
827 							   crtc_state->lane_count)) {
828 		return;
829 	}
830 
831 	/* Schedule a Hotplug Uevent to userspace to start modeset */
832 	schedule_work(&intel_connector->modeset_retry_work);
833 }
834 
835 /* Perform the link training on all LTTPRs and the DPRX on a link. */
836 static bool
837 intel_dp_link_train_all_phys(struct intel_dp *intel_dp,
838 			     const struct intel_crtc_state *crtc_state,
839 			     int lttpr_count)
840 {
841 	bool ret = true;
842 	int i;
843 
844 	intel_dp_prepare_link_train(intel_dp, crtc_state);
845 
846 	for (i = lttpr_count - 1; i >= 0; i--) {
847 		enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i);
848 
849 		ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy);
850 		intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy);
851 
852 		if (!ret)
853 			break;
854 	}
855 
856 	if (ret)
857 		intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX);
858 
859 	if (intel_dp->set_idle_link_train)
860 		intel_dp->set_idle_link_train(intel_dp, crtc_state);
861 
862 	return ret;
863 }
864 
865 /**
866  * intel_dp_start_link_train - start link training
867  * @intel_dp: DP struct
868  * @crtc_state: state for CRTC attached to the encoder
869  *
870  * Start the link training of the @intel_dp port, scheduling a fallback
871  * retraining with reduced link rate/lane parameters if the link training
872  * fails.
873  * After calling this function intel_dp_stop_link_train() must be called.
874  */
875 void intel_dp_start_link_train(struct intel_dp *intel_dp,
876 			       const struct intel_crtc_state *crtc_state)
877 {
878 	/*
879 	 * TODO: Reiniting LTTPRs here won't be needed once proper connector
880 	 * HW state readout is added.
881 	 */
882 	int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp);
883 
884 	if (lttpr_count < 0)
885 		/* Still continue with enabling the port and link training. */
886 		lttpr_count = 0;
887 
888 	if (!intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count))
889 		intel_dp_schedule_fallback_link_training(intel_dp, crtc_state);
890 }
891