1 /* 2 * Copyright © 2008-2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include "i915_drv.h" 25 #include "intel_display_types.h" 26 #include "intel_dp.h" 27 #include "intel_dp_link_training.h" 28 29 #define LT_MSG_PREFIX "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] " 30 #define LT_MSG_ARGS(_intel_dp, _dp_phy) (_intel_dp)->attached_connector->base.base.id, \ 31 (_intel_dp)->attached_connector->base.name, \ 32 dp_to_dig_port(_intel_dp)->base.base.base.id, \ 33 dp_to_dig_port(_intel_dp)->base.base.name, \ 34 drm_dp_phy_name(_dp_phy) 35 36 #define lt_dbg(_intel_dp, _dp_phy, _format, ...) \ 37 drm_dbg_kms(&dp_to_i915(_intel_dp)->drm, \ 38 LT_MSG_PREFIX _format, \ 39 LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__) 40 41 #define lt_err(_intel_dp, _dp_phy, _format, ...) do { \ 42 if (intel_digital_port_connected(&dp_to_dig_port(_intel_dp)->base)) \ 43 drm_err(&dp_to_i915(_intel_dp)->drm, \ 44 LT_MSG_PREFIX _format, \ 45 LT_MSG_ARGS(_intel_dp, _dp_phy), ## __VA_ARGS__); \ 46 else \ 47 lt_dbg(_intel_dp, _dp_phy, "Sink disconnected: " _format, ## __VA_ARGS__); \ 48 } while (0) 49 50 static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp) 51 { 52 memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); 53 } 54 55 static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp) 56 { 57 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - 58 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0; 59 } 60 61 static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp, 62 enum drm_dp_phy dp_phy) 63 { 64 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; 65 } 66 67 static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, 68 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 69 enum drm_dp_phy dp_phy) 70 { 71 u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 72 73 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { 74 lt_dbg(intel_dp, dp_phy, "failed to read the PHY caps\n"); 75 return; 76 } 77 78 lt_dbg(intel_dp, dp_phy, "PHY capabilities: %*ph\n", 79 (int)sizeof(intel_dp->lttpr_phy_caps[0]), 80 phy_caps); 81 } 82 83 static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, 84 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 85 { 86 int ret; 87 88 ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd, 89 intel_dp->lttpr_common_caps); 90 if (ret < 0) 91 goto reset_caps; 92 93 lt_dbg(intel_dp, DP_PHY_DPRX, "LTTPR common capabilities: %*ph\n", 94 (int)sizeof(intel_dp->lttpr_common_caps), 95 intel_dp->lttpr_common_caps); 96 97 /* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */ 98 if (intel_dp->lttpr_common_caps[0] < 0x14) 99 goto reset_caps; 100 101 return true; 102 103 reset_caps: 104 intel_dp_reset_lttpr_common_caps(intel_dp); 105 return false; 106 } 107 108 static bool 109 intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) 110 { 111 u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : 112 DP_PHY_REPEATER_MODE_NON_TRANSPARENT; 113 114 return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1; 115 } 116 117 static bool intel_dp_lttpr_transparent_mode_enabled(struct intel_dp *intel_dp) 118 { 119 return intel_dp->lttpr_common_caps[DP_PHY_REPEATER_MODE - 120 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] == 121 DP_PHY_REPEATER_MODE_TRANSPARENT; 122 } 123 124 /* 125 * Read the LTTPR common capabilities and switch the LTTPR PHYs to 126 * non-transparent mode if this is supported. Preserve the 127 * transparent/non-transparent mode on an active link. 128 * 129 * Return the number of detected LTTPRs in non-transparent mode or 0 if the 130 * LTTPRs are in transparent mode or the detection failed. 131 */ 132 static int intel_dp_init_lttpr_phys(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 133 { 134 int lttpr_count; 135 136 if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd)) 137 return 0; 138 139 lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 140 /* 141 * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are 142 * detected as this breaks link training at least on the Dell WD19TB 143 * dock. 144 */ 145 if (lttpr_count == 0) 146 return 0; 147 148 /* 149 * Don't change the mode on an active link, to prevent a loss of link 150 * synchronization. See DP Standard v2.0 3.6.7. about the LTTPR 151 * resetting its internal state when the mode is changed from 152 * non-transparent to transparent. 153 */ 154 if (intel_dp->link_trained) { 155 if (lttpr_count < 0 || intel_dp_lttpr_transparent_mode_enabled(intel_dp)) 156 goto out_reset_lttpr_count; 157 158 return lttpr_count; 159 } 160 161 /* 162 * See DP Standard v2.0 3.6.6.1. about the explicit disabling of 163 * non-transparent mode and the disable->enable non-transparent mode 164 * sequence. 165 */ 166 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 167 168 /* 169 * In case of unsupported number of LTTPRs or failing to switch to 170 * non-transparent mode fall-back to transparent link training mode, 171 * still taking into account any LTTPR common lane- rate/count limits. 172 */ 173 if (lttpr_count < 0) 174 return 0; 175 176 if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) { 177 lt_dbg(intel_dp, DP_PHY_DPRX, 178 "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n"); 179 180 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 181 182 goto out_reset_lttpr_count; 183 } 184 185 return lttpr_count; 186 187 out_reset_lttpr_count: 188 intel_dp_reset_lttpr_count(intel_dp); 189 190 return 0; 191 } 192 193 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 194 { 195 int lttpr_count; 196 int i; 197 198 lttpr_count = intel_dp_init_lttpr_phys(intel_dp, dpcd); 199 200 for (i = 0; i < lttpr_count; i++) 201 intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i)); 202 203 return lttpr_count; 204 } 205 206 /** 207 * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode 208 * @intel_dp: Intel DP struct 209 * 210 * Read the LTTPR common and DPRX capabilities and switch to non-transparent 211 * link training mode if any is detected and read the PHY capabilities for all 212 * detected LTTPRs. In case of an LTTPR detection error or if the number of 213 * LTTPRs is more than is supported (8), fall back to the no-LTTPR, 214 * transparent mode link training mode. 215 * 216 * Returns: 217 * >0 if LTTPRs were detected and the non-transparent LT mode was set. The 218 * DPRX capabilities are read out. 219 * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a 220 * detection failure and the transparent LT mode was set. The DPRX 221 * capabilities are read out. 222 * <0 Reading out the DPRX capabilities failed. 223 */ 224 int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) 225 { 226 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 227 int lttpr_count = 0; 228 229 /* 230 * Detecting LTTPRs must be avoided on platforms with an AUX timeout 231 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1). 232 */ 233 if (!intel_dp_is_edp(intel_dp) && 234 (DISPLAY_VER(i915) >= 10 && !IS_GEMINILAKE(i915))) { 235 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 236 237 if (drm_dp_dpcd_probe(&intel_dp->aux, DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV)) 238 return -EIO; 239 240 if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd)) 241 return -EIO; 242 243 lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd); 244 } 245 246 /* 247 * The DPTX shall read the DPRX caps after LTTPR detection, so re-read 248 * it here. 249 */ 250 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) { 251 intel_dp_reset_lttpr_common_caps(intel_dp); 252 return -EIO; 253 } 254 255 return lttpr_count; 256 } 257 258 static u8 dp_voltage_max(u8 preemph) 259 { 260 switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) { 261 case DP_TRAIN_PRE_EMPH_LEVEL_0: 262 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 263 case DP_TRAIN_PRE_EMPH_LEVEL_1: 264 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 265 case DP_TRAIN_PRE_EMPH_LEVEL_2: 266 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1; 267 case DP_TRAIN_PRE_EMPH_LEVEL_3: 268 default: 269 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 270 } 271 } 272 273 static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp, 274 enum drm_dp_phy dp_phy) 275 { 276 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 277 278 if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps)) 279 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 280 else 281 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 282 } 283 284 static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp, 285 enum drm_dp_phy dp_phy) 286 { 287 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 288 289 if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps)) 290 return DP_TRAIN_PRE_EMPH_LEVEL_3; 291 else 292 return DP_TRAIN_PRE_EMPH_LEVEL_2; 293 } 294 295 static bool 296 intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp, 297 enum drm_dp_phy dp_phy) 298 { 299 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 300 int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 301 302 drm_WARN_ON_ONCE(&i915->drm, lttpr_count <= 0 && dp_phy != DP_PHY_DPRX); 303 304 return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1); 305 } 306 307 static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp, 308 const struct intel_crtc_state *crtc_state, 309 enum drm_dp_phy dp_phy) 310 { 311 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 312 u8 voltage_max; 313 314 /* 315 * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from 316 * the DPRX_PHY we train. 317 */ 318 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 319 voltage_max = intel_dp->voltage_max(intel_dp, crtc_state); 320 else 321 voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1); 322 323 drm_WARN_ON_ONCE(&i915->drm, 324 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 && 325 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3); 326 327 return voltage_max; 328 } 329 330 static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, 331 enum drm_dp_phy dp_phy) 332 { 333 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 334 u8 preemph_max; 335 336 /* 337 * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from 338 * the DPRX_PHY we train. 339 */ 340 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 341 preemph_max = intel_dp->preemph_max(intel_dp); 342 else 343 preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1); 344 345 drm_WARN_ON_ONCE(&i915->drm, 346 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 && 347 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3); 348 349 return preemph_max; 350 } 351 352 static bool has_per_lane_signal_levels(struct intel_dp *intel_dp, 353 enum drm_dp_phy dp_phy) 354 { 355 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 356 357 return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) || 358 DISPLAY_VER(i915) >= 11; 359 } 360 361 /* 128b/132b */ 362 static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp, 363 const struct intel_crtc_state *crtc_state, 364 enum drm_dp_phy dp_phy, 365 const u8 link_status[DP_LINK_STATUS_SIZE], 366 int lane) 367 { 368 u8 tx_ffe = 0; 369 370 if (has_per_lane_signal_levels(intel_dp, dp_phy)) { 371 lane = min(lane, crtc_state->lane_count - 1); 372 tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane); 373 } else { 374 for (lane = 0; lane < crtc_state->lane_count; lane++) 375 tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane)); 376 } 377 378 return tx_ffe; 379 } 380 381 /* 8b/10b */ 382 static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp, 383 const struct intel_crtc_state *crtc_state, 384 enum drm_dp_phy dp_phy, 385 const u8 link_status[DP_LINK_STATUS_SIZE], 386 int lane) 387 { 388 u8 v = 0; 389 u8 p = 0; 390 u8 voltage_max; 391 u8 preemph_max; 392 393 if (has_per_lane_signal_levels(intel_dp, dp_phy)) { 394 lane = min(lane, crtc_state->lane_count - 1); 395 396 v = drm_dp_get_adjust_request_voltage(link_status, lane); 397 p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 398 } else { 399 for (lane = 0; lane < crtc_state->lane_count; lane++) { 400 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); 401 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); 402 } 403 } 404 405 preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy); 406 if (p >= preemph_max) 407 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 408 409 v = min(v, dp_voltage_max(p)); 410 411 voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy); 412 if (v >= voltage_max) 413 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 414 415 return v | p; 416 } 417 418 static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp, 419 const struct intel_crtc_state *crtc_state, 420 enum drm_dp_phy dp_phy, 421 const u8 link_status[DP_LINK_STATUS_SIZE], 422 int lane) 423 { 424 if (intel_dp_is_uhbr(crtc_state)) 425 return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state, 426 dp_phy, link_status, lane); 427 else 428 return intel_dp_get_lane_adjust_vswing_preemph(intel_dp, crtc_state, 429 dp_phy, link_status, lane); 430 } 431 432 #define TRAIN_REQ_FMT "%d/%d/%d/%d" 433 #define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \ 434 (drm_dp_get_adjust_request_voltage((link_status), (lane)) >> DP_TRAIN_VOLTAGE_SWING_SHIFT) 435 #define TRAIN_REQ_VSWING_ARGS(link_status) \ 436 _TRAIN_REQ_VSWING_ARGS(link_status, 0), \ 437 _TRAIN_REQ_VSWING_ARGS(link_status, 1), \ 438 _TRAIN_REQ_VSWING_ARGS(link_status, 2), \ 439 _TRAIN_REQ_VSWING_ARGS(link_status, 3) 440 #define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \ 441 (drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT) 442 #define TRAIN_REQ_PREEMPH_ARGS(link_status) \ 443 _TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \ 444 _TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \ 445 _TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \ 446 _TRAIN_REQ_PREEMPH_ARGS(link_status, 3) 447 #define _TRAIN_REQ_TX_FFE_ARGS(link_status, lane) \ 448 drm_dp_get_adjust_tx_ffe_preset((link_status), (lane)) 449 #define TRAIN_REQ_TX_FFE_ARGS(link_status) \ 450 _TRAIN_REQ_TX_FFE_ARGS(link_status, 0), \ 451 _TRAIN_REQ_TX_FFE_ARGS(link_status, 1), \ 452 _TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \ 453 _TRAIN_REQ_TX_FFE_ARGS(link_status, 3) 454 455 void 456 intel_dp_get_adjust_train(struct intel_dp *intel_dp, 457 const struct intel_crtc_state *crtc_state, 458 enum drm_dp_phy dp_phy, 459 const u8 link_status[DP_LINK_STATUS_SIZE]) 460 { 461 int lane; 462 463 if (intel_dp_is_uhbr(crtc_state)) { 464 lt_dbg(intel_dp, dp_phy, 465 "128b/132b, lanes: %d, " 466 "TX FFE request: " TRAIN_REQ_FMT "\n", 467 crtc_state->lane_count, 468 TRAIN_REQ_TX_FFE_ARGS(link_status)); 469 } else { 470 lt_dbg(intel_dp, dp_phy, 471 "8b/10b, lanes: %d, " 472 "vswing request: " TRAIN_REQ_FMT ", " 473 "pre-emphasis request: " TRAIN_REQ_FMT "\n", 474 crtc_state->lane_count, 475 TRAIN_REQ_VSWING_ARGS(link_status), 476 TRAIN_REQ_PREEMPH_ARGS(link_status)); 477 } 478 479 for (lane = 0; lane < 4; lane++) 480 intel_dp->train_set[lane] = 481 intel_dp_get_lane_adjust_train(intel_dp, crtc_state, 482 dp_phy, link_status, lane); 483 } 484 485 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp, 486 enum drm_dp_phy dp_phy) 487 { 488 return dp_phy == DP_PHY_DPRX ? 489 DP_TRAINING_PATTERN_SET : 490 DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy); 491 } 492 493 static bool 494 intel_dp_set_link_train(struct intel_dp *intel_dp, 495 const struct intel_crtc_state *crtc_state, 496 enum drm_dp_phy dp_phy, 497 u8 dp_train_pat) 498 { 499 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 500 u8 buf[sizeof(intel_dp->train_set) + 1]; 501 int len; 502 503 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 504 dp_phy, dp_train_pat); 505 506 buf[0] = dp_train_pat; 507 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 508 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); 509 len = crtc_state->lane_count + 1; 510 511 return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len; 512 } 513 514 static char dp_training_pattern_name(u8 train_pat) 515 { 516 switch (train_pat) { 517 case DP_TRAINING_PATTERN_1: 518 case DP_TRAINING_PATTERN_2: 519 case DP_TRAINING_PATTERN_3: 520 return '0' + train_pat; 521 case DP_TRAINING_PATTERN_4: 522 return '4'; 523 default: 524 MISSING_CASE(train_pat); 525 return '?'; 526 } 527 } 528 529 void 530 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 531 const struct intel_crtc_state *crtc_state, 532 enum drm_dp_phy dp_phy, 533 u8 dp_train_pat) 534 { 535 u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat); 536 537 if (train_pat != DP_TRAINING_PATTERN_DISABLE) 538 lt_dbg(intel_dp, dp_phy, "Using DP training pattern TPS%c\n", 539 dp_training_pattern_name(train_pat)); 540 541 intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat); 542 } 543 544 #define TRAIN_SET_FMT "%d%s/%d%s/%d%s/%d%s" 545 #define _TRAIN_SET_VSWING_ARGS(train_set) \ 546 ((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \ 547 (train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : "" 548 #define TRAIN_SET_VSWING_ARGS(train_set) \ 549 _TRAIN_SET_VSWING_ARGS((train_set)[0]), \ 550 _TRAIN_SET_VSWING_ARGS((train_set)[1]), \ 551 _TRAIN_SET_VSWING_ARGS((train_set)[2]), \ 552 _TRAIN_SET_VSWING_ARGS((train_set)[3]) 553 #define _TRAIN_SET_PREEMPH_ARGS(train_set) \ 554 ((train_set) & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT, \ 555 (train_set) & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? "(max)" : "" 556 #define TRAIN_SET_PREEMPH_ARGS(train_set) \ 557 _TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \ 558 _TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \ 559 _TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \ 560 _TRAIN_SET_PREEMPH_ARGS((train_set)[3]) 561 #define _TRAIN_SET_TX_FFE_ARGS(train_set) \ 562 ((train_set) & DP_TX_FFE_PRESET_VALUE_MASK), "" 563 #define TRAIN_SET_TX_FFE_ARGS(train_set) \ 564 _TRAIN_SET_TX_FFE_ARGS((train_set)[0]), \ 565 _TRAIN_SET_TX_FFE_ARGS((train_set)[1]), \ 566 _TRAIN_SET_TX_FFE_ARGS((train_set)[2]), \ 567 _TRAIN_SET_TX_FFE_ARGS((train_set)[3]) 568 569 void intel_dp_set_signal_levels(struct intel_dp *intel_dp, 570 const struct intel_crtc_state *crtc_state, 571 enum drm_dp_phy dp_phy) 572 { 573 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 574 575 if (intel_dp_is_uhbr(crtc_state)) { 576 lt_dbg(intel_dp, dp_phy, 577 "128b/132b, lanes: %d, " 578 "TX FFE presets: " TRAIN_SET_FMT "\n", 579 crtc_state->lane_count, 580 TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set)); 581 } else { 582 lt_dbg(intel_dp, dp_phy, 583 "8b/10b, lanes: %d, " 584 "vswing levels: " TRAIN_SET_FMT ", " 585 "pre-emphasis levels: " TRAIN_SET_FMT "\n", 586 crtc_state->lane_count, 587 TRAIN_SET_VSWING_ARGS(intel_dp->train_set), 588 TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set)); 589 } 590 591 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 592 encoder->set_signal_levels(encoder, crtc_state); 593 } 594 595 static bool 596 intel_dp_reset_link_train(struct intel_dp *intel_dp, 597 const struct intel_crtc_state *crtc_state, 598 enum drm_dp_phy dp_phy, 599 u8 dp_train_pat) 600 { 601 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 602 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 603 return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat); 604 } 605 606 static bool 607 intel_dp_update_link_train(struct intel_dp *intel_dp, 608 const struct intel_crtc_state *crtc_state, 609 enum drm_dp_phy dp_phy) 610 { 611 int reg = dp_phy == DP_PHY_DPRX ? 612 DP_TRAINING_LANE0_SET : 613 DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy); 614 int ret; 615 616 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 617 618 ret = drm_dp_dpcd_write(&intel_dp->aux, reg, 619 intel_dp->train_set, crtc_state->lane_count); 620 621 return ret == crtc_state->lane_count; 622 } 623 624 /* 128b/132b */ 625 static bool intel_dp_lane_max_tx_ffe_reached(u8 train_set_lane) 626 { 627 return (train_set_lane & DP_TX_FFE_PRESET_VALUE_MASK) == 628 DP_TX_FFE_PRESET_VALUE_MASK; 629 } 630 631 /* 632 * 8b/10b 633 * 634 * FIXME: The DP spec is very confusing here, also the Link CTS spec seems to 635 * have self contradicting tests around this area. 636 * 637 * In lieu of better ideas let's just stop when we've reached the max supported 638 * vswing with its max pre-emphasis, which is either 2+1 or 3+0 depending on 639 * whether vswing level 3 is supported or not. 640 */ 641 static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane) 642 { 643 u8 v = (train_set_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >> 644 DP_TRAIN_VOLTAGE_SWING_SHIFT; 645 u8 p = (train_set_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >> 646 DP_TRAIN_PRE_EMPHASIS_SHIFT; 647 648 if ((train_set_lane & DP_TRAIN_MAX_SWING_REACHED) == 0) 649 return false; 650 651 if (v + p != 3) 652 return false; 653 654 return true; 655 } 656 657 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp, 658 const struct intel_crtc_state *crtc_state) 659 { 660 int lane; 661 662 for (lane = 0; lane < crtc_state->lane_count; lane++) { 663 u8 train_set_lane = intel_dp->train_set[lane]; 664 665 if (intel_dp_is_uhbr(crtc_state)) { 666 if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane)) 667 return false; 668 } else { 669 if (!intel_dp_lane_max_vswing_reached(train_set_lane)) 670 return false; 671 } 672 } 673 674 return true; 675 } 676 677 static void 678 intel_dp_update_downspread_ctrl(struct intel_dp *intel_dp, 679 const struct intel_crtc_state *crtc_state) 680 { 681 u8 link_config[2]; 682 683 link_config[0] = crtc_state->vrr.flipline ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; 684 link_config[1] = intel_dp_is_uhbr(crtc_state) ? 685 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B; 686 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 687 } 688 689 static void 690 intel_dp_update_link_bw_set(struct intel_dp *intel_dp, 691 const struct intel_crtc_state *crtc_state, 692 u8 link_bw, u8 rate_select) 693 { 694 u8 lane_count = crtc_state->lane_count; 695 696 if (crtc_state->enhanced_framing) 697 lane_count |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 698 699 if (link_bw) { 700 /* DP and eDP v1.3 and earlier link bw set method. */ 701 u8 link_config[] = { link_bw, lane_count }; 702 703 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 704 ARRAY_SIZE(link_config)); 705 } else { 706 /* 707 * eDP v1.4 and later link rate set method. 708 * 709 * eDP v1.4x sinks shall ignore DP_LINK_RATE_SET if 710 * DP_LINK_BW_SET is set. Avoid writing DP_LINK_BW_SET. 711 * 712 * eDP v1.5 sinks allow choosing either, and the last choice 713 * shall be active. 714 */ 715 drm_dp_dpcd_writeb(&intel_dp->aux, DP_LANE_COUNT_SET, lane_count); 716 drm_dp_dpcd_writeb(&intel_dp->aux, DP_LINK_RATE_SET, rate_select); 717 } 718 } 719 720 /* 721 * Prepare link training by configuring the link parameters. On DDI platforms 722 * also enable the port here. 723 */ 724 static bool 725 intel_dp_prepare_link_train(struct intel_dp *intel_dp, 726 const struct intel_crtc_state *crtc_state) 727 { 728 u8 link_bw, rate_select; 729 730 if (intel_dp->prepare_link_retrain) 731 intel_dp->prepare_link_retrain(intel_dp, crtc_state); 732 733 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, 734 &link_bw, &rate_select); 735 736 /* 737 * WaEdpLinkRateDataReload 738 * 739 * Parade PS8461E MUX (used on varius TGL+ laptops) needs 740 * to snoop the link rates reported by the sink when we 741 * use LINK_RATE_SET in order to operate in jitter cleaning 742 * mode (as opposed to redriver mode). Unfortunately it 743 * loses track of the snooped link rates when powered down, 744 * so we need to make it re-snoop often. Without this high 745 * link rates are not stable. 746 */ 747 if (!link_bw) { 748 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 749 750 lt_dbg(intel_dp, DP_PHY_DPRX, "Reloading eDP link rates\n"); 751 752 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 753 sink_rates, sizeof(sink_rates)); 754 } 755 756 if (link_bw) 757 lt_dbg(intel_dp, DP_PHY_DPRX, "Using LINK_BW_SET value %02x\n", 758 link_bw); 759 else 760 lt_dbg(intel_dp, DP_PHY_DPRX, 761 "Using LINK_RATE_SET value %02x\n", 762 rate_select); 763 /* 764 * Spec DP2.1 Section 3.5.2.16 765 * Prior to LT DPTX should set 128b/132b DP Channel coding and then set link rate 766 */ 767 intel_dp_update_downspread_ctrl(intel_dp, crtc_state); 768 intel_dp_update_link_bw_set(intel_dp, crtc_state, link_bw, 769 rate_select); 770 771 return true; 772 } 773 774 static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state, 775 const u8 old_link_status[DP_LINK_STATUS_SIZE], 776 const u8 new_link_status[DP_LINK_STATUS_SIZE]) 777 { 778 int lane; 779 780 for (lane = 0; lane < crtc_state->lane_count; lane++) { 781 u8 old, new; 782 783 if (intel_dp_is_uhbr(crtc_state)) { 784 old = drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane); 785 new = drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane); 786 } else { 787 old = drm_dp_get_adjust_request_voltage(old_link_status, lane) | 788 drm_dp_get_adjust_request_pre_emphasis(old_link_status, lane); 789 new = drm_dp_get_adjust_request_voltage(new_link_status, lane) | 790 drm_dp_get_adjust_request_pre_emphasis(new_link_status, lane); 791 } 792 793 if (old != new) 794 return true; 795 } 796 797 return false; 798 } 799 800 void 801 intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy, 802 const u8 link_status[DP_LINK_STATUS_SIZE]) 803 { 804 lt_dbg(intel_dp, dp_phy, 805 "ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n", 806 link_status[0], link_status[1], link_status[2], 807 link_status[3], link_status[4], link_status[5]); 808 } 809 810 /* 811 * Perform the link training clock recovery phase on the given DP PHY using 812 * training pattern 1. 813 */ 814 static bool 815 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, 816 const struct intel_crtc_state *crtc_state, 817 enum drm_dp_phy dp_phy) 818 { 819 u8 old_link_status[DP_LINK_STATUS_SIZE] = {}; 820 int voltage_tries, cr_tries, max_cr_tries; 821 u8 link_status[DP_LINK_STATUS_SIZE]; 822 bool max_vswing_reached = false; 823 int delay_us; 824 825 delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux, 826 intel_dp->dpcd, dp_phy, 827 intel_dp_is_uhbr(crtc_state)); 828 829 /* clock recovery */ 830 if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy, 831 DP_TRAINING_PATTERN_1 | 832 DP_LINK_SCRAMBLING_DISABLE)) { 833 lt_err(intel_dp, dp_phy, "Failed to enable link training\n"); 834 return false; 835 } 836 837 /* 838 * The DP 1.4 spec defines the max clock recovery retries value 839 * as 10 but for pre-DP 1.4 devices we set a very tolerant 840 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x 841 * x 5 identical voltage retries). Since the previous specs didn't 842 * define a limit and created the possibility of an infinite loop 843 * we want to prevent any sync from triggering that corner case. 844 */ 845 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 846 max_cr_tries = 10; 847 else 848 max_cr_tries = 80; 849 850 voltage_tries = 1; 851 for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) { 852 usleep_range(delay_us, 2 * delay_us); 853 854 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 855 link_status) < 0) { 856 lt_err(intel_dp, dp_phy, "Failed to get link status\n"); 857 return false; 858 } 859 860 if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) { 861 lt_dbg(intel_dp, dp_phy, "Clock recovery OK\n"); 862 return true; 863 } 864 865 if (voltage_tries == 5) { 866 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 867 lt_dbg(intel_dp, dp_phy, "Same voltage tried 5 times\n"); 868 return false; 869 } 870 871 if (max_vswing_reached) { 872 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 873 lt_dbg(intel_dp, dp_phy, "Max Voltage Swing reached\n"); 874 return false; 875 } 876 877 /* Update training set as requested by target */ 878 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 879 link_status); 880 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 881 lt_err(intel_dp, dp_phy, "Failed to update link training\n"); 882 return false; 883 } 884 885 if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status)) 886 ++voltage_tries; 887 else 888 voltage_tries = 1; 889 890 memcpy(old_link_status, link_status, sizeof(link_status)); 891 892 if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state)) 893 max_vswing_reached = true; 894 } 895 896 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 897 lt_err(intel_dp, dp_phy, "Failed clock recovery %d times, giving up!\n", 898 max_cr_tries); 899 900 return false; 901 } 902 903 /* 904 * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2 905 * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or 906 * 1.2 devices that support it, TPS2 otherwise. 907 */ 908 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, 909 const struct intel_crtc_state *crtc_state, 910 enum drm_dp_phy dp_phy) 911 { 912 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 913 bool source_tps3, sink_tps3, source_tps4, sink_tps4; 914 915 /* UHBR+ use separate 128b/132b TPS2 */ 916 if (intel_dp_is_uhbr(crtc_state)) 917 return DP_TRAINING_PATTERN_2; 918 919 /* 920 * TPS4 support is mandatory for all downstream devices that 921 * support HBR3. There are no known eDP panels that support 922 * TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification. 923 * LTTPRs must support TPS4. 924 */ 925 source_tps4 = intel_dp_source_supports_tps4(i915); 926 sink_tps4 = dp_phy != DP_PHY_DPRX || 927 drm_dp_tps4_supported(intel_dp->dpcd); 928 if (source_tps4 && sink_tps4) { 929 return DP_TRAINING_PATTERN_4; 930 } else if (crtc_state->port_clock == 810000) { 931 if (!source_tps4) 932 lt_dbg(intel_dp, dp_phy, 933 "8.1 Gbps link rate without source TPS4 support\n"); 934 if (!sink_tps4) 935 lt_dbg(intel_dp, dp_phy, 936 "8.1 Gbps link rate without sink TPS4 support\n"); 937 } 938 939 /* 940 * TPS3 support is mandatory for downstream devices that 941 * support HBR2. However, not all sinks follow the spec. 942 */ 943 source_tps3 = intel_dp_source_supports_tps3(i915); 944 sink_tps3 = dp_phy != DP_PHY_DPRX || 945 drm_dp_tps3_supported(intel_dp->dpcd); 946 if (source_tps3 && sink_tps3) { 947 return DP_TRAINING_PATTERN_3; 948 } else if (crtc_state->port_clock >= 540000) { 949 if (!source_tps3) 950 lt_dbg(intel_dp, dp_phy, 951 ">=5.4/6.48 Gbps link rate without source TPS3 support\n"); 952 if (!sink_tps3) 953 lt_dbg(intel_dp, dp_phy, 954 ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); 955 } 956 957 return DP_TRAINING_PATTERN_2; 958 } 959 960 /* 961 * Perform the link training channel equalization phase on the given DP PHY 962 * using one of training pattern 2, 3 or 4 depending on the source and 963 * sink capabilities. 964 */ 965 static bool 966 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp, 967 const struct intel_crtc_state *crtc_state, 968 enum drm_dp_phy dp_phy) 969 { 970 int tries; 971 u32 training_pattern; 972 u8 link_status[DP_LINK_STATUS_SIZE]; 973 bool channel_eq = false; 974 int delay_us; 975 976 delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux, 977 intel_dp->dpcd, dp_phy, 978 intel_dp_is_uhbr(crtc_state)); 979 980 training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy); 981 /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ 982 if (training_pattern != DP_TRAINING_PATTERN_4) 983 training_pattern |= DP_LINK_SCRAMBLING_DISABLE; 984 985 /* channel equalization */ 986 if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, 987 training_pattern)) { 988 lt_err(intel_dp, dp_phy, "Failed to start channel equalization\n"); 989 return false; 990 } 991 992 for (tries = 0; tries < 5; tries++) { 993 usleep_range(delay_us, 2 * delay_us); 994 995 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 996 link_status) < 0) { 997 lt_err(intel_dp, dp_phy, "Failed to get link status\n"); 998 break; 999 } 1000 1001 /* Make sure clock is still ok */ 1002 if (!drm_dp_clock_recovery_ok(link_status, 1003 crtc_state->lane_count)) { 1004 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 1005 lt_dbg(intel_dp, dp_phy, 1006 "Clock recovery check failed, cannot continue channel equalization\n"); 1007 break; 1008 } 1009 1010 if (drm_dp_channel_eq_ok(link_status, 1011 crtc_state->lane_count)) { 1012 channel_eq = true; 1013 lt_dbg(intel_dp, dp_phy, "Channel EQ done. DP Training successful\n"); 1014 break; 1015 } 1016 1017 /* Update training set as requested by target */ 1018 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 1019 link_status); 1020 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 1021 lt_err(intel_dp, dp_phy, "Failed to update link training\n"); 1022 break; 1023 } 1024 } 1025 1026 /* Try 5 times, else fail and try at lower BW */ 1027 if (tries == 5) { 1028 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 1029 lt_dbg(intel_dp, dp_phy, "Channel equalization failed 5 times\n"); 1030 } 1031 1032 return channel_eq; 1033 } 1034 1035 static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp, 1036 enum drm_dp_phy dp_phy) 1037 { 1038 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 1039 u8 val = DP_TRAINING_PATTERN_DISABLE; 1040 1041 return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1; 1042 } 1043 1044 static int 1045 intel_dp_128b132b_intra_hop(struct intel_dp *intel_dp, 1046 const struct intel_crtc_state *crtc_state) 1047 { 1048 u8 sink_status; 1049 int ret; 1050 1051 ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_STATUS, &sink_status); 1052 if (ret != 1) { 1053 lt_dbg(intel_dp, DP_PHY_DPRX, "Failed to read sink status\n"); 1054 return ret < 0 ? ret : -EIO; 1055 } 1056 1057 return sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION ? 1 : 0; 1058 } 1059 1060 /** 1061 * intel_dp_stop_link_train - stop link training 1062 * @intel_dp: DP struct 1063 * @crtc_state: state for CRTC attached to the encoder 1064 * 1065 * Stop the link training of the @intel_dp port, disabling the training 1066 * pattern in the sink's DPCD, and disabling the test pattern symbol 1067 * generation on the port. 1068 * 1069 * What symbols are output on the port after this point is 1070 * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern 1071 * with the pipe being disabled, on older platforms it's HW specific if/how an 1072 * idle pattern is generated, as the pipe is already enabled here for those. 1073 * 1074 * This function must be called after intel_dp_start_link_train(). 1075 */ 1076 void intel_dp_stop_link_train(struct intel_dp *intel_dp, 1077 const struct intel_crtc_state *crtc_state) 1078 { 1079 intel_dp->link_trained = true; 1080 1081 intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX); 1082 intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX, 1083 DP_TRAINING_PATTERN_DISABLE); 1084 1085 if (intel_dp_is_uhbr(crtc_state) && 1086 wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) { 1087 lt_dbg(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clearing\n"); 1088 } 1089 } 1090 1091 static bool 1092 intel_dp_link_train_phy(struct intel_dp *intel_dp, 1093 const struct intel_crtc_state *crtc_state, 1094 enum drm_dp_phy dp_phy) 1095 { 1096 bool ret = false; 1097 1098 if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy)) 1099 goto out; 1100 1101 if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy)) 1102 goto out; 1103 1104 ret = true; 1105 1106 out: 1107 lt_dbg(intel_dp, dp_phy, 1108 "Link Training %s at link rate = %d, lane count = %d\n", 1109 ret ? "passed" : "failed", 1110 crtc_state->port_clock, crtc_state->lane_count); 1111 1112 return ret; 1113 } 1114 1115 static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, 1116 const struct intel_crtc_state *crtc_state) 1117 { 1118 struct intel_connector *intel_connector = intel_dp->attached_connector; 1119 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1120 1121 if (!intel_digital_port_connected(&dp_to_dig_port(intel_dp)->base)) { 1122 lt_dbg(intel_dp, DP_PHY_DPRX, "Link Training failed on disconnected sink.\n"); 1123 return; 1124 } 1125 1126 if (intel_dp->hobl_active) { 1127 lt_dbg(intel_dp, DP_PHY_DPRX, 1128 "Link Training failed with HOBL active, not enabling it from now on\n"); 1129 intel_dp->hobl_failed = true; 1130 } else if (intel_dp_get_link_train_fallback_values(intel_dp, 1131 crtc_state->port_clock, 1132 crtc_state->lane_count)) { 1133 return; 1134 } 1135 1136 /* Schedule a Hotplug Uevent to userspace to start modeset */ 1137 queue_work(i915->unordered_wq, &intel_connector->modeset_retry_work); 1138 } 1139 1140 /* Perform the link training on all LTTPRs and the DPRX on a link. */ 1141 static bool 1142 intel_dp_link_train_all_phys(struct intel_dp *intel_dp, 1143 const struct intel_crtc_state *crtc_state, 1144 int lttpr_count) 1145 { 1146 bool ret = true; 1147 int i; 1148 1149 for (i = lttpr_count - 1; i >= 0; i--) { 1150 enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i); 1151 1152 ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy); 1153 intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy); 1154 1155 if (!ret) 1156 break; 1157 } 1158 1159 if (ret) 1160 ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX); 1161 1162 if (intel_dp->set_idle_link_train) 1163 intel_dp->set_idle_link_train(intel_dp, crtc_state); 1164 1165 return ret; 1166 } 1167 1168 /* 1169 * 128b/132b DP LANEx_EQ_DONE Sequence (DP 2.0 E11 3.5.2.16.1) 1170 */ 1171 static bool 1172 intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, 1173 const struct intel_crtc_state *crtc_state) 1174 { 1175 u8 link_status[DP_LINK_STATUS_SIZE]; 1176 int delay_us; 1177 int try, max_tries = 20; 1178 unsigned long deadline; 1179 bool timeout = false; 1180 1181 /* 1182 * Reset signal levels. Start transmitting 128b/132b TPS1. 1183 * 1184 * Put DPRX and LTTPRs (if any) into intra-hop AUX mode by writing TPS1 1185 * in DP_TRAINING_PATTERN_SET. 1186 */ 1187 if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX, 1188 DP_TRAINING_PATTERN_1)) { 1189 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS1\n"); 1190 return false; 1191 } 1192 1193 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1194 1195 /* Read the initial TX FFE settings. */ 1196 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1197 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read TX FFE presets\n"); 1198 return false; 1199 } 1200 1201 /* Update signal levels and training set as requested. */ 1202 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1203 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1204 lt_err(intel_dp, DP_PHY_DPRX, "Failed to set initial TX FFE settings\n"); 1205 return false; 1206 } 1207 1208 /* Start transmitting 128b/132b TPS2. */ 1209 if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX, 1210 DP_TRAINING_PATTERN_2)) { 1211 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2\n"); 1212 return false; 1213 } 1214 1215 /* Time budget for the LANEx_EQ_DONE Sequence */ 1216 deadline = jiffies + msecs_to_jiffies_timeout(400); 1217 1218 for (try = 0; try < max_tries; try++) { 1219 usleep_range(delay_us, 2 * delay_us); 1220 1221 /* 1222 * The delay may get updated. The transmitter shall read the 1223 * delay before link status during link training. 1224 */ 1225 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1226 1227 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1228 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1229 return false; 1230 } 1231 1232 if (drm_dp_128b132b_link_training_failed(link_status)) { 1233 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1234 lt_err(intel_dp, DP_PHY_DPRX, 1235 "Downstream link training failure\n"); 1236 return false; 1237 } 1238 1239 if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) { 1240 lt_dbg(intel_dp, DP_PHY_DPRX, "Lane channel eq done\n"); 1241 break; 1242 } 1243 1244 if (timeout) { 1245 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1246 lt_err(intel_dp, DP_PHY_DPRX, "Lane channel eq timeout\n"); 1247 return false; 1248 } 1249 1250 if (time_after(jiffies, deadline)) 1251 timeout = true; /* try one last time after deadline */ 1252 1253 /* Update signal levels and training set as requested. */ 1254 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1255 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1256 lt_err(intel_dp, DP_PHY_DPRX, "Failed to update TX FFE settings\n"); 1257 return false; 1258 } 1259 } 1260 1261 if (try == max_tries) { 1262 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1263 lt_err(intel_dp, DP_PHY_DPRX, "Max loop count reached\n"); 1264 return false; 1265 } 1266 1267 for (;;) { 1268 if (time_after(jiffies, deadline)) 1269 timeout = true; /* try one last time after deadline */ 1270 1271 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1272 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1273 return false; 1274 } 1275 1276 if (drm_dp_128b132b_link_training_failed(link_status)) { 1277 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1278 lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n"); 1279 return false; 1280 } 1281 1282 if (drm_dp_128b132b_eq_interlane_align_done(link_status)) { 1283 lt_dbg(intel_dp, DP_PHY_DPRX, "Interlane align done\n"); 1284 break; 1285 } 1286 1287 if (timeout) { 1288 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1289 lt_err(intel_dp, DP_PHY_DPRX, "Interlane align timeout\n"); 1290 return false; 1291 } 1292 1293 usleep_range(2000, 3000); 1294 } 1295 1296 return true; 1297 } 1298 1299 /* 1300 * 128b/132b DP LANEx_CDS_DONE Sequence (DP 2.0 E11 3.5.2.16.2) 1301 */ 1302 static bool 1303 intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp, 1304 const struct intel_crtc_state *crtc_state, 1305 int lttpr_count) 1306 { 1307 u8 link_status[DP_LINK_STATUS_SIZE]; 1308 unsigned long deadline; 1309 1310 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 1311 DP_TRAINING_PATTERN_2_CDS) != 1) { 1312 lt_err(intel_dp, DP_PHY_DPRX, "Failed to start 128b/132b TPS2 CDS\n"); 1313 return false; 1314 } 1315 1316 /* Time budget for the LANEx_CDS_DONE Sequence */ 1317 deadline = jiffies + msecs_to_jiffies_timeout((lttpr_count + 1) * 20); 1318 1319 for (;;) { 1320 bool timeout = false; 1321 1322 if (time_after(jiffies, deadline)) 1323 timeout = true; /* try one last time after deadline */ 1324 1325 usleep_range(2000, 3000); 1326 1327 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1328 lt_err(intel_dp, DP_PHY_DPRX, "Failed to read link status\n"); 1329 return false; 1330 } 1331 1332 if (drm_dp_128b132b_eq_interlane_align_done(link_status) && 1333 drm_dp_128b132b_cds_interlane_align_done(link_status) && 1334 drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) { 1335 lt_dbg(intel_dp, DP_PHY_DPRX, "CDS interlane align done\n"); 1336 break; 1337 } 1338 1339 if (drm_dp_128b132b_link_training_failed(link_status)) { 1340 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1341 lt_err(intel_dp, DP_PHY_DPRX, "Downstream link training failure\n"); 1342 return false; 1343 } 1344 1345 if (timeout) { 1346 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1347 lt_err(intel_dp, DP_PHY_DPRX, "CDS timeout\n"); 1348 return false; 1349 } 1350 } 1351 1352 return true; 1353 } 1354 1355 /* 1356 * 128b/132b link training sequence. (DP 2.0 E11 SCR on link training.) 1357 */ 1358 static bool 1359 intel_dp_128b132b_link_train(struct intel_dp *intel_dp, 1360 const struct intel_crtc_state *crtc_state, 1361 int lttpr_count) 1362 { 1363 bool passed = false; 1364 1365 if (wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) { 1366 lt_err(intel_dp, DP_PHY_DPRX, "128b/132b intra-hop not clear\n"); 1367 return false; 1368 } 1369 1370 if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) && 1371 intel_dp_128b132b_lane_cds(intel_dp, crtc_state, lttpr_count)) 1372 passed = true; 1373 1374 lt_dbg(intel_dp, DP_PHY_DPRX, 1375 "128b/132b Link Training %s at link rate = %d, lane count = %d\n", 1376 passed ? "passed" : "failed", 1377 crtc_state->port_clock, crtc_state->lane_count); 1378 1379 return passed; 1380 } 1381 1382 /** 1383 * intel_dp_start_link_train - start link training 1384 * @intel_dp: DP struct 1385 * @crtc_state: state for CRTC attached to the encoder 1386 * 1387 * Start the link training of the @intel_dp port, scheduling a fallback 1388 * retraining with reduced link rate/lane parameters if the link training 1389 * fails. 1390 * After calling this function intel_dp_stop_link_train() must be called. 1391 */ 1392 void intel_dp_start_link_train(struct intel_dp *intel_dp, 1393 const struct intel_crtc_state *crtc_state) 1394 { 1395 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1396 bool passed; 1397 /* 1398 * Reinit the LTTPRs here to ensure that they are switched to 1399 * non-transparent mode. During an earlier LTTPR detection this 1400 * could've been prevented by an active link. 1401 */ 1402 int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp); 1403 1404 if (lttpr_count < 0) 1405 /* Still continue with enabling the port and link training. */ 1406 lttpr_count = 0; 1407 1408 intel_dp_prepare_link_train(intel_dp, crtc_state); 1409 1410 if (intel_dp_is_uhbr(crtc_state)) 1411 passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count); 1412 else 1413 passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); 1414 1415 /* 1416 * Ignore the link failure in CI 1417 * 1418 * In fixed enviroments like CI, sometimes unexpected long HPDs are 1419 * generated by the displays. If ignore_long_hpd flag is set, such long 1420 * HPDs are ignored. And probably as a consequence of these ignored 1421 * long HPDs, subsequent link trainings are failed resulting into CI 1422 * execution failures. 1423 * 1424 * For test cases which rely on the link training or processing of HPDs 1425 * ignore_long_hpd flag can unset from the testcase. 1426 */ 1427 if (!passed && i915->display.hotplug.ignore_long_hpd) { 1428 lt_dbg(intel_dp, DP_PHY_DPRX, "Ignore the link failure\n"); 1429 return; 1430 } 1431 1432 if (!passed) 1433 intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); 1434 } 1435 1436 void intel_dp_128b132b_sdp_crc16(struct intel_dp *intel_dp, 1437 const struct intel_crtc_state *crtc_state) 1438 { 1439 /* 1440 * VIDEO_DIP_CTL register bit 31 should be set to '0' to not 1441 * disable SDP CRC. This is applicable for Display version 13. 1442 * Default value of bit 31 is '0' hence discarding the write 1443 * TODO: Corrective actions on SDP corruption yet to be defined 1444 */ 1445 if (intel_dp_is_uhbr(crtc_state)) 1446 /* DP v2.0 SCR on SDP CRC16 for 128b/132b Link Layer */ 1447 drm_dp_dpcd_writeb(&intel_dp->aux, 1448 DP_SDP_ERROR_DETECTION_CONFIGURATION, 1449 DP_SDP_CRC16_128B132B_EN); 1450 1451 lt_dbg(intel_dp, DP_PHY_DPRX, "DP2.0 SDP CRC16 for 128b/132b enabled\n"); 1452 } 1453