1 /* 2 * Copyright © 2008-2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include "intel_display_types.h" 25 #include "intel_dp.h" 26 #include "intel_dp_link_training.h" 27 28 static void 29 intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE]) 30 { 31 32 DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x", 33 link_status[0], link_status[1], link_status[2], 34 link_status[3], link_status[4], link_status[5]); 35 } 36 37 static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp) 38 { 39 memset(&intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); 40 } 41 42 static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp) 43 { 44 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - 45 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0; 46 } 47 48 static const char *intel_dp_phy_name(enum drm_dp_phy dp_phy, 49 char *buf, size_t buf_size) 50 { 51 if (dp_phy == DP_PHY_DPRX) 52 snprintf(buf, buf_size, "DPRX"); 53 else 54 snprintf(buf, buf_size, "LTTPR %d", dp_phy - DP_PHY_LTTPR1 + 1); 55 56 return buf; 57 } 58 59 static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp, 60 enum drm_dp_phy dp_phy) 61 { 62 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; 63 } 64 65 static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, 66 enum drm_dp_phy dp_phy) 67 { 68 u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 69 char phy_name[10]; 70 71 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)); 72 73 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) { 74 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 75 "failed to read the PHY caps for %s\n", 76 phy_name); 77 return; 78 } 79 80 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 81 "%s PHY capabilities: %*ph\n", 82 phy_name, 83 (int)sizeof(intel_dp->lttpr_phy_caps[0]), 84 phy_caps); 85 } 86 87 static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp) 88 { 89 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 90 91 if (intel_dp_is_edp(intel_dp)) 92 return false; 93 94 /* 95 * Detecting LTTPRs must be avoided on platforms with an AUX timeout 96 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1). 97 */ 98 if (INTEL_GEN(i915) < 10) 99 return false; 100 101 if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, 102 intel_dp->lttpr_common_caps) < 0) 103 goto reset_caps; 104 105 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 106 "LTTPR common capabilities: %*ph\n", 107 (int)sizeof(intel_dp->lttpr_common_caps), 108 intel_dp->lttpr_common_caps); 109 110 /* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */ 111 if (intel_dp->lttpr_common_caps[0] < 0x14) 112 goto reset_caps; 113 114 return true; 115 116 reset_caps: 117 intel_dp_reset_lttpr_common_caps(intel_dp); 118 return false; 119 } 120 121 static bool 122 intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) 123 { 124 u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : 125 DP_PHY_REPEATER_MODE_NON_TRANSPARENT; 126 127 return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1; 128 } 129 130 /** 131 * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode 132 * @intel_dp: Intel DP struct 133 * 134 * Read the LTTPR common and DPRX capabilities and switch to non-transparent 135 * link training mode if any is detected and read the PHY capabilities for all 136 * detected LTTPRs. In case of an LTTPR detection error or if the number of 137 * LTTPRs is more than is supported (8), fall back to the no-LTTPR, 138 * transparent mode link training mode. 139 * 140 * Returns: 141 * >0 if LTTPRs were detected and the non-transparent LT mode was set. The 142 * DPRX capabilities are read out. 143 * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a 144 * detection failure and the transparent LT mode was set. The DPRX 145 * capabilities are read out. 146 * <0 Reading out the DPRX capabilities failed. 147 */ 148 int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) 149 { 150 int lttpr_count; 151 bool ret; 152 int i; 153 154 ret = intel_dp_read_lttpr_common_caps(intel_dp); 155 156 /* The DPTX shall read the DPRX caps after LTTPR detection. */ 157 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) { 158 intel_dp_reset_lttpr_common_caps(intel_dp); 159 return -EIO; 160 } 161 162 if (!ret) 163 return 0; 164 165 /* 166 * The 0xF0000-0xF02FF range is only valid if the DPCD revision is 167 * at least 1.4. 168 */ 169 if (intel_dp->dpcd[DP_DPCD_REV] < 0x14) { 170 intel_dp_reset_lttpr_common_caps(intel_dp); 171 return 0; 172 } 173 174 lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 175 /* 176 * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are 177 * detected as this breaks link training at least on the Dell WD19TB 178 * dock. 179 */ 180 if (lttpr_count == 0) 181 return 0; 182 183 /* 184 * See DP Standard v2.0 3.6.6.1. about the explicit disabling of 185 * non-transparent mode and the disable->enable non-transparent mode 186 * sequence. 187 */ 188 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 189 190 /* 191 * In case of unsupported number of LTTPRs or failing to switch to 192 * non-transparent mode fall-back to transparent link training mode, 193 * still taking into account any LTTPR common lane- rate/count limits. 194 */ 195 if (lttpr_count < 0) 196 return 0; 197 198 if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) { 199 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 200 "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n"); 201 202 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 203 intel_dp_reset_lttpr_count(intel_dp); 204 205 return 0; 206 } 207 208 for (i = 0; i < lttpr_count; i++) 209 intel_dp_read_lttpr_phy_caps(intel_dp, DP_PHY_LTTPR(i)); 210 211 return lttpr_count; 212 } 213 EXPORT_SYMBOL(intel_dp_init_lttpr_and_dprx_caps); 214 215 static u8 dp_voltage_max(u8 preemph) 216 { 217 switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) { 218 case DP_TRAIN_PRE_EMPH_LEVEL_0: 219 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 220 case DP_TRAIN_PRE_EMPH_LEVEL_1: 221 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 222 case DP_TRAIN_PRE_EMPH_LEVEL_2: 223 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1; 224 case DP_TRAIN_PRE_EMPH_LEVEL_3: 225 default: 226 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 227 } 228 } 229 230 static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp, 231 enum drm_dp_phy dp_phy) 232 { 233 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 234 235 if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps)) 236 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 237 else 238 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 239 } 240 241 static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp, 242 enum drm_dp_phy dp_phy) 243 { 244 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 245 246 if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps)) 247 return DP_TRAIN_PRE_EMPH_LEVEL_3; 248 else 249 return DP_TRAIN_PRE_EMPH_LEVEL_2; 250 } 251 252 static bool 253 intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp, 254 enum drm_dp_phy dp_phy) 255 { 256 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 257 int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 258 259 drm_WARN_ON_ONCE(&i915->drm, lttpr_count <= 0 && dp_phy != DP_PHY_DPRX); 260 261 return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1); 262 } 263 264 static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp, 265 const struct intel_crtc_state *crtc_state, 266 enum drm_dp_phy dp_phy) 267 { 268 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 269 u8 voltage_max; 270 271 /* 272 * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from 273 * the DPRX_PHY we train. 274 */ 275 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 276 voltage_max = intel_dp->voltage_max(intel_dp, crtc_state); 277 else 278 voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1); 279 280 drm_WARN_ON_ONCE(&i915->drm, 281 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 && 282 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3); 283 284 return voltage_max; 285 } 286 287 static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, 288 enum drm_dp_phy dp_phy) 289 { 290 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 291 u8 preemph_max; 292 293 /* 294 * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from 295 * the DPRX_PHY we train. 296 */ 297 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 298 preemph_max = intel_dp->preemph_max(intel_dp); 299 else 300 preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1); 301 302 drm_WARN_ON_ONCE(&i915->drm, 303 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 && 304 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3); 305 306 return preemph_max; 307 } 308 309 void 310 intel_dp_get_adjust_train(struct intel_dp *intel_dp, 311 const struct intel_crtc_state *crtc_state, 312 enum drm_dp_phy dp_phy, 313 const u8 link_status[DP_LINK_STATUS_SIZE]) 314 { 315 u8 v = 0; 316 u8 p = 0; 317 int lane; 318 u8 voltage_max; 319 u8 preemph_max; 320 321 for (lane = 0; lane < crtc_state->lane_count; lane++) { 322 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); 323 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); 324 } 325 326 preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy); 327 if (p >= preemph_max) 328 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 329 330 v = min(v, dp_voltage_max(p)); 331 332 voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy); 333 if (v >= voltage_max) 334 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 335 336 for (lane = 0; lane < 4; lane++) 337 intel_dp->train_set[lane] = v | p; 338 } 339 340 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp, 341 enum drm_dp_phy dp_phy) 342 { 343 return dp_phy == DP_PHY_DPRX ? 344 DP_TRAINING_PATTERN_SET : 345 DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy); 346 } 347 348 static bool 349 intel_dp_set_link_train(struct intel_dp *intel_dp, 350 const struct intel_crtc_state *crtc_state, 351 enum drm_dp_phy dp_phy, 352 u8 dp_train_pat) 353 { 354 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 355 u8 buf[sizeof(intel_dp->train_set) + 1]; 356 int len; 357 358 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 359 dp_train_pat); 360 361 buf[0] = dp_train_pat; 362 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 363 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); 364 len = crtc_state->lane_count + 1; 365 366 return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len; 367 } 368 369 void intel_dp_set_signal_levels(struct intel_dp *intel_dp, 370 const struct intel_crtc_state *crtc_state, 371 enum drm_dp_phy dp_phy) 372 { 373 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 374 u8 train_set = intel_dp->train_set[0]; 375 char phy_name[10]; 376 377 drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n", 378 train_set & DP_TRAIN_VOLTAGE_SWING_MASK, 379 train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "", 380 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> 381 DP_TRAIN_PRE_EMPHASIS_SHIFT, 382 train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? 383 " (max)" : "", 384 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name))); 385 386 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 387 intel_dp->set_signal_levels(intel_dp, crtc_state); 388 } 389 390 static bool 391 intel_dp_reset_link_train(struct intel_dp *intel_dp, 392 const struct intel_crtc_state *crtc_state, 393 enum drm_dp_phy dp_phy, 394 u8 dp_train_pat) 395 { 396 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 397 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 398 return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat); 399 } 400 401 static bool 402 intel_dp_update_link_train(struct intel_dp *intel_dp, 403 const struct intel_crtc_state *crtc_state, 404 enum drm_dp_phy dp_phy) 405 { 406 int reg = dp_phy == DP_PHY_DPRX ? 407 DP_TRAINING_LANE0_SET : 408 DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy); 409 int ret; 410 411 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 412 413 ret = drm_dp_dpcd_write(&intel_dp->aux, reg, 414 intel_dp->train_set, crtc_state->lane_count); 415 416 return ret == crtc_state->lane_count; 417 } 418 419 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp, 420 const struct intel_crtc_state *crtc_state) 421 { 422 int lane; 423 424 for (lane = 0; lane < crtc_state->lane_count; lane++) 425 if ((intel_dp->train_set[lane] & 426 DP_TRAIN_MAX_SWING_REACHED) == 0) 427 return false; 428 429 return true; 430 } 431 432 /* 433 * Prepare link training by configuring the link parameters. On DDI platforms 434 * also enable the port here. 435 */ 436 static bool 437 intel_dp_prepare_link_train(struct intel_dp *intel_dp, 438 const struct intel_crtc_state *crtc_state) 439 { 440 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 441 u8 link_config[2]; 442 u8 link_bw, rate_select; 443 444 if (intel_dp->prepare_link_retrain) 445 intel_dp->prepare_link_retrain(intel_dp, crtc_state); 446 447 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, 448 &link_bw, &rate_select); 449 450 if (link_bw) 451 drm_dbg_kms(&i915->drm, 452 "Using LINK_BW_SET value %02x\n", link_bw); 453 else 454 drm_dbg_kms(&i915->drm, 455 "Using LINK_RATE_SET value %02x\n", rate_select); 456 457 /* Write the link configuration data */ 458 link_config[0] = link_bw; 459 link_config[1] = crtc_state->lane_count; 460 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 461 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 462 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); 463 464 /* eDP 1.4 rate select method. */ 465 if (!link_bw) 466 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET, 467 &rate_select, 1); 468 469 link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; 470 link_config[1] = DP_SET_ANSI_8B10B; 471 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 472 473 intel_dp->DP |= DP_PORT_EN; 474 475 return true; 476 } 477 478 static void intel_dp_link_training_clock_recovery_delay(struct intel_dp *intel_dp, 479 enum drm_dp_phy dp_phy) 480 { 481 if (dp_phy == DP_PHY_DPRX) 482 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 483 else 484 drm_dp_lttpr_link_train_clock_recovery_delay(); 485 } 486 487 /* 488 * Perform the link training clock recovery phase on the given DP PHY using 489 * training pattern 1. 490 */ 491 static bool 492 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, 493 const struct intel_crtc_state *crtc_state, 494 enum drm_dp_phy dp_phy) 495 { 496 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 497 u8 voltage; 498 int voltage_tries, cr_tries, max_cr_tries; 499 bool max_vswing_reached = false; 500 501 /* clock recovery */ 502 if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy, 503 DP_TRAINING_PATTERN_1 | 504 DP_LINK_SCRAMBLING_DISABLE)) { 505 drm_err(&i915->drm, "failed to enable link training\n"); 506 return false; 507 } 508 509 /* 510 * The DP 1.4 spec defines the max clock recovery retries value 511 * as 10 but for pre-DP 1.4 devices we set a very tolerant 512 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x 513 * x 5 identical voltage retries). Since the previous specs didn't 514 * define a limit and created the possibility of an infinite loop 515 * we want to prevent any sync from triggering that corner case. 516 */ 517 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 518 max_cr_tries = 10; 519 else 520 max_cr_tries = 80; 521 522 voltage_tries = 1; 523 for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) { 524 u8 link_status[DP_LINK_STATUS_SIZE]; 525 526 intel_dp_link_training_clock_recovery_delay(intel_dp, dp_phy); 527 528 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 529 link_status) < 0) { 530 drm_err(&i915->drm, "failed to get link status\n"); 531 return false; 532 } 533 534 if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) { 535 drm_dbg_kms(&i915->drm, "clock recovery OK\n"); 536 return true; 537 } 538 539 if (voltage_tries == 5) { 540 drm_dbg_kms(&i915->drm, 541 "Same voltage tried 5 times\n"); 542 return false; 543 } 544 545 if (max_vswing_reached) { 546 drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n"); 547 return false; 548 } 549 550 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 551 552 /* Update training set as requested by target */ 553 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 554 link_status); 555 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 556 drm_err(&i915->drm, 557 "failed to update link training\n"); 558 return false; 559 } 560 561 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == 562 voltage) 563 ++voltage_tries; 564 else 565 voltage_tries = 1; 566 567 if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state)) 568 max_vswing_reached = true; 569 570 } 571 drm_err(&i915->drm, 572 "Failed clock recovery %d times, giving up!\n", max_cr_tries); 573 return false; 574 } 575 576 /* 577 * Pick training pattern for channel equalization. Training pattern 4 for HBR3 578 * or for 1.4 devices that support it, training Pattern 3 for HBR2 579 * or 1.2 devices that support it, Training Pattern 2 otherwise. 580 */ 581 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, 582 const struct intel_crtc_state *crtc_state, 583 enum drm_dp_phy dp_phy) 584 { 585 bool source_tps3, sink_tps3, source_tps4, sink_tps4; 586 587 /* 588 * Intel platforms that support HBR3 also support TPS4. It is mandatory 589 * for all downstream devices that support HBR3. There are no known eDP 590 * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 591 * specification. 592 * LTTPRs must support TPS4. 593 */ 594 source_tps4 = intel_dp_source_supports_hbr3(intel_dp); 595 sink_tps4 = dp_phy != DP_PHY_DPRX || 596 drm_dp_tps4_supported(intel_dp->dpcd); 597 if (source_tps4 && sink_tps4) { 598 return DP_TRAINING_PATTERN_4; 599 } else if (crtc_state->port_clock == 810000) { 600 if (!source_tps4) 601 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 602 "8.1 Gbps link rate without source HBR3/TPS4 support\n"); 603 if (!sink_tps4) 604 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 605 "8.1 Gbps link rate without sink TPS4 support\n"); 606 } 607 /* 608 * Intel platforms that support HBR2 also support TPS3. TPS3 support is 609 * also mandatory for downstream devices that support HBR2. However, not 610 * all sinks follow the spec. 611 */ 612 source_tps3 = intel_dp_source_supports_hbr2(intel_dp); 613 sink_tps3 = dp_phy != DP_PHY_DPRX || 614 drm_dp_tps3_supported(intel_dp->dpcd); 615 if (source_tps3 && sink_tps3) { 616 return DP_TRAINING_PATTERN_3; 617 } else if (crtc_state->port_clock >= 540000) { 618 if (!source_tps3) 619 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 620 ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n"); 621 if (!sink_tps3) 622 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 623 ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); 624 } 625 626 return DP_TRAINING_PATTERN_2; 627 } 628 629 static void 630 intel_dp_link_training_channel_equalization_delay(struct intel_dp *intel_dp, 631 enum drm_dp_phy dp_phy) 632 { 633 if (dp_phy == DP_PHY_DPRX) { 634 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 635 } else { 636 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 637 638 drm_dp_lttpr_link_train_channel_eq_delay(phy_caps); 639 } 640 } 641 642 /* 643 * Perform the link training channel equalization phase on the given DP PHY 644 * using one of training pattern 2, 3 or 4 depending on the source and 645 * sink capabilities. 646 */ 647 static bool 648 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp, 649 const struct intel_crtc_state *crtc_state, 650 enum drm_dp_phy dp_phy) 651 { 652 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 653 int tries; 654 u32 training_pattern; 655 u8 link_status[DP_LINK_STATUS_SIZE]; 656 bool channel_eq = false; 657 658 training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy); 659 /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ 660 if (training_pattern != DP_TRAINING_PATTERN_4) 661 training_pattern |= DP_LINK_SCRAMBLING_DISABLE; 662 663 /* channel equalization */ 664 if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, 665 training_pattern)) { 666 drm_err(&i915->drm, "failed to start channel equalization\n"); 667 return false; 668 } 669 670 for (tries = 0; tries < 5; tries++) { 671 intel_dp_link_training_channel_equalization_delay(intel_dp, 672 dp_phy); 673 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 674 link_status) < 0) { 675 drm_err(&i915->drm, 676 "failed to get link status\n"); 677 break; 678 } 679 680 /* Make sure clock is still ok */ 681 if (!drm_dp_clock_recovery_ok(link_status, 682 crtc_state->lane_count)) { 683 intel_dp_dump_link_status(link_status); 684 drm_dbg_kms(&i915->drm, 685 "Clock recovery check failed, cannot " 686 "continue channel equalization\n"); 687 break; 688 } 689 690 if (drm_dp_channel_eq_ok(link_status, 691 crtc_state->lane_count)) { 692 channel_eq = true; 693 drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training " 694 "successful\n"); 695 break; 696 } 697 698 /* Update training set as requested by target */ 699 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 700 link_status); 701 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 702 drm_err(&i915->drm, 703 "failed to update link training\n"); 704 break; 705 } 706 } 707 708 /* Try 5 times, else fail and try at lower BW */ 709 if (tries == 5) { 710 intel_dp_dump_link_status(link_status); 711 drm_dbg_kms(&i915->drm, 712 "Channel equalization failed 5 times\n"); 713 } 714 715 return channel_eq; 716 } 717 718 static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp, 719 enum drm_dp_phy dp_phy) 720 { 721 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 722 u8 val = DP_TRAINING_PATTERN_DISABLE; 723 724 return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1; 725 } 726 727 /** 728 * intel_dp_stop_link_train - stop link training 729 * @intel_dp: DP struct 730 * @crtc_state: state for CRTC attached to the encoder 731 * 732 * Stop the link training of the @intel_dp port, disabling the training 733 * pattern in the sink's DPCD, and disabling the test pattern symbol 734 * generation on the port. 735 * 736 * What symbols are output on the port after this point is 737 * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern 738 * with the pipe being disabled, on older platforms it's HW specific if/how an 739 * idle pattern is generated, as the pipe is already enabled here for those. 740 * 741 * This function must be called after intel_dp_start_link_train(). 742 */ 743 void intel_dp_stop_link_train(struct intel_dp *intel_dp, 744 const struct intel_crtc_state *crtc_state) 745 { 746 intel_dp->link_trained = true; 747 748 intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX); 749 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 750 DP_TRAINING_PATTERN_DISABLE); 751 } 752 753 static bool 754 intel_dp_link_train_phy(struct intel_dp *intel_dp, 755 const struct intel_crtc_state *crtc_state, 756 enum drm_dp_phy dp_phy) 757 { 758 struct intel_connector *intel_connector = intel_dp->attached_connector; 759 char phy_name[10]; 760 bool ret = false; 761 762 if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy)) 763 goto out; 764 765 if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy)) 766 goto out; 767 768 ret = true; 769 770 out: 771 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 772 "[CONNECTOR:%d:%s] Link Training %s at link rate = %d, lane count = %d, at %s", 773 intel_connector->base.base.id, 774 intel_connector->base.name, 775 ret ? "passed" : "failed", 776 crtc_state->port_clock, crtc_state->lane_count, 777 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name))); 778 779 return ret; 780 } 781 782 static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, 783 const struct intel_crtc_state *crtc_state) 784 { 785 struct intel_connector *intel_connector = intel_dp->attached_connector; 786 787 if (intel_dp->hobl_active) { 788 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 789 "Link Training failed with HOBL active, not enabling it from now on"); 790 intel_dp->hobl_failed = true; 791 } else if (intel_dp_get_link_train_fallback_values(intel_dp, 792 crtc_state->port_clock, 793 crtc_state->lane_count)) { 794 return; 795 } 796 797 /* Schedule a Hotplug Uevent to userspace to start modeset */ 798 schedule_work(&intel_connector->modeset_retry_work); 799 } 800 801 /* Perform the link training on all LTTPRs and the DPRX on a link. */ 802 static bool 803 intel_dp_link_train_all_phys(struct intel_dp *intel_dp, 804 const struct intel_crtc_state *crtc_state, 805 int lttpr_count) 806 { 807 bool ret = true; 808 int i; 809 810 intel_dp_prepare_link_train(intel_dp, crtc_state); 811 812 for (i = lttpr_count - 1; i >= 0; i--) { 813 enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i); 814 815 ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy); 816 intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy); 817 818 if (!ret) 819 break; 820 } 821 822 if (ret) 823 intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX); 824 825 if (intel_dp->set_idle_link_train) 826 intel_dp->set_idle_link_train(intel_dp, crtc_state); 827 828 return ret; 829 } 830 831 /** 832 * intel_dp_start_link_train - start link training 833 * @intel_dp: DP struct 834 * @crtc_state: state for CRTC attached to the encoder 835 * 836 * Start the link training of the @intel_dp port, scheduling a fallback 837 * retraining with reduced link rate/lane parameters if the link training 838 * fails. 839 * After calling this function intel_dp_stop_link_train() must be called. 840 */ 841 void intel_dp_start_link_train(struct intel_dp *intel_dp, 842 const struct intel_crtc_state *crtc_state) 843 { 844 /* 845 * TODO: Reiniting LTTPRs here won't be needed once proper connector 846 * HW state readout is added. 847 */ 848 int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp); 849 850 if (lttpr_count < 0) 851 return; 852 853 if (!intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count)) 854 intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); 855 } 856