1 /* 2 * Copyright © 2008-2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include "i915_drv.h" 25 #include "intel_display_types.h" 26 #include "intel_dp.h" 27 #include "intel_dp_link_training.h" 28 29 static void intel_dp_reset_lttpr_common_caps(struct intel_dp *intel_dp) 30 { 31 memset(intel_dp->lttpr_common_caps, 0, sizeof(intel_dp->lttpr_common_caps)); 32 } 33 34 static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp) 35 { 36 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - 37 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0; 38 } 39 40 static const char *intel_dp_phy_name(enum drm_dp_phy dp_phy, 41 char *buf, size_t buf_size) 42 { 43 if (dp_phy == DP_PHY_DPRX) 44 snprintf(buf, buf_size, "DPRX"); 45 else 46 snprintf(buf, buf_size, "LTTPR %d", dp_phy - DP_PHY_LTTPR1 + 1); 47 48 return buf; 49 } 50 51 static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp, 52 enum drm_dp_phy dp_phy) 53 { 54 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; 55 } 56 57 static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, 58 const u8 dpcd[DP_RECEIVER_CAP_SIZE], 59 enum drm_dp_phy dp_phy) 60 { 61 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 62 u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 63 char phy_name[10]; 64 65 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)); 66 67 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dpcd, dp_phy, phy_caps) < 0) { 68 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 69 "[ENCODER:%d:%s][%s] failed to read the PHY caps\n", 70 encoder->base.base.id, encoder->base.name, phy_name); 71 return; 72 } 73 74 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 75 "[ENCODER:%d:%s][%s] PHY capabilities: %*ph\n", 76 encoder->base.base.id, encoder->base.name, phy_name, 77 (int)sizeof(intel_dp->lttpr_phy_caps[0]), 78 phy_caps); 79 } 80 81 static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp, 82 const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 83 { 84 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 85 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 86 int ret; 87 88 if (intel_dp_is_edp(intel_dp)) 89 return false; 90 91 /* 92 * Detecting LTTPRs must be avoided on platforms with an AUX timeout 93 * period < 3.2ms. (see DP Standard v2.0, 2.11.2, 3.6.6.1). 94 */ 95 if (DISPLAY_VER(i915) < 10 || IS_GEMINILAKE(i915)) 96 return false; 97 98 ret = drm_dp_read_lttpr_common_caps(&intel_dp->aux, dpcd, 99 intel_dp->lttpr_common_caps); 100 if (ret < 0) 101 goto reset_caps; 102 103 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 104 "[ENCODER:%d:%s] LTTPR common capabilities: %*ph\n", 105 encoder->base.base.id, encoder->base.name, 106 (int)sizeof(intel_dp->lttpr_common_caps), 107 intel_dp->lttpr_common_caps); 108 109 /* The minimum value of LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV is 1.4 */ 110 if (intel_dp->lttpr_common_caps[0] < 0x14) 111 goto reset_caps; 112 113 return true; 114 115 reset_caps: 116 intel_dp_reset_lttpr_common_caps(intel_dp); 117 return false; 118 } 119 120 static bool 121 intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) 122 { 123 u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : 124 DP_PHY_REPEATER_MODE_NON_TRANSPARENT; 125 126 return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1; 127 } 128 129 static int intel_dp_init_lttpr(struct intel_dp *intel_dp, const u8 dpcd[DP_RECEIVER_CAP_SIZE]) 130 { 131 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 132 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 133 int lttpr_count; 134 int i; 135 136 if (!intel_dp_read_lttpr_common_caps(intel_dp, dpcd)) 137 return 0; 138 139 lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 140 /* 141 * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are 142 * detected as this breaks link training at least on the Dell WD19TB 143 * dock. 144 */ 145 if (lttpr_count == 0) 146 return 0; 147 148 /* 149 * See DP Standard v2.0 3.6.6.1. about the explicit disabling of 150 * non-transparent mode and the disable->enable non-transparent mode 151 * sequence. 152 */ 153 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 154 155 /* 156 * In case of unsupported number of LTTPRs or failing to switch to 157 * non-transparent mode fall-back to transparent link training mode, 158 * still taking into account any LTTPR common lane- rate/count limits. 159 */ 160 if (lttpr_count < 0) 161 return 0; 162 163 if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) { 164 drm_dbg_kms(&i915->drm, 165 "[ENCODER:%d:%s] Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n", 166 encoder->base.base.id, encoder->base.name); 167 168 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 169 intel_dp_reset_lttpr_count(intel_dp); 170 171 return 0; 172 } 173 174 for (i = 0; i < lttpr_count; i++) 175 intel_dp_read_lttpr_phy_caps(intel_dp, dpcd, DP_PHY_LTTPR(i)); 176 177 return lttpr_count; 178 } 179 180 /** 181 * intel_dp_init_lttpr_and_dprx_caps - detect LTTPR and DPRX caps, init the LTTPR link training mode 182 * @intel_dp: Intel DP struct 183 * 184 * Read the LTTPR common and DPRX capabilities and switch to non-transparent 185 * link training mode if any is detected and read the PHY capabilities for all 186 * detected LTTPRs. In case of an LTTPR detection error or if the number of 187 * LTTPRs is more than is supported (8), fall back to the no-LTTPR, 188 * transparent mode link training mode. 189 * 190 * Returns: 191 * >0 if LTTPRs were detected and the non-transparent LT mode was set. The 192 * DPRX capabilities are read out. 193 * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a 194 * detection failure and the transparent LT mode was set. The DPRX 195 * capabilities are read out. 196 * <0 Reading out the DPRX capabilities failed. 197 */ 198 int intel_dp_init_lttpr_and_dprx_caps(struct intel_dp *intel_dp) 199 { 200 u8 dpcd[DP_RECEIVER_CAP_SIZE]; 201 int lttpr_count; 202 203 if (drm_dp_read_dpcd_caps(&intel_dp->aux, dpcd)) 204 return -EIO; 205 206 lttpr_count = intel_dp_init_lttpr(intel_dp, dpcd); 207 208 /* 209 * The DPTX shall read the DPRX caps after LTTPR detection, so re-read 210 * it here. 211 */ 212 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd)) { 213 intel_dp_reset_lttpr_common_caps(intel_dp); 214 return -EIO; 215 } 216 217 return lttpr_count; 218 } 219 220 static u8 dp_voltage_max(u8 preemph) 221 { 222 switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) { 223 case DP_TRAIN_PRE_EMPH_LEVEL_0: 224 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 225 case DP_TRAIN_PRE_EMPH_LEVEL_1: 226 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 227 case DP_TRAIN_PRE_EMPH_LEVEL_2: 228 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1; 229 case DP_TRAIN_PRE_EMPH_LEVEL_3: 230 default: 231 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 232 } 233 } 234 235 static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp, 236 enum drm_dp_phy dp_phy) 237 { 238 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 239 240 if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps)) 241 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 242 else 243 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 244 } 245 246 static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp, 247 enum drm_dp_phy dp_phy) 248 { 249 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 250 251 if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps)) 252 return DP_TRAIN_PRE_EMPH_LEVEL_3; 253 else 254 return DP_TRAIN_PRE_EMPH_LEVEL_2; 255 } 256 257 static bool 258 intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp, 259 enum drm_dp_phy dp_phy) 260 { 261 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 262 int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 263 264 drm_WARN_ON_ONCE(&i915->drm, lttpr_count <= 0 && dp_phy != DP_PHY_DPRX); 265 266 return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1); 267 } 268 269 static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp, 270 const struct intel_crtc_state *crtc_state, 271 enum drm_dp_phy dp_phy) 272 { 273 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 274 u8 voltage_max; 275 276 /* 277 * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from 278 * the DPRX_PHY we train. 279 */ 280 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 281 voltage_max = intel_dp->voltage_max(intel_dp, crtc_state); 282 else 283 voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1); 284 285 drm_WARN_ON_ONCE(&i915->drm, 286 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 && 287 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3); 288 289 return voltage_max; 290 } 291 292 static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, 293 enum drm_dp_phy dp_phy) 294 { 295 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 296 u8 preemph_max; 297 298 /* 299 * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from 300 * the DPRX_PHY we train. 301 */ 302 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 303 preemph_max = intel_dp->preemph_max(intel_dp); 304 else 305 preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1); 306 307 drm_WARN_ON_ONCE(&i915->drm, 308 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 && 309 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3); 310 311 return preemph_max; 312 } 313 314 static bool has_per_lane_signal_levels(struct intel_dp *intel_dp, 315 enum drm_dp_phy dp_phy) 316 { 317 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 318 319 return !intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy) || 320 DISPLAY_VER(i915) >= 11; 321 } 322 323 /* 128b/132b */ 324 static u8 intel_dp_get_lane_adjust_tx_ffe_preset(struct intel_dp *intel_dp, 325 const struct intel_crtc_state *crtc_state, 326 enum drm_dp_phy dp_phy, 327 const u8 link_status[DP_LINK_STATUS_SIZE], 328 int lane) 329 { 330 u8 tx_ffe = 0; 331 332 if (has_per_lane_signal_levels(intel_dp, dp_phy)) { 333 lane = min(lane, crtc_state->lane_count - 1); 334 tx_ffe = drm_dp_get_adjust_tx_ffe_preset(link_status, lane); 335 } else { 336 for (lane = 0; lane < crtc_state->lane_count; lane++) 337 tx_ffe = max(tx_ffe, drm_dp_get_adjust_tx_ffe_preset(link_status, lane)); 338 } 339 340 return tx_ffe; 341 } 342 343 /* 8b/10b */ 344 static u8 intel_dp_get_lane_adjust_vswing_preemph(struct intel_dp *intel_dp, 345 const struct intel_crtc_state *crtc_state, 346 enum drm_dp_phy dp_phy, 347 const u8 link_status[DP_LINK_STATUS_SIZE], 348 int lane) 349 { 350 u8 v = 0; 351 u8 p = 0; 352 u8 voltage_max; 353 u8 preemph_max; 354 355 if (has_per_lane_signal_levels(intel_dp, dp_phy)) { 356 lane = min(lane, crtc_state->lane_count - 1); 357 358 v = drm_dp_get_adjust_request_voltage(link_status, lane); 359 p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); 360 } else { 361 for (lane = 0; lane < crtc_state->lane_count; lane++) { 362 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); 363 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); 364 } 365 } 366 367 preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy); 368 if (p >= preemph_max) 369 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 370 371 v = min(v, dp_voltage_max(p)); 372 373 voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy); 374 if (v >= voltage_max) 375 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 376 377 return v | p; 378 } 379 380 static u8 intel_dp_get_lane_adjust_train(struct intel_dp *intel_dp, 381 const struct intel_crtc_state *crtc_state, 382 enum drm_dp_phy dp_phy, 383 const u8 link_status[DP_LINK_STATUS_SIZE], 384 int lane) 385 { 386 if (intel_dp_is_uhbr(crtc_state)) 387 return intel_dp_get_lane_adjust_tx_ffe_preset(intel_dp, crtc_state, 388 dp_phy, link_status, lane); 389 else 390 return intel_dp_get_lane_adjust_vswing_preemph(intel_dp, crtc_state, 391 dp_phy, link_status, lane); 392 } 393 394 #define TRAIN_REQ_FMT "%d/%d/%d/%d" 395 #define _TRAIN_REQ_VSWING_ARGS(link_status, lane) \ 396 (drm_dp_get_adjust_request_voltage((link_status), (lane)) >> DP_TRAIN_VOLTAGE_SWING_SHIFT) 397 #define TRAIN_REQ_VSWING_ARGS(link_status) \ 398 _TRAIN_REQ_VSWING_ARGS(link_status, 0), \ 399 _TRAIN_REQ_VSWING_ARGS(link_status, 1), \ 400 _TRAIN_REQ_VSWING_ARGS(link_status, 2), \ 401 _TRAIN_REQ_VSWING_ARGS(link_status, 3) 402 #define _TRAIN_REQ_PREEMPH_ARGS(link_status, lane) \ 403 (drm_dp_get_adjust_request_pre_emphasis((link_status), (lane)) >> DP_TRAIN_PRE_EMPHASIS_SHIFT) 404 #define TRAIN_REQ_PREEMPH_ARGS(link_status) \ 405 _TRAIN_REQ_PREEMPH_ARGS(link_status, 0), \ 406 _TRAIN_REQ_PREEMPH_ARGS(link_status, 1), \ 407 _TRAIN_REQ_PREEMPH_ARGS(link_status, 2), \ 408 _TRAIN_REQ_PREEMPH_ARGS(link_status, 3) 409 #define _TRAIN_REQ_TX_FFE_ARGS(link_status, lane) \ 410 drm_dp_get_adjust_tx_ffe_preset((link_status), (lane)) 411 #define TRAIN_REQ_TX_FFE_ARGS(link_status) \ 412 _TRAIN_REQ_TX_FFE_ARGS(link_status, 0), \ 413 _TRAIN_REQ_TX_FFE_ARGS(link_status, 1), \ 414 _TRAIN_REQ_TX_FFE_ARGS(link_status, 2), \ 415 _TRAIN_REQ_TX_FFE_ARGS(link_status, 3) 416 417 void 418 intel_dp_get_adjust_train(struct intel_dp *intel_dp, 419 const struct intel_crtc_state *crtc_state, 420 enum drm_dp_phy dp_phy, 421 const u8 link_status[DP_LINK_STATUS_SIZE]) 422 { 423 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 424 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 425 char phy_name[10]; 426 int lane; 427 428 if (intel_dp_is_uhbr(crtc_state)) { 429 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s][%s] 128b/132b, lanes: %d, " 430 "TX FFE request: " TRAIN_REQ_FMT "\n", 431 encoder->base.base.id, encoder->base.name, 432 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)), 433 crtc_state->lane_count, 434 TRAIN_REQ_TX_FFE_ARGS(link_status)); 435 } else { 436 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s][%s] 8b/10b, lanes: %d, " 437 "vswing request: " TRAIN_REQ_FMT ", " 438 "pre-emphasis request: " TRAIN_REQ_FMT "\n", 439 encoder->base.base.id, encoder->base.name, 440 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)), 441 crtc_state->lane_count, 442 TRAIN_REQ_VSWING_ARGS(link_status), 443 TRAIN_REQ_PREEMPH_ARGS(link_status)); 444 } 445 446 for (lane = 0; lane < 4; lane++) 447 intel_dp->train_set[lane] = 448 intel_dp_get_lane_adjust_train(intel_dp, crtc_state, 449 dp_phy, link_status, lane); 450 } 451 452 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp, 453 enum drm_dp_phy dp_phy) 454 { 455 return dp_phy == DP_PHY_DPRX ? 456 DP_TRAINING_PATTERN_SET : 457 DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy); 458 } 459 460 static bool 461 intel_dp_set_link_train(struct intel_dp *intel_dp, 462 const struct intel_crtc_state *crtc_state, 463 enum drm_dp_phy dp_phy, 464 u8 dp_train_pat) 465 { 466 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 467 u8 buf[sizeof(intel_dp->train_set) + 1]; 468 int len; 469 470 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 471 dp_phy, dp_train_pat); 472 473 buf[0] = dp_train_pat; 474 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 475 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); 476 len = crtc_state->lane_count + 1; 477 478 return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len; 479 } 480 481 static char dp_training_pattern_name(u8 train_pat) 482 { 483 switch (train_pat) { 484 case DP_TRAINING_PATTERN_1: 485 case DP_TRAINING_PATTERN_2: 486 case DP_TRAINING_PATTERN_3: 487 return '0' + train_pat; 488 case DP_TRAINING_PATTERN_4: 489 return '4'; 490 default: 491 MISSING_CASE(train_pat); 492 return '?'; 493 } 494 } 495 496 void 497 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 498 const struct intel_crtc_state *crtc_state, 499 enum drm_dp_phy dp_phy, 500 u8 dp_train_pat) 501 { 502 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 503 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 504 u8 train_pat = intel_dp_training_pattern_symbol(dp_train_pat); 505 char phy_name[10]; 506 507 if (train_pat != DP_TRAINING_PATTERN_DISABLE) 508 drm_dbg_kms(&i915->drm, 509 "[ENCODER:%d:%s][%s] Using DP training pattern TPS%c\n", 510 encoder->base.base.id, encoder->base.name, 511 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)), 512 dp_training_pattern_name(train_pat)); 513 514 intel_dp->set_link_train(intel_dp, crtc_state, dp_train_pat); 515 } 516 517 #define TRAIN_SET_FMT "%d%s/%d%s/%d%s/%d%s" 518 #define _TRAIN_SET_VSWING_ARGS(train_set) \ 519 ((train_set) & DP_TRAIN_VOLTAGE_SWING_MASK) >> DP_TRAIN_VOLTAGE_SWING_SHIFT, \ 520 (train_set) & DP_TRAIN_MAX_SWING_REACHED ? "(max)" : "" 521 #define TRAIN_SET_VSWING_ARGS(train_set) \ 522 _TRAIN_SET_VSWING_ARGS((train_set)[0]), \ 523 _TRAIN_SET_VSWING_ARGS((train_set)[1]), \ 524 _TRAIN_SET_VSWING_ARGS((train_set)[2]), \ 525 _TRAIN_SET_VSWING_ARGS((train_set)[3]) 526 #define _TRAIN_SET_PREEMPH_ARGS(train_set) \ 527 ((train_set) & DP_TRAIN_PRE_EMPHASIS_MASK) >> DP_TRAIN_PRE_EMPHASIS_SHIFT, \ 528 (train_set) & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? "(max)" : "" 529 #define TRAIN_SET_PREEMPH_ARGS(train_set) \ 530 _TRAIN_SET_PREEMPH_ARGS((train_set)[0]), \ 531 _TRAIN_SET_PREEMPH_ARGS((train_set)[1]), \ 532 _TRAIN_SET_PREEMPH_ARGS((train_set)[2]), \ 533 _TRAIN_SET_PREEMPH_ARGS((train_set)[3]) 534 #define _TRAIN_SET_TX_FFE_ARGS(train_set) \ 535 ((train_set) & DP_TX_FFE_PRESET_VALUE_MASK), "" 536 #define TRAIN_SET_TX_FFE_ARGS(train_set) \ 537 _TRAIN_SET_TX_FFE_ARGS((train_set)[0]), \ 538 _TRAIN_SET_TX_FFE_ARGS((train_set)[1]), \ 539 _TRAIN_SET_TX_FFE_ARGS((train_set)[2]), \ 540 _TRAIN_SET_TX_FFE_ARGS((train_set)[3]) 541 542 void intel_dp_set_signal_levels(struct intel_dp *intel_dp, 543 const struct intel_crtc_state *crtc_state, 544 enum drm_dp_phy dp_phy) 545 { 546 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 547 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 548 char phy_name[10]; 549 550 if (intel_dp_is_uhbr(crtc_state)) { 551 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s][%s] 128b/132b, lanes: %d, " 552 "TX FFE presets: " TRAIN_SET_FMT "\n", 553 encoder->base.base.id, encoder->base.name, 554 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)), 555 crtc_state->lane_count, 556 TRAIN_SET_TX_FFE_ARGS(intel_dp->train_set)); 557 } else { 558 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s][%s] 8b/10b, lanes: %d, " 559 "vswing levels: " TRAIN_SET_FMT ", " 560 "pre-emphasis levels: " TRAIN_SET_FMT "\n", 561 encoder->base.base.id, encoder->base.name, 562 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)), 563 crtc_state->lane_count, 564 TRAIN_SET_VSWING_ARGS(intel_dp->train_set), 565 TRAIN_SET_PREEMPH_ARGS(intel_dp->train_set)); 566 } 567 568 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 569 encoder->set_signal_levels(encoder, crtc_state); 570 } 571 572 static bool 573 intel_dp_reset_link_train(struct intel_dp *intel_dp, 574 const struct intel_crtc_state *crtc_state, 575 enum drm_dp_phy dp_phy, 576 u8 dp_train_pat) 577 { 578 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 579 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 580 return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat); 581 } 582 583 static bool 584 intel_dp_update_link_train(struct intel_dp *intel_dp, 585 const struct intel_crtc_state *crtc_state, 586 enum drm_dp_phy dp_phy) 587 { 588 int reg = dp_phy == DP_PHY_DPRX ? 589 DP_TRAINING_LANE0_SET : 590 DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy); 591 int ret; 592 593 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 594 595 ret = drm_dp_dpcd_write(&intel_dp->aux, reg, 596 intel_dp->train_set, crtc_state->lane_count); 597 598 return ret == crtc_state->lane_count; 599 } 600 601 /* 128b/132b */ 602 static bool intel_dp_lane_max_tx_ffe_reached(u8 train_set_lane) 603 { 604 return (train_set_lane & DP_TX_FFE_PRESET_VALUE_MASK) == 605 DP_TX_FFE_PRESET_VALUE_MASK; 606 } 607 608 /* 609 * 8b/10b 610 * 611 * FIXME: The DP spec is very confusing here, also the Link CTS spec seems to 612 * have self contradicting tests around this area. 613 * 614 * In lieu of better ideas let's just stop when we've reached the max supported 615 * vswing with its max pre-emphasis, which is either 2+1 or 3+0 depending on 616 * whether vswing level 3 is supported or not. 617 */ 618 static bool intel_dp_lane_max_vswing_reached(u8 train_set_lane) 619 { 620 u8 v = (train_set_lane & DP_TRAIN_VOLTAGE_SWING_MASK) >> 621 DP_TRAIN_VOLTAGE_SWING_SHIFT; 622 u8 p = (train_set_lane & DP_TRAIN_PRE_EMPHASIS_MASK) >> 623 DP_TRAIN_PRE_EMPHASIS_SHIFT; 624 625 if ((train_set_lane & DP_TRAIN_MAX_SWING_REACHED) == 0) 626 return false; 627 628 if (v + p != 3) 629 return false; 630 631 return true; 632 } 633 634 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp, 635 const struct intel_crtc_state *crtc_state) 636 { 637 int lane; 638 639 for (lane = 0; lane < crtc_state->lane_count; lane++) { 640 u8 train_set_lane = intel_dp->train_set[lane]; 641 642 if (intel_dp_is_uhbr(crtc_state)) { 643 if (!intel_dp_lane_max_tx_ffe_reached(train_set_lane)) 644 return false; 645 } else { 646 if (!intel_dp_lane_max_vswing_reached(train_set_lane)) 647 return false; 648 } 649 } 650 651 return true; 652 } 653 654 /* 655 * Prepare link training by configuring the link parameters. On DDI platforms 656 * also enable the port here. 657 */ 658 static bool 659 intel_dp_prepare_link_train(struct intel_dp *intel_dp, 660 const struct intel_crtc_state *crtc_state) 661 { 662 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 663 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 664 u8 link_config[2]; 665 u8 link_bw, rate_select; 666 667 if (intel_dp->prepare_link_retrain) 668 intel_dp->prepare_link_retrain(intel_dp, crtc_state); 669 670 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, 671 &link_bw, &rate_select); 672 673 if (link_bw) 674 drm_dbg_kms(&i915->drm, 675 "[ENCODER:%d:%s] Using LINK_BW_SET value %02x\n", 676 encoder->base.base.id, encoder->base.name, link_bw); 677 else 678 drm_dbg_kms(&i915->drm, 679 "[ENCODER:%d:%s] Using LINK_RATE_SET value %02x\n", 680 encoder->base.base.id, encoder->base.name, rate_select); 681 682 /* Write the link configuration data */ 683 link_config[0] = link_bw; 684 link_config[1] = crtc_state->lane_count; 685 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 686 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 687 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); 688 689 /* eDP 1.4 rate select method. */ 690 if (!link_bw) 691 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET, 692 &rate_select, 1); 693 694 link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; 695 link_config[1] = intel_dp_is_uhbr(crtc_state) ? 696 DP_SET_ANSI_128B132B : DP_SET_ANSI_8B10B; 697 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 698 699 return true; 700 } 701 702 static bool intel_dp_adjust_request_changed(const struct intel_crtc_state *crtc_state, 703 const u8 old_link_status[DP_LINK_STATUS_SIZE], 704 const u8 new_link_status[DP_LINK_STATUS_SIZE]) 705 { 706 int lane; 707 708 for (lane = 0; lane < crtc_state->lane_count; lane++) { 709 u8 old, new; 710 711 if (intel_dp_is_uhbr(crtc_state)) { 712 old = drm_dp_get_adjust_tx_ffe_preset(old_link_status, lane); 713 new = drm_dp_get_adjust_tx_ffe_preset(new_link_status, lane); 714 } else { 715 old = drm_dp_get_adjust_request_voltage(old_link_status, lane) | 716 drm_dp_get_adjust_request_pre_emphasis(old_link_status, lane); 717 new = drm_dp_get_adjust_request_voltage(new_link_status, lane) | 718 drm_dp_get_adjust_request_pre_emphasis(new_link_status, lane); 719 } 720 721 if (old != new) 722 return true; 723 } 724 725 return false; 726 } 727 728 void 729 intel_dp_dump_link_status(struct intel_dp *intel_dp, enum drm_dp_phy dp_phy, 730 const u8 link_status[DP_LINK_STATUS_SIZE]) 731 { 732 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 733 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 734 char phy_name[10]; 735 736 drm_dbg_kms(&i915->drm, 737 "[ENCODER:%d:%s][%s] ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x\n", 738 encoder->base.base.id, encoder->base.name, 739 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)), 740 link_status[0], link_status[1], link_status[2], 741 link_status[3], link_status[4], link_status[5]); 742 } 743 744 /* 745 * Perform the link training clock recovery phase on the given DP PHY using 746 * training pattern 1. 747 */ 748 static bool 749 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, 750 const struct intel_crtc_state *crtc_state, 751 enum drm_dp_phy dp_phy) 752 { 753 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 754 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 755 u8 old_link_status[DP_LINK_STATUS_SIZE] = {}; 756 int voltage_tries, cr_tries, max_cr_tries; 757 u8 link_status[DP_LINK_STATUS_SIZE]; 758 bool max_vswing_reached = false; 759 char phy_name[10]; 760 int delay_us; 761 762 delay_us = drm_dp_read_clock_recovery_delay(&intel_dp->aux, 763 intel_dp->dpcd, dp_phy, 764 intel_dp_is_uhbr(crtc_state)); 765 766 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)); 767 768 /* clock recovery */ 769 if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy, 770 DP_TRAINING_PATTERN_1 | 771 DP_LINK_SCRAMBLING_DISABLE)) { 772 drm_err(&i915->drm, "[ENCODER:%d:%s][%s] Failed to enable link training\n", 773 encoder->base.base.id, encoder->base.name, phy_name); 774 return false; 775 } 776 777 /* 778 * The DP 1.4 spec defines the max clock recovery retries value 779 * as 10 but for pre-DP 1.4 devices we set a very tolerant 780 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x 781 * x 5 identical voltage retries). Since the previous specs didn't 782 * define a limit and created the possibility of an infinite loop 783 * we want to prevent any sync from triggering that corner case. 784 */ 785 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 786 max_cr_tries = 10; 787 else 788 max_cr_tries = 80; 789 790 voltage_tries = 1; 791 for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) { 792 usleep_range(delay_us, 2 * delay_us); 793 794 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 795 link_status) < 0) { 796 drm_err(&i915->drm, "[ENCODER:%d:%s][%s] Failed to get link status\n", 797 encoder->base.base.id, encoder->base.name, phy_name); 798 return false; 799 } 800 801 if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) { 802 drm_dbg_kms(&i915->drm, 803 "[ENCODER:%d:%s][%s] Clock recovery OK\n", 804 encoder->base.base.id, encoder->base.name, phy_name); 805 return true; 806 } 807 808 if (voltage_tries == 5) { 809 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 810 drm_dbg_kms(&i915->drm, 811 "[ENCODER:%d:%s][%s] Same voltage tried 5 times\n", 812 encoder->base.base.id, encoder->base.name, phy_name); 813 return false; 814 } 815 816 if (max_vswing_reached) { 817 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 818 drm_dbg_kms(&i915->drm, 819 "[ENCODER:%d:%s][%s] Max Voltage Swing reached\n", 820 encoder->base.base.id, encoder->base.name, phy_name); 821 return false; 822 } 823 824 /* Update training set as requested by target */ 825 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 826 link_status); 827 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 828 drm_err(&i915->drm, 829 "[ENCODER:%d:%s][%s] Failed to update link training\n", 830 encoder->base.base.id, encoder->base.name, phy_name); 831 return false; 832 } 833 834 if (!intel_dp_adjust_request_changed(crtc_state, old_link_status, link_status)) 835 ++voltage_tries; 836 else 837 voltage_tries = 1; 838 839 memcpy(old_link_status, link_status, sizeof(link_status)); 840 841 if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state)) 842 max_vswing_reached = true; 843 } 844 845 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 846 drm_err(&i915->drm, 847 "[ENCODER:%d:%s][%s] Failed clock recovery %d times, giving up!\n", 848 encoder->base.base.id, encoder->base.name, phy_name, max_cr_tries); 849 850 return false; 851 } 852 853 /* 854 * Pick Training Pattern Sequence (TPS) for channel equalization. 128b/132b TPS2 855 * for UHBR+, TPS4 for HBR3 or for 1.4 devices that support it, TPS3 for HBR2 or 856 * 1.2 devices that support it, TPS2 otherwise. 857 */ 858 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, 859 const struct intel_crtc_state *crtc_state, 860 enum drm_dp_phy dp_phy) 861 { 862 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 863 bool source_tps3, sink_tps3, source_tps4, sink_tps4; 864 865 /* UHBR+ use separate 128b/132b TPS2 */ 866 if (intel_dp_is_uhbr(crtc_state)) 867 return DP_TRAINING_PATTERN_2; 868 869 /* 870 * TPS4 support is mandatory for all downstream devices that 871 * support HBR3. There are no known eDP panels that support 872 * TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 specification. 873 * LTTPRs must support TPS4. 874 */ 875 source_tps4 = intel_dp_source_supports_tps4(i915); 876 sink_tps4 = dp_phy != DP_PHY_DPRX || 877 drm_dp_tps4_supported(intel_dp->dpcd); 878 if (source_tps4 && sink_tps4) { 879 return DP_TRAINING_PATTERN_4; 880 } else if (crtc_state->port_clock == 810000) { 881 if (!source_tps4) 882 drm_dbg_kms(&i915->drm, 883 "8.1 Gbps link rate without source TPS4 support\n"); 884 if (!sink_tps4) 885 drm_dbg_kms(&i915->drm, 886 "8.1 Gbps link rate without sink TPS4 support\n"); 887 } 888 889 /* 890 * TPS3 support is mandatory for downstream devices that 891 * support HBR2. However, not all sinks follow the spec. 892 */ 893 source_tps3 = intel_dp_source_supports_tps3(i915); 894 sink_tps3 = dp_phy != DP_PHY_DPRX || 895 drm_dp_tps3_supported(intel_dp->dpcd); 896 if (source_tps3 && sink_tps3) { 897 return DP_TRAINING_PATTERN_3; 898 } else if (crtc_state->port_clock >= 540000) { 899 if (!source_tps3) 900 drm_dbg_kms(&i915->drm, 901 ">=5.4/6.48 Gbps link rate without source TPS3 support\n"); 902 if (!sink_tps3) 903 drm_dbg_kms(&i915->drm, 904 ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); 905 } 906 907 return DP_TRAINING_PATTERN_2; 908 } 909 910 /* 911 * Perform the link training channel equalization phase on the given DP PHY 912 * using one of training pattern 2, 3 or 4 depending on the source and 913 * sink capabilities. 914 */ 915 static bool 916 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp, 917 const struct intel_crtc_state *crtc_state, 918 enum drm_dp_phy dp_phy) 919 { 920 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 921 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 922 int tries; 923 u32 training_pattern; 924 u8 link_status[DP_LINK_STATUS_SIZE]; 925 bool channel_eq = false; 926 char phy_name[10]; 927 int delay_us; 928 929 delay_us = drm_dp_read_channel_eq_delay(&intel_dp->aux, 930 intel_dp->dpcd, dp_phy, 931 intel_dp_is_uhbr(crtc_state)); 932 933 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)); 934 935 training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy); 936 /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ 937 if (training_pattern != DP_TRAINING_PATTERN_4) 938 training_pattern |= DP_LINK_SCRAMBLING_DISABLE; 939 940 /* channel equalization */ 941 if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, 942 training_pattern)) { 943 drm_err(&i915->drm, 944 "[ENCODER:%d:%s][%s] Failed to start channel equalization\n", 945 encoder->base.base.id, encoder->base.name, 946 phy_name); 947 return false; 948 } 949 950 for (tries = 0; tries < 5; tries++) { 951 usleep_range(delay_us, 2 * delay_us); 952 953 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 954 link_status) < 0) { 955 drm_err(&i915->drm, 956 "[ENCODER:%d:%s][%s] Failed to get link status\n", 957 encoder->base.base.id, encoder->base.name, phy_name); 958 break; 959 } 960 961 /* Make sure clock is still ok */ 962 if (!drm_dp_clock_recovery_ok(link_status, 963 crtc_state->lane_count)) { 964 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 965 drm_dbg_kms(&i915->drm, 966 "[ENCODER:%d:%s][%s] Clock recovery check failed, cannot " 967 "continue channel equalization\n", 968 encoder->base.base.id, encoder->base.name, phy_name); 969 break; 970 } 971 972 if (drm_dp_channel_eq_ok(link_status, 973 crtc_state->lane_count)) { 974 channel_eq = true; 975 drm_dbg_kms(&i915->drm, 976 "[ENCODER:%d:%s][%s] Channel EQ done. DP Training successful\n", 977 encoder->base.base.id, encoder->base.name, phy_name); 978 break; 979 } 980 981 /* Update training set as requested by target */ 982 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 983 link_status); 984 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 985 drm_err(&i915->drm, 986 "[ENCODER:%d:%s][%s] Failed to update link training\n", 987 encoder->base.base.id, encoder->base.name, phy_name); 988 break; 989 } 990 } 991 992 /* Try 5 times, else fail and try at lower BW */ 993 if (tries == 5) { 994 intel_dp_dump_link_status(intel_dp, dp_phy, link_status); 995 drm_dbg_kms(&i915->drm, 996 "[ENCODER:%d:%s][%s] Channel equalization failed 5 times\n", 997 encoder->base.base.id, encoder->base.name, phy_name); 998 } 999 1000 return channel_eq; 1001 } 1002 1003 static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp, 1004 enum drm_dp_phy dp_phy) 1005 { 1006 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 1007 u8 val = DP_TRAINING_PATTERN_DISABLE; 1008 1009 return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1; 1010 } 1011 1012 static int 1013 intel_dp_128b132b_intra_hop(struct intel_dp *intel_dp, 1014 const struct intel_crtc_state *crtc_state) 1015 { 1016 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1017 u8 sink_status; 1018 int ret; 1019 1020 ret = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_STATUS, &sink_status); 1021 if (ret != 1) { 1022 drm_dbg_kms(&i915->drm, "Failed to read sink status\n"); 1023 return ret < 0 ? ret : -EIO; 1024 } 1025 1026 return sink_status & DP_INTRA_HOP_AUX_REPLY_INDICATION ? 1 : 0; 1027 } 1028 1029 /** 1030 * intel_dp_stop_link_train - stop link training 1031 * @intel_dp: DP struct 1032 * @crtc_state: state for CRTC attached to the encoder 1033 * 1034 * Stop the link training of the @intel_dp port, disabling the training 1035 * pattern in the sink's DPCD, and disabling the test pattern symbol 1036 * generation on the port. 1037 * 1038 * What symbols are output on the port after this point is 1039 * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern 1040 * with the pipe being disabled, on older platforms it's HW specific if/how an 1041 * idle pattern is generated, as the pipe is already enabled here for those. 1042 * 1043 * This function must be called after intel_dp_start_link_train(). 1044 */ 1045 void intel_dp_stop_link_train(struct intel_dp *intel_dp, 1046 const struct intel_crtc_state *crtc_state) 1047 { 1048 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1049 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1050 1051 intel_dp->link_trained = true; 1052 1053 intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX); 1054 intel_dp_program_link_training_pattern(intel_dp, crtc_state, DP_PHY_DPRX, 1055 DP_TRAINING_PATTERN_DISABLE); 1056 1057 if (intel_dp_is_uhbr(crtc_state) && 1058 wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) { 1059 drm_dbg_kms(&i915->drm, 1060 "[ENCODER:%d:%s] 128b/132b intra-hop not clearing\n", 1061 encoder->base.base.id, encoder->base.name); 1062 } 1063 } 1064 1065 static bool 1066 intel_dp_link_train_phy(struct intel_dp *intel_dp, 1067 const struct intel_crtc_state *crtc_state, 1068 enum drm_dp_phy dp_phy) 1069 { 1070 struct intel_connector *connector = intel_dp->attached_connector; 1071 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1072 char phy_name[10]; 1073 bool ret = false; 1074 1075 if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy)) 1076 goto out; 1077 1078 if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy)) 1079 goto out; 1080 1081 ret = true; 1082 1083 out: 1084 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 1085 "[CONNECTOR:%d:%s][ENCODER:%d:%s][%s] Link Training %s at link rate = %d, lane count = %d\n", 1086 connector->base.base.id, connector->base.name, 1087 encoder->base.base.id, encoder->base.name, 1088 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)), 1089 ret ? "passed" : "failed", 1090 crtc_state->port_clock, crtc_state->lane_count); 1091 1092 return ret; 1093 } 1094 1095 static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, 1096 const struct intel_crtc_state *crtc_state) 1097 { 1098 struct intel_connector *intel_connector = intel_dp->attached_connector; 1099 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1100 1101 if (intel_dp->hobl_active) { 1102 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 1103 "[ENCODER:%d:%s] Link Training failed with HOBL active, " 1104 "not enabling it from now on", 1105 encoder->base.base.id, encoder->base.name); 1106 intel_dp->hobl_failed = true; 1107 } else if (intel_dp_get_link_train_fallback_values(intel_dp, 1108 crtc_state->port_clock, 1109 crtc_state->lane_count)) { 1110 return; 1111 } 1112 1113 /* Schedule a Hotplug Uevent to userspace to start modeset */ 1114 schedule_work(&intel_connector->modeset_retry_work); 1115 } 1116 1117 /* Perform the link training on all LTTPRs and the DPRX on a link. */ 1118 static bool 1119 intel_dp_link_train_all_phys(struct intel_dp *intel_dp, 1120 const struct intel_crtc_state *crtc_state, 1121 int lttpr_count) 1122 { 1123 bool ret = true; 1124 int i; 1125 1126 for (i = lttpr_count - 1; i >= 0; i--) { 1127 enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i); 1128 1129 ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy); 1130 intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy); 1131 1132 if (!ret) 1133 break; 1134 } 1135 1136 if (ret) 1137 ret = intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX); 1138 1139 if (intel_dp->set_idle_link_train) 1140 intel_dp->set_idle_link_train(intel_dp, crtc_state); 1141 1142 return ret; 1143 } 1144 1145 /* 1146 * 128b/132b DP LANEx_EQ_DONE Sequence (DP 2.0 E11 3.5.2.16.1) 1147 */ 1148 static bool 1149 intel_dp_128b132b_lane_eq(struct intel_dp *intel_dp, 1150 const struct intel_crtc_state *crtc_state) 1151 { 1152 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1153 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1154 u8 link_status[DP_LINK_STATUS_SIZE]; 1155 int delay_us; 1156 int try, max_tries = 20; 1157 unsigned long deadline; 1158 bool timeout = false; 1159 1160 /* 1161 * Reset signal levels. Start transmitting 128b/132b TPS1. 1162 * 1163 * Put DPRX and LTTPRs (if any) into intra-hop AUX mode by writing TPS1 1164 * in DP_TRAINING_PATTERN_SET. 1165 */ 1166 if (!intel_dp_reset_link_train(intel_dp, crtc_state, DP_PHY_DPRX, 1167 DP_TRAINING_PATTERN_1)) { 1168 drm_err(&i915->drm, 1169 "[ENCODER:%d:%s] Failed to start 128b/132b TPS1\n", 1170 encoder->base.base.id, encoder->base.name); 1171 return false; 1172 } 1173 1174 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1175 1176 /* Read the initial TX FFE settings. */ 1177 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1178 drm_err(&i915->drm, 1179 "[ENCODER:%d:%s] Failed to read TX FFE presets\n", 1180 encoder->base.base.id, encoder->base.name); 1181 return false; 1182 } 1183 1184 /* Update signal levels and training set as requested. */ 1185 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1186 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1187 drm_err(&i915->drm, 1188 "[ENCODER:%d:%s] Failed to set initial TX FFE settings\n", 1189 encoder->base.base.id, encoder->base.name); 1190 return false; 1191 } 1192 1193 /* Start transmitting 128b/132b TPS2. */ 1194 if (!intel_dp_set_link_train(intel_dp, crtc_state, DP_PHY_DPRX, 1195 DP_TRAINING_PATTERN_2)) { 1196 drm_err(&i915->drm, 1197 "[ENCODER:%d:%s] Failed to start 128b/132b TPS2\n", 1198 encoder->base.base.id, encoder->base.name); 1199 return false; 1200 } 1201 1202 /* Time budget for the LANEx_EQ_DONE Sequence */ 1203 deadline = jiffies + msecs_to_jiffies_timeout(400); 1204 1205 for (try = 0; try < max_tries; try++) { 1206 usleep_range(delay_us, 2 * delay_us); 1207 1208 /* 1209 * The delay may get updated. The transmitter shall read the 1210 * delay before link status during link training. 1211 */ 1212 delay_us = drm_dp_128b132b_read_aux_rd_interval(&intel_dp->aux); 1213 1214 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1215 drm_err(&i915->drm, 1216 "[ENCODER:%d:%s] Failed to read link status\n", 1217 encoder->base.base.id, encoder->base.name); 1218 return false; 1219 } 1220 1221 if (drm_dp_128b132b_link_training_failed(link_status)) { 1222 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1223 drm_err(&i915->drm, 1224 "[ENCODER:%d:%s] Downstream link training failure\n", 1225 encoder->base.base.id, encoder->base.name); 1226 return false; 1227 } 1228 1229 if (drm_dp_128b132b_lane_channel_eq_done(link_status, crtc_state->lane_count)) { 1230 drm_dbg_kms(&i915->drm, 1231 "[ENCODER:%d:%s] Lane channel eq done\n", 1232 encoder->base.base.id, encoder->base.name); 1233 break; 1234 } 1235 1236 if (timeout) { 1237 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1238 drm_err(&i915->drm, 1239 "[ENCODER:%d:%s] Lane channel eq timeout\n", 1240 encoder->base.base.id, encoder->base.name); 1241 return false; 1242 } 1243 1244 if (time_after(jiffies, deadline)) 1245 timeout = true; /* try one last time after deadline */ 1246 1247 /* Update signal levels and training set as requested. */ 1248 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, link_status); 1249 if (!intel_dp_update_link_train(intel_dp, crtc_state, DP_PHY_DPRX)) { 1250 drm_err(&i915->drm, 1251 "[ENCODER:%d:%s] Failed to update TX FFE settings\n", 1252 encoder->base.base.id, encoder->base.name); 1253 return false; 1254 } 1255 } 1256 1257 if (try == max_tries) { 1258 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1259 drm_err(&i915->drm, 1260 "[ENCODER:%d:%s] Max loop count reached\n", 1261 encoder->base.base.id, encoder->base.name); 1262 return false; 1263 } 1264 1265 for (;;) { 1266 if (time_after(jiffies, deadline)) 1267 timeout = true; /* try one last time after deadline */ 1268 1269 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1270 drm_err(&i915->drm, 1271 "[ENCODER:%d:%s] Failed to read link status\n", 1272 encoder->base.base.id, encoder->base.name); 1273 return false; 1274 } 1275 1276 if (drm_dp_128b132b_link_training_failed(link_status)) { 1277 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1278 drm_err(&i915->drm, 1279 "[ENCODER:%d:%s] Downstream link training failure\n", 1280 encoder->base.base.id, encoder->base.name); 1281 return false; 1282 } 1283 1284 if (drm_dp_128b132b_eq_interlane_align_done(link_status)) { 1285 drm_dbg_kms(&i915->drm, 1286 "[ENCODER:%d:%s] Interlane align done\n", 1287 encoder->base.base.id, encoder->base.name); 1288 break; 1289 } 1290 1291 if (timeout) { 1292 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1293 drm_err(&i915->drm, 1294 "[ENCODER:%d:%s] Interlane align timeout\n", 1295 encoder->base.base.id, encoder->base.name); 1296 return false; 1297 } 1298 1299 usleep_range(2000, 3000); 1300 } 1301 1302 return true; 1303 } 1304 1305 /* 1306 * 128b/132b DP LANEx_CDS_DONE Sequence (DP 2.0 E11 3.5.2.16.2) 1307 */ 1308 static bool 1309 intel_dp_128b132b_lane_cds(struct intel_dp *intel_dp, 1310 const struct intel_crtc_state *crtc_state, 1311 int lttpr_count) 1312 { 1313 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1314 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1315 u8 link_status[DP_LINK_STATUS_SIZE]; 1316 unsigned long deadline; 1317 1318 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TRAINING_PATTERN_SET, 1319 DP_TRAINING_PATTERN_2_CDS) != 1) { 1320 drm_err(&i915->drm, 1321 "[ENCODER:%d:%s] Failed to start 128b/132b TPS2 CDS\n", 1322 encoder->base.base.id, encoder->base.name); 1323 return false; 1324 } 1325 1326 /* Time budget for the LANEx_CDS_DONE Sequence */ 1327 deadline = jiffies + msecs_to_jiffies_timeout((lttpr_count + 1) * 20); 1328 1329 for (;;) { 1330 bool timeout = false; 1331 1332 if (time_after(jiffies, deadline)) 1333 timeout = true; /* try one last time after deadline */ 1334 1335 usleep_range(2000, 3000); 1336 1337 if (drm_dp_dpcd_read_link_status(&intel_dp->aux, link_status) < 0) { 1338 drm_err(&i915->drm, 1339 "[ENCODER:%d:%s] Failed to read link status\n", 1340 encoder->base.base.id, encoder->base.name); 1341 return false; 1342 } 1343 1344 if (drm_dp_128b132b_eq_interlane_align_done(link_status) && 1345 drm_dp_128b132b_cds_interlane_align_done(link_status) && 1346 drm_dp_128b132b_lane_symbol_locked(link_status, crtc_state->lane_count)) { 1347 drm_dbg_kms(&i915->drm, 1348 "[ENCODER:%d:%s] CDS interlane align done\n", 1349 encoder->base.base.id, encoder->base.name); 1350 break; 1351 } 1352 1353 if (drm_dp_128b132b_link_training_failed(link_status)) { 1354 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1355 drm_err(&i915->drm, 1356 "[ENCODER:%d:%s] Downstream link training failure\n", 1357 encoder->base.base.id, encoder->base.name); 1358 return false; 1359 } 1360 1361 if (timeout) { 1362 intel_dp_dump_link_status(intel_dp, DP_PHY_DPRX, link_status); 1363 drm_err(&i915->drm, 1364 "[ENCODER:%d:%s] CDS timeout\n", 1365 encoder->base.base.id, encoder->base.name); 1366 return false; 1367 } 1368 } 1369 1370 /* FIXME: Should DP_TRAINING_PATTERN_DISABLE be written first? */ 1371 if (intel_dp->set_idle_link_train) 1372 intel_dp->set_idle_link_train(intel_dp, crtc_state); 1373 1374 return true; 1375 } 1376 1377 /* 1378 * 128b/132b link training sequence. (DP 2.0 E11 SCR on link training.) 1379 */ 1380 static bool 1381 intel_dp_128b132b_link_train(struct intel_dp *intel_dp, 1382 const struct intel_crtc_state *crtc_state, 1383 int lttpr_count) 1384 { 1385 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1386 struct intel_connector *connector = intel_dp->attached_connector; 1387 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1388 bool passed = false; 1389 1390 if (wait_for(intel_dp_128b132b_intra_hop(intel_dp, crtc_state) == 0, 500)) { 1391 drm_err(&i915->drm, 1392 "[ENCODER:%d:%s] 128b/132b intra-hop not clear\n", 1393 encoder->base.base.id, encoder->base.name); 1394 return false; 1395 } 1396 1397 if (intel_dp_128b132b_lane_eq(intel_dp, crtc_state) && 1398 intel_dp_128b132b_lane_cds(intel_dp, crtc_state, lttpr_count)) 1399 passed = true; 1400 1401 drm_dbg_kms(&i915->drm, 1402 "[CONNECTOR:%d:%s][ENCODER:%d:%s] 128b/132b Link Training %s at link rate = %d, lane count = %d\n", 1403 connector->base.base.id, connector->base.name, 1404 encoder->base.base.id, encoder->base.name, 1405 passed ? "passed" : "failed", 1406 crtc_state->port_clock, crtc_state->lane_count); 1407 1408 return passed; 1409 } 1410 1411 /** 1412 * intel_dp_start_link_train - start link training 1413 * @intel_dp: DP struct 1414 * @crtc_state: state for CRTC attached to the encoder 1415 * 1416 * Start the link training of the @intel_dp port, scheduling a fallback 1417 * retraining with reduced link rate/lane parameters if the link training 1418 * fails. 1419 * After calling this function intel_dp_stop_link_train() must be called. 1420 */ 1421 void intel_dp_start_link_train(struct intel_dp *intel_dp, 1422 const struct intel_crtc_state *crtc_state) 1423 { 1424 bool passed; 1425 /* 1426 * TODO: Reiniting LTTPRs here won't be needed once proper connector 1427 * HW state readout is added. 1428 */ 1429 int lttpr_count = intel_dp_init_lttpr_and_dprx_caps(intel_dp); 1430 1431 if (lttpr_count < 0) 1432 /* Still continue with enabling the port and link training. */ 1433 lttpr_count = 0; 1434 1435 intel_dp_prepare_link_train(intel_dp, crtc_state); 1436 1437 if (intel_dp_is_uhbr(crtc_state)) 1438 passed = intel_dp_128b132b_link_train(intel_dp, crtc_state, lttpr_count); 1439 else 1440 passed = intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count); 1441 1442 if (!passed) 1443 intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); 1444 } 1445