1 /* 2 * Copyright © 2008-2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include "intel_display_types.h" 25 #include "intel_dp.h" 26 #include "intel_dp_link_training.h" 27 28 static void 29 intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE]) 30 { 31 32 DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x", 33 link_status[0], link_status[1], link_status[2], 34 link_status[3], link_status[4], link_status[5]); 35 } 36 37 static int intel_dp_lttpr_count(struct intel_dp *intel_dp) 38 { 39 int count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 40 41 /* 42 * Pretend no LTTPRs in case of LTTPR detection error, or 43 * if too many (>8) LTTPRs are detected. This translates to link 44 * training in transparent mode. 45 */ 46 return count <= 0 ? 0 : count; 47 } 48 49 static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp) 50 { 51 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - 52 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0; 53 } 54 55 static const char *intel_dp_phy_name(enum drm_dp_phy dp_phy, 56 char *buf, size_t buf_size) 57 { 58 if (dp_phy == DP_PHY_DPRX) 59 snprintf(buf, buf_size, "DPRX"); 60 else 61 snprintf(buf, buf_size, "LTTPR %d", dp_phy - DP_PHY_LTTPR1 + 1); 62 63 return buf; 64 } 65 66 static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp, 67 enum drm_dp_phy dp_phy) 68 { 69 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; 70 } 71 72 static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, 73 enum drm_dp_phy dp_phy) 74 { 75 u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 76 char phy_name[10]; 77 78 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)); 79 80 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) { 81 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 82 "failed to read the PHY caps for %s\n", 83 phy_name); 84 return; 85 } 86 87 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 88 "%s PHY capabilities: %*ph\n", 89 phy_name, 90 (int)sizeof(intel_dp->lttpr_phy_caps[0]), 91 phy_caps); 92 } 93 94 static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp) 95 { 96 if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, 97 intel_dp->lttpr_common_caps) < 0) { 98 memset(intel_dp->lttpr_common_caps, 0, 99 sizeof(intel_dp->lttpr_common_caps)); 100 return false; 101 } 102 103 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 104 "LTTPR common capabilities: %*ph\n", 105 (int)sizeof(intel_dp->lttpr_common_caps), 106 intel_dp->lttpr_common_caps); 107 108 return true; 109 } 110 111 static bool 112 intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) 113 { 114 u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : 115 DP_PHY_REPEATER_MODE_NON_TRANSPARENT; 116 117 return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1; 118 } 119 120 /** 121 * intel_dp_lttpr_init - detect LTTPRs and init the LTTPR link training mode 122 * @intel_dp: Intel DP struct 123 * 124 * Read the LTTPR common capabilities, switch to non-transparent link training 125 * mode if any is detected and read the PHY capabilities for all detected 126 * LTTPRs. In case of an LTTPR detection error or if the number of 127 * LTTPRs is more than is supported (8), fall back to the no-LTTPR, 128 * transparent mode link training mode. 129 * 130 * Returns: 131 * >0 if LTTPRs were detected and the non-transparent LT mode was set 132 * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a 133 * detection failure and the transparent LT mode was set 134 */ 135 int intel_dp_lttpr_init(struct intel_dp *intel_dp) 136 { 137 int lttpr_count; 138 bool ret; 139 int i; 140 141 if (intel_dp_is_edp(intel_dp)) 142 return 0; 143 144 ret = intel_dp_read_lttpr_common_caps(intel_dp); 145 146 /* 147 * See DP Standard v2.0 3.6.6.1. about the explicit disabling of 148 * non-transparent mode and the disable->enable non-transparent mode 149 * sequence. 150 */ 151 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 152 153 if (!ret) 154 return 0; 155 156 lttpr_count = intel_dp_lttpr_count(intel_dp); 157 158 /* 159 * In case of unsupported number of LTTPRs or failing to switch to 160 * non-transparent mode fall-back to transparent link training mode, 161 * still taking into account any LTTPR common lane- rate/count limits. 162 */ 163 if (lttpr_count == 0) 164 return 0; 165 166 if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) { 167 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 168 "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n"); 169 170 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 171 intel_dp_reset_lttpr_count(intel_dp); 172 173 return 0; 174 } 175 176 for (i = 0; i < lttpr_count; i++) 177 intel_dp_read_lttpr_phy_caps(intel_dp, DP_PHY_LTTPR(i)); 178 179 return lttpr_count; 180 } 181 EXPORT_SYMBOL(intel_dp_lttpr_init); 182 183 static u8 dp_voltage_max(u8 preemph) 184 { 185 switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) { 186 case DP_TRAIN_PRE_EMPH_LEVEL_0: 187 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 188 case DP_TRAIN_PRE_EMPH_LEVEL_1: 189 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 190 case DP_TRAIN_PRE_EMPH_LEVEL_2: 191 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1; 192 case DP_TRAIN_PRE_EMPH_LEVEL_3: 193 default: 194 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 195 } 196 } 197 198 static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp, 199 enum drm_dp_phy dp_phy) 200 { 201 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 202 203 if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps)) 204 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 205 else 206 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 207 } 208 209 static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp, 210 enum drm_dp_phy dp_phy) 211 { 212 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 213 214 if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps)) 215 return DP_TRAIN_PRE_EMPH_LEVEL_3; 216 else 217 return DP_TRAIN_PRE_EMPH_LEVEL_2; 218 } 219 220 static bool 221 intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp, 222 enum drm_dp_phy dp_phy) 223 { 224 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 225 int lttpr_count = intel_dp_lttpr_count(intel_dp); 226 227 drm_WARN_ON_ONCE(&i915->drm, lttpr_count == 0 && dp_phy != DP_PHY_DPRX); 228 229 return lttpr_count == 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1); 230 } 231 232 static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp, 233 const struct intel_crtc_state *crtc_state, 234 enum drm_dp_phy dp_phy) 235 { 236 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 237 u8 voltage_max; 238 239 /* 240 * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from 241 * the DPRX_PHY we train. 242 */ 243 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 244 voltage_max = intel_dp->voltage_max(intel_dp, crtc_state); 245 else 246 voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1); 247 248 drm_WARN_ON_ONCE(&i915->drm, 249 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 && 250 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3); 251 252 return voltage_max; 253 } 254 255 static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, 256 enum drm_dp_phy dp_phy) 257 { 258 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 259 u8 preemph_max; 260 261 /* 262 * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from 263 * the DPRX_PHY we train. 264 */ 265 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 266 preemph_max = intel_dp->preemph_max(intel_dp); 267 else 268 preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1); 269 270 drm_WARN_ON_ONCE(&i915->drm, 271 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 && 272 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3); 273 274 return preemph_max; 275 } 276 277 void 278 intel_dp_get_adjust_train(struct intel_dp *intel_dp, 279 const struct intel_crtc_state *crtc_state, 280 enum drm_dp_phy dp_phy, 281 const u8 link_status[DP_LINK_STATUS_SIZE]) 282 { 283 u8 v = 0; 284 u8 p = 0; 285 int lane; 286 u8 voltage_max; 287 u8 preemph_max; 288 289 for (lane = 0; lane < crtc_state->lane_count; lane++) { 290 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); 291 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); 292 } 293 294 preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy); 295 if (p >= preemph_max) 296 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 297 298 v = min(v, dp_voltage_max(p)); 299 300 voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy); 301 if (v >= voltage_max) 302 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 303 304 for (lane = 0; lane < 4; lane++) 305 intel_dp->train_set[lane] = v | p; 306 } 307 308 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp, 309 enum drm_dp_phy dp_phy) 310 { 311 return dp_phy == DP_PHY_DPRX ? 312 DP_TRAINING_PATTERN_SET : 313 DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy); 314 } 315 316 static bool 317 intel_dp_set_link_train(struct intel_dp *intel_dp, 318 const struct intel_crtc_state *crtc_state, 319 enum drm_dp_phy dp_phy, 320 u8 dp_train_pat) 321 { 322 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 323 u8 buf[sizeof(intel_dp->train_set) + 1]; 324 int len; 325 326 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 327 dp_train_pat); 328 329 buf[0] = dp_train_pat; 330 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 331 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); 332 len = crtc_state->lane_count + 1; 333 334 return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len; 335 } 336 337 void intel_dp_set_signal_levels(struct intel_dp *intel_dp, 338 const struct intel_crtc_state *crtc_state, 339 enum drm_dp_phy dp_phy) 340 { 341 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 342 u8 train_set = intel_dp->train_set[0]; 343 char phy_name[10]; 344 345 drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n", 346 train_set & DP_TRAIN_VOLTAGE_SWING_MASK, 347 train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "", 348 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> 349 DP_TRAIN_PRE_EMPHASIS_SHIFT, 350 train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? 351 " (max)" : "", 352 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name))); 353 354 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 355 intel_dp->set_signal_levels(intel_dp, crtc_state); 356 } 357 358 static bool 359 intel_dp_reset_link_train(struct intel_dp *intel_dp, 360 const struct intel_crtc_state *crtc_state, 361 enum drm_dp_phy dp_phy, 362 u8 dp_train_pat) 363 { 364 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 365 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 366 return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat); 367 } 368 369 static bool 370 intel_dp_update_link_train(struct intel_dp *intel_dp, 371 const struct intel_crtc_state *crtc_state, 372 enum drm_dp_phy dp_phy) 373 { 374 int reg = dp_phy == DP_PHY_DPRX ? 375 DP_TRAINING_LANE0_SET : 376 DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy); 377 int ret; 378 379 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 380 381 ret = drm_dp_dpcd_write(&intel_dp->aux, reg, 382 intel_dp->train_set, crtc_state->lane_count); 383 384 return ret == crtc_state->lane_count; 385 } 386 387 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp, 388 const struct intel_crtc_state *crtc_state) 389 { 390 int lane; 391 392 for (lane = 0; lane < crtc_state->lane_count; lane++) 393 if ((intel_dp->train_set[lane] & 394 DP_TRAIN_MAX_SWING_REACHED) == 0) 395 return false; 396 397 return true; 398 } 399 400 /* 401 * Prepare link training by configuring the link parameters. On DDI platforms 402 * also enable the port here. 403 */ 404 static bool 405 intel_dp_prepare_link_train(struct intel_dp *intel_dp, 406 const struct intel_crtc_state *crtc_state) 407 { 408 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 409 u8 link_config[2]; 410 u8 link_bw, rate_select; 411 412 if (intel_dp->prepare_link_retrain) 413 intel_dp->prepare_link_retrain(intel_dp, crtc_state); 414 415 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, 416 &link_bw, &rate_select); 417 418 if (link_bw) 419 drm_dbg_kms(&i915->drm, 420 "Using LINK_BW_SET value %02x\n", link_bw); 421 else 422 drm_dbg_kms(&i915->drm, 423 "Using LINK_RATE_SET value %02x\n", rate_select); 424 425 /* Write the link configuration data */ 426 link_config[0] = link_bw; 427 link_config[1] = crtc_state->lane_count; 428 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 429 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 430 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); 431 432 /* eDP 1.4 rate select method. */ 433 if (!link_bw) 434 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET, 435 &rate_select, 1); 436 437 link_config[0] = 0; 438 link_config[1] = DP_SET_ANSI_8B10B; 439 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 440 441 intel_dp->DP |= DP_PORT_EN; 442 443 return true; 444 } 445 446 static void intel_dp_link_training_clock_recovery_delay(struct intel_dp *intel_dp, 447 enum drm_dp_phy dp_phy) 448 { 449 if (dp_phy == DP_PHY_DPRX) 450 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 451 else 452 drm_dp_lttpr_link_train_clock_recovery_delay(); 453 } 454 455 /* 456 * Perform the link training clock recovery phase on the given DP PHY using 457 * training pattern 1. 458 */ 459 static bool 460 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, 461 const struct intel_crtc_state *crtc_state, 462 enum drm_dp_phy dp_phy) 463 { 464 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 465 u8 voltage; 466 int voltage_tries, cr_tries, max_cr_tries; 467 bool max_vswing_reached = false; 468 469 /* clock recovery */ 470 if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy, 471 DP_TRAINING_PATTERN_1 | 472 DP_LINK_SCRAMBLING_DISABLE)) { 473 drm_err(&i915->drm, "failed to enable link training\n"); 474 return false; 475 } 476 477 /* 478 * The DP 1.4 spec defines the max clock recovery retries value 479 * as 10 but for pre-DP 1.4 devices we set a very tolerant 480 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x 481 * x 5 identical voltage retries). Since the previous specs didn't 482 * define a limit and created the possibility of an infinite loop 483 * we want to prevent any sync from triggering that corner case. 484 */ 485 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 486 max_cr_tries = 10; 487 else 488 max_cr_tries = 80; 489 490 voltage_tries = 1; 491 for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) { 492 u8 link_status[DP_LINK_STATUS_SIZE]; 493 494 intel_dp_link_training_clock_recovery_delay(intel_dp, dp_phy); 495 496 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 497 link_status) < 0) { 498 drm_err(&i915->drm, "failed to get link status\n"); 499 return false; 500 } 501 502 if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) { 503 drm_dbg_kms(&i915->drm, "clock recovery OK\n"); 504 return true; 505 } 506 507 if (voltage_tries == 5) { 508 drm_dbg_kms(&i915->drm, 509 "Same voltage tried 5 times\n"); 510 return false; 511 } 512 513 if (max_vswing_reached) { 514 drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n"); 515 return false; 516 } 517 518 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 519 520 /* Update training set as requested by target */ 521 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 522 link_status); 523 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 524 drm_err(&i915->drm, 525 "failed to update link training\n"); 526 return false; 527 } 528 529 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == 530 voltage) 531 ++voltage_tries; 532 else 533 voltage_tries = 1; 534 535 if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state)) 536 max_vswing_reached = true; 537 538 } 539 drm_err(&i915->drm, 540 "Failed clock recovery %d times, giving up!\n", max_cr_tries); 541 return false; 542 } 543 544 /* 545 * Pick training pattern for channel equalization. Training pattern 4 for HBR3 546 * or for 1.4 devices that support it, training Pattern 3 for HBR2 547 * or 1.2 devices that support it, Training Pattern 2 otherwise. 548 */ 549 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, 550 const struct intel_crtc_state *crtc_state, 551 enum drm_dp_phy dp_phy) 552 { 553 bool source_tps3, sink_tps3, source_tps4, sink_tps4; 554 555 /* 556 * Intel platforms that support HBR3 also support TPS4. It is mandatory 557 * for all downstream devices that support HBR3. There are no known eDP 558 * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 559 * specification. 560 * LTTPRs must support TPS4. 561 */ 562 source_tps4 = intel_dp_source_supports_hbr3(intel_dp); 563 sink_tps4 = dp_phy != DP_PHY_DPRX || 564 drm_dp_tps4_supported(intel_dp->dpcd); 565 if (source_tps4 && sink_tps4) { 566 return DP_TRAINING_PATTERN_4; 567 } else if (crtc_state->port_clock == 810000) { 568 if (!source_tps4) 569 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 570 "8.1 Gbps link rate without source HBR3/TPS4 support\n"); 571 if (!sink_tps4) 572 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 573 "8.1 Gbps link rate without sink TPS4 support\n"); 574 } 575 /* 576 * Intel platforms that support HBR2 also support TPS3. TPS3 support is 577 * also mandatory for downstream devices that support HBR2. However, not 578 * all sinks follow the spec. 579 */ 580 source_tps3 = intel_dp_source_supports_hbr2(intel_dp); 581 sink_tps3 = dp_phy != DP_PHY_DPRX || 582 drm_dp_tps3_supported(intel_dp->dpcd); 583 if (source_tps3 && sink_tps3) { 584 return DP_TRAINING_PATTERN_3; 585 } else if (crtc_state->port_clock >= 540000) { 586 if (!source_tps3) 587 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 588 ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n"); 589 if (!sink_tps3) 590 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 591 ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); 592 } 593 594 return DP_TRAINING_PATTERN_2; 595 } 596 597 static void 598 intel_dp_link_training_channel_equalization_delay(struct intel_dp *intel_dp, 599 enum drm_dp_phy dp_phy) 600 { 601 if (dp_phy == DP_PHY_DPRX) { 602 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 603 } else { 604 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 605 606 drm_dp_lttpr_link_train_channel_eq_delay(phy_caps); 607 } 608 } 609 610 /* 611 * Perform the link training channel equalization phase on the given DP PHY 612 * using one of training pattern 2, 3 or 4 depending on the source and 613 * sink capabilities. 614 */ 615 static bool 616 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp, 617 const struct intel_crtc_state *crtc_state, 618 enum drm_dp_phy dp_phy) 619 { 620 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 621 int tries; 622 u32 training_pattern; 623 u8 link_status[DP_LINK_STATUS_SIZE]; 624 bool channel_eq = false; 625 626 training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy); 627 /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ 628 if (training_pattern != DP_TRAINING_PATTERN_4) 629 training_pattern |= DP_LINK_SCRAMBLING_DISABLE; 630 631 /* channel equalization */ 632 if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, 633 training_pattern)) { 634 drm_err(&i915->drm, "failed to start channel equalization\n"); 635 return false; 636 } 637 638 for (tries = 0; tries < 5; tries++) { 639 intel_dp_link_training_channel_equalization_delay(intel_dp, 640 dp_phy); 641 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 642 link_status) < 0) { 643 drm_err(&i915->drm, 644 "failed to get link status\n"); 645 break; 646 } 647 648 /* Make sure clock is still ok */ 649 if (!drm_dp_clock_recovery_ok(link_status, 650 crtc_state->lane_count)) { 651 intel_dp_dump_link_status(link_status); 652 drm_dbg_kms(&i915->drm, 653 "Clock recovery check failed, cannot " 654 "continue channel equalization\n"); 655 break; 656 } 657 658 if (drm_dp_channel_eq_ok(link_status, 659 crtc_state->lane_count)) { 660 channel_eq = true; 661 drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training " 662 "successful\n"); 663 break; 664 } 665 666 /* Update training set as requested by target */ 667 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 668 link_status); 669 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 670 drm_err(&i915->drm, 671 "failed to update link training\n"); 672 break; 673 } 674 } 675 676 /* Try 5 times, else fail and try at lower BW */ 677 if (tries == 5) { 678 intel_dp_dump_link_status(link_status); 679 drm_dbg_kms(&i915->drm, 680 "Channel equalization failed 5 times\n"); 681 } 682 683 return channel_eq; 684 } 685 686 static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp, 687 enum drm_dp_phy dp_phy) 688 { 689 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 690 u8 val = DP_TRAINING_PATTERN_DISABLE; 691 692 return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1; 693 } 694 695 /** 696 * intel_dp_stop_link_train - stop link training 697 * @intel_dp: DP struct 698 * @crtc_state: state for CRTC attached to the encoder 699 * 700 * Stop the link training of the @intel_dp port, disabling the test pattern 701 * symbol generation on the port and disabling the training pattern in 702 * the sink's DPCD. 703 * 704 * What symbols are output on the port after this point is 705 * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern 706 * with the pipe being disabled, on older platforms it's HW specific if/how an 707 * idle pattern is generated, as the pipe is already enabled here for those. 708 * 709 * This function must be called after intel_dp_start_link_train(). 710 */ 711 void intel_dp_stop_link_train(struct intel_dp *intel_dp, 712 const struct intel_crtc_state *crtc_state) 713 { 714 intel_dp->link_trained = true; 715 716 intel_dp_program_link_training_pattern(intel_dp, 717 crtc_state, 718 DP_TRAINING_PATTERN_DISABLE); 719 intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX); 720 } 721 722 static bool 723 intel_dp_link_train_phy(struct intel_dp *intel_dp, 724 const struct intel_crtc_state *crtc_state, 725 enum drm_dp_phy dp_phy) 726 { 727 struct intel_connector *intel_connector = intel_dp->attached_connector; 728 char phy_name[10]; 729 bool ret = false; 730 731 if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy)) 732 goto out; 733 734 if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy)) 735 goto out; 736 737 ret = true; 738 739 out: 740 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 741 "[CONNECTOR:%d:%s] Link Training %s at link rate = %d, lane count = %d, at %s", 742 intel_connector->base.base.id, 743 intel_connector->base.name, 744 ret ? "passed" : "failed", 745 crtc_state->port_clock, crtc_state->lane_count, 746 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name))); 747 748 return ret; 749 } 750 751 static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, 752 const struct intel_crtc_state *crtc_state) 753 { 754 struct intel_connector *intel_connector = intel_dp->attached_connector; 755 756 if (intel_dp->hobl_active) { 757 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 758 "Link Training failed with HOBL active, not enabling it from now on"); 759 intel_dp->hobl_failed = true; 760 } else if (intel_dp_get_link_train_fallback_values(intel_dp, 761 crtc_state->port_clock, 762 crtc_state->lane_count)) { 763 return; 764 } 765 766 /* Schedule a Hotplug Uevent to userspace to start modeset */ 767 schedule_work(&intel_connector->modeset_retry_work); 768 } 769 770 /* Perform the link training on all LTTPRs and the DPRX on a link. */ 771 static bool 772 intel_dp_link_train_all_phys(struct intel_dp *intel_dp, 773 const struct intel_crtc_state *crtc_state, 774 int lttpr_count) 775 { 776 bool ret = true; 777 int i; 778 779 intel_dp_prepare_link_train(intel_dp, crtc_state); 780 781 for (i = lttpr_count - 1; i >= 0; i--) { 782 enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i); 783 784 ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy); 785 intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy); 786 787 if (!ret) 788 break; 789 } 790 791 if (ret) 792 intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX); 793 794 if (intel_dp->set_idle_link_train) 795 intel_dp->set_idle_link_train(intel_dp, crtc_state); 796 797 return ret; 798 } 799 800 /** 801 * intel_dp_start_link_train - start link training 802 * @intel_dp: DP struct 803 * @crtc_state: state for CRTC attached to the encoder 804 * 805 * Start the link training of the @intel_dp port, scheduling a fallback 806 * retraining with reduced link rate/lane parameters if the link training 807 * fails. 808 * After calling this function intel_dp_stop_link_train() must be called. 809 */ 810 void intel_dp_start_link_train(struct intel_dp *intel_dp, 811 const struct intel_crtc_state *crtc_state) 812 { 813 /* 814 * TODO: Reiniting LTTPRs here won't be needed once proper connector 815 * HW state readout is added. 816 */ 817 int lttpr_count = intel_dp_lttpr_init(intel_dp); 818 819 if (!intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count)) 820 intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); 821 } 822