1 /* 2 * Copyright © 2008-2015 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 */ 23 24 #include "intel_display_types.h" 25 #include "intel_dp.h" 26 #include "intel_dp_link_training.h" 27 28 static void 29 intel_dp_dump_link_status(const u8 link_status[DP_LINK_STATUS_SIZE]) 30 { 31 32 DRM_DEBUG_KMS("ln0_1:0x%x ln2_3:0x%x align:0x%x sink:0x%x adj_req0_1:0x%x adj_req2_3:0x%x", 33 link_status[0], link_status[1], link_status[2], 34 link_status[3], link_status[4], link_status[5]); 35 } 36 37 static void intel_dp_reset_lttpr_count(struct intel_dp *intel_dp) 38 { 39 intel_dp->lttpr_common_caps[DP_PHY_REPEATER_CNT - 40 DP_LT_TUNABLE_PHY_REPEATER_FIELD_DATA_STRUCTURE_REV] = 0; 41 } 42 43 static const char *intel_dp_phy_name(enum drm_dp_phy dp_phy, 44 char *buf, size_t buf_size) 45 { 46 if (dp_phy == DP_PHY_DPRX) 47 snprintf(buf, buf_size, "DPRX"); 48 else 49 snprintf(buf, buf_size, "LTTPR %d", dp_phy - DP_PHY_LTTPR1 + 1); 50 51 return buf; 52 } 53 54 static u8 *intel_dp_lttpr_phy_caps(struct intel_dp *intel_dp, 55 enum drm_dp_phy dp_phy) 56 { 57 return intel_dp->lttpr_phy_caps[dp_phy - DP_PHY_LTTPR1]; 58 } 59 60 static void intel_dp_read_lttpr_phy_caps(struct intel_dp *intel_dp, 61 enum drm_dp_phy dp_phy) 62 { 63 u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 64 char phy_name[10]; 65 66 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name)); 67 68 if (drm_dp_read_lttpr_phy_caps(&intel_dp->aux, dp_phy, phy_caps) < 0) { 69 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 70 "failed to read the PHY caps for %s\n", 71 phy_name); 72 return; 73 } 74 75 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 76 "%s PHY capabilities: %*ph\n", 77 phy_name, 78 (int)sizeof(intel_dp->lttpr_phy_caps[0]), 79 phy_caps); 80 } 81 82 static bool intel_dp_read_lttpr_common_caps(struct intel_dp *intel_dp) 83 { 84 if (drm_dp_read_lttpr_common_caps(&intel_dp->aux, 85 intel_dp->lttpr_common_caps) < 0) { 86 memset(intel_dp->lttpr_common_caps, 0, 87 sizeof(intel_dp->lttpr_common_caps)); 88 return false; 89 } 90 91 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 92 "LTTPR common capabilities: %*ph\n", 93 (int)sizeof(intel_dp->lttpr_common_caps), 94 intel_dp->lttpr_common_caps); 95 96 return true; 97 } 98 99 static bool 100 intel_dp_set_lttpr_transparent_mode(struct intel_dp *intel_dp, bool enable) 101 { 102 u8 val = enable ? DP_PHY_REPEATER_MODE_TRANSPARENT : 103 DP_PHY_REPEATER_MODE_NON_TRANSPARENT; 104 105 return drm_dp_dpcd_write(&intel_dp->aux, DP_PHY_REPEATER_MODE, &val, 1) == 1; 106 } 107 108 /** 109 * intel_dp_lttpr_init - detect LTTPRs and init the LTTPR link training mode 110 * @intel_dp: Intel DP struct 111 * 112 * Read the LTTPR common capabilities, switch to non-transparent link training 113 * mode if any is detected and read the PHY capabilities for all detected 114 * LTTPRs. In case of an LTTPR detection error or if the number of 115 * LTTPRs is more than is supported (8), fall back to the no-LTTPR, 116 * transparent mode link training mode. 117 * 118 * Returns: 119 * >0 if LTTPRs were detected and the non-transparent LT mode was set 120 * 0 if no LTTPRs or more than 8 LTTPRs were detected or in case of a 121 * detection failure and the transparent LT mode was set 122 */ 123 int intel_dp_lttpr_init(struct intel_dp *intel_dp) 124 { 125 int lttpr_count; 126 bool ret; 127 int i; 128 129 if (intel_dp_is_edp(intel_dp)) 130 return 0; 131 132 ret = intel_dp_read_lttpr_common_caps(intel_dp); 133 if (!ret) 134 return 0; 135 136 lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 137 /* 138 * Prevent setting LTTPR transparent mode explicitly if no LTTPRs are 139 * detected as this breaks link training at least on the Dell WD19TB 140 * dock. 141 */ 142 if (lttpr_count == 0) 143 return 0; 144 145 /* 146 * See DP Standard v2.0 3.6.6.1. about the explicit disabling of 147 * non-transparent mode and the disable->enable non-transparent mode 148 * sequence. 149 */ 150 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 151 152 /* 153 * In case of unsupported number of LTTPRs or failing to switch to 154 * non-transparent mode fall-back to transparent link training mode, 155 * still taking into account any LTTPR common lane- rate/count limits. 156 */ 157 if (lttpr_count < 0) 158 return 0; 159 160 if (!intel_dp_set_lttpr_transparent_mode(intel_dp, false)) { 161 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 162 "Switching to LTTPR non-transparent LT mode failed, fall-back to transparent mode\n"); 163 164 intel_dp_set_lttpr_transparent_mode(intel_dp, true); 165 intel_dp_reset_lttpr_count(intel_dp); 166 167 return 0; 168 } 169 170 for (i = 0; i < lttpr_count; i++) 171 intel_dp_read_lttpr_phy_caps(intel_dp, DP_PHY_LTTPR(i)); 172 173 return lttpr_count; 174 } 175 EXPORT_SYMBOL(intel_dp_lttpr_init); 176 177 static u8 dp_voltage_max(u8 preemph) 178 { 179 switch (preemph & DP_TRAIN_PRE_EMPHASIS_MASK) { 180 case DP_TRAIN_PRE_EMPH_LEVEL_0: 181 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 182 case DP_TRAIN_PRE_EMPH_LEVEL_1: 183 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 184 case DP_TRAIN_PRE_EMPH_LEVEL_2: 185 return DP_TRAIN_VOLTAGE_SWING_LEVEL_1; 186 case DP_TRAIN_PRE_EMPH_LEVEL_3: 187 default: 188 return DP_TRAIN_VOLTAGE_SWING_LEVEL_0; 189 } 190 } 191 192 static u8 intel_dp_lttpr_voltage_max(struct intel_dp *intel_dp, 193 enum drm_dp_phy dp_phy) 194 { 195 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 196 197 if (drm_dp_lttpr_voltage_swing_level_3_supported(phy_caps)) 198 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 199 else 200 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 201 } 202 203 static u8 intel_dp_lttpr_preemph_max(struct intel_dp *intel_dp, 204 enum drm_dp_phy dp_phy) 205 { 206 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 207 208 if (drm_dp_lttpr_pre_emphasis_level_3_supported(phy_caps)) 209 return DP_TRAIN_PRE_EMPH_LEVEL_3; 210 else 211 return DP_TRAIN_PRE_EMPH_LEVEL_2; 212 } 213 214 static bool 215 intel_dp_phy_is_downstream_of_source(struct intel_dp *intel_dp, 216 enum drm_dp_phy dp_phy) 217 { 218 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 219 int lttpr_count = drm_dp_lttpr_count(intel_dp->lttpr_common_caps); 220 221 drm_WARN_ON_ONCE(&i915->drm, lttpr_count <= 0 && dp_phy != DP_PHY_DPRX); 222 223 return lttpr_count <= 0 || dp_phy == DP_PHY_LTTPR(lttpr_count - 1); 224 } 225 226 static u8 intel_dp_phy_voltage_max(struct intel_dp *intel_dp, 227 const struct intel_crtc_state *crtc_state, 228 enum drm_dp_phy dp_phy) 229 { 230 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 231 u8 voltage_max; 232 233 /* 234 * Get voltage_max from the DPTX_PHY (source or LTTPR) upstream from 235 * the DPRX_PHY we train. 236 */ 237 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 238 voltage_max = intel_dp->voltage_max(intel_dp, crtc_state); 239 else 240 voltage_max = intel_dp_lttpr_voltage_max(intel_dp, dp_phy + 1); 241 242 drm_WARN_ON_ONCE(&i915->drm, 243 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_2 && 244 voltage_max != DP_TRAIN_VOLTAGE_SWING_LEVEL_3); 245 246 return voltage_max; 247 } 248 249 static u8 intel_dp_phy_preemph_max(struct intel_dp *intel_dp, 250 enum drm_dp_phy dp_phy) 251 { 252 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 253 u8 preemph_max; 254 255 /* 256 * Get preemph_max from the DPTX_PHY (source or LTTPR) upstream from 257 * the DPRX_PHY we train. 258 */ 259 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 260 preemph_max = intel_dp->preemph_max(intel_dp); 261 else 262 preemph_max = intel_dp_lttpr_preemph_max(intel_dp, dp_phy + 1); 263 264 drm_WARN_ON_ONCE(&i915->drm, 265 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_2 && 266 preemph_max != DP_TRAIN_PRE_EMPH_LEVEL_3); 267 268 return preemph_max; 269 } 270 271 void 272 intel_dp_get_adjust_train(struct intel_dp *intel_dp, 273 const struct intel_crtc_state *crtc_state, 274 enum drm_dp_phy dp_phy, 275 const u8 link_status[DP_LINK_STATUS_SIZE]) 276 { 277 u8 v = 0; 278 u8 p = 0; 279 int lane; 280 u8 voltage_max; 281 u8 preemph_max; 282 283 for (lane = 0; lane < crtc_state->lane_count; lane++) { 284 v = max(v, drm_dp_get_adjust_request_voltage(link_status, lane)); 285 p = max(p, drm_dp_get_adjust_request_pre_emphasis(link_status, lane)); 286 } 287 288 preemph_max = intel_dp_phy_preemph_max(intel_dp, dp_phy); 289 if (p >= preemph_max) 290 p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; 291 292 v = min(v, dp_voltage_max(p)); 293 294 voltage_max = intel_dp_phy_voltage_max(intel_dp, crtc_state, dp_phy); 295 if (v >= voltage_max) 296 v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; 297 298 for (lane = 0; lane < 4; lane++) 299 intel_dp->train_set[lane] = v | p; 300 } 301 302 static int intel_dp_training_pattern_set_reg(struct intel_dp *intel_dp, 303 enum drm_dp_phy dp_phy) 304 { 305 return dp_phy == DP_PHY_DPRX ? 306 DP_TRAINING_PATTERN_SET : 307 DP_TRAINING_PATTERN_SET_PHY_REPEATER(dp_phy); 308 } 309 310 static bool 311 intel_dp_set_link_train(struct intel_dp *intel_dp, 312 const struct intel_crtc_state *crtc_state, 313 enum drm_dp_phy dp_phy, 314 u8 dp_train_pat) 315 { 316 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 317 u8 buf[sizeof(intel_dp->train_set) + 1]; 318 int len; 319 320 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 321 dp_train_pat); 322 323 buf[0] = dp_train_pat; 324 /* DP_TRAINING_LANEx_SET follow DP_TRAINING_PATTERN_SET */ 325 memcpy(buf + 1, intel_dp->train_set, crtc_state->lane_count); 326 len = crtc_state->lane_count + 1; 327 328 return drm_dp_dpcd_write(&intel_dp->aux, reg, buf, len) == len; 329 } 330 331 void intel_dp_set_signal_levels(struct intel_dp *intel_dp, 332 const struct intel_crtc_state *crtc_state, 333 enum drm_dp_phy dp_phy) 334 { 335 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 336 u8 train_set = intel_dp->train_set[0]; 337 char phy_name[10]; 338 339 drm_dbg_kms(&dev_priv->drm, "Using vswing level %d%s, pre-emphasis level %d%s, at %s\n", 340 train_set & DP_TRAIN_VOLTAGE_SWING_MASK, 341 train_set & DP_TRAIN_MAX_SWING_REACHED ? " (max)" : "", 342 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> 343 DP_TRAIN_PRE_EMPHASIS_SHIFT, 344 train_set & DP_TRAIN_MAX_PRE_EMPHASIS_REACHED ? 345 " (max)" : "", 346 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name))); 347 348 if (intel_dp_phy_is_downstream_of_source(intel_dp, dp_phy)) 349 intel_dp->set_signal_levels(intel_dp, crtc_state); 350 } 351 352 static bool 353 intel_dp_reset_link_train(struct intel_dp *intel_dp, 354 const struct intel_crtc_state *crtc_state, 355 enum drm_dp_phy dp_phy, 356 u8 dp_train_pat) 357 { 358 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); 359 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 360 return intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, dp_train_pat); 361 } 362 363 static bool 364 intel_dp_update_link_train(struct intel_dp *intel_dp, 365 const struct intel_crtc_state *crtc_state, 366 enum drm_dp_phy dp_phy) 367 { 368 int reg = dp_phy == DP_PHY_DPRX ? 369 DP_TRAINING_LANE0_SET : 370 DP_TRAINING_LANE0_SET_PHY_REPEATER(dp_phy); 371 int ret; 372 373 intel_dp_set_signal_levels(intel_dp, crtc_state, dp_phy); 374 375 ret = drm_dp_dpcd_write(&intel_dp->aux, reg, 376 intel_dp->train_set, crtc_state->lane_count); 377 378 return ret == crtc_state->lane_count; 379 } 380 381 static bool intel_dp_link_max_vswing_reached(struct intel_dp *intel_dp, 382 const struct intel_crtc_state *crtc_state) 383 { 384 int lane; 385 386 for (lane = 0; lane < crtc_state->lane_count; lane++) 387 if ((intel_dp->train_set[lane] & 388 DP_TRAIN_MAX_SWING_REACHED) == 0) 389 return false; 390 391 return true; 392 } 393 394 /* 395 * Prepare link training by configuring the link parameters. On DDI platforms 396 * also enable the port here. 397 */ 398 static bool 399 intel_dp_prepare_link_train(struct intel_dp *intel_dp, 400 const struct intel_crtc_state *crtc_state) 401 { 402 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 403 u8 link_config[2]; 404 u8 link_bw, rate_select; 405 406 if (intel_dp->prepare_link_retrain) 407 intel_dp->prepare_link_retrain(intel_dp, crtc_state); 408 409 intel_dp_compute_rate(intel_dp, crtc_state->port_clock, 410 &link_bw, &rate_select); 411 412 if (link_bw) 413 drm_dbg_kms(&i915->drm, 414 "Using LINK_BW_SET value %02x\n", link_bw); 415 else 416 drm_dbg_kms(&i915->drm, 417 "Using LINK_RATE_SET value %02x\n", rate_select); 418 419 /* Write the link configuration data */ 420 link_config[0] = link_bw; 421 link_config[1] = crtc_state->lane_count; 422 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 423 link_config[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; 424 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_BW_SET, link_config, 2); 425 426 /* eDP 1.4 rate select method. */ 427 if (!link_bw) 428 drm_dp_dpcd_write(&intel_dp->aux, DP_LINK_RATE_SET, 429 &rate_select, 1); 430 431 link_config[0] = crtc_state->vrr.enable ? DP_MSA_TIMING_PAR_IGNORE_EN : 0; 432 link_config[1] = DP_SET_ANSI_8B10B; 433 drm_dp_dpcd_write(&intel_dp->aux, DP_DOWNSPREAD_CTRL, link_config, 2); 434 435 intel_dp->DP |= DP_PORT_EN; 436 437 return true; 438 } 439 440 static void intel_dp_link_training_clock_recovery_delay(struct intel_dp *intel_dp, 441 enum drm_dp_phy dp_phy) 442 { 443 if (dp_phy == DP_PHY_DPRX) 444 drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); 445 else 446 drm_dp_lttpr_link_train_clock_recovery_delay(); 447 } 448 449 /* 450 * Perform the link training clock recovery phase on the given DP PHY using 451 * training pattern 1. 452 */ 453 static bool 454 intel_dp_link_training_clock_recovery(struct intel_dp *intel_dp, 455 const struct intel_crtc_state *crtc_state, 456 enum drm_dp_phy dp_phy) 457 { 458 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 459 u8 voltage; 460 int voltage_tries, cr_tries, max_cr_tries; 461 bool max_vswing_reached = false; 462 463 /* clock recovery */ 464 if (!intel_dp_reset_link_train(intel_dp, crtc_state, dp_phy, 465 DP_TRAINING_PATTERN_1 | 466 DP_LINK_SCRAMBLING_DISABLE)) { 467 drm_err(&i915->drm, "failed to enable link training\n"); 468 return false; 469 } 470 471 /* 472 * The DP 1.4 spec defines the max clock recovery retries value 473 * as 10 but for pre-DP 1.4 devices we set a very tolerant 474 * retry limit of 80 (4 voltage levels x 4 preemphasis levels x 475 * x 5 identical voltage retries). Since the previous specs didn't 476 * define a limit and created the possibility of an infinite loop 477 * we want to prevent any sync from triggering that corner case. 478 */ 479 if (intel_dp->dpcd[DP_DPCD_REV] >= DP_DPCD_REV_14) 480 max_cr_tries = 10; 481 else 482 max_cr_tries = 80; 483 484 voltage_tries = 1; 485 for (cr_tries = 0; cr_tries < max_cr_tries; ++cr_tries) { 486 u8 link_status[DP_LINK_STATUS_SIZE]; 487 488 intel_dp_link_training_clock_recovery_delay(intel_dp, dp_phy); 489 490 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 491 link_status) < 0) { 492 drm_err(&i915->drm, "failed to get link status\n"); 493 return false; 494 } 495 496 if (drm_dp_clock_recovery_ok(link_status, crtc_state->lane_count)) { 497 drm_dbg_kms(&i915->drm, "clock recovery OK\n"); 498 return true; 499 } 500 501 if (voltage_tries == 5) { 502 drm_dbg_kms(&i915->drm, 503 "Same voltage tried 5 times\n"); 504 return false; 505 } 506 507 if (max_vswing_reached) { 508 drm_dbg_kms(&i915->drm, "Max Voltage Swing reached\n"); 509 return false; 510 } 511 512 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; 513 514 /* Update training set as requested by target */ 515 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 516 link_status); 517 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 518 drm_err(&i915->drm, 519 "failed to update link training\n"); 520 return false; 521 } 522 523 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == 524 voltage) 525 ++voltage_tries; 526 else 527 voltage_tries = 1; 528 529 if (intel_dp_link_max_vswing_reached(intel_dp, crtc_state)) 530 max_vswing_reached = true; 531 532 } 533 drm_err(&i915->drm, 534 "Failed clock recovery %d times, giving up!\n", max_cr_tries); 535 return false; 536 } 537 538 /* 539 * Pick training pattern for channel equalization. Training pattern 4 for HBR3 540 * or for 1.4 devices that support it, training Pattern 3 for HBR2 541 * or 1.2 devices that support it, Training Pattern 2 otherwise. 542 */ 543 static u32 intel_dp_training_pattern(struct intel_dp *intel_dp, 544 const struct intel_crtc_state *crtc_state, 545 enum drm_dp_phy dp_phy) 546 { 547 bool source_tps3, sink_tps3, source_tps4, sink_tps4; 548 549 /* 550 * Intel platforms that support HBR3 also support TPS4. It is mandatory 551 * for all downstream devices that support HBR3. There are no known eDP 552 * panels that support TPS4 as of Feb 2018 as per VESA eDP_v1.4b_E1 553 * specification. 554 * LTTPRs must support TPS4. 555 */ 556 source_tps4 = intel_dp_source_supports_hbr3(intel_dp); 557 sink_tps4 = dp_phy != DP_PHY_DPRX || 558 drm_dp_tps4_supported(intel_dp->dpcd); 559 if (source_tps4 && sink_tps4) { 560 return DP_TRAINING_PATTERN_4; 561 } else if (crtc_state->port_clock == 810000) { 562 if (!source_tps4) 563 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 564 "8.1 Gbps link rate without source HBR3/TPS4 support\n"); 565 if (!sink_tps4) 566 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 567 "8.1 Gbps link rate without sink TPS4 support\n"); 568 } 569 /* 570 * Intel platforms that support HBR2 also support TPS3. TPS3 support is 571 * also mandatory for downstream devices that support HBR2. However, not 572 * all sinks follow the spec. 573 */ 574 source_tps3 = intel_dp_source_supports_hbr2(intel_dp); 575 sink_tps3 = dp_phy != DP_PHY_DPRX || 576 drm_dp_tps3_supported(intel_dp->dpcd); 577 if (source_tps3 && sink_tps3) { 578 return DP_TRAINING_PATTERN_3; 579 } else if (crtc_state->port_clock >= 540000) { 580 if (!source_tps3) 581 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 582 ">=5.4/6.48 Gbps link rate without source HBR2/TPS3 support\n"); 583 if (!sink_tps3) 584 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 585 ">=5.4/6.48 Gbps link rate without sink TPS3 support\n"); 586 } 587 588 return DP_TRAINING_PATTERN_2; 589 } 590 591 static void 592 intel_dp_link_training_channel_equalization_delay(struct intel_dp *intel_dp, 593 enum drm_dp_phy dp_phy) 594 { 595 if (dp_phy == DP_PHY_DPRX) { 596 drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); 597 } else { 598 const u8 *phy_caps = intel_dp_lttpr_phy_caps(intel_dp, dp_phy); 599 600 drm_dp_lttpr_link_train_channel_eq_delay(phy_caps); 601 } 602 } 603 604 /* 605 * Perform the link training channel equalization phase on the given DP PHY 606 * using one of training pattern 2, 3 or 4 depending on the source and 607 * sink capabilities. 608 */ 609 static bool 610 intel_dp_link_training_channel_equalization(struct intel_dp *intel_dp, 611 const struct intel_crtc_state *crtc_state, 612 enum drm_dp_phy dp_phy) 613 { 614 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 615 int tries; 616 u32 training_pattern; 617 u8 link_status[DP_LINK_STATUS_SIZE]; 618 bool channel_eq = false; 619 620 training_pattern = intel_dp_training_pattern(intel_dp, crtc_state, dp_phy); 621 /* Scrambling is disabled for TPS2/3 and enabled for TPS4 */ 622 if (training_pattern != DP_TRAINING_PATTERN_4) 623 training_pattern |= DP_LINK_SCRAMBLING_DISABLE; 624 625 /* channel equalization */ 626 if (!intel_dp_set_link_train(intel_dp, crtc_state, dp_phy, 627 training_pattern)) { 628 drm_err(&i915->drm, "failed to start channel equalization\n"); 629 return false; 630 } 631 632 for (tries = 0; tries < 5; tries++) { 633 intel_dp_link_training_channel_equalization_delay(intel_dp, 634 dp_phy); 635 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, dp_phy, 636 link_status) < 0) { 637 drm_err(&i915->drm, 638 "failed to get link status\n"); 639 break; 640 } 641 642 /* Make sure clock is still ok */ 643 if (!drm_dp_clock_recovery_ok(link_status, 644 crtc_state->lane_count)) { 645 intel_dp_dump_link_status(link_status); 646 drm_dbg_kms(&i915->drm, 647 "Clock recovery check failed, cannot " 648 "continue channel equalization\n"); 649 break; 650 } 651 652 if (drm_dp_channel_eq_ok(link_status, 653 crtc_state->lane_count)) { 654 channel_eq = true; 655 drm_dbg_kms(&i915->drm, "Channel EQ done. DP Training " 656 "successful\n"); 657 break; 658 } 659 660 /* Update training set as requested by target */ 661 intel_dp_get_adjust_train(intel_dp, crtc_state, dp_phy, 662 link_status); 663 if (!intel_dp_update_link_train(intel_dp, crtc_state, dp_phy)) { 664 drm_err(&i915->drm, 665 "failed to update link training\n"); 666 break; 667 } 668 } 669 670 /* Try 5 times, else fail and try at lower BW */ 671 if (tries == 5) { 672 intel_dp_dump_link_status(link_status); 673 drm_dbg_kms(&i915->drm, 674 "Channel equalization failed 5 times\n"); 675 } 676 677 return channel_eq; 678 } 679 680 static bool intel_dp_disable_dpcd_training_pattern(struct intel_dp *intel_dp, 681 enum drm_dp_phy dp_phy) 682 { 683 int reg = intel_dp_training_pattern_set_reg(intel_dp, dp_phy); 684 u8 val = DP_TRAINING_PATTERN_DISABLE; 685 686 return drm_dp_dpcd_write(&intel_dp->aux, reg, &val, 1) == 1; 687 } 688 689 /** 690 * intel_dp_stop_link_train - stop link training 691 * @intel_dp: DP struct 692 * @crtc_state: state for CRTC attached to the encoder 693 * 694 * Stop the link training of the @intel_dp port, disabling the training 695 * pattern in the sink's DPCD, and disabling the test pattern symbol 696 * generation on the port. 697 * 698 * What symbols are output on the port after this point is 699 * platform specific: On DDI/VLV/CHV platforms it will be the idle pattern 700 * with the pipe being disabled, on older platforms it's HW specific if/how an 701 * idle pattern is generated, as the pipe is already enabled here for those. 702 * 703 * This function must be called after intel_dp_start_link_train(). 704 */ 705 void intel_dp_stop_link_train(struct intel_dp *intel_dp, 706 const struct intel_crtc_state *crtc_state) 707 { 708 intel_dp->link_trained = true; 709 710 intel_dp_disable_dpcd_training_pattern(intel_dp, DP_PHY_DPRX); 711 intel_dp_program_link_training_pattern(intel_dp, crtc_state, 712 DP_TRAINING_PATTERN_DISABLE); 713 } 714 715 static bool 716 intel_dp_link_train_phy(struct intel_dp *intel_dp, 717 const struct intel_crtc_state *crtc_state, 718 enum drm_dp_phy dp_phy) 719 { 720 struct intel_connector *intel_connector = intel_dp->attached_connector; 721 char phy_name[10]; 722 bool ret = false; 723 724 if (!intel_dp_link_training_clock_recovery(intel_dp, crtc_state, dp_phy)) 725 goto out; 726 727 if (!intel_dp_link_training_channel_equalization(intel_dp, crtc_state, dp_phy)) 728 goto out; 729 730 ret = true; 731 732 out: 733 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 734 "[CONNECTOR:%d:%s] Link Training %s at link rate = %d, lane count = %d, at %s", 735 intel_connector->base.base.id, 736 intel_connector->base.name, 737 ret ? "passed" : "failed", 738 crtc_state->port_clock, crtc_state->lane_count, 739 intel_dp_phy_name(dp_phy, phy_name, sizeof(phy_name))); 740 741 return ret; 742 } 743 744 static void intel_dp_schedule_fallback_link_training(struct intel_dp *intel_dp, 745 const struct intel_crtc_state *crtc_state) 746 { 747 struct intel_connector *intel_connector = intel_dp->attached_connector; 748 749 if (intel_dp->hobl_active) { 750 drm_dbg_kms(&dp_to_i915(intel_dp)->drm, 751 "Link Training failed with HOBL active, not enabling it from now on"); 752 intel_dp->hobl_failed = true; 753 } else if (intel_dp_get_link_train_fallback_values(intel_dp, 754 crtc_state->port_clock, 755 crtc_state->lane_count)) { 756 return; 757 } 758 759 /* Schedule a Hotplug Uevent to userspace to start modeset */ 760 schedule_work(&intel_connector->modeset_retry_work); 761 } 762 763 /* Perform the link training on all LTTPRs and the DPRX on a link. */ 764 static bool 765 intel_dp_link_train_all_phys(struct intel_dp *intel_dp, 766 const struct intel_crtc_state *crtc_state, 767 int lttpr_count) 768 { 769 bool ret = true; 770 int i; 771 772 intel_dp_prepare_link_train(intel_dp, crtc_state); 773 774 for (i = lttpr_count - 1; i >= 0; i--) { 775 enum drm_dp_phy dp_phy = DP_PHY_LTTPR(i); 776 777 ret = intel_dp_link_train_phy(intel_dp, crtc_state, dp_phy); 778 intel_dp_disable_dpcd_training_pattern(intel_dp, dp_phy); 779 780 if (!ret) 781 break; 782 } 783 784 if (ret) 785 intel_dp_link_train_phy(intel_dp, crtc_state, DP_PHY_DPRX); 786 787 if (intel_dp->set_idle_link_train) 788 intel_dp->set_idle_link_train(intel_dp, crtc_state); 789 790 return ret; 791 } 792 793 /** 794 * intel_dp_start_link_train - start link training 795 * @intel_dp: DP struct 796 * @crtc_state: state for CRTC attached to the encoder 797 * 798 * Start the link training of the @intel_dp port, scheduling a fallback 799 * retraining with reduced link rate/lane parameters if the link training 800 * fails. 801 * After calling this function intel_dp_stop_link_train() must be called. 802 */ 803 void intel_dp_start_link_train(struct intel_dp *intel_dp, 804 const struct intel_crtc_state *crtc_state) 805 { 806 /* 807 * TODO: Reiniting LTTPRs here won't be needed once proper connector 808 * HW state readout is added. 809 */ 810 int lttpr_count = intel_dp_lttpr_init(intel_dp); 811 812 if (!intel_dp_link_train_all_phys(intel_dp, crtc_state, lttpr_count)) 813 intel_dp_schedule_fallback_link_training(intel_dp, crtc_state); 814 } 815