1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2020 Google, Inc. 4 * 5 * Authors: 6 * Sean Paul <seanpaul@chromium.org> 7 */ 8 9 #include <drm/drm_dp_helper.h> 10 #include <drm/drm_dp_mst_helper.h> 11 #include <drm/drm_hdcp.h> 12 #include <drm/drm_print.h> 13 14 #include "intel_display_types.h" 15 #include "intel_ddi.h" 16 #include "intel_dp.h" 17 #include "intel_hdcp.h" 18 19 static unsigned int transcoder_to_stream_enc_status(enum transcoder cpu_transcoder) 20 { 21 u32 stream_enc_mask; 22 23 switch (cpu_transcoder) { 24 case TRANSCODER_A: 25 stream_enc_mask = HDCP_STATUS_STREAM_A_ENC; 26 break; 27 case TRANSCODER_B: 28 stream_enc_mask = HDCP_STATUS_STREAM_B_ENC; 29 break; 30 case TRANSCODER_C: 31 stream_enc_mask = HDCP_STATUS_STREAM_C_ENC; 32 break; 33 case TRANSCODER_D: 34 stream_enc_mask = HDCP_STATUS_STREAM_D_ENC; 35 break; 36 default: 37 stream_enc_mask = 0; 38 } 39 40 return stream_enc_mask; 41 } 42 43 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout) 44 { 45 long ret; 46 47 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count)) 48 ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C, 49 msecs_to_jiffies(timeout)); 50 51 if (!ret) 52 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n"); 53 } 54 55 static 56 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 57 u8 *an) 58 { 59 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 60 u8 aksv[DRM_HDCP_KSV_LEN] = {}; 61 ssize_t dpcd_ret; 62 63 /* Output An first, that's easy */ 64 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN, 65 an, DRM_HDCP_AN_LEN); 66 if (dpcd_ret != DRM_HDCP_AN_LEN) { 67 drm_dbg_kms(&i915->drm, 68 "Failed to write An over DP/AUX (%zd)\n", 69 dpcd_ret); 70 return dpcd_ret >= 0 ? -EIO : dpcd_ret; 71 } 72 73 /* 74 * Since Aksv is Oh-So-Secret, we can't access it in software. So we 75 * send an empty buffer of the correct length through the DP helpers. On 76 * the other side, in the transfer hook, we'll generate a flag based on 77 * the destination address which will tickle the hardware to output the 78 * Aksv on our behalf after the header is sent. 79 */ 80 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV, 81 aksv, DRM_HDCP_KSV_LEN); 82 if (dpcd_ret != DRM_HDCP_KSV_LEN) { 83 drm_dbg_kms(&i915->drm, 84 "Failed to write Aksv over DP/AUX (%zd)\n", 85 dpcd_ret); 86 return dpcd_ret >= 0 ? -EIO : dpcd_ret; 87 } 88 return 0; 89 } 90 91 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port, 92 u8 *bksv) 93 { 94 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 95 ssize_t ret; 96 97 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, 98 DRM_HDCP_KSV_LEN); 99 if (ret != DRM_HDCP_KSV_LEN) { 100 drm_dbg_kms(&i915->drm, 101 "Read Bksv from DP/AUX failed (%zd)\n", ret); 102 return ret >= 0 ? -EIO : ret; 103 } 104 return 0; 105 } 106 107 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port, 108 u8 *bstatus) 109 { 110 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 111 ssize_t ret; 112 113 /* 114 * For some reason the HDMI and DP HDCP specs call this register 115 * definition by different names. In the HDMI spec, it's called BSTATUS, 116 * but in DP it's called BINFO. 117 */ 118 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO, 119 bstatus, DRM_HDCP_BSTATUS_LEN); 120 if (ret != DRM_HDCP_BSTATUS_LEN) { 121 drm_dbg_kms(&i915->drm, 122 "Read bstatus from DP/AUX failed (%zd)\n", ret); 123 return ret >= 0 ? -EIO : ret; 124 } 125 return 0; 126 } 127 128 static 129 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *dig_port, 130 u8 *bcaps) 131 { 132 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 133 ssize_t ret; 134 135 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BCAPS, 136 bcaps, 1); 137 if (ret != 1) { 138 drm_dbg_kms(&i915->drm, 139 "Read bcaps from DP/AUX failed (%zd)\n", ret); 140 return ret >= 0 ? -EIO : ret; 141 } 142 143 return 0; 144 } 145 146 static 147 int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port, 148 bool *repeater_present) 149 { 150 ssize_t ret; 151 u8 bcaps; 152 153 ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps); 154 if (ret) 155 return ret; 156 157 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT; 158 return 0; 159 } 160 161 static 162 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 163 u8 *ri_prime) 164 { 165 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 166 ssize_t ret; 167 168 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, 169 ri_prime, DRM_HDCP_RI_LEN); 170 if (ret != DRM_HDCP_RI_LEN) { 171 drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n", 172 ret); 173 return ret >= 0 ? -EIO : ret; 174 } 175 return 0; 176 } 177 178 static 179 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 180 bool *ksv_ready) 181 { 182 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 183 ssize_t ret; 184 u8 bstatus; 185 186 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, 187 &bstatus, 1); 188 if (ret != 1) { 189 drm_dbg_kms(&i915->drm, 190 "Read bstatus from DP/AUX failed (%zd)\n", ret); 191 return ret >= 0 ? -EIO : ret; 192 } 193 *ksv_ready = bstatus & DP_BSTATUS_READY; 194 return 0; 195 } 196 197 static 198 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 199 int num_downstream, u8 *ksv_fifo) 200 { 201 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 202 ssize_t ret; 203 int i; 204 205 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */ 206 for (i = 0; i < num_downstream; i += 3) { 207 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN; 208 ret = drm_dp_dpcd_read(&dig_port->dp.aux, 209 DP_AUX_HDCP_KSV_FIFO, 210 ksv_fifo + i * DRM_HDCP_KSV_LEN, 211 len); 212 if (ret != len) { 213 drm_dbg_kms(&i915->drm, 214 "Read ksv[%d] from DP/AUX failed (%zd)\n", 215 i, ret); 216 return ret >= 0 ? -EIO : ret; 217 } 218 } 219 return 0; 220 } 221 222 static 223 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 224 int i, u32 *part) 225 { 226 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 227 ssize_t ret; 228 229 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 230 return -EINVAL; 231 232 ret = drm_dp_dpcd_read(&dig_port->dp.aux, 233 DP_AUX_HDCP_V_PRIME(i), part, 234 DRM_HDCP_V_PRIME_PART_LEN); 235 if (ret != DRM_HDCP_V_PRIME_PART_LEN) { 236 drm_dbg_kms(&i915->drm, 237 "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret); 238 return ret >= 0 ? -EIO : ret; 239 } 240 return 0; 241 } 242 243 static 244 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 245 enum transcoder cpu_transcoder, 246 bool enable) 247 { 248 /* Not used for single stream DisplayPort setups */ 249 return 0; 250 } 251 252 static 253 bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port, 254 struct intel_connector *connector) 255 { 256 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 257 ssize_t ret; 258 u8 bstatus; 259 260 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, 261 &bstatus, 1); 262 if (ret != 1) { 263 drm_dbg_kms(&i915->drm, 264 "Read bstatus from DP/AUX failed (%zd)\n", ret); 265 return false; 266 } 267 268 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ)); 269 } 270 271 static 272 int intel_dp_hdcp_capable(struct intel_digital_port *dig_port, 273 bool *hdcp_capable) 274 { 275 ssize_t ret; 276 u8 bcaps; 277 278 ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps); 279 if (ret) 280 return ret; 281 282 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE; 283 return 0; 284 } 285 286 struct hdcp2_dp_errata_stream_type { 287 u8 msg_id; 288 u8 stream_type; 289 } __packed; 290 291 struct hdcp2_dp_msg_data { 292 u8 msg_id; 293 u32 offset; 294 bool msg_detectable; 295 u32 timeout; 296 u32 timeout2; /* Added for non_paired situation */ 297 }; 298 299 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = { 300 { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 }, 301 { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET, 302 false, HDCP_2_2_CERT_TIMEOUT_MS, 0 }, 303 { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET, 304 false, 0, 0 }, 305 { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET, 306 false, 0, 0 }, 307 { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET, 308 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, 309 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS }, 310 { HDCP_2_2_AKE_SEND_PAIRING_INFO, 311 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true, 312 HDCP_2_2_PAIRING_TIMEOUT_MS, 0 }, 313 { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 }, 314 { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET, 315 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 }, 316 { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false, 317 0, 0 }, 318 { HDCP_2_2_REP_SEND_RECVID_LIST, 319 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true, 320 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 }, 321 { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false, 322 0, 0 }, 323 { HDCP_2_2_REP_STREAM_MANAGE, 324 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false, 325 0, 0 }, 326 { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET, 327 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 }, 328 /* local define to shovel this through the write_2_2 interface */ 329 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 330 { HDCP_2_2_ERRATA_DP_STREAM_TYPE, 331 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false, 332 0, 0 }, 333 }; 334 335 static int 336 intel_dp_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 337 u8 *rx_status) 338 { 339 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 340 ssize_t ret; 341 342 ret = drm_dp_dpcd_read(&dig_port->dp.aux, 343 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status, 344 HDCP_2_2_DP_RXSTATUS_LEN); 345 if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { 346 drm_dbg_kms(&i915->drm, 347 "Read bstatus from DP/AUX failed (%zd)\n", ret); 348 return ret >= 0 ? -EIO : ret; 349 } 350 351 return 0; 352 } 353 354 static 355 int hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 356 u8 msg_id, bool *msg_ready) 357 { 358 u8 rx_status; 359 int ret; 360 361 *msg_ready = false; 362 ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status); 363 if (ret < 0) 364 return ret; 365 366 switch (msg_id) { 367 case HDCP_2_2_AKE_SEND_HPRIME: 368 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status)) 369 *msg_ready = true; 370 break; 371 case HDCP_2_2_AKE_SEND_PAIRING_INFO: 372 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status)) 373 *msg_ready = true; 374 break; 375 case HDCP_2_2_REP_SEND_RECVID_LIST: 376 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) 377 *msg_ready = true; 378 break; 379 default: 380 DRM_ERROR("Unidentified msg_id: %d\n", msg_id); 381 return -EINVAL; 382 } 383 384 return 0; 385 } 386 387 static ssize_t 388 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 389 const struct hdcp2_dp_msg_data *hdcp2_msg_data) 390 { 391 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 392 struct intel_dp *dp = &dig_port->dp; 393 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; 394 u8 msg_id = hdcp2_msg_data->msg_id; 395 int ret, timeout; 396 bool msg_ready = false; 397 398 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired) 399 timeout = hdcp2_msg_data->timeout2; 400 else 401 timeout = hdcp2_msg_data->timeout; 402 403 /* 404 * There is no way to detect the CERT, LPRIME and STREAM_READY 405 * availability. So Wait for timeout and read the msg. 406 */ 407 if (!hdcp2_msg_data->msg_detectable) { 408 mdelay(timeout); 409 ret = 0; 410 } else { 411 /* 412 * As we want to check the msg availability at timeout, Ignoring 413 * the timeout at wait for CP_IRQ. 414 */ 415 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout); 416 ret = hdcp2_detect_msg_availability(dig_port, 417 msg_id, &msg_ready); 418 if (!msg_ready) 419 ret = -ETIMEDOUT; 420 } 421 422 if (ret) 423 drm_dbg_kms(&i915->drm, 424 "msg_id %d, ret %d, timeout(mSec): %d\n", 425 hdcp2_msg_data->msg_id, ret, timeout); 426 427 return ret; 428 } 429 430 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) 431 { 432 int i; 433 434 for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++) 435 if (hdcp2_dp_msg_data[i].msg_id == msg_id) 436 return &hdcp2_dp_msg_data[i]; 437 438 return NULL; 439 } 440 441 static 442 int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port, 443 void *buf, size_t size) 444 { 445 struct intel_dp *dp = &dig_port->dp; 446 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; 447 unsigned int offset; 448 u8 *byte = buf; 449 ssize_t ret, bytes_to_write, len; 450 const struct hdcp2_dp_msg_data *hdcp2_msg_data; 451 452 hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte); 453 if (!hdcp2_msg_data) 454 return -EINVAL; 455 456 offset = hdcp2_msg_data->offset; 457 458 /* No msg_id in DP HDCP2.2 msgs */ 459 bytes_to_write = size - 1; 460 byte++; 461 462 hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count); 463 464 while (bytes_to_write) { 465 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ? 466 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write; 467 468 ret = drm_dp_dpcd_write(&dig_port->dp.aux, 469 offset, (void *)byte, len); 470 if (ret < 0) 471 return ret; 472 473 bytes_to_write -= ret; 474 byte += ret; 475 offset += ret; 476 } 477 478 return size; 479 } 480 481 static 482 ssize_t get_receiver_id_list_size(struct intel_digital_port *dig_port) 483 { 484 u8 rx_info[HDCP_2_2_RXINFO_LEN]; 485 u32 dev_cnt; 486 ssize_t ret; 487 488 ret = drm_dp_dpcd_read(&dig_port->dp.aux, 489 DP_HDCP_2_2_REG_RXINFO_OFFSET, 490 (void *)rx_info, HDCP_2_2_RXINFO_LEN); 491 if (ret != HDCP_2_2_RXINFO_LEN) 492 return ret >= 0 ? -EIO : ret; 493 494 dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | 495 HDCP_2_2_DEV_COUNT_LO(rx_info[1])); 496 497 if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT) 498 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT; 499 500 ret = sizeof(struct hdcp2_rep_send_receiverid_list) - 501 HDCP_2_2_RECEIVER_IDS_MAX_LEN + 502 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN); 503 504 return ret; 505 } 506 507 static 508 int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port, 509 u8 msg_id, void *buf, size_t size) 510 { 511 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 512 unsigned int offset; 513 u8 *byte = buf; 514 ssize_t ret, bytes_to_recv, len; 515 const struct hdcp2_dp_msg_data *hdcp2_msg_data; 516 517 hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id); 518 if (!hdcp2_msg_data) 519 return -EINVAL; 520 offset = hdcp2_msg_data->offset; 521 522 ret = intel_dp_hdcp2_wait_for_msg(dig_port, hdcp2_msg_data); 523 if (ret < 0) 524 return ret; 525 526 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) { 527 ret = get_receiver_id_list_size(dig_port); 528 if (ret < 0) 529 return ret; 530 531 size = ret; 532 } 533 bytes_to_recv = size - 1; 534 535 /* DP adaptation msgs has no msg_id */ 536 byte++; 537 538 while (bytes_to_recv) { 539 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ? 540 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv; 541 542 ret = drm_dp_dpcd_read(&dig_port->dp.aux, offset, 543 (void *)byte, len); 544 if (ret < 0) { 545 drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n", 546 msg_id, ret); 547 return ret; 548 } 549 550 bytes_to_recv -= ret; 551 byte += ret; 552 offset += ret; 553 } 554 byte = buf; 555 *byte = msg_id; 556 557 return size; 558 } 559 560 static 561 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port, 562 bool is_repeater, u8 content_type) 563 { 564 int ret; 565 struct hdcp2_dp_errata_stream_type stream_type_msg; 566 567 if (is_repeater) 568 return 0; 569 570 /* 571 * Errata for DP: As Stream type is used for encryption, Receiver 572 * should be communicated with stream type for the decryption of the 573 * content. 574 * Repeater will be communicated with stream type as a part of it's 575 * auth later in time. 576 */ 577 stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE; 578 stream_type_msg.stream_type = content_type; 579 580 ret = intel_dp_hdcp2_write_msg(dig_port, &stream_type_msg, 581 sizeof(stream_type_msg)); 582 583 return ret < 0 ? ret : 0; 584 585 } 586 587 static 588 int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port, 589 struct intel_connector *connector) 590 { 591 u8 rx_status; 592 int ret; 593 594 ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status); 595 if (ret) 596 return ret; 597 598 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status)) 599 ret = HDCP_REAUTH_REQUEST; 600 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status)) 601 ret = HDCP_LINK_INTEGRITY_FAILURE; 602 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) 603 ret = HDCP_TOPOLOGY_CHANGE; 604 605 return ret; 606 } 607 608 static 609 int intel_dp_hdcp2_capable(struct intel_digital_port *dig_port, 610 bool *capable) 611 { 612 u8 rx_caps[3]; 613 int ret; 614 615 *capable = false; 616 ret = drm_dp_dpcd_read(&dig_port->dp.aux, 617 DP_HDCP_2_2_REG_RX_CAPS_OFFSET, 618 rx_caps, HDCP_2_2_RXCAPS_LEN); 619 if (ret != HDCP_2_2_RXCAPS_LEN) 620 return ret >= 0 ? -EIO : ret; 621 622 if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL && 623 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2])) 624 *capable = true; 625 626 return 0; 627 } 628 629 static const struct intel_hdcp_shim intel_dp_hdcp_shim = { 630 .write_an_aksv = intel_dp_hdcp_write_an_aksv, 631 .read_bksv = intel_dp_hdcp_read_bksv, 632 .read_bstatus = intel_dp_hdcp_read_bstatus, 633 .repeater_present = intel_dp_hdcp_repeater_present, 634 .read_ri_prime = intel_dp_hdcp_read_ri_prime, 635 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, 636 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, 637 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, 638 .toggle_signalling = intel_dp_hdcp_toggle_signalling, 639 .check_link = intel_dp_hdcp_check_link, 640 .hdcp_capable = intel_dp_hdcp_capable, 641 .write_2_2_msg = intel_dp_hdcp2_write_msg, 642 .read_2_2_msg = intel_dp_hdcp2_read_msg, 643 .config_stream_type = intel_dp_hdcp2_config_stream_type, 644 .check_2_2_link = intel_dp_hdcp2_check_link, 645 .hdcp_2_2_capable = intel_dp_hdcp2_capable, 646 .protocol = HDCP_PROTOCOL_DP, 647 }; 648 649 static int 650 intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector, 651 bool enable) 652 { 653 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 654 struct drm_i915_private *i915 = to_i915(connector->base.dev); 655 struct intel_hdcp *hdcp = &connector->hdcp; 656 int ret; 657 658 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 659 hdcp->stream_transcoder, enable, 660 TRANS_DDI_HDCP_SELECT); 661 if (ret) 662 drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n", 663 enable ? "Enable" : "Disable", ret); 664 return ret; 665 } 666 667 static int 668 intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector, 669 bool enable) 670 { 671 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 672 struct drm_i915_private *i915 = to_i915(connector->base.dev); 673 struct intel_hdcp *hdcp = &connector->hdcp; 674 enum port port = dig_port->base.port; 675 enum transcoder cpu_transcoder = hdcp->stream_transcoder; 676 u32 stream_enc_status; 677 int ret; 678 679 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable); 680 if (ret) 681 return ret; 682 683 stream_enc_status = transcoder_to_stream_enc_status(cpu_transcoder); 684 if (!stream_enc_status) 685 return -EINVAL; 686 687 /* Wait for encryption confirmation */ 688 if (intel_de_wait_for_register(i915, 689 HDCP_STATUS(i915, cpu_transcoder, port), 690 stream_enc_status, 691 enable ? stream_enc_status : 0, 692 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 693 drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n", 694 transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled"); 695 return -ETIMEDOUT; 696 } 697 698 return 0; 699 } 700 701 static bool intel_dp_mst_get_qses_status(struct intel_digital_port *dig_port, 702 struct intel_connector *connector) 703 { 704 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 705 struct drm_dp_query_stream_enc_status_ack_reply reply; 706 struct intel_dp *intel_dp = &dig_port->dp; 707 int ret; 708 709 ret = drm_dp_send_query_stream_enc_status(&intel_dp->mst_mgr, 710 connector->port, &reply); 711 if (ret) { 712 drm_dbg_kms(&i915->drm, 713 "[%s:%d] failed QSES ret=%d\n", 714 connector->base.name, connector->base.base.id, ret); 715 return false; 716 } 717 718 drm_dbg_kms(&i915->drm, "[%s:%d] QSES stream auth: %d stream enc: %d\n", 719 connector->base.name, connector->base.base.id, 720 reply.auth_completed, reply.encryption_enabled); 721 722 return reply.auth_completed && reply.encryption_enabled; 723 } 724 725 static int 726 intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector, 727 bool enable) 728 { 729 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 730 struct drm_i915_private *i915 = to_i915(connector->base.dev); 731 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 732 struct intel_hdcp *hdcp = &connector->hdcp; 733 enum transcoder cpu_transcoder = hdcp->stream_transcoder; 734 enum pipe pipe = (enum pipe)cpu_transcoder; 735 enum port port = dig_port->base.port; 736 int ret; 737 738 drm_WARN_ON(&i915->drm, enable && 739 !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port)) 740 & AUTH_STREAM_TYPE) != data->streams[0].stream_type); 741 742 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable); 743 if (ret) 744 return ret; 745 746 /* Wait for encryption confirmation */ 747 if (intel_de_wait_for_register(i915, 748 HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe), 749 STREAM_ENCRYPTION_STATUS, 750 enable ? STREAM_ENCRYPTION_STATUS : 0, 751 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 752 drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n", 753 transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled"); 754 return -ETIMEDOUT; 755 } 756 757 return 0; 758 } 759 760 /* 761 * DP v2.0 I.3.3 ignore the stream signature L' in QSES reply msg reply. 762 * I.3.5 MST source device may use a QSES msg to query downstream status 763 * for a particular stream. 764 */ 765 static 766 int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port, 767 struct intel_connector *connector) 768 { 769 struct intel_hdcp *hdcp = &connector->hdcp; 770 int ret; 771 772 /* 773 * We do need to do the Link Check only for the connector involved with 774 * HDCP port authentication and encryption. 775 * We can re-use the hdcp->is_repeater flag to know that the connector 776 * involved with HDCP port authentication and encryption. 777 */ 778 if (hdcp->is_repeater) { 779 ret = intel_dp_hdcp2_check_link(dig_port, connector); 780 if (ret) 781 return ret; 782 } 783 784 return intel_dp_mst_get_qses_status(dig_port, connector) ? 0 : -EINVAL; 785 } 786 787 static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = { 788 .write_an_aksv = intel_dp_hdcp_write_an_aksv, 789 .read_bksv = intel_dp_hdcp_read_bksv, 790 .read_bstatus = intel_dp_hdcp_read_bstatus, 791 .repeater_present = intel_dp_hdcp_repeater_present, 792 .read_ri_prime = intel_dp_hdcp_read_ri_prime, 793 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, 794 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, 795 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, 796 .toggle_signalling = intel_dp_hdcp_toggle_signalling, 797 .stream_encryption = intel_dp_mst_hdcp_stream_encryption, 798 .check_link = intel_dp_hdcp_check_link, 799 .hdcp_capable = intel_dp_hdcp_capable, 800 .write_2_2_msg = intel_dp_hdcp2_write_msg, 801 .read_2_2_msg = intel_dp_hdcp2_read_msg, 802 .config_stream_type = intel_dp_hdcp2_config_stream_type, 803 .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption, 804 .check_2_2_link = intel_dp_mst_hdcp2_check_link, 805 .hdcp_2_2_capable = intel_dp_hdcp2_capable, 806 .protocol = HDCP_PROTOCOL_DP, 807 }; 808 809 int intel_dp_init_hdcp(struct intel_digital_port *dig_port, 810 struct intel_connector *intel_connector) 811 { 812 struct drm_device *dev = intel_connector->base.dev; 813 struct drm_i915_private *dev_priv = to_i915(dev); 814 struct intel_encoder *intel_encoder = &dig_port->base; 815 enum port port = intel_encoder->port; 816 struct intel_dp *intel_dp = &dig_port->dp; 817 818 if (!is_hdcp_supported(dev_priv, port)) 819 return 0; 820 821 if (intel_connector->mst_port) 822 return intel_hdcp_init(intel_connector, dig_port, 823 &intel_dp_mst_hdcp_shim); 824 else if (!intel_dp_is_edp(intel_dp)) 825 return intel_hdcp_init(intel_connector, dig_port, 826 &intel_dp_hdcp_shim); 827 828 return 0; 829 } 830