1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright (C) 2020 Google, Inc. 4 * 5 * Authors: 6 * Sean Paul <seanpaul@chromium.org> 7 */ 8 9 #include <drm/display/drm_dp_helper.h> 10 #include <drm/display/drm_dp_mst_helper.h> 11 #include <drm/display/drm_hdcp_helper.h> 12 #include <drm/drm_print.h> 13 14 #include "intel_ddi.h" 15 #include "intel_de.h" 16 #include "intel_display_types.h" 17 #include "intel_dp.h" 18 #include "intel_dp_hdcp.h" 19 #include "intel_hdcp.h" 20 #include "intel_hdcp_regs.h" 21 22 static u32 transcoder_to_stream_enc_status(enum transcoder cpu_transcoder) 23 { 24 switch (cpu_transcoder) { 25 case TRANSCODER_A: 26 return HDCP_STATUS_STREAM_A_ENC; 27 case TRANSCODER_B: 28 return HDCP_STATUS_STREAM_B_ENC; 29 case TRANSCODER_C: 30 return HDCP_STATUS_STREAM_C_ENC; 31 case TRANSCODER_D: 32 return HDCP_STATUS_STREAM_D_ENC; 33 default: 34 return 0; 35 } 36 } 37 38 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout) 39 { 40 long ret; 41 42 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count)) 43 ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C, 44 msecs_to_jiffies(timeout)); 45 46 if (!ret) 47 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n"); 48 } 49 50 static 51 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 52 u8 *an) 53 { 54 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 55 u8 aksv[DRM_HDCP_KSV_LEN] = {}; 56 ssize_t dpcd_ret; 57 58 /* Output An first, that's easy */ 59 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN, 60 an, DRM_HDCP_AN_LEN); 61 if (dpcd_ret != DRM_HDCP_AN_LEN) { 62 drm_dbg_kms(&i915->drm, 63 "Failed to write An over DP/AUX (%zd)\n", 64 dpcd_ret); 65 return dpcd_ret >= 0 ? -EIO : dpcd_ret; 66 } 67 68 /* 69 * Since Aksv is Oh-So-Secret, we can't access it in software. So we 70 * send an empty buffer of the correct length through the DP helpers. On 71 * the other side, in the transfer hook, we'll generate a flag based on 72 * the destination address which will tickle the hardware to output the 73 * Aksv on our behalf after the header is sent. 74 */ 75 dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV, 76 aksv, DRM_HDCP_KSV_LEN); 77 if (dpcd_ret != DRM_HDCP_KSV_LEN) { 78 drm_dbg_kms(&i915->drm, 79 "Failed to write Aksv over DP/AUX (%zd)\n", 80 dpcd_ret); 81 return dpcd_ret >= 0 ? -EIO : dpcd_ret; 82 } 83 return 0; 84 } 85 86 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port, 87 u8 *bksv) 88 { 89 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 90 ssize_t ret; 91 92 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, 93 DRM_HDCP_KSV_LEN); 94 if (ret != DRM_HDCP_KSV_LEN) { 95 drm_dbg_kms(&i915->drm, 96 "Read Bksv from DP/AUX failed (%zd)\n", ret); 97 return ret >= 0 ? -EIO : ret; 98 } 99 return 0; 100 } 101 102 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port, 103 u8 *bstatus) 104 { 105 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 106 ssize_t ret; 107 108 /* 109 * For some reason the HDMI and DP HDCP specs call this register 110 * definition by different names. In the HDMI spec, it's called BSTATUS, 111 * but in DP it's called BINFO. 112 */ 113 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO, 114 bstatus, DRM_HDCP_BSTATUS_LEN); 115 if (ret != DRM_HDCP_BSTATUS_LEN) { 116 drm_dbg_kms(&i915->drm, 117 "Read bstatus from DP/AUX failed (%zd)\n", ret); 118 return ret >= 0 ? -EIO : ret; 119 } 120 return 0; 121 } 122 123 static 124 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *dig_port, 125 u8 *bcaps) 126 { 127 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 128 ssize_t ret; 129 130 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BCAPS, 131 bcaps, 1); 132 if (ret != 1) { 133 drm_dbg_kms(&i915->drm, 134 "Read bcaps from DP/AUX failed (%zd)\n", ret); 135 return ret >= 0 ? -EIO : ret; 136 } 137 138 return 0; 139 } 140 141 static 142 int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port, 143 bool *repeater_present) 144 { 145 ssize_t ret; 146 u8 bcaps; 147 148 ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps); 149 if (ret) 150 return ret; 151 152 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT; 153 return 0; 154 } 155 156 static 157 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 158 u8 *ri_prime) 159 { 160 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 161 ssize_t ret; 162 163 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, 164 ri_prime, DRM_HDCP_RI_LEN); 165 if (ret != DRM_HDCP_RI_LEN) { 166 drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n", 167 ret); 168 return ret >= 0 ? -EIO : ret; 169 } 170 return 0; 171 } 172 173 static 174 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 175 bool *ksv_ready) 176 { 177 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 178 ssize_t ret; 179 u8 bstatus; 180 181 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, 182 &bstatus, 1); 183 if (ret != 1) { 184 drm_dbg_kms(&i915->drm, 185 "Read bstatus from DP/AUX failed (%zd)\n", ret); 186 return ret >= 0 ? -EIO : ret; 187 } 188 *ksv_ready = bstatus & DP_BSTATUS_READY; 189 return 0; 190 } 191 192 static 193 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 194 int num_downstream, u8 *ksv_fifo) 195 { 196 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 197 ssize_t ret; 198 int i; 199 200 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */ 201 for (i = 0; i < num_downstream; i += 3) { 202 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN; 203 ret = drm_dp_dpcd_read(&dig_port->dp.aux, 204 DP_AUX_HDCP_KSV_FIFO, 205 ksv_fifo + i * DRM_HDCP_KSV_LEN, 206 len); 207 if (ret != len) { 208 drm_dbg_kms(&i915->drm, 209 "Read ksv[%d] from DP/AUX failed (%zd)\n", 210 i, ret); 211 return ret >= 0 ? -EIO : ret; 212 } 213 } 214 return 0; 215 } 216 217 static 218 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 219 int i, u32 *part) 220 { 221 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 222 ssize_t ret; 223 224 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 225 return -EINVAL; 226 227 ret = drm_dp_dpcd_read(&dig_port->dp.aux, 228 DP_AUX_HDCP_V_PRIME(i), part, 229 DRM_HDCP_V_PRIME_PART_LEN); 230 if (ret != DRM_HDCP_V_PRIME_PART_LEN) { 231 drm_dbg_kms(&i915->drm, 232 "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret); 233 return ret >= 0 ? -EIO : ret; 234 } 235 return 0; 236 } 237 238 static 239 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 240 enum transcoder cpu_transcoder, 241 bool enable) 242 { 243 /* Not used for single stream DisplayPort setups */ 244 return 0; 245 } 246 247 static 248 bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port, 249 struct intel_connector *connector) 250 { 251 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 252 ssize_t ret; 253 u8 bstatus; 254 255 ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, 256 &bstatus, 1); 257 if (ret != 1) { 258 drm_dbg_kms(&i915->drm, 259 "Read bstatus from DP/AUX failed (%zd)\n", ret); 260 return false; 261 } 262 263 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ)); 264 } 265 266 static 267 int intel_dp_hdcp_capable(struct intel_digital_port *dig_port, 268 bool *hdcp_capable) 269 { 270 ssize_t ret; 271 u8 bcaps; 272 273 ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps); 274 if (ret) 275 return ret; 276 277 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE; 278 return 0; 279 } 280 281 struct hdcp2_dp_errata_stream_type { 282 u8 msg_id; 283 u8 stream_type; 284 } __packed; 285 286 struct hdcp2_dp_msg_data { 287 u8 msg_id; 288 u32 offset; 289 bool msg_detectable; 290 u32 timeout; 291 u32 timeout2; /* Added for non_paired situation */ 292 /* Timeout to read entire msg */ 293 u32 msg_read_timeout; 294 }; 295 296 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = { 297 { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0, 0}, 298 { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET, 299 false, HDCP_2_2_CERT_TIMEOUT_MS, 0, HDCP_2_2_DP_CERT_READ_TIMEOUT_MS}, 300 { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET, 301 false, 0, 0, 0 }, 302 { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET, 303 false, 0, 0, 0 }, 304 { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET, 305 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, 306 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS, HDCP_2_2_DP_HPRIME_READ_TIMEOUT_MS}, 307 { HDCP_2_2_AKE_SEND_PAIRING_INFO, 308 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true, 309 HDCP_2_2_PAIRING_TIMEOUT_MS, 0, HDCP_2_2_DP_PAIRING_READ_TIMEOUT_MS }, 310 { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0, 0 }, 311 { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET, 312 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0, 0 }, 313 { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false, 314 0, 0, 0 }, 315 { HDCP_2_2_REP_SEND_RECVID_LIST, 316 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true, 317 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0, 0 }, 318 { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false, 319 0, 0, 0 }, 320 { HDCP_2_2_REP_STREAM_MANAGE, 321 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false, 322 0, 0, 0}, 323 { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET, 324 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0, 0 }, 325 /* local define to shovel this through the write_2_2 interface */ 326 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 327 { HDCP_2_2_ERRATA_DP_STREAM_TYPE, 328 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false, 329 0, 0 }, 330 }; 331 332 static int 333 intel_dp_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 334 u8 *rx_status) 335 { 336 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 337 ssize_t ret; 338 339 ret = drm_dp_dpcd_read(&dig_port->dp.aux, 340 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status, 341 HDCP_2_2_DP_RXSTATUS_LEN); 342 if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { 343 drm_dbg_kms(&i915->drm, 344 "Read bstatus from DP/AUX failed (%zd)\n", ret); 345 return ret >= 0 ? -EIO : ret; 346 } 347 348 return 0; 349 } 350 351 static 352 int hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 353 u8 msg_id, bool *msg_ready) 354 { 355 u8 rx_status; 356 int ret; 357 358 *msg_ready = false; 359 ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status); 360 if (ret < 0) 361 return ret; 362 363 switch (msg_id) { 364 case HDCP_2_2_AKE_SEND_HPRIME: 365 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status)) 366 *msg_ready = true; 367 break; 368 case HDCP_2_2_AKE_SEND_PAIRING_INFO: 369 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status)) 370 *msg_ready = true; 371 break; 372 case HDCP_2_2_REP_SEND_RECVID_LIST: 373 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) 374 *msg_ready = true; 375 break; 376 default: 377 DRM_ERROR("Unidentified msg_id: %d\n", msg_id); 378 return -EINVAL; 379 } 380 381 return 0; 382 } 383 384 static ssize_t 385 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 386 const struct hdcp2_dp_msg_data *hdcp2_msg_data) 387 { 388 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 389 struct intel_dp *dp = &dig_port->dp; 390 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; 391 u8 msg_id = hdcp2_msg_data->msg_id; 392 int ret, timeout; 393 bool msg_ready = false; 394 395 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired) 396 timeout = hdcp2_msg_data->timeout2; 397 else 398 timeout = hdcp2_msg_data->timeout; 399 400 /* 401 * There is no way to detect the CERT, LPRIME and STREAM_READY 402 * availability. So Wait for timeout and read the msg. 403 */ 404 if (!hdcp2_msg_data->msg_detectable) { 405 mdelay(timeout); 406 ret = 0; 407 } else { 408 /* 409 * As we want to check the msg availability at timeout, Ignoring 410 * the timeout at wait for CP_IRQ. 411 */ 412 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout); 413 ret = hdcp2_detect_msg_availability(dig_port, 414 msg_id, &msg_ready); 415 if (!msg_ready) 416 ret = -ETIMEDOUT; 417 } 418 419 if (ret) 420 drm_dbg_kms(&i915->drm, 421 "msg_id %d, ret %d, timeout(mSec): %d\n", 422 hdcp2_msg_data->msg_id, ret, timeout); 423 424 return ret; 425 } 426 427 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) 428 { 429 int i; 430 431 for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++) 432 if (hdcp2_dp_msg_data[i].msg_id == msg_id) 433 return &hdcp2_dp_msg_data[i]; 434 435 return NULL; 436 } 437 438 static 439 int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port, 440 void *buf, size_t size) 441 { 442 unsigned int offset; 443 u8 *byte = buf; 444 ssize_t ret, bytes_to_write, len; 445 const struct hdcp2_dp_msg_data *hdcp2_msg_data; 446 447 hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte); 448 if (!hdcp2_msg_data) 449 return -EINVAL; 450 451 offset = hdcp2_msg_data->offset; 452 453 /* No msg_id in DP HDCP2.2 msgs */ 454 bytes_to_write = size - 1; 455 byte++; 456 457 while (bytes_to_write) { 458 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ? 459 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write; 460 461 ret = drm_dp_dpcd_write(&dig_port->dp.aux, 462 offset, (void *)byte, len); 463 if (ret < 0) 464 return ret; 465 466 bytes_to_write -= ret; 467 byte += ret; 468 offset += ret; 469 } 470 471 return size; 472 } 473 474 static 475 ssize_t get_receiver_id_list_rx_info(struct intel_digital_port *dig_port, u32 *dev_cnt, u8 *byte) 476 { 477 ssize_t ret; 478 u8 *rx_info = byte; 479 480 ret = drm_dp_dpcd_read(&dig_port->dp.aux, 481 DP_HDCP_2_2_REG_RXINFO_OFFSET, 482 (void *)rx_info, HDCP_2_2_RXINFO_LEN); 483 if (ret != HDCP_2_2_RXINFO_LEN) 484 return ret >= 0 ? -EIO : ret; 485 486 *dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | 487 HDCP_2_2_DEV_COUNT_LO(rx_info[1])); 488 489 if (*dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT) 490 *dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT; 491 492 return ret; 493 } 494 495 static 496 int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port, 497 u8 msg_id, void *buf, size_t size) 498 { 499 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 500 struct intel_dp *dp = &dig_port->dp; 501 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; 502 unsigned int offset; 503 u8 *byte = buf; 504 ssize_t ret, bytes_to_recv, len; 505 const struct hdcp2_dp_msg_data *hdcp2_msg_data; 506 ktime_t msg_end = ktime_set(0, 0); 507 bool msg_expired; 508 u32 dev_cnt; 509 510 hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id); 511 if (!hdcp2_msg_data) 512 return -EINVAL; 513 offset = hdcp2_msg_data->offset; 514 515 ret = intel_dp_hdcp2_wait_for_msg(dig_port, hdcp2_msg_data); 516 if (ret < 0) 517 return ret; 518 519 hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count); 520 521 /* DP adaptation msgs has no msg_id */ 522 byte++; 523 524 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) { 525 ret = get_receiver_id_list_rx_info(dig_port, &dev_cnt, byte); 526 if (ret < 0) 527 return ret; 528 529 byte += ret; 530 size = sizeof(struct hdcp2_rep_send_receiverid_list) - 531 HDCP_2_2_RXINFO_LEN - HDCP_2_2_RECEIVER_IDS_MAX_LEN + 532 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN); 533 offset += HDCP_2_2_RXINFO_LEN; 534 } 535 536 bytes_to_recv = size - 1; 537 538 while (bytes_to_recv) { 539 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ? 540 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv; 541 542 /* Entire msg read timeout since initiate of msg read */ 543 if (bytes_to_recv == size - 1 && hdcp2_msg_data->msg_read_timeout > 0) 544 msg_end = ktime_add_ms(ktime_get_raw(), 545 hdcp2_msg_data->msg_read_timeout); 546 547 ret = drm_dp_dpcd_read(&dig_port->dp.aux, offset, 548 (void *)byte, len); 549 if (ret < 0) { 550 drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n", 551 msg_id, ret); 552 return ret; 553 } 554 555 bytes_to_recv -= ret; 556 byte += ret; 557 offset += ret; 558 } 559 560 if (hdcp2_msg_data->msg_read_timeout > 0) { 561 msg_expired = ktime_after(ktime_get_raw(), msg_end); 562 if (msg_expired) { 563 drm_dbg_kms(&i915->drm, "msg_id %d, entire msg read timeout(mSec): %d\n", 564 msg_id, hdcp2_msg_data->msg_read_timeout); 565 return -ETIMEDOUT; 566 } 567 } 568 569 byte = buf; 570 *byte = msg_id; 571 572 return size; 573 } 574 575 static 576 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port, 577 bool is_repeater, u8 content_type) 578 { 579 int ret; 580 struct hdcp2_dp_errata_stream_type stream_type_msg; 581 582 if (is_repeater) 583 return 0; 584 585 /* 586 * Errata for DP: As Stream type is used for encryption, Receiver 587 * should be communicated with stream type for the decryption of the 588 * content. 589 * Repeater will be communicated with stream type as a part of it's 590 * auth later in time. 591 */ 592 stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE; 593 stream_type_msg.stream_type = content_type; 594 595 ret = intel_dp_hdcp2_write_msg(dig_port, &stream_type_msg, 596 sizeof(stream_type_msg)); 597 598 return ret < 0 ? ret : 0; 599 600 } 601 602 static 603 int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port, 604 struct intel_connector *connector) 605 { 606 u8 rx_status; 607 int ret; 608 609 ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status); 610 if (ret) 611 return ret; 612 613 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status)) 614 ret = HDCP_REAUTH_REQUEST; 615 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status)) 616 ret = HDCP_LINK_INTEGRITY_FAILURE; 617 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) 618 ret = HDCP_TOPOLOGY_CHANGE; 619 620 return ret; 621 } 622 623 static 624 int intel_dp_hdcp2_capable(struct intel_digital_port *dig_port, 625 bool *capable) 626 { 627 u8 rx_caps[3]; 628 int ret; 629 630 *capable = false; 631 ret = drm_dp_dpcd_read(&dig_port->dp.aux, 632 DP_HDCP_2_2_REG_RX_CAPS_OFFSET, 633 rx_caps, HDCP_2_2_RXCAPS_LEN); 634 if (ret != HDCP_2_2_RXCAPS_LEN) 635 return ret >= 0 ? -EIO : ret; 636 637 if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL && 638 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2])) 639 *capable = true; 640 641 return 0; 642 } 643 644 static const struct intel_hdcp_shim intel_dp_hdcp_shim = { 645 .write_an_aksv = intel_dp_hdcp_write_an_aksv, 646 .read_bksv = intel_dp_hdcp_read_bksv, 647 .read_bstatus = intel_dp_hdcp_read_bstatus, 648 .repeater_present = intel_dp_hdcp_repeater_present, 649 .read_ri_prime = intel_dp_hdcp_read_ri_prime, 650 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, 651 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, 652 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, 653 .toggle_signalling = intel_dp_hdcp_toggle_signalling, 654 .check_link = intel_dp_hdcp_check_link, 655 .hdcp_capable = intel_dp_hdcp_capable, 656 .write_2_2_msg = intel_dp_hdcp2_write_msg, 657 .read_2_2_msg = intel_dp_hdcp2_read_msg, 658 .config_stream_type = intel_dp_hdcp2_config_stream_type, 659 .check_2_2_link = intel_dp_hdcp2_check_link, 660 .hdcp_2_2_capable = intel_dp_hdcp2_capable, 661 .protocol = HDCP_PROTOCOL_DP, 662 }; 663 664 static int 665 intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector, 666 bool enable) 667 { 668 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 669 struct drm_i915_private *i915 = to_i915(connector->base.dev); 670 struct intel_hdcp *hdcp = &connector->hdcp; 671 int ret; 672 673 ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 674 hdcp->stream_transcoder, enable, 675 TRANS_DDI_HDCP_SELECT); 676 if (ret) 677 drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n", 678 enable ? "Enable" : "Disable", ret); 679 return ret; 680 } 681 682 static int 683 intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector, 684 bool enable) 685 { 686 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 687 struct drm_i915_private *i915 = to_i915(connector->base.dev); 688 struct intel_hdcp *hdcp = &connector->hdcp; 689 enum port port = dig_port->base.port; 690 enum transcoder cpu_transcoder = hdcp->stream_transcoder; 691 u32 stream_enc_status; 692 int ret; 693 694 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable); 695 if (ret) 696 return ret; 697 698 stream_enc_status = transcoder_to_stream_enc_status(cpu_transcoder); 699 if (!stream_enc_status) 700 return -EINVAL; 701 702 /* Wait for encryption confirmation */ 703 if (intel_de_wait_for_register(i915, 704 HDCP_STATUS(i915, cpu_transcoder, port), 705 stream_enc_status, 706 enable ? stream_enc_status : 0, 707 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 708 drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n", 709 transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled"); 710 return -ETIMEDOUT; 711 } 712 713 return 0; 714 } 715 716 static int 717 intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector, 718 bool enable) 719 { 720 struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 721 struct drm_i915_private *i915 = to_i915(connector->base.dev); 722 struct hdcp_port_data *data = &dig_port->hdcp_port_data; 723 struct intel_hdcp *hdcp = &connector->hdcp; 724 enum transcoder cpu_transcoder = hdcp->stream_transcoder; 725 enum pipe pipe = (enum pipe)cpu_transcoder; 726 enum port port = dig_port->base.port; 727 int ret; 728 729 drm_WARN_ON(&i915->drm, enable && 730 !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port)) 731 & AUTH_STREAM_TYPE) != data->streams[0].stream_type); 732 733 ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable); 734 if (ret) 735 return ret; 736 737 /* Wait for encryption confirmation */ 738 if (intel_de_wait_for_register(i915, 739 HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe), 740 STREAM_ENCRYPTION_STATUS, 741 enable ? STREAM_ENCRYPTION_STATUS : 0, 742 HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 743 drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n", 744 transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled"); 745 return -ETIMEDOUT; 746 } 747 748 return 0; 749 } 750 751 static 752 int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port, 753 struct intel_connector *connector) 754 { 755 struct intel_hdcp *hdcp = &connector->hdcp; 756 int ret; 757 758 /* 759 * We do need to do the Link Check only for the connector involved with 760 * HDCP port authentication and encryption. 761 * We can re-use the hdcp->is_repeater flag to know that the connector 762 * involved with HDCP port authentication and encryption. 763 */ 764 if (hdcp->is_repeater) { 765 ret = intel_dp_hdcp2_check_link(dig_port, connector); 766 if (ret) 767 return ret; 768 } 769 770 return 0; 771 } 772 773 static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = { 774 .write_an_aksv = intel_dp_hdcp_write_an_aksv, 775 .read_bksv = intel_dp_hdcp_read_bksv, 776 .read_bstatus = intel_dp_hdcp_read_bstatus, 777 .repeater_present = intel_dp_hdcp_repeater_present, 778 .read_ri_prime = intel_dp_hdcp_read_ri_prime, 779 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, 780 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, 781 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, 782 .toggle_signalling = intel_dp_hdcp_toggle_signalling, 783 .stream_encryption = intel_dp_mst_hdcp_stream_encryption, 784 .check_link = intel_dp_hdcp_check_link, 785 .hdcp_capable = intel_dp_hdcp_capable, 786 .write_2_2_msg = intel_dp_hdcp2_write_msg, 787 .read_2_2_msg = intel_dp_hdcp2_read_msg, 788 .config_stream_type = intel_dp_hdcp2_config_stream_type, 789 .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption, 790 .check_2_2_link = intel_dp_mst_hdcp2_check_link, 791 .hdcp_2_2_capable = intel_dp_hdcp2_capable, 792 .protocol = HDCP_PROTOCOL_DP, 793 }; 794 795 int intel_dp_hdcp_init(struct intel_digital_port *dig_port, 796 struct intel_connector *intel_connector) 797 { 798 struct drm_device *dev = intel_connector->base.dev; 799 struct drm_i915_private *dev_priv = to_i915(dev); 800 struct intel_encoder *intel_encoder = &dig_port->base; 801 enum port port = intel_encoder->port; 802 struct intel_dp *intel_dp = &dig_port->dp; 803 804 if (!is_hdcp_supported(dev_priv, port)) 805 return 0; 806 807 if (intel_connector->mst_port) 808 return intel_hdcp_init(intel_connector, dig_port, 809 &intel_dp_mst_hdcp_shim); 810 else if (!intel_dp_is_edp(intel_dp)) 811 return intel_hdcp_init(intel_connector, dig_port, 812 &intel_dp_hdcp_shim); 813 814 return 0; 815 } 816