1 /* SPDX-License-Identifier: MIT */
2 /*
3  * Copyright (C) 2020 Google, Inc.
4  *
5  * Authors:
6  * Sean Paul <seanpaul@chromium.org>
7  */
8 
9 #include <drm/display/drm_dp_helper.h>
10 #include <drm/display/drm_dp_mst_helper.h>
11 #include <drm/display/drm_hdcp_helper.h>
12 #include <drm/drm_print.h>
13 
14 #include "i915_reg.h"
15 #include "intel_ddi.h"
16 #include "intel_de.h"
17 #include "intel_display_types.h"
18 #include "intel_dp.h"
19 #include "intel_dp_hdcp.h"
20 #include "intel_hdcp.h"
21 #include "intel_hdcp_regs.h"
22 
23 static u32 transcoder_to_stream_enc_status(enum transcoder cpu_transcoder)
24 {
25 	switch (cpu_transcoder) {
26 	case TRANSCODER_A:
27 		return HDCP_STATUS_STREAM_A_ENC;
28 	case TRANSCODER_B:
29 		return HDCP_STATUS_STREAM_B_ENC;
30 	case TRANSCODER_C:
31 		return HDCP_STATUS_STREAM_C_ENC;
32 	case TRANSCODER_D:
33 		return HDCP_STATUS_STREAM_D_ENC;
34 	default:
35 		return 0;
36 	}
37 }
38 
39 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout)
40 {
41 	long ret;
42 
43 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count))
44 	ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C,
45 					       msecs_to_jiffies(timeout));
46 
47 	if (!ret)
48 		DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n");
49 }
50 
51 static
52 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port,
53 				u8 *an)
54 {
55 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
56 	u8 aksv[DRM_HDCP_KSV_LEN] = {};
57 	ssize_t dpcd_ret;
58 
59 	/* Output An first, that's easy */
60 	dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN,
61 				     an, DRM_HDCP_AN_LEN);
62 	if (dpcd_ret != DRM_HDCP_AN_LEN) {
63 		drm_dbg_kms(&i915->drm,
64 			    "Failed to write An over DP/AUX (%zd)\n",
65 			    dpcd_ret);
66 		return dpcd_ret >= 0 ? -EIO : dpcd_ret;
67 	}
68 
69 	/*
70 	 * Since Aksv is Oh-So-Secret, we can't access it in software. So we
71 	 * send an empty buffer of the correct length through the DP helpers. On
72 	 * the other side, in the transfer hook, we'll generate a flag based on
73 	 * the destination address which will tickle the hardware to output the
74 	 * Aksv on our behalf after the header is sent.
75 	 */
76 	dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV,
77 				     aksv, DRM_HDCP_KSV_LEN);
78 	if (dpcd_ret != DRM_HDCP_KSV_LEN) {
79 		drm_dbg_kms(&i915->drm,
80 			    "Failed to write Aksv over DP/AUX (%zd)\n",
81 			    dpcd_ret);
82 		return dpcd_ret >= 0 ? -EIO : dpcd_ret;
83 	}
84 	return 0;
85 }
86 
87 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port,
88 				   u8 *bksv)
89 {
90 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
91 	ssize_t ret;
92 
93 	ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv,
94 			       DRM_HDCP_KSV_LEN);
95 	if (ret != DRM_HDCP_KSV_LEN) {
96 		drm_dbg_kms(&i915->drm,
97 			    "Read Bksv from DP/AUX failed (%zd)\n", ret);
98 		return ret >= 0 ? -EIO : ret;
99 	}
100 	return 0;
101 }
102 
103 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port,
104 				      u8 *bstatus)
105 {
106 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
107 	ssize_t ret;
108 
109 	/*
110 	 * For some reason the HDMI and DP HDCP specs call this register
111 	 * definition by different names. In the HDMI spec, it's called BSTATUS,
112 	 * but in DP it's called BINFO.
113 	 */
114 	ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO,
115 			       bstatus, DRM_HDCP_BSTATUS_LEN);
116 	if (ret != DRM_HDCP_BSTATUS_LEN) {
117 		drm_dbg_kms(&i915->drm,
118 			    "Read bstatus from DP/AUX failed (%zd)\n", ret);
119 		return ret >= 0 ? -EIO : ret;
120 	}
121 	return 0;
122 }
123 
124 static
125 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *dig_port,
126 			     u8 *bcaps)
127 {
128 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
129 	ssize_t ret;
130 
131 	ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BCAPS,
132 			       bcaps, 1);
133 	if (ret != 1) {
134 		drm_dbg_kms(&i915->drm,
135 			    "Read bcaps from DP/AUX failed (%zd)\n", ret);
136 		return ret >= 0 ? -EIO : ret;
137 	}
138 
139 	return 0;
140 }
141 
142 static
143 int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port,
144 				   bool *repeater_present)
145 {
146 	ssize_t ret;
147 	u8 bcaps;
148 
149 	ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps);
150 	if (ret)
151 		return ret;
152 
153 	*repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT;
154 	return 0;
155 }
156 
157 static
158 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port,
159 				u8 *ri_prime)
160 {
161 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
162 	ssize_t ret;
163 
164 	ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME,
165 			       ri_prime, DRM_HDCP_RI_LEN);
166 	if (ret != DRM_HDCP_RI_LEN) {
167 		drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n",
168 			    ret);
169 		return ret >= 0 ? -EIO : ret;
170 	}
171 	return 0;
172 }
173 
174 static
175 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port,
176 				 bool *ksv_ready)
177 {
178 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
179 	ssize_t ret;
180 	u8 bstatus;
181 
182 	ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
183 			       &bstatus, 1);
184 	if (ret != 1) {
185 		drm_dbg_kms(&i915->drm,
186 			    "Read bstatus from DP/AUX failed (%zd)\n", ret);
187 		return ret >= 0 ? -EIO : ret;
188 	}
189 	*ksv_ready = bstatus & DP_BSTATUS_READY;
190 	return 0;
191 }
192 
193 static
194 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port,
195 				int num_downstream, u8 *ksv_fifo)
196 {
197 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
198 	ssize_t ret;
199 	int i;
200 
201 	/* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */
202 	for (i = 0; i < num_downstream; i += 3) {
203 		size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN;
204 		ret = drm_dp_dpcd_read(&dig_port->dp.aux,
205 				       DP_AUX_HDCP_KSV_FIFO,
206 				       ksv_fifo + i * DRM_HDCP_KSV_LEN,
207 				       len);
208 		if (ret != len) {
209 			drm_dbg_kms(&i915->drm,
210 				    "Read ksv[%d] from DP/AUX failed (%zd)\n",
211 				    i, ret);
212 			return ret >= 0 ? -EIO : ret;
213 		}
214 	}
215 	return 0;
216 }
217 
218 static
219 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port,
220 				    int i, u32 *part)
221 {
222 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
223 	ssize_t ret;
224 
225 	if (i >= DRM_HDCP_V_PRIME_NUM_PARTS)
226 		return -EINVAL;
227 
228 	ret = drm_dp_dpcd_read(&dig_port->dp.aux,
229 			       DP_AUX_HDCP_V_PRIME(i), part,
230 			       DRM_HDCP_V_PRIME_PART_LEN);
231 	if (ret != DRM_HDCP_V_PRIME_PART_LEN) {
232 		drm_dbg_kms(&i915->drm,
233 			    "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret);
234 		return ret >= 0 ? -EIO : ret;
235 	}
236 	return 0;
237 }
238 
239 static
240 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *dig_port,
241 				    enum transcoder cpu_transcoder,
242 				    bool enable)
243 {
244 	/* Not used for single stream DisplayPort setups */
245 	return 0;
246 }
247 
248 static
249 bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port,
250 			      struct intel_connector *connector)
251 {
252 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
253 	ssize_t ret;
254 	u8 bstatus;
255 
256 	ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS,
257 			       &bstatus, 1);
258 	if (ret != 1) {
259 		drm_dbg_kms(&i915->drm,
260 			    "Read bstatus from DP/AUX failed (%zd)\n", ret);
261 		return false;
262 	}
263 
264 	return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ));
265 }
266 
267 static
268 int intel_dp_hdcp_capable(struct intel_digital_port *dig_port,
269 			  bool *hdcp_capable)
270 {
271 	ssize_t ret;
272 	u8 bcaps;
273 
274 	ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps);
275 	if (ret)
276 		return ret;
277 
278 	*hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE;
279 	return 0;
280 }
281 
282 struct hdcp2_dp_errata_stream_type {
283 	u8	msg_id;
284 	u8	stream_type;
285 } __packed;
286 
287 struct hdcp2_dp_msg_data {
288 	u8 msg_id;
289 	u32 offset;
290 	bool msg_detectable;
291 	u32 timeout;
292 	u32 timeout2; /* Added for non_paired situation */
293 	/* Timeout to read entire msg */
294 	u32 msg_read_timeout;
295 };
296 
297 static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = {
298 	{ HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0, 0},
299 	{ HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET,
300 	  false, HDCP_2_2_CERT_TIMEOUT_MS, 0, HDCP_2_2_DP_CERT_READ_TIMEOUT_MS},
301 	{ HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET,
302 	  false, 0, 0, 0 },
303 	{ HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET,
304 	  false, 0, 0, 0 },
305 	{ HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET,
306 	  true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS,
307 	  HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS, HDCP_2_2_DP_HPRIME_READ_TIMEOUT_MS},
308 	{ HDCP_2_2_AKE_SEND_PAIRING_INFO,
309 	  DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true,
310 	  HDCP_2_2_PAIRING_TIMEOUT_MS, 0, HDCP_2_2_DP_PAIRING_READ_TIMEOUT_MS },
311 	{ HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0, 0 },
312 	{ HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET,
313 	  false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0, 0 },
314 	{ HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false,
315 	  0, 0, 0 },
316 	{ HDCP_2_2_REP_SEND_RECVID_LIST,
317 	  DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true,
318 	  HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0, 0 },
319 	{ HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false,
320 	  0, 0, 0 },
321 	{ HDCP_2_2_REP_STREAM_MANAGE,
322 	  DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false,
323 	  0, 0, 0},
324 	{ HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET,
325 	  false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0, 0 },
326 /* local define to shovel this through the write_2_2 interface */
327 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE	50
328 	{ HDCP_2_2_ERRATA_DP_STREAM_TYPE,
329 	  DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false,
330 	  0, 0 },
331 };
332 
333 static int
334 intel_dp_hdcp2_read_rx_status(struct intel_digital_port *dig_port,
335 			      u8 *rx_status)
336 {
337 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
338 	ssize_t ret;
339 
340 	ret = drm_dp_dpcd_read(&dig_port->dp.aux,
341 			       DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status,
342 			       HDCP_2_2_DP_RXSTATUS_LEN);
343 	if (ret != HDCP_2_2_DP_RXSTATUS_LEN) {
344 		drm_dbg_kms(&i915->drm,
345 			    "Read bstatus from DP/AUX failed (%zd)\n", ret);
346 		return ret >= 0 ? -EIO : ret;
347 	}
348 
349 	return 0;
350 }
351 
352 static
353 int hdcp2_detect_msg_availability(struct intel_digital_port *dig_port,
354 				  u8 msg_id, bool *msg_ready)
355 {
356 	u8 rx_status;
357 	int ret;
358 
359 	*msg_ready = false;
360 	ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status);
361 	if (ret < 0)
362 		return ret;
363 
364 	switch (msg_id) {
365 	case HDCP_2_2_AKE_SEND_HPRIME:
366 		if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status))
367 			*msg_ready = true;
368 		break;
369 	case HDCP_2_2_AKE_SEND_PAIRING_INFO:
370 		if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status))
371 			*msg_ready = true;
372 		break;
373 	case HDCP_2_2_REP_SEND_RECVID_LIST:
374 		if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
375 			*msg_ready = true;
376 		break;
377 	default:
378 		DRM_ERROR("Unidentified msg_id: %d\n", msg_id);
379 		return -EINVAL;
380 	}
381 
382 	return 0;
383 }
384 
385 static ssize_t
386 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *dig_port,
387 			    const struct hdcp2_dp_msg_data *hdcp2_msg_data)
388 {
389 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
390 	struct intel_dp *dp = &dig_port->dp;
391 	struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
392 	u8 msg_id = hdcp2_msg_data->msg_id;
393 	int ret, timeout;
394 	bool msg_ready = false;
395 
396 	if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired)
397 		timeout = hdcp2_msg_data->timeout2;
398 	else
399 		timeout = hdcp2_msg_data->timeout;
400 
401 	/*
402 	 * There is no way to detect the CERT, LPRIME and STREAM_READY
403 	 * availability. So Wait for timeout and read the msg.
404 	 */
405 	if (!hdcp2_msg_data->msg_detectable) {
406 		mdelay(timeout);
407 		ret = 0;
408 	} else {
409 		/*
410 		 * As we want to check the msg availability at timeout, Ignoring
411 		 * the timeout at wait for CP_IRQ.
412 		 */
413 		intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout);
414 		ret = hdcp2_detect_msg_availability(dig_port,
415 						    msg_id, &msg_ready);
416 		if (!msg_ready)
417 			ret = -ETIMEDOUT;
418 	}
419 
420 	if (ret)
421 		drm_dbg_kms(&i915->drm,
422 			    "msg_id %d, ret %d, timeout(mSec): %d\n",
423 			    hdcp2_msg_data->msg_id, ret, timeout);
424 
425 	return ret;
426 }
427 
428 static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id)
429 {
430 	int i;
431 
432 	for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++)
433 		if (hdcp2_dp_msg_data[i].msg_id == msg_id)
434 			return &hdcp2_dp_msg_data[i];
435 
436 	return NULL;
437 }
438 
439 static
440 int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port,
441 			     void *buf, size_t size)
442 {
443 	unsigned int offset;
444 	u8 *byte = buf;
445 	ssize_t ret, bytes_to_write, len;
446 	const struct hdcp2_dp_msg_data *hdcp2_msg_data;
447 
448 	hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte);
449 	if (!hdcp2_msg_data)
450 		return -EINVAL;
451 
452 	offset = hdcp2_msg_data->offset;
453 
454 	/* No msg_id in DP HDCP2.2 msgs */
455 	bytes_to_write = size - 1;
456 	byte++;
457 
458 	while (bytes_to_write) {
459 		len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ?
460 				DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write;
461 
462 		ret = drm_dp_dpcd_write(&dig_port->dp.aux,
463 					offset, (void *)byte, len);
464 		if (ret < 0)
465 			return ret;
466 
467 		bytes_to_write -= ret;
468 		byte += ret;
469 		offset += ret;
470 	}
471 
472 	return size;
473 }
474 
475 static
476 ssize_t get_receiver_id_list_rx_info(struct intel_digital_port *dig_port, u32 *dev_cnt, u8 *byte)
477 {
478 	ssize_t ret;
479 	u8 *rx_info = byte;
480 
481 	ret = drm_dp_dpcd_read(&dig_port->dp.aux,
482 			       DP_HDCP_2_2_REG_RXINFO_OFFSET,
483 			       (void *)rx_info, HDCP_2_2_RXINFO_LEN);
484 	if (ret != HDCP_2_2_RXINFO_LEN)
485 		return ret >= 0 ? -EIO : ret;
486 
487 	*dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 |
488 		   HDCP_2_2_DEV_COUNT_LO(rx_info[1]));
489 
490 	if (*dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT)
491 		*dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT;
492 
493 	return ret;
494 }
495 
496 static
497 int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port,
498 			    u8 msg_id, void *buf, size_t size)
499 {
500 	struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
501 	struct intel_dp *dp = &dig_port->dp;
502 	struct intel_hdcp *hdcp = &dp->attached_connector->hdcp;
503 	unsigned int offset;
504 	u8 *byte = buf;
505 	ssize_t ret, bytes_to_recv, len;
506 	const struct hdcp2_dp_msg_data *hdcp2_msg_data;
507 	ktime_t msg_end = ktime_set(0, 0);
508 	bool msg_expired;
509 	u32 dev_cnt;
510 
511 	hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id);
512 	if (!hdcp2_msg_data)
513 		return -EINVAL;
514 	offset = hdcp2_msg_data->offset;
515 
516 	ret = intel_dp_hdcp2_wait_for_msg(dig_port, hdcp2_msg_data);
517 	if (ret < 0)
518 		return ret;
519 
520 	hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count);
521 
522 	/* DP adaptation msgs has no msg_id */
523 	byte++;
524 
525 	if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) {
526 		ret = get_receiver_id_list_rx_info(dig_port, &dev_cnt, byte);
527 		if (ret < 0)
528 			return ret;
529 
530 		byte += ret;
531 		size = sizeof(struct hdcp2_rep_send_receiverid_list) -
532 		HDCP_2_2_RXINFO_LEN - HDCP_2_2_RECEIVER_IDS_MAX_LEN +
533 		(dev_cnt * HDCP_2_2_RECEIVER_ID_LEN);
534 		offset += HDCP_2_2_RXINFO_LEN;
535 	}
536 
537 	bytes_to_recv = size - 1;
538 
539 	while (bytes_to_recv) {
540 		len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ?
541 		      DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv;
542 
543 		/* Entire msg read timeout since initiate of msg read */
544 		if (bytes_to_recv == size - 1 && hdcp2_msg_data->msg_read_timeout > 0)
545 			msg_end = ktime_add_ms(ktime_get_raw(),
546 					       hdcp2_msg_data->msg_read_timeout);
547 
548 		ret = drm_dp_dpcd_read(&dig_port->dp.aux, offset,
549 				       (void *)byte, len);
550 		if (ret < 0) {
551 			drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n",
552 				    msg_id, ret);
553 			return ret;
554 		}
555 
556 		bytes_to_recv -= ret;
557 		byte += ret;
558 		offset += ret;
559 	}
560 
561 	if (hdcp2_msg_data->msg_read_timeout > 0) {
562 		msg_expired = ktime_after(ktime_get_raw(), msg_end);
563 		if (msg_expired) {
564 			drm_dbg_kms(&i915->drm, "msg_id %d, entire msg read timeout(mSec): %d\n",
565 				    msg_id, hdcp2_msg_data->msg_read_timeout);
566 			return -ETIMEDOUT;
567 		}
568 	}
569 
570 	byte = buf;
571 	*byte = msg_id;
572 
573 	return size;
574 }
575 
576 static
577 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port,
578 				      bool is_repeater, u8 content_type)
579 {
580 	int ret;
581 	struct hdcp2_dp_errata_stream_type stream_type_msg;
582 
583 	if (is_repeater)
584 		return 0;
585 
586 	/*
587 	 * Errata for DP: As Stream type is used for encryption, Receiver
588 	 * should be communicated with stream type for the decryption of the
589 	 * content.
590 	 * Repeater will be communicated with stream type as a part of it's
591 	 * auth later in time.
592 	 */
593 	stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE;
594 	stream_type_msg.stream_type = content_type;
595 
596 	ret =  intel_dp_hdcp2_write_msg(dig_port, &stream_type_msg,
597 					sizeof(stream_type_msg));
598 
599 	return ret < 0 ? ret : 0;
600 
601 }
602 
603 static
604 int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port,
605 			      struct intel_connector *connector)
606 {
607 	u8 rx_status;
608 	int ret;
609 
610 	ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status);
611 	if (ret)
612 		return ret;
613 
614 	if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status))
615 		ret = HDCP_REAUTH_REQUEST;
616 	else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status))
617 		ret = HDCP_LINK_INTEGRITY_FAILURE;
618 	else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status))
619 		ret = HDCP_TOPOLOGY_CHANGE;
620 
621 	return ret;
622 }
623 
624 static
625 int intel_dp_hdcp2_capable(struct intel_digital_port *dig_port,
626 			   bool *capable)
627 {
628 	u8 rx_caps[3];
629 	int ret;
630 
631 	*capable = false;
632 	ret = drm_dp_dpcd_read(&dig_port->dp.aux,
633 			       DP_HDCP_2_2_REG_RX_CAPS_OFFSET,
634 			       rx_caps, HDCP_2_2_RXCAPS_LEN);
635 	if (ret != HDCP_2_2_RXCAPS_LEN)
636 		return ret >= 0 ? -EIO : ret;
637 
638 	if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL &&
639 	    HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2]))
640 		*capable = true;
641 
642 	return 0;
643 }
644 
645 static const struct intel_hdcp_shim intel_dp_hdcp_shim = {
646 	.write_an_aksv = intel_dp_hdcp_write_an_aksv,
647 	.read_bksv = intel_dp_hdcp_read_bksv,
648 	.read_bstatus = intel_dp_hdcp_read_bstatus,
649 	.repeater_present = intel_dp_hdcp_repeater_present,
650 	.read_ri_prime = intel_dp_hdcp_read_ri_prime,
651 	.read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
652 	.read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
653 	.read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
654 	.toggle_signalling = intel_dp_hdcp_toggle_signalling,
655 	.check_link = intel_dp_hdcp_check_link,
656 	.hdcp_capable = intel_dp_hdcp_capable,
657 	.write_2_2_msg = intel_dp_hdcp2_write_msg,
658 	.read_2_2_msg = intel_dp_hdcp2_read_msg,
659 	.config_stream_type = intel_dp_hdcp2_config_stream_type,
660 	.check_2_2_link = intel_dp_hdcp2_check_link,
661 	.hdcp_2_2_capable = intel_dp_hdcp2_capable,
662 	.protocol = HDCP_PROTOCOL_DP,
663 };
664 
665 static int
666 intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector,
667 				       bool enable)
668 {
669 	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
670 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
671 	struct intel_hdcp *hdcp = &connector->hdcp;
672 	int ret;
673 
674 	ret = intel_ddi_toggle_hdcp_bits(&dig_port->base,
675 					 hdcp->stream_transcoder, enable,
676 					 TRANS_DDI_HDCP_SELECT);
677 	if (ret)
678 		drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n",
679 			enable ? "Enable" : "Disable", ret);
680 	return ret;
681 }
682 
683 static int
684 intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector,
685 				    bool enable)
686 {
687 	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
688 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
689 	struct intel_hdcp *hdcp = &connector->hdcp;
690 	enum port port = dig_port->base.port;
691 	enum transcoder cpu_transcoder = hdcp->stream_transcoder;
692 	u32 stream_enc_status;
693 	int ret;
694 
695 	ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
696 	if (ret)
697 		return ret;
698 
699 	stream_enc_status =  transcoder_to_stream_enc_status(cpu_transcoder);
700 	if (!stream_enc_status)
701 		return -EINVAL;
702 
703 	/* Wait for encryption confirmation */
704 	if (intel_de_wait_for_register(i915,
705 				       HDCP_STATUS(i915, cpu_transcoder, port),
706 				       stream_enc_status,
707 				       enable ? stream_enc_status : 0,
708 				       HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
709 		drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
710 			transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
711 		return -ETIMEDOUT;
712 	}
713 
714 	return 0;
715 }
716 
717 static int
718 intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector,
719 				     bool enable)
720 {
721 	struct intel_digital_port *dig_port = intel_attached_dig_port(connector);
722 	struct drm_i915_private *i915 = to_i915(connector->base.dev);
723 	struct hdcp_port_data *data = &dig_port->hdcp_port_data;
724 	struct intel_hdcp *hdcp = &connector->hdcp;
725 	enum transcoder cpu_transcoder = hdcp->stream_transcoder;
726 	enum pipe pipe = (enum pipe)cpu_transcoder;
727 	enum port port = dig_port->base.port;
728 	int ret;
729 
730 	drm_WARN_ON(&i915->drm, enable &&
731 		    !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port))
732 		    & AUTH_STREAM_TYPE) != data->streams[0].stream_type);
733 
734 	ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable);
735 	if (ret)
736 		return ret;
737 
738 	/* Wait for encryption confirmation */
739 	if (intel_de_wait_for_register(i915,
740 				       HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe),
741 				       STREAM_ENCRYPTION_STATUS,
742 				       enable ? STREAM_ENCRYPTION_STATUS : 0,
743 				       HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) {
744 		drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n",
745 			transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled");
746 		return -ETIMEDOUT;
747 	}
748 
749 	return 0;
750 }
751 
752 static
753 int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port,
754 				  struct intel_connector *connector)
755 {
756 	struct intel_hdcp *hdcp = &connector->hdcp;
757 	int ret;
758 
759 	/*
760 	 * We do need to do the Link Check only for the connector involved with
761 	 * HDCP port authentication and encryption.
762 	 * We can re-use the hdcp->is_repeater flag to know that the connector
763 	 * involved with HDCP port authentication and encryption.
764 	 */
765 	if (hdcp->is_repeater) {
766 		ret = intel_dp_hdcp2_check_link(dig_port, connector);
767 		if (ret)
768 			return ret;
769 	}
770 
771 	return 0;
772 }
773 
774 static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = {
775 	.write_an_aksv = intel_dp_hdcp_write_an_aksv,
776 	.read_bksv = intel_dp_hdcp_read_bksv,
777 	.read_bstatus = intel_dp_hdcp_read_bstatus,
778 	.repeater_present = intel_dp_hdcp_repeater_present,
779 	.read_ri_prime = intel_dp_hdcp_read_ri_prime,
780 	.read_ksv_ready = intel_dp_hdcp_read_ksv_ready,
781 	.read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo,
782 	.read_v_prime_part = intel_dp_hdcp_read_v_prime_part,
783 	.toggle_signalling = intel_dp_hdcp_toggle_signalling,
784 	.stream_encryption = intel_dp_mst_hdcp_stream_encryption,
785 	.check_link = intel_dp_hdcp_check_link,
786 	.hdcp_capable = intel_dp_hdcp_capable,
787 	.write_2_2_msg = intel_dp_hdcp2_write_msg,
788 	.read_2_2_msg = intel_dp_hdcp2_read_msg,
789 	.config_stream_type = intel_dp_hdcp2_config_stream_type,
790 	.stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption,
791 	.check_2_2_link = intel_dp_mst_hdcp2_check_link,
792 	.hdcp_2_2_capable = intel_dp_hdcp2_capable,
793 	.protocol = HDCP_PROTOCOL_DP,
794 };
795 
796 int intel_dp_hdcp_init(struct intel_digital_port *dig_port,
797 		       struct intel_connector *intel_connector)
798 {
799 	struct drm_device *dev = intel_connector->base.dev;
800 	struct drm_i915_private *dev_priv = to_i915(dev);
801 	struct intel_encoder *intel_encoder = &dig_port->base;
802 	enum port port = intel_encoder->port;
803 	struct intel_dp *intel_dp = &dig_port->dp;
804 
805 	if (!is_hdcp_supported(dev_priv, port))
806 		return 0;
807 
808 	if (intel_connector->mst_port)
809 		return intel_hdcp_init(intel_connector, dig_port,
810 				       &intel_dp_mst_hdcp_shim);
811 	else if (!intel_dp_is_edp(intel_dp))
812 		return intel_hdcp_init(intel_connector, dig_port,
813 				       &intel_dp_hdcp_shim);
814 
815 	return 0;
816 }
817