1d079b7e4SSean Paul /* SPDX-License-Identifier: MIT */ 2d079b7e4SSean Paul /* 3d079b7e4SSean Paul * Copyright (C) 2020 Google, Inc. 4d079b7e4SSean Paul * 5d079b7e4SSean Paul * Authors: 6d079b7e4SSean Paul * Sean Paul <seanpaul@chromium.org> 7d079b7e4SSean Paul */ 8d079b7e4SSean Paul 9d079b7e4SSean Paul #include <drm/drm_dp_helper.h> 101fa01409SSean Paul #include <drm/drm_dp_mst_helper.h> 11d079b7e4SSean Paul #include <drm/drm_hdcp.h> 12d079b7e4SSean Paul #include <drm/drm_print.h> 13d079b7e4SSean Paul 14d079b7e4SSean Paul #include "intel_display_types.h" 151fa01409SSean Paul #include "intel_ddi.h" 16d079b7e4SSean Paul #include "intel_dp.h" 17d079b7e4SSean Paul #include "intel_hdcp.h" 18d079b7e4SSean Paul 191a67a168SAnshuman Gupta static unsigned int transcoder_to_stream_enc_status(enum transcoder cpu_transcoder) 201a67a168SAnshuman Gupta { 211a67a168SAnshuman Gupta u32 stream_enc_mask; 221a67a168SAnshuman Gupta 231a67a168SAnshuman Gupta switch (cpu_transcoder) { 241a67a168SAnshuman Gupta case TRANSCODER_A: 251a67a168SAnshuman Gupta stream_enc_mask = HDCP_STATUS_STREAM_A_ENC; 261a67a168SAnshuman Gupta break; 271a67a168SAnshuman Gupta case TRANSCODER_B: 281a67a168SAnshuman Gupta stream_enc_mask = HDCP_STATUS_STREAM_B_ENC; 291a67a168SAnshuman Gupta break; 301a67a168SAnshuman Gupta case TRANSCODER_C: 311a67a168SAnshuman Gupta stream_enc_mask = HDCP_STATUS_STREAM_C_ENC; 321a67a168SAnshuman Gupta break; 331a67a168SAnshuman Gupta case TRANSCODER_D: 341a67a168SAnshuman Gupta stream_enc_mask = HDCP_STATUS_STREAM_D_ENC; 351a67a168SAnshuman Gupta break; 361a67a168SAnshuman Gupta default: 371a67a168SAnshuman Gupta stream_enc_mask = 0; 381a67a168SAnshuman Gupta } 391a67a168SAnshuman Gupta 401a67a168SAnshuman Gupta return stream_enc_mask; 411a67a168SAnshuman Gupta } 421a67a168SAnshuman Gupta 43d079b7e4SSean Paul static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout) 44d079b7e4SSean Paul { 45d079b7e4SSean Paul long ret; 46d079b7e4SSean Paul 47d079b7e4SSean Paul #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count)) 48d079b7e4SSean Paul ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C, 49d079b7e4SSean Paul msecs_to_jiffies(timeout)); 50d079b7e4SSean Paul 51d079b7e4SSean Paul if (!ret) 52d079b7e4SSean Paul DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n"); 53d079b7e4SSean Paul } 54d079b7e4SSean Paul 55d079b7e4SSean Paul static 56d079b7e4SSean Paul int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *dig_port, 57d079b7e4SSean Paul u8 *an) 58d079b7e4SSean Paul { 59d079b7e4SSean Paul struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 60d079b7e4SSean Paul u8 aksv[DRM_HDCP_KSV_LEN] = {}; 61d079b7e4SSean Paul ssize_t dpcd_ret; 62d079b7e4SSean Paul 63d079b7e4SSean Paul /* Output An first, that's easy */ 64d079b7e4SSean Paul dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AN, 65d079b7e4SSean Paul an, DRM_HDCP_AN_LEN); 66d079b7e4SSean Paul if (dpcd_ret != DRM_HDCP_AN_LEN) { 67d079b7e4SSean Paul drm_dbg_kms(&i915->drm, 68d079b7e4SSean Paul "Failed to write An over DP/AUX (%zd)\n", 69d079b7e4SSean Paul dpcd_ret); 70d079b7e4SSean Paul return dpcd_ret >= 0 ? -EIO : dpcd_ret; 71d079b7e4SSean Paul } 72d079b7e4SSean Paul 73d079b7e4SSean Paul /* 74d079b7e4SSean Paul * Since Aksv is Oh-So-Secret, we can't access it in software. So we 75d079b7e4SSean Paul * send an empty buffer of the correct length through the DP helpers. On 76d079b7e4SSean Paul * the other side, in the transfer hook, we'll generate a flag based on 77d079b7e4SSean Paul * the destination address which will tickle the hardware to output the 78d079b7e4SSean Paul * Aksv on our behalf after the header is sent. 79d079b7e4SSean Paul */ 80d079b7e4SSean Paul dpcd_ret = drm_dp_dpcd_write(&dig_port->dp.aux, DP_AUX_HDCP_AKSV, 81d079b7e4SSean Paul aksv, DRM_HDCP_KSV_LEN); 82d079b7e4SSean Paul if (dpcd_ret != DRM_HDCP_KSV_LEN) { 83d079b7e4SSean Paul drm_dbg_kms(&i915->drm, 84d079b7e4SSean Paul "Failed to write Aksv over DP/AUX (%zd)\n", 85d079b7e4SSean Paul dpcd_ret); 86d079b7e4SSean Paul return dpcd_ret >= 0 ? -EIO : dpcd_ret; 87d079b7e4SSean Paul } 88d079b7e4SSean Paul return 0; 89d079b7e4SSean Paul } 90d079b7e4SSean Paul 91d079b7e4SSean Paul static int intel_dp_hdcp_read_bksv(struct intel_digital_port *dig_port, 92d079b7e4SSean Paul u8 *bksv) 93d079b7e4SSean Paul { 94d079b7e4SSean Paul struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 95d079b7e4SSean Paul ssize_t ret; 96d079b7e4SSean Paul 97d079b7e4SSean Paul ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, 98d079b7e4SSean Paul DRM_HDCP_KSV_LEN); 99d079b7e4SSean Paul if (ret != DRM_HDCP_KSV_LEN) { 100d079b7e4SSean Paul drm_dbg_kms(&i915->drm, 101d079b7e4SSean Paul "Read Bksv from DP/AUX failed (%zd)\n", ret); 102d079b7e4SSean Paul return ret >= 0 ? -EIO : ret; 103d079b7e4SSean Paul } 104d079b7e4SSean Paul return 0; 105d079b7e4SSean Paul } 106d079b7e4SSean Paul 107d079b7e4SSean Paul static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *dig_port, 108d079b7e4SSean Paul u8 *bstatus) 109d079b7e4SSean Paul { 110d079b7e4SSean Paul struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 111d079b7e4SSean Paul ssize_t ret; 112d079b7e4SSean Paul 113d079b7e4SSean Paul /* 114d079b7e4SSean Paul * For some reason the HDMI and DP HDCP specs call this register 115d079b7e4SSean Paul * definition by different names. In the HDMI spec, it's called BSTATUS, 116d079b7e4SSean Paul * but in DP it's called BINFO. 117d079b7e4SSean Paul */ 118d079b7e4SSean Paul ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BINFO, 119d079b7e4SSean Paul bstatus, DRM_HDCP_BSTATUS_LEN); 120d079b7e4SSean Paul if (ret != DRM_HDCP_BSTATUS_LEN) { 121d079b7e4SSean Paul drm_dbg_kms(&i915->drm, 122d079b7e4SSean Paul "Read bstatus from DP/AUX failed (%zd)\n", ret); 123d079b7e4SSean Paul return ret >= 0 ? -EIO : ret; 124d079b7e4SSean Paul } 125d079b7e4SSean Paul return 0; 126d079b7e4SSean Paul } 127d079b7e4SSean Paul 128d079b7e4SSean Paul static 129d079b7e4SSean Paul int intel_dp_hdcp_read_bcaps(struct intel_digital_port *dig_port, 130d079b7e4SSean Paul u8 *bcaps) 131d079b7e4SSean Paul { 132d079b7e4SSean Paul struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 133d079b7e4SSean Paul ssize_t ret; 134d079b7e4SSean Paul 135d079b7e4SSean Paul ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BCAPS, 136d079b7e4SSean Paul bcaps, 1); 137d079b7e4SSean Paul if (ret != 1) { 138d079b7e4SSean Paul drm_dbg_kms(&i915->drm, 139d079b7e4SSean Paul "Read bcaps from DP/AUX failed (%zd)\n", ret); 140d079b7e4SSean Paul return ret >= 0 ? -EIO : ret; 141d079b7e4SSean Paul } 142d079b7e4SSean Paul 143d079b7e4SSean Paul return 0; 144d079b7e4SSean Paul } 145d079b7e4SSean Paul 146d079b7e4SSean Paul static 147d079b7e4SSean Paul int intel_dp_hdcp_repeater_present(struct intel_digital_port *dig_port, 148d079b7e4SSean Paul bool *repeater_present) 149d079b7e4SSean Paul { 150d079b7e4SSean Paul ssize_t ret; 151d079b7e4SSean Paul u8 bcaps; 152d079b7e4SSean Paul 153d079b7e4SSean Paul ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps); 154d079b7e4SSean Paul if (ret) 155d079b7e4SSean Paul return ret; 156d079b7e4SSean Paul 157d079b7e4SSean Paul *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT; 158d079b7e4SSean Paul return 0; 159d079b7e4SSean Paul } 160d079b7e4SSean Paul 161d079b7e4SSean Paul static 162d079b7e4SSean Paul int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *dig_port, 163d079b7e4SSean Paul u8 *ri_prime) 164d079b7e4SSean Paul { 165d079b7e4SSean Paul struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 166d079b7e4SSean Paul ssize_t ret; 167d079b7e4SSean Paul 168d079b7e4SSean Paul ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, 169d079b7e4SSean Paul ri_prime, DRM_HDCP_RI_LEN); 170d079b7e4SSean Paul if (ret != DRM_HDCP_RI_LEN) { 171d079b7e4SSean Paul drm_dbg_kms(&i915->drm, "Read Ri' from DP/AUX failed (%zd)\n", 172d079b7e4SSean Paul ret); 173d079b7e4SSean Paul return ret >= 0 ? -EIO : ret; 174d079b7e4SSean Paul } 175d079b7e4SSean Paul return 0; 176d079b7e4SSean Paul } 177d079b7e4SSean Paul 178d079b7e4SSean Paul static 179d079b7e4SSean Paul int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *dig_port, 180d079b7e4SSean Paul bool *ksv_ready) 181d079b7e4SSean Paul { 182d079b7e4SSean Paul struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 183d079b7e4SSean Paul ssize_t ret; 184d079b7e4SSean Paul u8 bstatus; 185d079b7e4SSean Paul 186d079b7e4SSean Paul ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, 187d079b7e4SSean Paul &bstatus, 1); 188d079b7e4SSean Paul if (ret != 1) { 189d079b7e4SSean Paul drm_dbg_kms(&i915->drm, 190d079b7e4SSean Paul "Read bstatus from DP/AUX failed (%zd)\n", ret); 191d079b7e4SSean Paul return ret >= 0 ? -EIO : ret; 192d079b7e4SSean Paul } 193d079b7e4SSean Paul *ksv_ready = bstatus & DP_BSTATUS_READY; 194d079b7e4SSean Paul return 0; 195d079b7e4SSean Paul } 196d079b7e4SSean Paul 197d079b7e4SSean Paul static 198d079b7e4SSean Paul int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *dig_port, 199d079b7e4SSean Paul int num_downstream, u8 *ksv_fifo) 200d079b7e4SSean Paul { 201d079b7e4SSean Paul struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 202d079b7e4SSean Paul ssize_t ret; 203d079b7e4SSean Paul int i; 204d079b7e4SSean Paul 205d079b7e4SSean Paul /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */ 206d079b7e4SSean Paul for (i = 0; i < num_downstream; i += 3) { 207d079b7e4SSean Paul size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN; 208d079b7e4SSean Paul ret = drm_dp_dpcd_read(&dig_port->dp.aux, 209d079b7e4SSean Paul DP_AUX_HDCP_KSV_FIFO, 210d079b7e4SSean Paul ksv_fifo + i * DRM_HDCP_KSV_LEN, 211d079b7e4SSean Paul len); 212d079b7e4SSean Paul if (ret != len) { 213d079b7e4SSean Paul drm_dbg_kms(&i915->drm, 214d079b7e4SSean Paul "Read ksv[%d] from DP/AUX failed (%zd)\n", 215d079b7e4SSean Paul i, ret); 216d079b7e4SSean Paul return ret >= 0 ? -EIO : ret; 217d079b7e4SSean Paul } 218d079b7e4SSean Paul } 219d079b7e4SSean Paul return 0; 220d079b7e4SSean Paul } 221d079b7e4SSean Paul 222d079b7e4SSean Paul static 223d079b7e4SSean Paul int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *dig_port, 224d079b7e4SSean Paul int i, u32 *part) 225d079b7e4SSean Paul { 226d079b7e4SSean Paul struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 227d079b7e4SSean Paul ssize_t ret; 228d079b7e4SSean Paul 229d079b7e4SSean Paul if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 230d079b7e4SSean Paul return -EINVAL; 231d079b7e4SSean Paul 232d079b7e4SSean Paul ret = drm_dp_dpcd_read(&dig_port->dp.aux, 233d079b7e4SSean Paul DP_AUX_HDCP_V_PRIME(i), part, 234d079b7e4SSean Paul DRM_HDCP_V_PRIME_PART_LEN); 235d079b7e4SSean Paul if (ret != DRM_HDCP_V_PRIME_PART_LEN) { 236d079b7e4SSean Paul drm_dbg_kms(&i915->drm, 237d079b7e4SSean Paul "Read v'[%d] from DP/AUX failed (%zd)\n", i, ret); 238d079b7e4SSean Paul return ret >= 0 ? -EIO : ret; 239d079b7e4SSean Paul } 240d079b7e4SSean Paul return 0; 241d079b7e4SSean Paul } 242d079b7e4SSean Paul 243d079b7e4SSean Paul static 244d079b7e4SSean Paul int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *dig_port, 245d079b7e4SSean Paul enum transcoder cpu_transcoder, 246d079b7e4SSean Paul bool enable) 247d079b7e4SSean Paul { 248d079b7e4SSean Paul /* Not used for single stream DisplayPort setups */ 249d079b7e4SSean Paul return 0; 250d079b7e4SSean Paul } 251d079b7e4SSean Paul 252d079b7e4SSean Paul static 253038bac89SSean Paul bool intel_dp_hdcp_check_link(struct intel_digital_port *dig_port, 254038bac89SSean Paul struct intel_connector *connector) 255d079b7e4SSean Paul { 256d079b7e4SSean Paul struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 257d079b7e4SSean Paul ssize_t ret; 258d079b7e4SSean Paul u8 bstatus; 259d079b7e4SSean Paul 260d079b7e4SSean Paul ret = drm_dp_dpcd_read(&dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, 261d079b7e4SSean Paul &bstatus, 1); 262d079b7e4SSean Paul if (ret != 1) { 263d079b7e4SSean Paul drm_dbg_kms(&i915->drm, 264d079b7e4SSean Paul "Read bstatus from DP/AUX failed (%zd)\n", ret); 265d079b7e4SSean Paul return false; 266d079b7e4SSean Paul } 267d079b7e4SSean Paul 268d079b7e4SSean Paul return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ)); 269d079b7e4SSean Paul } 270d079b7e4SSean Paul 271d079b7e4SSean Paul static 272d079b7e4SSean Paul int intel_dp_hdcp_capable(struct intel_digital_port *dig_port, 273d079b7e4SSean Paul bool *hdcp_capable) 274d079b7e4SSean Paul { 275d079b7e4SSean Paul ssize_t ret; 276d079b7e4SSean Paul u8 bcaps; 277d079b7e4SSean Paul 278d079b7e4SSean Paul ret = intel_dp_hdcp_read_bcaps(dig_port, &bcaps); 279d079b7e4SSean Paul if (ret) 280d079b7e4SSean Paul return ret; 281d079b7e4SSean Paul 282d079b7e4SSean Paul *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE; 283d079b7e4SSean Paul return 0; 284d079b7e4SSean Paul } 285d079b7e4SSean Paul 286d079b7e4SSean Paul struct hdcp2_dp_errata_stream_type { 287d079b7e4SSean Paul u8 msg_id; 288d079b7e4SSean Paul u8 stream_type; 289d079b7e4SSean Paul } __packed; 290d079b7e4SSean Paul 291d079b7e4SSean Paul struct hdcp2_dp_msg_data { 292d079b7e4SSean Paul u8 msg_id; 293d079b7e4SSean Paul u32 offset; 294d079b7e4SSean Paul bool msg_detectable; 295d079b7e4SSean Paul u32 timeout; 296d079b7e4SSean Paul u32 timeout2; /* Added for non_paired situation */ 297d079b7e4SSean Paul }; 298d079b7e4SSean Paul 299d079b7e4SSean Paul static const struct hdcp2_dp_msg_data hdcp2_dp_msg_data[] = { 300d079b7e4SSean Paul { HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0 }, 301d079b7e4SSean Paul { HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET, 302d079b7e4SSean Paul false, HDCP_2_2_CERT_TIMEOUT_MS, 0 }, 303d079b7e4SSean Paul { HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET, 304d079b7e4SSean Paul false, 0, 0 }, 305d079b7e4SSean Paul { HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET, 306d079b7e4SSean Paul false, 0, 0 }, 307d079b7e4SSean Paul { HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET, 308d079b7e4SSean Paul true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, 309d079b7e4SSean Paul HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS }, 310d079b7e4SSean Paul { HDCP_2_2_AKE_SEND_PAIRING_INFO, 311d079b7e4SSean Paul DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true, 312d079b7e4SSean Paul HDCP_2_2_PAIRING_TIMEOUT_MS, 0 }, 313d079b7e4SSean Paul { HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0 }, 314d079b7e4SSean Paul { HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET, 315d079b7e4SSean Paul false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0 }, 316d079b7e4SSean Paul { HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false, 317d079b7e4SSean Paul 0, 0 }, 318d079b7e4SSean Paul { HDCP_2_2_REP_SEND_RECVID_LIST, 319d079b7e4SSean Paul DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true, 320d079b7e4SSean Paul HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0 }, 321d079b7e4SSean Paul { HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false, 322d079b7e4SSean Paul 0, 0 }, 323d079b7e4SSean Paul { HDCP_2_2_REP_STREAM_MANAGE, 324d079b7e4SSean Paul DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false, 325d079b7e4SSean Paul 0, 0 }, 326d079b7e4SSean Paul { HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET, 327d079b7e4SSean Paul false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0 }, 328d079b7e4SSean Paul /* local define to shovel this through the write_2_2 interface */ 329d079b7e4SSean Paul #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 330d079b7e4SSean Paul { HDCP_2_2_ERRATA_DP_STREAM_TYPE, 331d079b7e4SSean Paul DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false, 332d079b7e4SSean Paul 0, 0 }, 333d079b7e4SSean Paul }; 334d079b7e4SSean Paul 335d079b7e4SSean Paul static int 336d079b7e4SSean Paul intel_dp_hdcp2_read_rx_status(struct intel_digital_port *dig_port, 337d079b7e4SSean Paul u8 *rx_status) 338d079b7e4SSean Paul { 339d079b7e4SSean Paul struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 340d079b7e4SSean Paul ssize_t ret; 341d079b7e4SSean Paul 342d079b7e4SSean Paul ret = drm_dp_dpcd_read(&dig_port->dp.aux, 343d079b7e4SSean Paul DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status, 344d079b7e4SSean Paul HDCP_2_2_DP_RXSTATUS_LEN); 345d079b7e4SSean Paul if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { 346d079b7e4SSean Paul drm_dbg_kms(&i915->drm, 347d079b7e4SSean Paul "Read bstatus from DP/AUX failed (%zd)\n", ret); 348d079b7e4SSean Paul return ret >= 0 ? -EIO : ret; 349d079b7e4SSean Paul } 350d079b7e4SSean Paul 351d079b7e4SSean Paul return 0; 352d079b7e4SSean Paul } 353d079b7e4SSean Paul 354d079b7e4SSean Paul static 355d079b7e4SSean Paul int hdcp2_detect_msg_availability(struct intel_digital_port *dig_port, 356d079b7e4SSean Paul u8 msg_id, bool *msg_ready) 357d079b7e4SSean Paul { 358d079b7e4SSean Paul u8 rx_status; 359d079b7e4SSean Paul int ret; 360d079b7e4SSean Paul 361d079b7e4SSean Paul *msg_ready = false; 362d079b7e4SSean Paul ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status); 363d079b7e4SSean Paul if (ret < 0) 364d079b7e4SSean Paul return ret; 365d079b7e4SSean Paul 366d079b7e4SSean Paul switch (msg_id) { 367d079b7e4SSean Paul case HDCP_2_2_AKE_SEND_HPRIME: 368d079b7e4SSean Paul if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status)) 369d079b7e4SSean Paul *msg_ready = true; 370d079b7e4SSean Paul break; 371d079b7e4SSean Paul case HDCP_2_2_AKE_SEND_PAIRING_INFO: 372d079b7e4SSean Paul if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status)) 373d079b7e4SSean Paul *msg_ready = true; 374d079b7e4SSean Paul break; 375d079b7e4SSean Paul case HDCP_2_2_REP_SEND_RECVID_LIST: 376d079b7e4SSean Paul if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) 377d079b7e4SSean Paul *msg_ready = true; 378d079b7e4SSean Paul break; 379d079b7e4SSean Paul default: 380d079b7e4SSean Paul DRM_ERROR("Unidentified msg_id: %d\n", msg_id); 381d079b7e4SSean Paul return -EINVAL; 382d079b7e4SSean Paul } 383d079b7e4SSean Paul 384d079b7e4SSean Paul return 0; 385d079b7e4SSean Paul } 386d079b7e4SSean Paul 387d079b7e4SSean Paul static ssize_t 388d079b7e4SSean Paul intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *dig_port, 389d079b7e4SSean Paul const struct hdcp2_dp_msg_data *hdcp2_msg_data) 390d079b7e4SSean Paul { 391d079b7e4SSean Paul struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 392d079b7e4SSean Paul struct intel_dp *dp = &dig_port->dp; 393d079b7e4SSean Paul struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; 394d079b7e4SSean Paul u8 msg_id = hdcp2_msg_data->msg_id; 395d079b7e4SSean Paul int ret, timeout; 396d079b7e4SSean Paul bool msg_ready = false; 397d079b7e4SSean Paul 398d079b7e4SSean Paul if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired) 399d079b7e4SSean Paul timeout = hdcp2_msg_data->timeout2; 400d079b7e4SSean Paul else 401d079b7e4SSean Paul timeout = hdcp2_msg_data->timeout; 402d079b7e4SSean Paul 403d079b7e4SSean Paul /* 404d079b7e4SSean Paul * There is no way to detect the CERT, LPRIME and STREAM_READY 405d079b7e4SSean Paul * availability. So Wait for timeout and read the msg. 406d079b7e4SSean Paul */ 407d079b7e4SSean Paul if (!hdcp2_msg_data->msg_detectable) { 408d079b7e4SSean Paul mdelay(timeout); 409d079b7e4SSean Paul ret = 0; 410d079b7e4SSean Paul } else { 411d079b7e4SSean Paul /* 412d079b7e4SSean Paul * As we want to check the msg availability at timeout, Ignoring 413d079b7e4SSean Paul * the timeout at wait for CP_IRQ. 414d079b7e4SSean Paul */ 415d079b7e4SSean Paul intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout); 416d079b7e4SSean Paul ret = hdcp2_detect_msg_availability(dig_port, 417d079b7e4SSean Paul msg_id, &msg_ready); 418d079b7e4SSean Paul if (!msg_ready) 419d079b7e4SSean Paul ret = -ETIMEDOUT; 420d079b7e4SSean Paul } 421d079b7e4SSean Paul 422d079b7e4SSean Paul if (ret) 423d079b7e4SSean Paul drm_dbg_kms(&i915->drm, 424d079b7e4SSean Paul "msg_id %d, ret %d, timeout(mSec): %d\n", 425d079b7e4SSean Paul hdcp2_msg_data->msg_id, ret, timeout); 426d079b7e4SSean Paul 427d079b7e4SSean Paul return ret; 428d079b7e4SSean Paul } 429d079b7e4SSean Paul 430d079b7e4SSean Paul static const struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) 431d079b7e4SSean Paul { 432d079b7e4SSean Paul int i; 433d079b7e4SSean Paul 434d079b7e4SSean Paul for (i = 0; i < ARRAY_SIZE(hdcp2_dp_msg_data); i++) 435d079b7e4SSean Paul if (hdcp2_dp_msg_data[i].msg_id == msg_id) 436d079b7e4SSean Paul return &hdcp2_dp_msg_data[i]; 437d079b7e4SSean Paul 438d079b7e4SSean Paul return NULL; 439d079b7e4SSean Paul } 440d079b7e4SSean Paul 441d079b7e4SSean Paul static 442d079b7e4SSean Paul int intel_dp_hdcp2_write_msg(struct intel_digital_port *dig_port, 443d079b7e4SSean Paul void *buf, size_t size) 444d079b7e4SSean Paul { 445d079b7e4SSean Paul struct intel_dp *dp = &dig_port->dp; 446d079b7e4SSean Paul struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; 447d079b7e4SSean Paul unsigned int offset; 448d079b7e4SSean Paul u8 *byte = buf; 449d079b7e4SSean Paul ssize_t ret, bytes_to_write, len; 450d079b7e4SSean Paul const struct hdcp2_dp_msg_data *hdcp2_msg_data; 451d079b7e4SSean Paul 452d079b7e4SSean Paul hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte); 453d079b7e4SSean Paul if (!hdcp2_msg_data) 454d079b7e4SSean Paul return -EINVAL; 455d079b7e4SSean Paul 456d079b7e4SSean Paul offset = hdcp2_msg_data->offset; 457d079b7e4SSean Paul 458d079b7e4SSean Paul /* No msg_id in DP HDCP2.2 msgs */ 459d079b7e4SSean Paul bytes_to_write = size - 1; 460d079b7e4SSean Paul byte++; 461d079b7e4SSean Paul 462d079b7e4SSean Paul hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count); 463d079b7e4SSean Paul 464d079b7e4SSean Paul while (bytes_to_write) { 465d079b7e4SSean Paul len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ? 466d079b7e4SSean Paul DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write; 467d079b7e4SSean Paul 468d079b7e4SSean Paul ret = drm_dp_dpcd_write(&dig_port->dp.aux, 469d079b7e4SSean Paul offset, (void *)byte, len); 470d079b7e4SSean Paul if (ret < 0) 471d079b7e4SSean Paul return ret; 472d079b7e4SSean Paul 473d079b7e4SSean Paul bytes_to_write -= ret; 474d079b7e4SSean Paul byte += ret; 475d079b7e4SSean Paul offset += ret; 476d079b7e4SSean Paul } 477d079b7e4SSean Paul 478d079b7e4SSean Paul return size; 479d079b7e4SSean Paul } 480d079b7e4SSean Paul 481d079b7e4SSean Paul static 482d079b7e4SSean Paul ssize_t get_receiver_id_list_size(struct intel_digital_port *dig_port) 483d079b7e4SSean Paul { 484d079b7e4SSean Paul u8 rx_info[HDCP_2_2_RXINFO_LEN]; 485d079b7e4SSean Paul u32 dev_cnt; 486d079b7e4SSean Paul ssize_t ret; 487d079b7e4SSean Paul 488d079b7e4SSean Paul ret = drm_dp_dpcd_read(&dig_port->dp.aux, 489d079b7e4SSean Paul DP_HDCP_2_2_REG_RXINFO_OFFSET, 490d079b7e4SSean Paul (void *)rx_info, HDCP_2_2_RXINFO_LEN); 491d079b7e4SSean Paul if (ret != HDCP_2_2_RXINFO_LEN) 492d079b7e4SSean Paul return ret >= 0 ? -EIO : ret; 493d079b7e4SSean Paul 494d079b7e4SSean Paul dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | 495d079b7e4SSean Paul HDCP_2_2_DEV_COUNT_LO(rx_info[1])); 496d079b7e4SSean Paul 497d079b7e4SSean Paul if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT) 498d079b7e4SSean Paul dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT; 499d079b7e4SSean Paul 500d079b7e4SSean Paul ret = sizeof(struct hdcp2_rep_send_receiverid_list) - 501d079b7e4SSean Paul HDCP_2_2_RECEIVER_IDS_MAX_LEN + 502d079b7e4SSean Paul (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN); 503d079b7e4SSean Paul 504d079b7e4SSean Paul return ret; 505d079b7e4SSean Paul } 506d079b7e4SSean Paul 507d079b7e4SSean Paul static 508d079b7e4SSean Paul int intel_dp_hdcp2_read_msg(struct intel_digital_port *dig_port, 509d079b7e4SSean Paul u8 msg_id, void *buf, size_t size) 510d079b7e4SSean Paul { 511d079b7e4SSean Paul struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 512d079b7e4SSean Paul unsigned int offset; 513d079b7e4SSean Paul u8 *byte = buf; 514d079b7e4SSean Paul ssize_t ret, bytes_to_recv, len; 515d079b7e4SSean Paul const struct hdcp2_dp_msg_data *hdcp2_msg_data; 516d079b7e4SSean Paul 517d079b7e4SSean Paul hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id); 518d079b7e4SSean Paul if (!hdcp2_msg_data) 519d079b7e4SSean Paul return -EINVAL; 520d079b7e4SSean Paul offset = hdcp2_msg_data->offset; 521d079b7e4SSean Paul 522d079b7e4SSean Paul ret = intel_dp_hdcp2_wait_for_msg(dig_port, hdcp2_msg_data); 523d079b7e4SSean Paul if (ret < 0) 524d079b7e4SSean Paul return ret; 525d079b7e4SSean Paul 526d079b7e4SSean Paul if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) { 527d079b7e4SSean Paul ret = get_receiver_id_list_size(dig_port); 528d079b7e4SSean Paul if (ret < 0) 529d079b7e4SSean Paul return ret; 530d079b7e4SSean Paul 531d079b7e4SSean Paul size = ret; 532d079b7e4SSean Paul } 533d079b7e4SSean Paul bytes_to_recv = size - 1; 534d079b7e4SSean Paul 535d079b7e4SSean Paul /* DP adaptation msgs has no msg_id */ 536d079b7e4SSean Paul byte++; 537d079b7e4SSean Paul 538d079b7e4SSean Paul while (bytes_to_recv) { 539d079b7e4SSean Paul len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ? 540d079b7e4SSean Paul DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv; 541d079b7e4SSean Paul 542d079b7e4SSean Paul ret = drm_dp_dpcd_read(&dig_port->dp.aux, offset, 543d079b7e4SSean Paul (void *)byte, len); 544d079b7e4SSean Paul if (ret < 0) { 545d079b7e4SSean Paul drm_dbg_kms(&i915->drm, "msg_id %d, ret %zd\n", 546d079b7e4SSean Paul msg_id, ret); 547d079b7e4SSean Paul return ret; 548d079b7e4SSean Paul } 549d079b7e4SSean Paul 550d079b7e4SSean Paul bytes_to_recv -= ret; 551d079b7e4SSean Paul byte += ret; 552d079b7e4SSean Paul offset += ret; 553d079b7e4SSean Paul } 554d079b7e4SSean Paul byte = buf; 555d079b7e4SSean Paul *byte = msg_id; 556d079b7e4SSean Paul 557d079b7e4SSean Paul return size; 558d079b7e4SSean Paul } 559d079b7e4SSean Paul 560d079b7e4SSean Paul static 561d079b7e4SSean Paul int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *dig_port, 562d079b7e4SSean Paul bool is_repeater, u8 content_type) 563d079b7e4SSean Paul { 564d079b7e4SSean Paul int ret; 565d079b7e4SSean Paul struct hdcp2_dp_errata_stream_type stream_type_msg; 566d079b7e4SSean Paul 567d079b7e4SSean Paul if (is_repeater) 568d079b7e4SSean Paul return 0; 569d079b7e4SSean Paul 570d079b7e4SSean Paul /* 571d079b7e4SSean Paul * Errata for DP: As Stream type is used for encryption, Receiver 572d079b7e4SSean Paul * should be communicated with stream type for the decryption of the 573d079b7e4SSean Paul * content. 574d079b7e4SSean Paul * Repeater will be communicated with stream type as a part of it's 575d079b7e4SSean Paul * auth later in time. 576d079b7e4SSean Paul */ 577d079b7e4SSean Paul stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE; 578d079b7e4SSean Paul stream_type_msg.stream_type = content_type; 579d079b7e4SSean Paul 580d079b7e4SSean Paul ret = intel_dp_hdcp2_write_msg(dig_port, &stream_type_msg, 581d079b7e4SSean Paul sizeof(stream_type_msg)); 582d079b7e4SSean Paul 583d079b7e4SSean Paul return ret < 0 ? ret : 0; 584d079b7e4SSean Paul 585d079b7e4SSean Paul } 586d079b7e4SSean Paul 587d079b7e4SSean Paul static 5885bd29e32SAnshuman Gupta int intel_dp_hdcp2_check_link(struct intel_digital_port *dig_port, 5895bd29e32SAnshuman Gupta struct intel_connector *connector) 590d079b7e4SSean Paul { 591d079b7e4SSean Paul u8 rx_status; 592d079b7e4SSean Paul int ret; 593d079b7e4SSean Paul 594d079b7e4SSean Paul ret = intel_dp_hdcp2_read_rx_status(dig_port, &rx_status); 595d079b7e4SSean Paul if (ret) 596d079b7e4SSean Paul return ret; 597d079b7e4SSean Paul 598d079b7e4SSean Paul if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status)) 599d079b7e4SSean Paul ret = HDCP_REAUTH_REQUEST; 600d079b7e4SSean Paul else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status)) 601d079b7e4SSean Paul ret = HDCP_LINK_INTEGRITY_FAILURE; 602d079b7e4SSean Paul else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) 603d079b7e4SSean Paul ret = HDCP_TOPOLOGY_CHANGE; 604d079b7e4SSean Paul 605d079b7e4SSean Paul return ret; 606d079b7e4SSean Paul } 607d079b7e4SSean Paul 608d079b7e4SSean Paul static 609d079b7e4SSean Paul int intel_dp_hdcp2_capable(struct intel_digital_port *dig_port, 610d079b7e4SSean Paul bool *capable) 611d079b7e4SSean Paul { 612d079b7e4SSean Paul u8 rx_caps[3]; 613d079b7e4SSean Paul int ret; 614d079b7e4SSean Paul 615d079b7e4SSean Paul *capable = false; 616d079b7e4SSean Paul ret = drm_dp_dpcd_read(&dig_port->dp.aux, 617d079b7e4SSean Paul DP_HDCP_2_2_REG_RX_CAPS_OFFSET, 618d079b7e4SSean Paul rx_caps, HDCP_2_2_RXCAPS_LEN); 619d079b7e4SSean Paul if (ret != HDCP_2_2_RXCAPS_LEN) 620d079b7e4SSean Paul return ret >= 0 ? -EIO : ret; 621d079b7e4SSean Paul 622d079b7e4SSean Paul if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL && 623d079b7e4SSean Paul HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2])) 624d079b7e4SSean Paul *capable = true; 625d079b7e4SSean Paul 626d079b7e4SSean Paul return 0; 627d079b7e4SSean Paul } 628d079b7e4SSean Paul 629d079b7e4SSean Paul static const struct intel_hdcp_shim intel_dp_hdcp_shim = { 630d079b7e4SSean Paul .write_an_aksv = intel_dp_hdcp_write_an_aksv, 631d079b7e4SSean Paul .read_bksv = intel_dp_hdcp_read_bksv, 632d079b7e4SSean Paul .read_bstatus = intel_dp_hdcp_read_bstatus, 633d079b7e4SSean Paul .repeater_present = intel_dp_hdcp_repeater_present, 634d079b7e4SSean Paul .read_ri_prime = intel_dp_hdcp_read_ri_prime, 635d079b7e4SSean Paul .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, 636d079b7e4SSean Paul .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, 637d079b7e4SSean Paul .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, 638d079b7e4SSean Paul .toggle_signalling = intel_dp_hdcp_toggle_signalling, 639d079b7e4SSean Paul .check_link = intel_dp_hdcp_check_link, 640d079b7e4SSean Paul .hdcp_capable = intel_dp_hdcp_capable, 641d079b7e4SSean Paul .write_2_2_msg = intel_dp_hdcp2_write_msg, 642d079b7e4SSean Paul .read_2_2_msg = intel_dp_hdcp2_read_msg, 643d079b7e4SSean Paul .config_stream_type = intel_dp_hdcp2_config_stream_type, 644d079b7e4SSean Paul .check_2_2_link = intel_dp_hdcp2_check_link, 645d079b7e4SSean Paul .hdcp_2_2_capable = intel_dp_hdcp2_capable, 646d079b7e4SSean Paul .protocol = HDCP_PROTOCOL_DP, 647d079b7e4SSean Paul }; 648d079b7e4SSean Paul 6491fa01409SSean Paul static int 6501a67a168SAnshuman Gupta intel_dp_mst_toggle_hdcp_stream_select(struct intel_connector *connector, 6511fa01409SSean Paul bool enable) 6521fa01409SSean Paul { 6531a67a168SAnshuman Gupta struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 6541a67a168SAnshuman Gupta struct drm_i915_private *i915 = to_i915(connector->base.dev); 6551a67a168SAnshuman Gupta struct intel_hdcp *hdcp = &connector->hdcp; 6561fa01409SSean Paul int ret; 6571fa01409SSean Paul 6581a67a168SAnshuman Gupta ret = intel_ddi_toggle_hdcp_bits(&dig_port->base, 6591a67a168SAnshuman Gupta hdcp->stream_transcoder, enable, 6601a67a168SAnshuman Gupta TRANS_DDI_HDCP_SELECT); 6611fa01409SSean Paul if (ret) 6621a67a168SAnshuman Gupta drm_err(&i915->drm, "%s HDCP stream select failed (%d)\n", 6631fa01409SSean Paul enable ? "Enable" : "Disable", ret); 6641fa01409SSean Paul return ret; 6651fa01409SSean Paul } 6661fa01409SSean Paul 6671a67a168SAnshuman Gupta static int 6681a67a168SAnshuman Gupta intel_dp_mst_hdcp_stream_encryption(struct intel_connector *connector, 6691a67a168SAnshuman Gupta bool enable) 6701a67a168SAnshuman Gupta { 6711a67a168SAnshuman Gupta struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 6721a67a168SAnshuman Gupta struct drm_i915_private *i915 = to_i915(connector->base.dev); 6731a67a168SAnshuman Gupta struct intel_hdcp *hdcp = &connector->hdcp; 6741a67a168SAnshuman Gupta enum port port = dig_port->base.port; 6751a67a168SAnshuman Gupta enum transcoder cpu_transcoder = hdcp->stream_transcoder; 6761a67a168SAnshuman Gupta u32 stream_enc_status; 6771a67a168SAnshuman Gupta int ret; 6781a67a168SAnshuman Gupta 6791a67a168SAnshuman Gupta ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable); 6801a67a168SAnshuman Gupta if (ret) 6811a67a168SAnshuman Gupta return ret; 6821a67a168SAnshuman Gupta 6831a67a168SAnshuman Gupta stream_enc_status = transcoder_to_stream_enc_status(cpu_transcoder); 6841a67a168SAnshuman Gupta if (!stream_enc_status) 6851a67a168SAnshuman Gupta return -EINVAL; 6861a67a168SAnshuman Gupta 6871a67a168SAnshuman Gupta /* Wait for encryption confirmation */ 6881a67a168SAnshuman Gupta if (intel_de_wait_for_register(i915, 6891a67a168SAnshuman Gupta HDCP_STATUS(i915, cpu_transcoder, port), 6901a67a168SAnshuman Gupta stream_enc_status, 6911a67a168SAnshuman Gupta enable ? stream_enc_status : 0, 6921a67a168SAnshuman Gupta HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 6931a67a168SAnshuman Gupta drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n", 6941a67a168SAnshuman Gupta transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled"); 6951a67a168SAnshuman Gupta return -ETIMEDOUT; 6961a67a168SAnshuman Gupta } 6971a67a168SAnshuman Gupta 6981a67a168SAnshuman Gupta return 0; 6991a67a168SAnshuman Gupta } 7001a67a168SAnshuman Gupta 701e9fd05c3SAnshuman Gupta static int 702e9fd05c3SAnshuman Gupta intel_dp_mst_hdcp2_stream_encryption(struct intel_connector *connector, 703e9fd05c3SAnshuman Gupta bool enable) 704e9fd05c3SAnshuman Gupta { 705e9fd05c3SAnshuman Gupta struct intel_digital_port *dig_port = intel_attached_dig_port(connector); 706e9fd05c3SAnshuman Gupta struct drm_i915_private *i915 = to_i915(connector->base.dev); 707e9fd05c3SAnshuman Gupta struct hdcp_port_data *data = &dig_port->hdcp_port_data; 708e9fd05c3SAnshuman Gupta struct intel_hdcp *hdcp = &connector->hdcp; 709e9fd05c3SAnshuman Gupta enum transcoder cpu_transcoder = hdcp->stream_transcoder; 710e9fd05c3SAnshuman Gupta enum pipe pipe = (enum pipe)cpu_transcoder; 711e9fd05c3SAnshuman Gupta enum port port = dig_port->base.port; 712e9fd05c3SAnshuman Gupta int ret; 713e9fd05c3SAnshuman Gupta 714e9fd05c3SAnshuman Gupta drm_WARN_ON(&i915->drm, enable && 715e9fd05c3SAnshuman Gupta !!(intel_de_read(i915, HDCP2_AUTH_STREAM(i915, cpu_transcoder, port)) 716e9fd05c3SAnshuman Gupta & AUTH_STREAM_TYPE) != data->streams[0].stream_type); 717e9fd05c3SAnshuman Gupta 718e9fd05c3SAnshuman Gupta ret = intel_dp_mst_toggle_hdcp_stream_select(connector, enable); 719e9fd05c3SAnshuman Gupta if (ret) 720e9fd05c3SAnshuman Gupta return ret; 721e9fd05c3SAnshuman Gupta 722e9fd05c3SAnshuman Gupta /* Wait for encryption confirmation */ 723e9fd05c3SAnshuman Gupta if (intel_de_wait_for_register(i915, 724e9fd05c3SAnshuman Gupta HDCP2_STREAM_STATUS(i915, cpu_transcoder, pipe), 725e9fd05c3SAnshuman Gupta STREAM_ENCRYPTION_STATUS, 726e9fd05c3SAnshuman Gupta enable ? STREAM_ENCRYPTION_STATUS : 0, 727e9fd05c3SAnshuman Gupta HDCP_ENCRYPT_STATUS_CHANGE_TIMEOUT_MS)) { 728e9fd05c3SAnshuman Gupta drm_err(&i915->drm, "Timed out waiting for transcoder: %s stream encryption %s\n", 729e9fd05c3SAnshuman Gupta transcoder_name(cpu_transcoder), enable ? "enabled" : "disabled"); 730e9fd05c3SAnshuman Gupta return -ETIMEDOUT; 731e9fd05c3SAnshuman Gupta } 732e9fd05c3SAnshuman Gupta 733e9fd05c3SAnshuman Gupta return 0; 734e9fd05c3SAnshuman Gupta } 735e9fd05c3SAnshuman Gupta 736e9fd05c3SAnshuman Gupta static 737e9fd05c3SAnshuman Gupta int intel_dp_mst_hdcp2_check_link(struct intel_digital_port *dig_port, 738e9fd05c3SAnshuman Gupta struct intel_connector *connector) 739e9fd05c3SAnshuman Gupta { 740e9fd05c3SAnshuman Gupta struct intel_hdcp *hdcp = &connector->hdcp; 741e9fd05c3SAnshuman Gupta int ret; 742e9fd05c3SAnshuman Gupta 743e9fd05c3SAnshuman Gupta /* 744e9fd05c3SAnshuman Gupta * We do need to do the Link Check only for the connector involved with 745e9fd05c3SAnshuman Gupta * HDCP port authentication and encryption. 746e9fd05c3SAnshuman Gupta * We can re-use the hdcp->is_repeater flag to know that the connector 747e9fd05c3SAnshuman Gupta * involved with HDCP port authentication and encryption. 748e9fd05c3SAnshuman Gupta */ 749e9fd05c3SAnshuman Gupta if (hdcp->is_repeater) { 750e9fd05c3SAnshuman Gupta ret = intel_dp_hdcp2_check_link(dig_port, connector); 751e9fd05c3SAnshuman Gupta if (ret) 752e9fd05c3SAnshuman Gupta return ret; 753e9fd05c3SAnshuman Gupta } 754e9fd05c3SAnshuman Gupta 755*ee0735ffSJuston Li return 0; 756e9fd05c3SAnshuman Gupta } 757e9fd05c3SAnshuman Gupta 7581fa01409SSean Paul static const struct intel_hdcp_shim intel_dp_mst_hdcp_shim = { 7591fa01409SSean Paul .write_an_aksv = intel_dp_hdcp_write_an_aksv, 7601fa01409SSean Paul .read_bksv = intel_dp_hdcp_read_bksv, 7611fa01409SSean Paul .read_bstatus = intel_dp_hdcp_read_bstatus, 7621fa01409SSean Paul .repeater_present = intel_dp_hdcp_repeater_present, 7631fa01409SSean Paul .read_ri_prime = intel_dp_hdcp_read_ri_prime, 7641fa01409SSean Paul .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, 7651fa01409SSean Paul .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, 7661fa01409SSean Paul .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, 7671a67a168SAnshuman Gupta .toggle_signalling = intel_dp_hdcp_toggle_signalling, 7681a67a168SAnshuman Gupta .stream_encryption = intel_dp_mst_hdcp_stream_encryption, 76903b3a759SSean Paul .check_link = intel_dp_hdcp_check_link, 7701fa01409SSean Paul .hdcp_capable = intel_dp_hdcp_capable, 771e9fd05c3SAnshuman Gupta .write_2_2_msg = intel_dp_hdcp2_write_msg, 772e9fd05c3SAnshuman Gupta .read_2_2_msg = intel_dp_hdcp2_read_msg, 773e9fd05c3SAnshuman Gupta .config_stream_type = intel_dp_hdcp2_config_stream_type, 774e9fd05c3SAnshuman Gupta .stream_2_2_encryption = intel_dp_mst_hdcp2_stream_encryption, 775e9fd05c3SAnshuman Gupta .check_2_2_link = intel_dp_mst_hdcp2_check_link, 776e9fd05c3SAnshuman Gupta .hdcp_2_2_capable = intel_dp_hdcp2_capable, 7771fa01409SSean Paul .protocol = HDCP_PROTOCOL_DP, 7781fa01409SSean Paul }; 7791fa01409SSean Paul 780d079b7e4SSean Paul int intel_dp_init_hdcp(struct intel_digital_port *dig_port, 781d079b7e4SSean Paul struct intel_connector *intel_connector) 782d079b7e4SSean Paul { 783d079b7e4SSean Paul struct drm_device *dev = intel_connector->base.dev; 784d079b7e4SSean Paul struct drm_i915_private *dev_priv = to_i915(dev); 785d079b7e4SSean Paul struct intel_encoder *intel_encoder = &dig_port->base; 786d079b7e4SSean Paul enum port port = intel_encoder->port; 787d079b7e4SSean Paul struct intel_dp *intel_dp = &dig_port->dp; 788d079b7e4SSean Paul 789d079b7e4SSean Paul if (!is_hdcp_supported(dev_priv, port)) 790d079b7e4SSean Paul return 0; 791d079b7e4SSean Paul 7921fa01409SSean Paul if (intel_connector->mst_port) 79329b283a4SAnshuman Gupta return intel_hdcp_init(intel_connector, dig_port, 7941fa01409SSean Paul &intel_dp_mst_hdcp_shim); 7951fa01409SSean Paul else if (!intel_dp_is_edp(intel_dp)) 79629b283a4SAnshuman Gupta return intel_hdcp_init(intel_connector, dig_port, 797bf3657daSSean Paul &intel_dp_hdcp_shim); 798d079b7e4SSean Paul 799d079b7e4SSean Paul return 0; 800d079b7e4SSean Paul } 801