1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020-2021 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_trace.h" 8 #include "intel_display_types.h" 9 #include "intel_dp_aux.h" 10 #include "intel_pps.h" 11 #include "intel_tc.h" 12 13 u32 intel_dp_pack_aux(const u8 *src, int src_bytes) 14 { 15 int i; 16 u32 v = 0; 17 18 if (src_bytes > 4) 19 src_bytes = 4; 20 for (i = 0; i < src_bytes; i++) 21 v |= ((u32)src[i]) << ((3 - i) * 8); 22 return v; 23 } 24 25 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes) 26 { 27 int i; 28 29 if (dst_bytes > 4) 30 dst_bytes = 4; 31 for (i = 0; i < dst_bytes; i++) 32 dst[i] = src >> ((3 - i) * 8); 33 } 34 35 static u32 36 intel_dp_aux_wait_done(struct intel_dp *intel_dp) 37 { 38 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 39 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 40 const unsigned int timeout_ms = 10; 41 u32 status; 42 bool done; 43 44 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 45 done = wait_event_timeout(i915->gmbus_wait_queue, C, 46 msecs_to_jiffies_timeout(timeout_ms)); 47 48 /* just trace the final value */ 49 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); 50 51 if (!done) 52 drm_err(&i915->drm, 53 "%s: did not complete or timeout within %ums (status 0x%08x)\n", 54 intel_dp->aux.name, timeout_ms, status); 55 #undef C 56 57 return status; 58 } 59 60 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 61 { 62 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 63 64 if (index) 65 return 0; 66 67 /* 68 * The clock divider is based off the hrawclk, and would like to run at 69 * 2MHz. So, take the hrawclk value and divide by 2000 and use that 70 */ 71 return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000); 72 } 73 74 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 75 { 76 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 77 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 78 u32 freq; 79 80 if (index) 81 return 0; 82 83 /* 84 * The clock divider is based off the cdclk or PCH rawclk, and would 85 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and 86 * divide by 2000 and use that 87 */ 88 if (dig_port->aux_ch == AUX_CH_A) 89 freq = dev_priv->cdclk.hw.cdclk; 90 else 91 freq = RUNTIME_INFO(dev_priv)->rawclk_freq; 92 return DIV_ROUND_CLOSEST(freq, 2000); 93 } 94 95 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 96 { 97 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 98 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 99 100 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) { 101 /* Workaround for non-ULT HSW */ 102 switch (index) { 103 case 0: return 63; 104 case 1: return 72; 105 default: return 0; 106 } 107 } 108 109 return ilk_get_aux_clock_divider(intel_dp, index); 110 } 111 112 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 113 { 114 /* 115 * SKL doesn't need us to program the AUX clock divider (Hardware will 116 * derive the clock from CDCLK automatically). We still implement the 117 * get_aux_clock_divider vfunc to plug-in into the existing code. 118 */ 119 return index ? 0 : 1; 120 } 121 122 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, 123 int send_bytes, 124 u32 aux_clock_divider) 125 { 126 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 127 struct drm_i915_private *dev_priv = 128 to_i915(dig_port->base.base.dev); 129 u32 precharge, timeout; 130 131 if (IS_GEN(dev_priv, 6)) 132 precharge = 3; 133 else 134 precharge = 5; 135 136 if (IS_BROADWELL(dev_priv)) 137 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 138 else 139 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 140 141 return DP_AUX_CH_CTL_SEND_BUSY | 142 DP_AUX_CH_CTL_DONE | 143 DP_AUX_CH_CTL_INTERRUPT | 144 DP_AUX_CH_CTL_TIME_OUT_ERROR | 145 timeout | 146 DP_AUX_CH_CTL_RECEIVE_ERROR | 147 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 148 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 149 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 150 } 151 152 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, 153 int send_bytes, 154 u32 unused) 155 { 156 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 157 struct drm_i915_private *i915 = 158 to_i915(dig_port->base.base.dev); 159 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 160 u32 ret; 161 162 ret = DP_AUX_CH_CTL_SEND_BUSY | 163 DP_AUX_CH_CTL_DONE | 164 DP_AUX_CH_CTL_INTERRUPT | 165 DP_AUX_CH_CTL_TIME_OUT_ERROR | 166 DP_AUX_CH_CTL_TIME_OUT_MAX | 167 DP_AUX_CH_CTL_RECEIVE_ERROR | 168 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 169 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | 170 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); 171 172 if (intel_phy_is_tc(i915, phy) && 173 dig_port->tc_mode == TC_PORT_TBT_ALT) 174 ret |= DP_AUX_CH_CTL_TBT_IO; 175 176 return ret; 177 } 178 179 static int 180 intel_dp_aux_xfer(struct intel_dp *intel_dp, 181 const u8 *send, int send_bytes, 182 u8 *recv, int recv_size, 183 u32 aux_send_ctl_flags) 184 { 185 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 186 struct drm_i915_private *i915 = 187 to_i915(dig_port->base.base.dev); 188 struct intel_uncore *uncore = &i915->uncore; 189 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 190 bool is_tc_port = intel_phy_is_tc(i915, phy); 191 i915_reg_t ch_ctl, ch_data[5]; 192 u32 aux_clock_divider; 193 enum intel_display_power_domain aux_domain; 194 intel_wakeref_t aux_wakeref; 195 intel_wakeref_t pps_wakeref; 196 int i, ret, recv_bytes; 197 int try, clock = 0; 198 u32 status; 199 bool vdd; 200 201 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 202 for (i = 0; i < ARRAY_SIZE(ch_data); i++) 203 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); 204 205 if (is_tc_port) 206 intel_tc_port_lock(dig_port); 207 208 aux_domain = intel_aux_power_domain(dig_port); 209 210 aux_wakeref = intel_display_power_get(i915, aux_domain); 211 pps_wakeref = intel_pps_lock(intel_dp); 212 213 /* 214 * We will be called with VDD already enabled for dpcd/edid/oui reads. 215 * In such cases we want to leave VDD enabled and it's up to upper layers 216 * to turn it off. But for eg. i2c-dev access we need to turn it on/off 217 * ourselves. 218 */ 219 vdd = intel_pps_vdd_on_unlocked(intel_dp); 220 221 /* 222 * dp aux is extremely sensitive to irq latency, hence request the 223 * lowest possible wakeup latency and so prevent the cpu from going into 224 * deep sleep states. 225 */ 226 cpu_latency_qos_update_request(&intel_dp->pm_qos, 0); 227 228 intel_pps_check_power_unlocked(intel_dp); 229 230 /* Try to wait for any previous AUX channel activity */ 231 for (try = 0; try < 3; try++) { 232 status = intel_uncore_read_notrace(uncore, ch_ctl); 233 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 234 break; 235 msleep(1); 236 } 237 /* just trace the final value */ 238 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); 239 240 if (try == 3) { 241 const u32 status = intel_uncore_read(uncore, ch_ctl); 242 243 if (status != intel_dp->aux_busy_last_status) { 244 drm_WARN(&i915->drm, 1, 245 "%s: not started (status 0x%08x)\n", 246 intel_dp->aux.name, status); 247 intel_dp->aux_busy_last_status = status; 248 } 249 250 ret = -EBUSY; 251 goto out; 252 } 253 254 /* Only 5 data registers! */ 255 if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) { 256 ret = -E2BIG; 257 goto out; 258 } 259 260 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 261 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 262 send_bytes, 263 aux_clock_divider); 264 265 send_ctl |= aux_send_ctl_flags; 266 267 /* Must try at least 3 times according to DP spec */ 268 for (try = 0; try < 5; try++) { 269 /* Load the send data into the aux channel data registers */ 270 for (i = 0; i < send_bytes; i += 4) 271 intel_uncore_write(uncore, 272 ch_data[i >> 2], 273 intel_dp_pack_aux(send + i, 274 send_bytes - i)); 275 276 /* Send the command and wait for it to complete */ 277 intel_uncore_write(uncore, ch_ctl, send_ctl); 278 279 status = intel_dp_aux_wait_done(intel_dp); 280 281 /* Clear done status and any errors */ 282 intel_uncore_write(uncore, 283 ch_ctl, 284 status | 285 DP_AUX_CH_CTL_DONE | 286 DP_AUX_CH_CTL_TIME_OUT_ERROR | 287 DP_AUX_CH_CTL_RECEIVE_ERROR); 288 289 /* 290 * DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 291 * 400us delay required for errors and timeouts 292 * Timeout errors from the HW already meet this 293 * requirement so skip to next iteration 294 */ 295 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) 296 continue; 297 298 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 299 usleep_range(400, 500); 300 continue; 301 } 302 if (status & DP_AUX_CH_CTL_DONE) 303 goto done; 304 } 305 } 306 307 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 308 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n", 309 intel_dp->aux.name, status); 310 ret = -EBUSY; 311 goto out; 312 } 313 314 done: 315 /* 316 * Check for timeout or receive error. Timeouts occur when the sink is 317 * not connected. 318 */ 319 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 320 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n", 321 intel_dp->aux.name, status); 322 ret = -EIO; 323 goto out; 324 } 325 326 /* 327 * Timeouts occur when the device isn't connected, so they're "normal" 328 * -- don't fill the kernel log with these 329 */ 330 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 331 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n", 332 intel_dp->aux.name, status); 333 ret = -ETIMEDOUT; 334 goto out; 335 } 336 337 /* Unload any bytes sent back from the other side */ 338 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 339 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 340 341 /* 342 * By BSpec: "Message sizes of 0 or >20 are not allowed." 343 * We have no idea of what happened so we return -EBUSY so 344 * drm layer takes care for the necessary retries. 345 */ 346 if (recv_bytes == 0 || recv_bytes > 20) { 347 drm_dbg_kms(&i915->drm, 348 "%s: Forbidden recv_bytes = %d on aux transaction\n", 349 intel_dp->aux.name, recv_bytes); 350 ret = -EBUSY; 351 goto out; 352 } 353 354 if (recv_bytes > recv_size) 355 recv_bytes = recv_size; 356 357 for (i = 0; i < recv_bytes; i += 4) 358 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]), 359 recv + i, recv_bytes - i); 360 361 ret = recv_bytes; 362 out: 363 cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 364 365 if (vdd) 366 intel_pps_vdd_off_unlocked(intel_dp, false); 367 368 intel_pps_unlock(intel_dp, pps_wakeref); 369 intel_display_power_put_async(i915, aux_domain, aux_wakeref); 370 371 if (is_tc_port) 372 intel_tc_port_unlock(dig_port); 373 374 return ret; 375 } 376 377 #define BARE_ADDRESS_SIZE 3 378 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 379 380 static void 381 intel_dp_aux_header(u8 txbuf[HEADER_SIZE], 382 const struct drm_dp_aux_msg *msg) 383 { 384 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); 385 txbuf[1] = (msg->address >> 8) & 0xff; 386 txbuf[2] = msg->address & 0xff; 387 txbuf[3] = msg->size - 1; 388 } 389 390 static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg) 391 { 392 /* 393 * If we're trying to send the HDCP Aksv, we need to set a the Aksv 394 * select bit to inform the hardware to send the Aksv after our header 395 * since we can't access that data from software. 396 */ 397 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE && 398 msg->address == DP_AUX_HDCP_AKSV) 399 return DP_AUX_CH_CTL_AUX_AKSV_SELECT; 400 401 return 0; 402 } 403 404 static ssize_t 405 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 406 { 407 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 408 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 409 u8 txbuf[20], rxbuf[20]; 410 size_t txsize, rxsize; 411 u32 flags = intel_dp_aux_xfer_flags(msg); 412 int ret; 413 414 intel_dp_aux_header(txbuf, msg); 415 416 switch (msg->request & ~DP_AUX_I2C_MOT) { 417 case DP_AUX_NATIVE_WRITE: 418 case DP_AUX_I2C_WRITE: 419 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 420 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 421 rxsize = 2; /* 0 or 1 data bytes */ 422 423 if (drm_WARN_ON(&i915->drm, txsize > 20)) 424 return -E2BIG; 425 426 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size); 427 428 if (msg->buffer) 429 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 430 431 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 432 rxbuf, rxsize, flags); 433 if (ret > 0) { 434 msg->reply = rxbuf[0] >> 4; 435 436 if (ret > 1) { 437 /* Number of bytes written in a short write. */ 438 ret = clamp_t(int, rxbuf[1], 0, msg->size); 439 } else { 440 /* Return payload size. */ 441 ret = msg->size; 442 } 443 } 444 break; 445 446 case DP_AUX_NATIVE_READ: 447 case DP_AUX_I2C_READ: 448 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 449 rxsize = msg->size + 1; 450 451 if (drm_WARN_ON(&i915->drm, rxsize > 20)) 452 return -E2BIG; 453 454 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 455 rxbuf, rxsize, flags); 456 if (ret > 0) { 457 msg->reply = rxbuf[0] >> 4; 458 /* 459 * Assume happy day, and copy the data. The caller is 460 * expected to check msg->reply before touching it. 461 * 462 * Return payload size. 463 */ 464 ret--; 465 memcpy(msg->buffer, rxbuf + 1, ret); 466 } 467 break; 468 469 default: 470 ret = -EINVAL; 471 break; 472 } 473 474 return ret; 475 } 476 477 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) 478 { 479 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 480 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 481 enum aux_ch aux_ch = dig_port->aux_ch; 482 483 switch (aux_ch) { 484 case AUX_CH_B: 485 case AUX_CH_C: 486 case AUX_CH_D: 487 return DP_AUX_CH_CTL(aux_ch); 488 default: 489 MISSING_CASE(aux_ch); 490 return DP_AUX_CH_CTL(AUX_CH_B); 491 } 492 } 493 494 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) 495 { 496 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 497 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 498 enum aux_ch aux_ch = dig_port->aux_ch; 499 500 switch (aux_ch) { 501 case AUX_CH_B: 502 case AUX_CH_C: 503 case AUX_CH_D: 504 return DP_AUX_CH_DATA(aux_ch, index); 505 default: 506 MISSING_CASE(aux_ch); 507 return DP_AUX_CH_DATA(AUX_CH_B, index); 508 } 509 } 510 511 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) 512 { 513 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 514 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 515 enum aux_ch aux_ch = dig_port->aux_ch; 516 517 switch (aux_ch) { 518 case AUX_CH_A: 519 return DP_AUX_CH_CTL(aux_ch); 520 case AUX_CH_B: 521 case AUX_CH_C: 522 case AUX_CH_D: 523 return PCH_DP_AUX_CH_CTL(aux_ch); 524 default: 525 MISSING_CASE(aux_ch); 526 return DP_AUX_CH_CTL(AUX_CH_A); 527 } 528 } 529 530 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) 531 { 532 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 533 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 534 enum aux_ch aux_ch = dig_port->aux_ch; 535 536 switch (aux_ch) { 537 case AUX_CH_A: 538 return DP_AUX_CH_DATA(aux_ch, index); 539 case AUX_CH_B: 540 case AUX_CH_C: 541 case AUX_CH_D: 542 return PCH_DP_AUX_CH_DATA(aux_ch, index); 543 default: 544 MISSING_CASE(aux_ch); 545 return DP_AUX_CH_DATA(AUX_CH_A, index); 546 } 547 } 548 549 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) 550 { 551 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 552 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 553 enum aux_ch aux_ch = dig_port->aux_ch; 554 555 switch (aux_ch) { 556 case AUX_CH_A: 557 case AUX_CH_B: 558 case AUX_CH_C: 559 case AUX_CH_D: 560 case AUX_CH_E: 561 case AUX_CH_F: 562 return DP_AUX_CH_CTL(aux_ch); 563 default: 564 MISSING_CASE(aux_ch); 565 return DP_AUX_CH_CTL(AUX_CH_A); 566 } 567 } 568 569 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) 570 { 571 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 572 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 573 enum aux_ch aux_ch = dig_port->aux_ch; 574 575 switch (aux_ch) { 576 case AUX_CH_A: 577 case AUX_CH_B: 578 case AUX_CH_C: 579 case AUX_CH_D: 580 case AUX_CH_E: 581 case AUX_CH_F: 582 return DP_AUX_CH_DATA(aux_ch, index); 583 default: 584 MISSING_CASE(aux_ch); 585 return DP_AUX_CH_DATA(AUX_CH_A, index); 586 } 587 } 588 589 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) 590 { 591 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 592 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 593 enum aux_ch aux_ch = dig_port->aux_ch; 594 595 switch (aux_ch) { 596 case AUX_CH_A: 597 case AUX_CH_B: 598 case AUX_CH_C: 599 case AUX_CH_USBC1: 600 case AUX_CH_USBC2: 601 case AUX_CH_USBC3: 602 case AUX_CH_USBC4: 603 case AUX_CH_USBC5: 604 case AUX_CH_USBC6: 605 return DP_AUX_CH_CTL(aux_ch); 606 default: 607 MISSING_CASE(aux_ch); 608 return DP_AUX_CH_CTL(AUX_CH_A); 609 } 610 } 611 612 static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) 613 { 614 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 615 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 616 enum aux_ch aux_ch = dig_port->aux_ch; 617 618 switch (aux_ch) { 619 case AUX_CH_A: 620 case AUX_CH_B: 621 case AUX_CH_C: 622 case AUX_CH_USBC1: 623 case AUX_CH_USBC2: 624 case AUX_CH_USBC3: 625 case AUX_CH_USBC4: 626 case AUX_CH_USBC5: 627 case AUX_CH_USBC6: 628 return DP_AUX_CH_DATA(aux_ch, index); 629 default: 630 MISSING_CASE(aux_ch); 631 return DP_AUX_CH_DATA(AUX_CH_A, index); 632 } 633 } 634 635 void intel_dp_aux_fini(struct intel_dp *intel_dp) 636 { 637 if (cpu_latency_qos_request_active(&intel_dp->pm_qos)) 638 cpu_latency_qos_remove_request(&intel_dp->pm_qos); 639 640 kfree(intel_dp->aux.name); 641 } 642 643 void intel_dp_aux_init(struct intel_dp *intel_dp) 644 { 645 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 646 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 647 struct intel_encoder *encoder = &dig_port->base; 648 enum aux_ch aux_ch = dig_port->aux_ch; 649 650 if (INTEL_GEN(dev_priv) >= 12) { 651 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg; 652 intel_dp->aux_ch_data_reg = tgl_aux_data_reg; 653 } else if (INTEL_GEN(dev_priv) >= 9) { 654 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; 655 intel_dp->aux_ch_data_reg = skl_aux_data_reg; 656 } else if (HAS_PCH_SPLIT(dev_priv)) { 657 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; 658 intel_dp->aux_ch_data_reg = ilk_aux_data_reg; 659 } else { 660 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; 661 intel_dp->aux_ch_data_reg = g4x_aux_data_reg; 662 } 663 664 if (INTEL_GEN(dev_priv) >= 9) 665 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; 666 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 667 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 668 else if (HAS_PCH_SPLIT(dev_priv)) 669 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 670 else 671 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; 672 673 if (INTEL_GEN(dev_priv) >= 9) 674 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; 675 else 676 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; 677 678 drm_dp_aux_init(&intel_dp->aux); 679 680 /* Failure to allocate our preferred name is not critical */ 681 if (INTEL_GEN(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1) 682 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s", 683 aux_ch - AUX_CH_USBC1 + '1', 684 encoder->base.name); 685 else 686 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s", 687 aux_ch_name(aux_ch), 688 encoder->base.name); 689 690 intel_dp->aux.transfer = intel_dp_aux_transfer; 691 cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 692 } 693