1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020-2021 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "i915_trace.h" 9 #include "intel_bios.h" 10 #include "intel_de.h" 11 #include "intel_display_types.h" 12 #include "intel_dp_aux.h" 13 #include "intel_dp_aux_regs.h" 14 #include "intel_pps.h" 15 #include "intel_tc.h" 16 17 static u32 intel_dp_aux_pack(const u8 *src, int src_bytes) 18 { 19 int i; 20 u32 v = 0; 21 22 if (src_bytes > 4) 23 src_bytes = 4; 24 for (i = 0; i < src_bytes; i++) 25 v |= ((u32)src[i]) << ((3 - i) * 8); 26 return v; 27 } 28 29 static void intel_dp_aux_unpack(u32 src, u8 *dst, int dst_bytes) 30 { 31 int i; 32 33 if (dst_bytes > 4) 34 dst_bytes = 4; 35 for (i = 0; i < dst_bytes; i++) 36 dst[i] = src >> ((3 - i) * 8); 37 } 38 39 static u32 40 intel_dp_aux_wait_done(struct intel_dp *intel_dp) 41 { 42 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 43 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 44 const unsigned int timeout_ms = 10; 45 u32 status; 46 int ret; 47 48 ret = __intel_de_wait_for_register(i915, ch_ctl, 49 DP_AUX_CH_CTL_SEND_BUSY, 0, 50 2, timeout_ms, &status); 51 52 if (ret == -ETIMEDOUT) 53 drm_err(&i915->drm, 54 "%s: did not complete or timeout within %ums (status 0x%08x)\n", 55 intel_dp->aux.name, timeout_ms, status); 56 57 return status; 58 } 59 60 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 61 { 62 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 63 64 if (index) 65 return 0; 66 67 /* 68 * The clock divider is based off the hrawclk, and would like to run at 69 * 2MHz. So, take the hrawclk value and divide by 2000 and use that 70 */ 71 return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000); 72 } 73 74 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 75 { 76 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 77 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 78 u32 freq; 79 80 if (index) 81 return 0; 82 83 /* 84 * The clock divider is based off the cdclk or PCH rawclk, and would 85 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and 86 * divide by 2000 and use that 87 */ 88 if (dig_port->aux_ch == AUX_CH_A) 89 freq = dev_priv->display.cdclk.hw.cdclk; 90 else 91 freq = RUNTIME_INFO(dev_priv)->rawclk_freq; 92 return DIV_ROUND_CLOSEST(freq, 2000); 93 } 94 95 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 96 { 97 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 98 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 99 100 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) { 101 /* Workaround for non-ULT HSW */ 102 switch (index) { 103 case 0: return 63; 104 case 1: return 72; 105 default: return 0; 106 } 107 } 108 109 return ilk_get_aux_clock_divider(intel_dp, index); 110 } 111 112 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 113 { 114 /* 115 * SKL doesn't need us to program the AUX clock divider (Hardware will 116 * derive the clock from CDCLK automatically). We still implement the 117 * get_aux_clock_divider vfunc to plug-in into the existing code. 118 */ 119 return index ? 0 : 1; 120 } 121 122 static int intel_dp_aux_sync_len(void) 123 { 124 int precharge = 16; /* 10-16 */ 125 int preamble = 16; 126 127 return precharge + preamble; 128 } 129 130 static int intel_dp_aux_fw_sync_len(void) 131 { 132 int precharge = 10; /* 10-16 */ 133 int preamble = 8; 134 135 return precharge + preamble; 136 } 137 138 static int g4x_dp_aux_precharge_len(void) 139 { 140 int precharge_min = 10; 141 int preamble = 16; 142 143 /* HW wants the length of the extra precharge in 2us units */ 144 return (intel_dp_aux_sync_len() - 145 precharge_min - preamble) / 2; 146 } 147 148 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, 149 int send_bytes, 150 u32 aux_clock_divider) 151 { 152 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 153 struct drm_i915_private *dev_priv = 154 to_i915(dig_port->base.base.dev); 155 u32 timeout; 156 157 /* Max timeout value on G4x-BDW: 1.6ms */ 158 if (IS_BROADWELL(dev_priv)) 159 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 160 else 161 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 162 163 return DP_AUX_CH_CTL_SEND_BUSY | 164 DP_AUX_CH_CTL_DONE | 165 DP_AUX_CH_CTL_INTERRUPT | 166 DP_AUX_CH_CTL_TIME_OUT_ERROR | 167 timeout | 168 DP_AUX_CH_CTL_RECEIVE_ERROR | 169 DP_AUX_CH_CTL_MESSAGE_SIZE(send_bytes) | 170 DP_AUX_CH_CTL_PRECHARGE_2US(g4x_dp_aux_precharge_len()) | 171 DP_AUX_CH_CTL_BIT_CLOCK_2X(aux_clock_divider); 172 } 173 174 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, 175 int send_bytes, 176 u32 unused) 177 { 178 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 179 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 180 u32 ret; 181 182 /* 183 * Max timeout values: 184 * SKL-GLK: 1.6ms 185 * ICL+: 4ms 186 */ 187 ret = DP_AUX_CH_CTL_SEND_BUSY | 188 DP_AUX_CH_CTL_DONE | 189 DP_AUX_CH_CTL_INTERRUPT | 190 DP_AUX_CH_CTL_TIME_OUT_ERROR | 191 DP_AUX_CH_CTL_TIME_OUT_MAX | 192 DP_AUX_CH_CTL_RECEIVE_ERROR | 193 DP_AUX_CH_CTL_MESSAGE_SIZE(send_bytes) | 194 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(intel_dp_aux_fw_sync_len()) | 195 DP_AUX_CH_CTL_SYNC_PULSE_SKL(intel_dp_aux_sync_len()); 196 197 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 198 ret |= DP_AUX_CH_CTL_TBT_IO; 199 200 /* 201 * Power request bit is already set during aux power well enable. 202 * Preserve the bit across aux transactions. 203 */ 204 if (DISPLAY_VER(i915) >= 14) 205 ret |= XELPDP_DP_AUX_CH_CTL_POWER_REQUEST; 206 207 return ret; 208 } 209 210 static int 211 intel_dp_aux_xfer(struct intel_dp *intel_dp, 212 const u8 *send, int send_bytes, 213 u8 *recv, int recv_size, 214 u32 aux_send_ctl_flags) 215 { 216 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 217 struct drm_i915_private *i915 = 218 to_i915(dig_port->base.base.dev); 219 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 220 bool is_tc_port = intel_phy_is_tc(i915, phy); 221 i915_reg_t ch_ctl, ch_data[5]; 222 u32 aux_clock_divider; 223 enum intel_display_power_domain aux_domain; 224 intel_wakeref_t aux_wakeref; 225 intel_wakeref_t pps_wakeref; 226 int i, ret, recv_bytes; 227 int try, clock = 0; 228 u32 status; 229 bool vdd; 230 231 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 232 for (i = 0; i < ARRAY_SIZE(ch_data); i++) 233 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); 234 235 if (is_tc_port) { 236 intel_tc_port_lock(dig_port); 237 /* 238 * Abort transfers on a disconnected port as required by 239 * DP 1.4a link CTS 4.2.1.5, also avoiding the long AUX 240 * timeouts that would otherwise happen. 241 * TODO: abort the transfer on non-TC ports as well. 242 */ 243 if (!intel_tc_port_connected_locked(&dig_port->base)) { 244 ret = -ENXIO; 245 goto out_unlock; 246 } 247 } 248 249 aux_domain = intel_aux_power_domain(dig_port); 250 251 aux_wakeref = intel_display_power_get(i915, aux_domain); 252 pps_wakeref = intel_pps_lock(intel_dp); 253 254 /* 255 * We will be called with VDD already enabled for dpcd/edid/oui reads. 256 * In such cases we want to leave VDD enabled and it's up to upper layers 257 * to turn it off. But for eg. i2c-dev access we need to turn it on/off 258 * ourselves. 259 */ 260 vdd = intel_pps_vdd_on_unlocked(intel_dp); 261 262 /* 263 * dp aux is extremely sensitive to irq latency, hence request the 264 * lowest possible wakeup latency and so prevent the cpu from going into 265 * deep sleep states. 266 */ 267 cpu_latency_qos_update_request(&intel_dp->pm_qos, 0); 268 269 intel_pps_check_power_unlocked(intel_dp); 270 271 /* 272 * FIXME PSR should be disabled here to prevent 273 * it using the same AUX CH simultaneously 274 */ 275 276 /* Try to wait for any previous AUX channel activity */ 277 for (try = 0; try < 3; try++) { 278 status = intel_de_read_notrace(i915, ch_ctl); 279 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 280 break; 281 msleep(1); 282 } 283 /* just trace the final value */ 284 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); 285 286 if (try == 3) { 287 const u32 status = intel_de_read(i915, ch_ctl); 288 289 if (status != intel_dp->aux_busy_last_status) { 290 drm_WARN(&i915->drm, 1, 291 "%s: not started (status 0x%08x)\n", 292 intel_dp->aux.name, status); 293 intel_dp->aux_busy_last_status = status; 294 } 295 296 ret = -EBUSY; 297 goto out; 298 } 299 300 /* Only 5 data registers! */ 301 if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) { 302 ret = -E2BIG; 303 goto out; 304 } 305 306 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 307 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 308 send_bytes, 309 aux_clock_divider); 310 311 send_ctl |= aux_send_ctl_flags; 312 313 /* Must try at least 3 times according to DP spec */ 314 for (try = 0; try < 5; try++) { 315 /* Load the send data into the aux channel data registers */ 316 for (i = 0; i < send_bytes; i += 4) 317 intel_de_write(i915, ch_data[i >> 2], 318 intel_dp_aux_pack(send + i, 319 send_bytes - i)); 320 321 /* Send the command and wait for it to complete */ 322 intel_de_write(i915, ch_ctl, send_ctl); 323 324 status = intel_dp_aux_wait_done(intel_dp); 325 326 /* Clear done status and any errors */ 327 intel_de_write(i915, ch_ctl, 328 status | DP_AUX_CH_CTL_DONE | 329 DP_AUX_CH_CTL_TIME_OUT_ERROR | 330 DP_AUX_CH_CTL_RECEIVE_ERROR); 331 332 /* 333 * DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 334 * 400us delay required for errors and timeouts 335 * Timeout errors from the HW already meet this 336 * requirement so skip to next iteration 337 */ 338 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) 339 continue; 340 341 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 342 usleep_range(400, 500); 343 continue; 344 } 345 if (status & DP_AUX_CH_CTL_DONE) 346 goto done; 347 } 348 } 349 350 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 351 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n", 352 intel_dp->aux.name, status); 353 ret = -EBUSY; 354 goto out; 355 } 356 357 done: 358 /* 359 * Check for timeout or receive error. Timeouts occur when the sink is 360 * not connected. 361 */ 362 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 363 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n", 364 intel_dp->aux.name, status); 365 ret = -EIO; 366 goto out; 367 } 368 369 /* 370 * Timeouts occur when the device isn't connected, so they're "normal" 371 * -- don't fill the kernel log with these 372 */ 373 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 374 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n", 375 intel_dp->aux.name, status); 376 ret = -ETIMEDOUT; 377 goto out; 378 } 379 380 /* Unload any bytes sent back from the other side */ 381 recv_bytes = REG_FIELD_GET(DP_AUX_CH_CTL_MESSAGE_SIZE_MASK, status); 382 383 /* 384 * By BSpec: "Message sizes of 0 or >20 are not allowed." 385 * We have no idea of what happened so we return -EBUSY so 386 * drm layer takes care for the necessary retries. 387 */ 388 if (recv_bytes == 0 || recv_bytes > 20) { 389 drm_dbg_kms(&i915->drm, 390 "%s: Forbidden recv_bytes = %d on aux transaction\n", 391 intel_dp->aux.name, recv_bytes); 392 ret = -EBUSY; 393 goto out; 394 } 395 396 if (recv_bytes > recv_size) 397 recv_bytes = recv_size; 398 399 for (i = 0; i < recv_bytes; i += 4) 400 intel_dp_aux_unpack(intel_de_read(i915, ch_data[i >> 2]), 401 recv + i, recv_bytes - i); 402 403 ret = recv_bytes; 404 out: 405 cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 406 407 if (vdd) 408 intel_pps_vdd_off_unlocked(intel_dp, false); 409 410 intel_pps_unlock(intel_dp, pps_wakeref); 411 intel_display_power_put_async(i915, aux_domain, aux_wakeref); 412 out_unlock: 413 if (is_tc_port) 414 intel_tc_port_unlock(dig_port); 415 416 return ret; 417 } 418 419 #define BARE_ADDRESS_SIZE 3 420 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 421 422 static void 423 intel_dp_aux_header(u8 txbuf[HEADER_SIZE], 424 const struct drm_dp_aux_msg *msg) 425 { 426 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); 427 txbuf[1] = (msg->address >> 8) & 0xff; 428 txbuf[2] = msg->address & 0xff; 429 txbuf[3] = msg->size - 1; 430 } 431 432 static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg) 433 { 434 /* 435 * If we're trying to send the HDCP Aksv, we need to set a the Aksv 436 * select bit to inform the hardware to send the Aksv after our header 437 * since we can't access that data from software. 438 */ 439 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE && 440 msg->address == DP_AUX_HDCP_AKSV) 441 return DP_AUX_CH_CTL_AUX_AKSV_SELECT; 442 443 return 0; 444 } 445 446 static ssize_t 447 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 448 { 449 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 450 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 451 u8 txbuf[20], rxbuf[20]; 452 size_t txsize, rxsize; 453 u32 flags = intel_dp_aux_xfer_flags(msg); 454 int ret; 455 456 intel_dp_aux_header(txbuf, msg); 457 458 switch (msg->request & ~DP_AUX_I2C_MOT) { 459 case DP_AUX_NATIVE_WRITE: 460 case DP_AUX_I2C_WRITE: 461 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 462 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 463 rxsize = 2; /* 0 or 1 data bytes */ 464 465 if (drm_WARN_ON(&i915->drm, txsize > 20)) 466 return -E2BIG; 467 468 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size); 469 470 if (msg->buffer) 471 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 472 473 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 474 rxbuf, rxsize, flags); 475 if (ret > 0) { 476 msg->reply = rxbuf[0] >> 4; 477 478 if (ret > 1) { 479 /* Number of bytes written in a short write. */ 480 ret = clamp_t(int, rxbuf[1], 0, msg->size); 481 } else { 482 /* Return payload size. */ 483 ret = msg->size; 484 } 485 } 486 break; 487 488 case DP_AUX_NATIVE_READ: 489 case DP_AUX_I2C_READ: 490 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 491 rxsize = msg->size + 1; 492 493 if (drm_WARN_ON(&i915->drm, rxsize > 20)) 494 return -E2BIG; 495 496 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 497 rxbuf, rxsize, flags); 498 if (ret > 0) { 499 msg->reply = rxbuf[0] >> 4; 500 /* 501 * Assume happy day, and copy the data. The caller is 502 * expected to check msg->reply before touching it. 503 * 504 * Return payload size. 505 */ 506 ret--; 507 memcpy(msg->buffer, rxbuf + 1, ret); 508 } 509 break; 510 511 default: 512 ret = -EINVAL; 513 break; 514 } 515 516 return ret; 517 } 518 519 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) 520 { 521 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 522 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 523 enum aux_ch aux_ch = dig_port->aux_ch; 524 525 switch (aux_ch) { 526 case AUX_CH_B: 527 case AUX_CH_C: 528 case AUX_CH_D: 529 return DP_AUX_CH_CTL(aux_ch); 530 default: 531 MISSING_CASE(aux_ch); 532 return DP_AUX_CH_CTL(AUX_CH_B); 533 } 534 } 535 536 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) 537 { 538 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 539 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 540 enum aux_ch aux_ch = dig_port->aux_ch; 541 542 switch (aux_ch) { 543 case AUX_CH_B: 544 case AUX_CH_C: 545 case AUX_CH_D: 546 return DP_AUX_CH_DATA(aux_ch, index); 547 default: 548 MISSING_CASE(aux_ch); 549 return DP_AUX_CH_DATA(AUX_CH_B, index); 550 } 551 } 552 553 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) 554 { 555 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 556 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 557 enum aux_ch aux_ch = dig_port->aux_ch; 558 559 switch (aux_ch) { 560 case AUX_CH_A: 561 return DP_AUX_CH_CTL(aux_ch); 562 case AUX_CH_B: 563 case AUX_CH_C: 564 case AUX_CH_D: 565 return PCH_DP_AUX_CH_CTL(aux_ch); 566 default: 567 MISSING_CASE(aux_ch); 568 return DP_AUX_CH_CTL(AUX_CH_A); 569 } 570 } 571 572 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) 573 { 574 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 575 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 576 enum aux_ch aux_ch = dig_port->aux_ch; 577 578 switch (aux_ch) { 579 case AUX_CH_A: 580 return DP_AUX_CH_DATA(aux_ch, index); 581 case AUX_CH_B: 582 case AUX_CH_C: 583 case AUX_CH_D: 584 return PCH_DP_AUX_CH_DATA(aux_ch, index); 585 default: 586 MISSING_CASE(aux_ch); 587 return DP_AUX_CH_DATA(AUX_CH_A, index); 588 } 589 } 590 591 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) 592 { 593 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 594 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 595 enum aux_ch aux_ch = dig_port->aux_ch; 596 597 switch (aux_ch) { 598 case AUX_CH_A: 599 case AUX_CH_B: 600 case AUX_CH_C: 601 case AUX_CH_D: 602 case AUX_CH_E: 603 case AUX_CH_F: 604 return DP_AUX_CH_CTL(aux_ch); 605 default: 606 MISSING_CASE(aux_ch); 607 return DP_AUX_CH_CTL(AUX_CH_A); 608 } 609 } 610 611 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) 612 { 613 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 614 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 615 enum aux_ch aux_ch = dig_port->aux_ch; 616 617 switch (aux_ch) { 618 case AUX_CH_A: 619 case AUX_CH_B: 620 case AUX_CH_C: 621 case AUX_CH_D: 622 case AUX_CH_E: 623 case AUX_CH_F: 624 return DP_AUX_CH_DATA(aux_ch, index); 625 default: 626 MISSING_CASE(aux_ch); 627 return DP_AUX_CH_DATA(AUX_CH_A, index); 628 } 629 } 630 631 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) 632 { 633 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 634 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 635 enum aux_ch aux_ch = dig_port->aux_ch; 636 637 switch (aux_ch) { 638 case AUX_CH_A: 639 case AUX_CH_B: 640 case AUX_CH_C: 641 case AUX_CH_USBC1: 642 case AUX_CH_USBC2: 643 case AUX_CH_USBC3: 644 case AUX_CH_USBC4: 645 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 646 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 647 return DP_AUX_CH_CTL(aux_ch); 648 default: 649 MISSING_CASE(aux_ch); 650 return DP_AUX_CH_CTL(AUX_CH_A); 651 } 652 } 653 654 static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) 655 { 656 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 657 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 658 enum aux_ch aux_ch = dig_port->aux_ch; 659 660 switch (aux_ch) { 661 case AUX_CH_A: 662 case AUX_CH_B: 663 case AUX_CH_C: 664 case AUX_CH_USBC1: 665 case AUX_CH_USBC2: 666 case AUX_CH_USBC3: 667 case AUX_CH_USBC4: 668 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 669 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 670 return DP_AUX_CH_DATA(aux_ch, index); 671 default: 672 MISSING_CASE(aux_ch); 673 return DP_AUX_CH_DATA(AUX_CH_A, index); 674 } 675 } 676 677 static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) 678 { 679 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 680 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 681 enum aux_ch aux_ch = dig_port->aux_ch; 682 683 switch (aux_ch) { 684 case AUX_CH_A: 685 case AUX_CH_B: 686 case AUX_CH_USBC1: 687 case AUX_CH_USBC2: 688 case AUX_CH_USBC3: 689 case AUX_CH_USBC4: 690 return XELPDP_DP_AUX_CH_CTL(aux_ch); 691 default: 692 MISSING_CASE(aux_ch); 693 return XELPDP_DP_AUX_CH_CTL(AUX_CH_A); 694 } 695 } 696 697 static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index) 698 { 699 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 700 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 701 enum aux_ch aux_ch = dig_port->aux_ch; 702 703 switch (aux_ch) { 704 case AUX_CH_A: 705 case AUX_CH_B: 706 case AUX_CH_USBC1: 707 case AUX_CH_USBC2: 708 case AUX_CH_USBC3: 709 case AUX_CH_USBC4: 710 return XELPDP_DP_AUX_CH_DATA(aux_ch, index); 711 default: 712 MISSING_CASE(aux_ch); 713 return XELPDP_DP_AUX_CH_DATA(AUX_CH_A, index); 714 } 715 } 716 717 void intel_dp_aux_fini(struct intel_dp *intel_dp) 718 { 719 if (cpu_latency_qos_request_active(&intel_dp->pm_qos)) 720 cpu_latency_qos_remove_request(&intel_dp->pm_qos); 721 722 kfree(intel_dp->aux.name); 723 } 724 725 void intel_dp_aux_init(struct intel_dp *intel_dp) 726 { 727 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 728 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 729 struct intel_encoder *encoder = &dig_port->base; 730 enum aux_ch aux_ch = dig_port->aux_ch; 731 732 if (DISPLAY_VER(dev_priv) >= 14) { 733 intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg; 734 intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg; 735 } else if (DISPLAY_VER(dev_priv) >= 12) { 736 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg; 737 intel_dp->aux_ch_data_reg = tgl_aux_data_reg; 738 } else if (DISPLAY_VER(dev_priv) >= 9) { 739 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; 740 intel_dp->aux_ch_data_reg = skl_aux_data_reg; 741 } else if (HAS_PCH_SPLIT(dev_priv)) { 742 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; 743 intel_dp->aux_ch_data_reg = ilk_aux_data_reg; 744 } else { 745 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; 746 intel_dp->aux_ch_data_reg = g4x_aux_data_reg; 747 } 748 749 if (DISPLAY_VER(dev_priv) >= 9) 750 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; 751 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 752 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 753 else if (HAS_PCH_SPLIT(dev_priv)) 754 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 755 else 756 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; 757 758 if (DISPLAY_VER(dev_priv) >= 9) 759 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; 760 else 761 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; 762 763 intel_dp->aux.drm_dev = &dev_priv->drm; 764 drm_dp_aux_init(&intel_dp->aux); 765 766 /* Failure to allocate our preferred name is not critical */ 767 if (DISPLAY_VER(dev_priv) >= 13 && aux_ch >= AUX_CH_D_XELPD) 768 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s", 769 aux_ch_name(aux_ch - AUX_CH_D_XELPD + AUX_CH_D), 770 encoder->base.name); 771 else if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1) 772 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s", 773 aux_ch - AUX_CH_USBC1 + '1', 774 encoder->base.name); 775 else 776 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s", 777 aux_ch_name(aux_ch), 778 encoder->base.name); 779 780 intel_dp->aux.transfer = intel_dp_aux_transfer; 781 cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 782 } 783 784 static enum aux_ch default_aux_ch(struct intel_encoder *encoder) 785 { 786 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 787 788 /* SKL has DDI E but no AUX E */ 789 if (DISPLAY_VER(i915) == 9 && encoder->port == PORT_E) 790 return AUX_CH_A; 791 792 return (enum aux_ch)encoder->port; 793 } 794 795 enum aux_ch intel_dp_aux_ch(struct intel_encoder *encoder) 796 { 797 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 798 enum aux_ch aux_ch; 799 800 aux_ch = intel_bios_dp_aux_ch(encoder->devdata); 801 if (aux_ch != AUX_CH_NONE) { 802 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] using AUX %c (VBT)\n", 803 encoder->base.base.id, encoder->base.name, 804 aux_ch_name(aux_ch)); 805 return aux_ch; 806 } 807 808 aux_ch = default_aux_ch(encoder); 809 810 drm_dbg_kms(&i915->drm, 811 "[ENCODER:%d:%s] using AUX %c (platform default)\n", 812 encoder->base.base.id, encoder->base.name, 813 aux_ch_name(aux_ch)); 814 815 return aux_ch; 816 } 817 818 void intel_dp_aux_irq_handler(struct drm_i915_private *i915) 819 { 820 wake_up_all(&i915->display.gmbus.wait_queue); 821 } 822