1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020-2021 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "i915_trace.h" 9 #include "intel_bios.h" 10 #include "intel_de.h" 11 #include "intel_display_types.h" 12 #include "intel_dp_aux.h" 13 #include "intel_dp_aux_regs.h" 14 #include "intel_pps.h" 15 #include "intel_tc.h" 16 17 static u32 intel_dp_aux_pack(const u8 *src, int src_bytes) 18 { 19 int i; 20 u32 v = 0; 21 22 if (src_bytes > 4) 23 src_bytes = 4; 24 for (i = 0; i < src_bytes; i++) 25 v |= ((u32)src[i]) << ((3 - i) * 8); 26 return v; 27 } 28 29 static void intel_dp_aux_unpack(u32 src, u8 *dst, int dst_bytes) 30 { 31 int i; 32 33 if (dst_bytes > 4) 34 dst_bytes = 4; 35 for (i = 0; i < dst_bytes; i++) 36 dst[i] = src >> ((3 - i) * 8); 37 } 38 39 static u32 40 intel_dp_aux_wait_done(struct intel_dp *intel_dp) 41 { 42 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 43 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 44 const unsigned int timeout_ms = 10; 45 u32 status; 46 int ret; 47 48 ret = __intel_de_wait_for_register(i915, ch_ctl, 49 DP_AUX_CH_CTL_SEND_BUSY, 0, 50 2, timeout_ms, &status); 51 52 if (ret == -ETIMEDOUT) 53 drm_err(&i915->drm, 54 "%s: did not complete or timeout within %ums (status 0x%08x)\n", 55 intel_dp->aux.name, timeout_ms, status); 56 57 return status; 58 } 59 60 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 61 { 62 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 63 64 if (index) 65 return 0; 66 67 /* 68 * The clock divider is based off the hrawclk, and would like to run at 69 * 2MHz. So, take the hrawclk value and divide by 2000 and use that 70 */ 71 return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000); 72 } 73 74 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 75 { 76 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 77 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 78 u32 freq; 79 80 if (index) 81 return 0; 82 83 /* 84 * The clock divider is based off the cdclk or PCH rawclk, and would 85 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and 86 * divide by 2000 and use that 87 */ 88 if (dig_port->aux_ch == AUX_CH_A) 89 freq = dev_priv->display.cdclk.hw.cdclk; 90 else 91 freq = RUNTIME_INFO(dev_priv)->rawclk_freq; 92 return DIV_ROUND_CLOSEST(freq, 2000); 93 } 94 95 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 96 { 97 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 98 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 99 100 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) { 101 /* Workaround for non-ULT HSW */ 102 switch (index) { 103 case 0: return 63; 104 case 1: return 72; 105 default: return 0; 106 } 107 } 108 109 return ilk_get_aux_clock_divider(intel_dp, index); 110 } 111 112 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 113 { 114 /* 115 * SKL doesn't need us to program the AUX clock divider (Hardware will 116 * derive the clock from CDCLK automatically). We still implement the 117 * get_aux_clock_divider vfunc to plug-in into the existing code. 118 */ 119 return index ? 0 : 1; 120 } 121 122 static int intel_dp_aux_sync_len(void) 123 { 124 int precharge = 16; /* 10-16 */ 125 int preamble = 16; 126 127 return precharge + preamble; 128 } 129 130 static int intel_dp_aux_fw_sync_len(void) 131 { 132 int precharge = 16; /* 10-16 */ 133 int preamble = 8; 134 135 return precharge + preamble; 136 } 137 138 static int g4x_dp_aux_precharge_len(void) 139 { 140 int precharge_min = 10; 141 int preamble = 16; 142 143 /* HW wants the length of the extra precharge in 2us units */ 144 return (intel_dp_aux_sync_len() - 145 precharge_min - preamble) / 2; 146 } 147 148 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, 149 int send_bytes, 150 u32 aux_clock_divider) 151 { 152 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 153 struct drm_i915_private *dev_priv = 154 to_i915(dig_port->base.base.dev); 155 u32 timeout; 156 157 /* Max timeout value on G4x-BDW: 1.6ms */ 158 if (IS_BROADWELL(dev_priv)) 159 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 160 else 161 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 162 163 return DP_AUX_CH_CTL_SEND_BUSY | 164 DP_AUX_CH_CTL_DONE | 165 DP_AUX_CH_CTL_INTERRUPT | 166 DP_AUX_CH_CTL_TIME_OUT_ERROR | 167 timeout | 168 DP_AUX_CH_CTL_RECEIVE_ERROR | 169 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 170 (g4x_dp_aux_precharge_len() << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 171 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 172 } 173 174 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, 175 int send_bytes, 176 u32 unused) 177 { 178 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 179 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 180 u32 ret; 181 182 /* 183 * Max timeout values: 184 * SKL-GLK: 1.6ms 185 * ICL+: 4ms 186 */ 187 ret = DP_AUX_CH_CTL_SEND_BUSY | 188 DP_AUX_CH_CTL_DONE | 189 DP_AUX_CH_CTL_INTERRUPT | 190 DP_AUX_CH_CTL_TIME_OUT_ERROR | 191 DP_AUX_CH_CTL_TIME_OUT_MAX | 192 DP_AUX_CH_CTL_RECEIVE_ERROR | 193 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 194 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(intel_dp_aux_fw_sync_len()) | 195 DP_AUX_CH_CTL_SYNC_PULSE_SKL(intel_dp_aux_sync_len()); 196 197 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 198 ret |= DP_AUX_CH_CTL_TBT_IO; 199 200 /* 201 * Power request bit is already set during aux power well enable. 202 * Preserve the bit across aux transactions. 203 */ 204 if (DISPLAY_VER(i915) >= 14) 205 ret |= XELPDP_DP_AUX_CH_CTL_POWER_REQUEST; 206 207 return ret; 208 } 209 210 static int 211 intel_dp_aux_xfer(struct intel_dp *intel_dp, 212 const u8 *send, int send_bytes, 213 u8 *recv, int recv_size, 214 u32 aux_send_ctl_flags) 215 { 216 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 217 struct drm_i915_private *i915 = 218 to_i915(dig_port->base.base.dev); 219 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 220 bool is_tc_port = intel_phy_is_tc(i915, phy); 221 i915_reg_t ch_ctl, ch_data[5]; 222 u32 aux_clock_divider; 223 enum intel_display_power_domain aux_domain; 224 intel_wakeref_t aux_wakeref; 225 intel_wakeref_t pps_wakeref; 226 int i, ret, recv_bytes; 227 int try, clock = 0; 228 u32 status; 229 bool vdd; 230 231 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 232 for (i = 0; i < ARRAY_SIZE(ch_data); i++) 233 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); 234 235 if (is_tc_port) { 236 intel_tc_port_lock(dig_port); 237 /* 238 * Abort transfers on a disconnected port as required by 239 * DP 1.4a link CTS 4.2.1.5, also avoiding the long AUX 240 * timeouts that would otherwise happen. 241 * TODO: abort the transfer on non-TC ports as well. 242 */ 243 if (!intel_tc_port_connected_locked(&dig_port->base)) { 244 ret = -ENXIO; 245 goto out_unlock; 246 } 247 } 248 249 aux_domain = intel_aux_power_domain(dig_port); 250 251 aux_wakeref = intel_display_power_get(i915, aux_domain); 252 pps_wakeref = intel_pps_lock(intel_dp); 253 254 /* 255 * We will be called with VDD already enabled for dpcd/edid/oui reads. 256 * In such cases we want to leave VDD enabled and it's up to upper layers 257 * to turn it off. But for eg. i2c-dev access we need to turn it on/off 258 * ourselves. 259 */ 260 vdd = intel_pps_vdd_on_unlocked(intel_dp); 261 262 /* 263 * dp aux is extremely sensitive to irq latency, hence request the 264 * lowest possible wakeup latency and so prevent the cpu from going into 265 * deep sleep states. 266 */ 267 cpu_latency_qos_update_request(&intel_dp->pm_qos, 0); 268 269 intel_pps_check_power_unlocked(intel_dp); 270 271 /* Try to wait for any previous AUX channel activity */ 272 for (try = 0; try < 3; try++) { 273 status = intel_de_read_notrace(i915, ch_ctl); 274 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 275 break; 276 msleep(1); 277 } 278 /* just trace the final value */ 279 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); 280 281 if (try == 3) { 282 const u32 status = intel_de_read(i915, ch_ctl); 283 284 if (status != intel_dp->aux_busy_last_status) { 285 drm_WARN(&i915->drm, 1, 286 "%s: not started (status 0x%08x)\n", 287 intel_dp->aux.name, status); 288 intel_dp->aux_busy_last_status = status; 289 } 290 291 ret = -EBUSY; 292 goto out; 293 } 294 295 /* Only 5 data registers! */ 296 if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) { 297 ret = -E2BIG; 298 goto out; 299 } 300 301 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 302 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 303 send_bytes, 304 aux_clock_divider); 305 306 send_ctl |= aux_send_ctl_flags; 307 308 /* Must try at least 3 times according to DP spec */ 309 for (try = 0; try < 5; try++) { 310 /* Load the send data into the aux channel data registers */ 311 for (i = 0; i < send_bytes; i += 4) 312 intel_de_write(i915, ch_data[i >> 2], 313 intel_dp_aux_pack(send + i, 314 send_bytes - i)); 315 316 /* Send the command and wait for it to complete */ 317 intel_de_write(i915, ch_ctl, send_ctl); 318 319 status = intel_dp_aux_wait_done(intel_dp); 320 321 /* Clear done status and any errors */ 322 intel_de_write(i915, ch_ctl, 323 status | DP_AUX_CH_CTL_DONE | 324 DP_AUX_CH_CTL_TIME_OUT_ERROR | 325 DP_AUX_CH_CTL_RECEIVE_ERROR); 326 327 /* 328 * DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 329 * 400us delay required for errors and timeouts 330 * Timeout errors from the HW already meet this 331 * requirement so skip to next iteration 332 */ 333 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) 334 continue; 335 336 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 337 usleep_range(400, 500); 338 continue; 339 } 340 if (status & DP_AUX_CH_CTL_DONE) 341 goto done; 342 } 343 } 344 345 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 346 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n", 347 intel_dp->aux.name, status); 348 ret = -EBUSY; 349 goto out; 350 } 351 352 done: 353 /* 354 * Check for timeout or receive error. Timeouts occur when the sink is 355 * not connected. 356 */ 357 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 358 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n", 359 intel_dp->aux.name, status); 360 ret = -EIO; 361 goto out; 362 } 363 364 /* 365 * Timeouts occur when the device isn't connected, so they're "normal" 366 * -- don't fill the kernel log with these 367 */ 368 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 369 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n", 370 intel_dp->aux.name, status); 371 ret = -ETIMEDOUT; 372 goto out; 373 } 374 375 /* Unload any bytes sent back from the other side */ 376 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 377 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 378 379 /* 380 * By BSpec: "Message sizes of 0 or >20 are not allowed." 381 * We have no idea of what happened so we return -EBUSY so 382 * drm layer takes care for the necessary retries. 383 */ 384 if (recv_bytes == 0 || recv_bytes > 20) { 385 drm_dbg_kms(&i915->drm, 386 "%s: Forbidden recv_bytes = %d on aux transaction\n", 387 intel_dp->aux.name, recv_bytes); 388 ret = -EBUSY; 389 goto out; 390 } 391 392 if (recv_bytes > recv_size) 393 recv_bytes = recv_size; 394 395 for (i = 0; i < recv_bytes; i += 4) 396 intel_dp_aux_unpack(intel_de_read(i915, ch_data[i >> 2]), 397 recv + i, recv_bytes - i); 398 399 ret = recv_bytes; 400 out: 401 cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 402 403 if (vdd) 404 intel_pps_vdd_off_unlocked(intel_dp, false); 405 406 intel_pps_unlock(intel_dp, pps_wakeref); 407 intel_display_power_put_async(i915, aux_domain, aux_wakeref); 408 out_unlock: 409 if (is_tc_port) 410 intel_tc_port_unlock(dig_port); 411 412 return ret; 413 } 414 415 #define BARE_ADDRESS_SIZE 3 416 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 417 418 static void 419 intel_dp_aux_header(u8 txbuf[HEADER_SIZE], 420 const struct drm_dp_aux_msg *msg) 421 { 422 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); 423 txbuf[1] = (msg->address >> 8) & 0xff; 424 txbuf[2] = msg->address & 0xff; 425 txbuf[3] = msg->size - 1; 426 } 427 428 static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg) 429 { 430 /* 431 * If we're trying to send the HDCP Aksv, we need to set a the Aksv 432 * select bit to inform the hardware to send the Aksv after our header 433 * since we can't access that data from software. 434 */ 435 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE && 436 msg->address == DP_AUX_HDCP_AKSV) 437 return DP_AUX_CH_CTL_AUX_AKSV_SELECT; 438 439 return 0; 440 } 441 442 static ssize_t 443 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 444 { 445 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 446 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 447 u8 txbuf[20], rxbuf[20]; 448 size_t txsize, rxsize; 449 u32 flags = intel_dp_aux_xfer_flags(msg); 450 int ret; 451 452 intel_dp_aux_header(txbuf, msg); 453 454 switch (msg->request & ~DP_AUX_I2C_MOT) { 455 case DP_AUX_NATIVE_WRITE: 456 case DP_AUX_I2C_WRITE: 457 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 458 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 459 rxsize = 2; /* 0 or 1 data bytes */ 460 461 if (drm_WARN_ON(&i915->drm, txsize > 20)) 462 return -E2BIG; 463 464 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size); 465 466 if (msg->buffer) 467 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 468 469 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 470 rxbuf, rxsize, flags); 471 if (ret > 0) { 472 msg->reply = rxbuf[0] >> 4; 473 474 if (ret > 1) { 475 /* Number of bytes written in a short write. */ 476 ret = clamp_t(int, rxbuf[1], 0, msg->size); 477 } else { 478 /* Return payload size. */ 479 ret = msg->size; 480 } 481 } 482 break; 483 484 case DP_AUX_NATIVE_READ: 485 case DP_AUX_I2C_READ: 486 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 487 rxsize = msg->size + 1; 488 489 if (drm_WARN_ON(&i915->drm, rxsize > 20)) 490 return -E2BIG; 491 492 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 493 rxbuf, rxsize, flags); 494 if (ret > 0) { 495 msg->reply = rxbuf[0] >> 4; 496 /* 497 * Assume happy day, and copy the data. The caller is 498 * expected to check msg->reply before touching it. 499 * 500 * Return payload size. 501 */ 502 ret--; 503 memcpy(msg->buffer, rxbuf + 1, ret); 504 } 505 break; 506 507 default: 508 ret = -EINVAL; 509 break; 510 } 511 512 return ret; 513 } 514 515 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) 516 { 517 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 518 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 519 enum aux_ch aux_ch = dig_port->aux_ch; 520 521 switch (aux_ch) { 522 case AUX_CH_B: 523 case AUX_CH_C: 524 case AUX_CH_D: 525 return DP_AUX_CH_CTL(aux_ch); 526 default: 527 MISSING_CASE(aux_ch); 528 return DP_AUX_CH_CTL(AUX_CH_B); 529 } 530 } 531 532 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) 533 { 534 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 535 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 536 enum aux_ch aux_ch = dig_port->aux_ch; 537 538 switch (aux_ch) { 539 case AUX_CH_B: 540 case AUX_CH_C: 541 case AUX_CH_D: 542 return DP_AUX_CH_DATA(aux_ch, index); 543 default: 544 MISSING_CASE(aux_ch); 545 return DP_AUX_CH_DATA(AUX_CH_B, index); 546 } 547 } 548 549 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) 550 { 551 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 552 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 553 enum aux_ch aux_ch = dig_port->aux_ch; 554 555 switch (aux_ch) { 556 case AUX_CH_A: 557 return DP_AUX_CH_CTL(aux_ch); 558 case AUX_CH_B: 559 case AUX_CH_C: 560 case AUX_CH_D: 561 return PCH_DP_AUX_CH_CTL(aux_ch); 562 default: 563 MISSING_CASE(aux_ch); 564 return DP_AUX_CH_CTL(AUX_CH_A); 565 } 566 } 567 568 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) 569 { 570 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 571 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 572 enum aux_ch aux_ch = dig_port->aux_ch; 573 574 switch (aux_ch) { 575 case AUX_CH_A: 576 return DP_AUX_CH_DATA(aux_ch, index); 577 case AUX_CH_B: 578 case AUX_CH_C: 579 case AUX_CH_D: 580 return PCH_DP_AUX_CH_DATA(aux_ch, index); 581 default: 582 MISSING_CASE(aux_ch); 583 return DP_AUX_CH_DATA(AUX_CH_A, index); 584 } 585 } 586 587 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) 588 { 589 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 590 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 591 enum aux_ch aux_ch = dig_port->aux_ch; 592 593 switch (aux_ch) { 594 case AUX_CH_A: 595 case AUX_CH_B: 596 case AUX_CH_C: 597 case AUX_CH_D: 598 case AUX_CH_E: 599 case AUX_CH_F: 600 return DP_AUX_CH_CTL(aux_ch); 601 default: 602 MISSING_CASE(aux_ch); 603 return DP_AUX_CH_CTL(AUX_CH_A); 604 } 605 } 606 607 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) 608 { 609 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 610 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 611 enum aux_ch aux_ch = dig_port->aux_ch; 612 613 switch (aux_ch) { 614 case AUX_CH_A: 615 case AUX_CH_B: 616 case AUX_CH_C: 617 case AUX_CH_D: 618 case AUX_CH_E: 619 case AUX_CH_F: 620 return DP_AUX_CH_DATA(aux_ch, index); 621 default: 622 MISSING_CASE(aux_ch); 623 return DP_AUX_CH_DATA(AUX_CH_A, index); 624 } 625 } 626 627 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) 628 { 629 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 630 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 631 enum aux_ch aux_ch = dig_port->aux_ch; 632 633 switch (aux_ch) { 634 case AUX_CH_A: 635 case AUX_CH_B: 636 case AUX_CH_C: 637 case AUX_CH_USBC1: 638 case AUX_CH_USBC2: 639 case AUX_CH_USBC3: 640 case AUX_CH_USBC4: 641 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 642 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 643 return DP_AUX_CH_CTL(aux_ch); 644 default: 645 MISSING_CASE(aux_ch); 646 return DP_AUX_CH_CTL(AUX_CH_A); 647 } 648 } 649 650 static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) 651 { 652 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 653 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 654 enum aux_ch aux_ch = dig_port->aux_ch; 655 656 switch (aux_ch) { 657 case AUX_CH_A: 658 case AUX_CH_B: 659 case AUX_CH_C: 660 case AUX_CH_USBC1: 661 case AUX_CH_USBC2: 662 case AUX_CH_USBC3: 663 case AUX_CH_USBC4: 664 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 665 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 666 return DP_AUX_CH_DATA(aux_ch, index); 667 default: 668 MISSING_CASE(aux_ch); 669 return DP_AUX_CH_DATA(AUX_CH_A, index); 670 } 671 } 672 673 static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) 674 { 675 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 676 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 677 enum aux_ch aux_ch = dig_port->aux_ch; 678 679 switch (aux_ch) { 680 case AUX_CH_A: 681 case AUX_CH_B: 682 case AUX_CH_USBC1: 683 case AUX_CH_USBC2: 684 case AUX_CH_USBC3: 685 case AUX_CH_USBC4: 686 return XELPDP_DP_AUX_CH_CTL(aux_ch); 687 default: 688 MISSING_CASE(aux_ch); 689 return XELPDP_DP_AUX_CH_CTL(AUX_CH_A); 690 } 691 } 692 693 static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index) 694 { 695 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 696 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 697 enum aux_ch aux_ch = dig_port->aux_ch; 698 699 switch (aux_ch) { 700 case AUX_CH_A: 701 case AUX_CH_B: 702 case AUX_CH_USBC1: 703 case AUX_CH_USBC2: 704 case AUX_CH_USBC3: 705 case AUX_CH_USBC4: 706 return XELPDP_DP_AUX_CH_DATA(aux_ch, index); 707 default: 708 MISSING_CASE(aux_ch); 709 return XELPDP_DP_AUX_CH_DATA(AUX_CH_A, index); 710 } 711 } 712 713 void intel_dp_aux_fini(struct intel_dp *intel_dp) 714 { 715 if (cpu_latency_qos_request_active(&intel_dp->pm_qos)) 716 cpu_latency_qos_remove_request(&intel_dp->pm_qos); 717 718 kfree(intel_dp->aux.name); 719 } 720 721 void intel_dp_aux_init(struct intel_dp *intel_dp) 722 { 723 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 724 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 725 struct intel_encoder *encoder = &dig_port->base; 726 enum aux_ch aux_ch = dig_port->aux_ch; 727 728 if (DISPLAY_VER(dev_priv) >= 14) { 729 intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg; 730 intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg; 731 } else if (DISPLAY_VER(dev_priv) >= 12) { 732 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg; 733 intel_dp->aux_ch_data_reg = tgl_aux_data_reg; 734 } else if (DISPLAY_VER(dev_priv) >= 9) { 735 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; 736 intel_dp->aux_ch_data_reg = skl_aux_data_reg; 737 } else if (HAS_PCH_SPLIT(dev_priv)) { 738 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; 739 intel_dp->aux_ch_data_reg = ilk_aux_data_reg; 740 } else { 741 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; 742 intel_dp->aux_ch_data_reg = g4x_aux_data_reg; 743 } 744 745 if (DISPLAY_VER(dev_priv) >= 9) 746 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; 747 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 748 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 749 else if (HAS_PCH_SPLIT(dev_priv)) 750 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 751 else 752 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; 753 754 if (DISPLAY_VER(dev_priv) >= 9) 755 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; 756 else 757 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; 758 759 intel_dp->aux.drm_dev = &dev_priv->drm; 760 drm_dp_aux_init(&intel_dp->aux); 761 762 /* Failure to allocate our preferred name is not critical */ 763 if (DISPLAY_VER(dev_priv) >= 13 && aux_ch >= AUX_CH_D_XELPD) 764 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s", 765 aux_ch_name(aux_ch - AUX_CH_D_XELPD + AUX_CH_D), 766 encoder->base.name); 767 else if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1) 768 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s", 769 aux_ch - AUX_CH_USBC1 + '1', 770 encoder->base.name); 771 else 772 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s", 773 aux_ch_name(aux_ch), 774 encoder->base.name); 775 776 intel_dp->aux.transfer = intel_dp_aux_transfer; 777 cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 778 } 779 780 static enum aux_ch default_aux_ch(struct intel_encoder *encoder) 781 { 782 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 783 784 /* SKL has DDI E but no AUX E */ 785 if (DISPLAY_VER(i915) == 9 && encoder->port == PORT_E) 786 return AUX_CH_A; 787 788 return (enum aux_ch)encoder->port; 789 } 790 791 enum aux_ch intel_dp_aux_ch(struct intel_encoder *encoder) 792 { 793 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 794 enum aux_ch aux_ch; 795 796 aux_ch = intel_bios_dp_aux_ch(encoder->devdata); 797 if (aux_ch != AUX_CH_NONE) { 798 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] using AUX %c (VBT)\n", 799 encoder->base.base.id, encoder->base.name, 800 aux_ch_name(aux_ch)); 801 return aux_ch; 802 } 803 804 aux_ch = default_aux_ch(encoder); 805 806 drm_dbg_kms(&i915->drm, 807 "[ENCODER:%d:%s] using AUX %c (platform default)\n", 808 encoder->base.base.id, encoder->base.name, 809 aux_ch_name(aux_ch)); 810 811 return aux_ch; 812 } 813