1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020-2021 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "i915_trace.h" 9 #include "intel_bios.h" 10 #include "intel_de.h" 11 #include "intel_display_types.h" 12 #include "intel_dp_aux.h" 13 #include "intel_pps.h" 14 #include "intel_tc.h" 15 16 static u32 intel_dp_aux_pack(const u8 *src, int src_bytes) 17 { 18 int i; 19 u32 v = 0; 20 21 if (src_bytes > 4) 22 src_bytes = 4; 23 for (i = 0; i < src_bytes; i++) 24 v |= ((u32)src[i]) << ((3 - i) * 8); 25 return v; 26 } 27 28 static void intel_dp_aux_unpack(u32 src, u8 *dst, int dst_bytes) 29 { 30 int i; 31 32 if (dst_bytes > 4) 33 dst_bytes = 4; 34 for (i = 0; i < dst_bytes; i++) 35 dst[i] = src >> ((3 - i) * 8); 36 } 37 38 static u32 39 intel_dp_aux_wait_done(struct intel_dp *intel_dp) 40 { 41 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 42 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 43 const unsigned int timeout_ms = 10; 44 u32 status; 45 int ret; 46 47 ret = __intel_de_wait_for_register(i915, ch_ctl, 48 DP_AUX_CH_CTL_SEND_BUSY, 0, 49 2, timeout_ms, &status); 50 51 if (ret == -ETIMEDOUT) 52 drm_err(&i915->drm, 53 "%s: did not complete or timeout within %ums (status 0x%08x)\n", 54 intel_dp->aux.name, timeout_ms, status); 55 56 return status; 57 } 58 59 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 60 { 61 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 62 63 if (index) 64 return 0; 65 66 /* 67 * The clock divider is based off the hrawclk, and would like to run at 68 * 2MHz. So, take the hrawclk value and divide by 2000 and use that 69 */ 70 return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000); 71 } 72 73 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 74 { 75 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 76 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 77 u32 freq; 78 79 if (index) 80 return 0; 81 82 /* 83 * The clock divider is based off the cdclk or PCH rawclk, and would 84 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and 85 * divide by 2000 and use that 86 */ 87 if (dig_port->aux_ch == AUX_CH_A) 88 freq = dev_priv->display.cdclk.hw.cdclk; 89 else 90 freq = RUNTIME_INFO(dev_priv)->rawclk_freq; 91 return DIV_ROUND_CLOSEST(freq, 2000); 92 } 93 94 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 95 { 96 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 97 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 98 99 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) { 100 /* Workaround for non-ULT HSW */ 101 switch (index) { 102 case 0: return 63; 103 case 1: return 72; 104 default: return 0; 105 } 106 } 107 108 return ilk_get_aux_clock_divider(intel_dp, index); 109 } 110 111 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 112 { 113 /* 114 * SKL doesn't need us to program the AUX clock divider (Hardware will 115 * derive the clock from CDCLK automatically). We still implement the 116 * get_aux_clock_divider vfunc to plug-in into the existing code. 117 */ 118 return index ? 0 : 1; 119 } 120 121 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, 122 int send_bytes, 123 u32 aux_clock_divider) 124 { 125 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 126 struct drm_i915_private *dev_priv = 127 to_i915(dig_port->base.base.dev); 128 u32 timeout; 129 130 /* Max timeout value on G4x-BDW: 1.6ms */ 131 if (IS_BROADWELL(dev_priv)) 132 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 133 else 134 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 135 136 return DP_AUX_CH_CTL_SEND_BUSY | 137 DP_AUX_CH_CTL_DONE | 138 DP_AUX_CH_CTL_INTERRUPT | 139 DP_AUX_CH_CTL_TIME_OUT_ERROR | 140 timeout | 141 DP_AUX_CH_CTL_RECEIVE_ERROR | 142 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 143 (3 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 144 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 145 } 146 147 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, 148 int send_bytes, 149 u32 unused) 150 { 151 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 152 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 153 u32 ret; 154 155 /* 156 * Max timeout values: 157 * SKL-GLK: 1.6ms 158 * ICL+: 4ms 159 */ 160 ret = DP_AUX_CH_CTL_SEND_BUSY | 161 DP_AUX_CH_CTL_DONE | 162 DP_AUX_CH_CTL_INTERRUPT | 163 DP_AUX_CH_CTL_TIME_OUT_ERROR | 164 DP_AUX_CH_CTL_TIME_OUT_MAX | 165 DP_AUX_CH_CTL_RECEIVE_ERROR | 166 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 167 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | 168 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); 169 170 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 171 ret |= DP_AUX_CH_CTL_TBT_IO; 172 173 /* 174 * Power request bit is already set during aux power well enable. 175 * Preserve the bit across aux transactions. 176 */ 177 if (DISPLAY_VER(i915) >= 14) 178 ret |= XELPDP_DP_AUX_CH_CTL_POWER_REQUEST; 179 180 return ret; 181 } 182 183 static int 184 intel_dp_aux_xfer(struct intel_dp *intel_dp, 185 const u8 *send, int send_bytes, 186 u8 *recv, int recv_size, 187 u32 aux_send_ctl_flags) 188 { 189 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 190 struct drm_i915_private *i915 = 191 to_i915(dig_port->base.base.dev); 192 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 193 bool is_tc_port = intel_phy_is_tc(i915, phy); 194 i915_reg_t ch_ctl, ch_data[5]; 195 u32 aux_clock_divider; 196 enum intel_display_power_domain aux_domain; 197 intel_wakeref_t aux_wakeref; 198 intel_wakeref_t pps_wakeref; 199 int i, ret, recv_bytes; 200 int try, clock = 0; 201 u32 status; 202 bool vdd; 203 204 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 205 for (i = 0; i < ARRAY_SIZE(ch_data); i++) 206 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); 207 208 if (is_tc_port) 209 intel_tc_port_lock(dig_port); 210 211 aux_domain = intel_aux_power_domain(dig_port); 212 213 aux_wakeref = intel_display_power_get(i915, aux_domain); 214 pps_wakeref = intel_pps_lock(intel_dp); 215 216 /* 217 * We will be called with VDD already enabled for dpcd/edid/oui reads. 218 * In such cases we want to leave VDD enabled and it's up to upper layers 219 * to turn it off. But for eg. i2c-dev access we need to turn it on/off 220 * ourselves. 221 */ 222 vdd = intel_pps_vdd_on_unlocked(intel_dp); 223 224 /* 225 * dp aux is extremely sensitive to irq latency, hence request the 226 * lowest possible wakeup latency and so prevent the cpu from going into 227 * deep sleep states. 228 */ 229 cpu_latency_qos_update_request(&intel_dp->pm_qos, 0); 230 231 intel_pps_check_power_unlocked(intel_dp); 232 233 /* Try to wait for any previous AUX channel activity */ 234 for (try = 0; try < 3; try++) { 235 status = intel_de_read_notrace(i915, ch_ctl); 236 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 237 break; 238 msleep(1); 239 } 240 /* just trace the final value */ 241 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); 242 243 if (try == 3) { 244 const u32 status = intel_de_read(i915, ch_ctl); 245 246 if (status != intel_dp->aux_busy_last_status) { 247 drm_WARN(&i915->drm, 1, 248 "%s: not started (status 0x%08x)\n", 249 intel_dp->aux.name, status); 250 intel_dp->aux_busy_last_status = status; 251 } 252 253 ret = -EBUSY; 254 goto out; 255 } 256 257 /* Only 5 data registers! */ 258 if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) { 259 ret = -E2BIG; 260 goto out; 261 } 262 263 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 264 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 265 send_bytes, 266 aux_clock_divider); 267 268 send_ctl |= aux_send_ctl_flags; 269 270 /* Must try at least 3 times according to DP spec */ 271 for (try = 0; try < 5; try++) { 272 /* Load the send data into the aux channel data registers */ 273 for (i = 0; i < send_bytes; i += 4) 274 intel_de_write(i915, ch_data[i >> 2], 275 intel_dp_aux_pack(send + i, 276 send_bytes - i)); 277 278 /* Send the command and wait for it to complete */ 279 intel_de_write(i915, ch_ctl, send_ctl); 280 281 status = intel_dp_aux_wait_done(intel_dp); 282 283 /* Clear done status and any errors */ 284 intel_de_write(i915, ch_ctl, 285 status | DP_AUX_CH_CTL_DONE | 286 DP_AUX_CH_CTL_TIME_OUT_ERROR | 287 DP_AUX_CH_CTL_RECEIVE_ERROR); 288 289 /* 290 * DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 291 * 400us delay required for errors and timeouts 292 * Timeout errors from the HW already meet this 293 * requirement so skip to next iteration 294 */ 295 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) 296 continue; 297 298 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 299 usleep_range(400, 500); 300 continue; 301 } 302 if (status & DP_AUX_CH_CTL_DONE) 303 goto done; 304 } 305 } 306 307 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 308 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n", 309 intel_dp->aux.name, status); 310 ret = -EBUSY; 311 goto out; 312 } 313 314 done: 315 /* 316 * Check for timeout or receive error. Timeouts occur when the sink is 317 * not connected. 318 */ 319 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 320 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n", 321 intel_dp->aux.name, status); 322 ret = -EIO; 323 goto out; 324 } 325 326 /* 327 * Timeouts occur when the device isn't connected, so they're "normal" 328 * -- don't fill the kernel log with these 329 */ 330 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 331 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n", 332 intel_dp->aux.name, status); 333 ret = -ETIMEDOUT; 334 goto out; 335 } 336 337 /* Unload any bytes sent back from the other side */ 338 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 339 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 340 341 /* 342 * By BSpec: "Message sizes of 0 or >20 are not allowed." 343 * We have no idea of what happened so we return -EBUSY so 344 * drm layer takes care for the necessary retries. 345 */ 346 if (recv_bytes == 0 || recv_bytes > 20) { 347 drm_dbg_kms(&i915->drm, 348 "%s: Forbidden recv_bytes = %d on aux transaction\n", 349 intel_dp->aux.name, recv_bytes); 350 ret = -EBUSY; 351 goto out; 352 } 353 354 if (recv_bytes > recv_size) 355 recv_bytes = recv_size; 356 357 for (i = 0; i < recv_bytes; i += 4) 358 intel_dp_aux_unpack(intel_de_read(i915, ch_data[i >> 2]), 359 recv + i, recv_bytes - i); 360 361 ret = recv_bytes; 362 out: 363 cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 364 365 if (vdd) 366 intel_pps_vdd_off_unlocked(intel_dp, false); 367 368 intel_pps_unlock(intel_dp, pps_wakeref); 369 intel_display_power_put_async(i915, aux_domain, aux_wakeref); 370 371 if (is_tc_port) 372 intel_tc_port_unlock(dig_port); 373 374 return ret; 375 } 376 377 #define BARE_ADDRESS_SIZE 3 378 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 379 380 static void 381 intel_dp_aux_header(u8 txbuf[HEADER_SIZE], 382 const struct drm_dp_aux_msg *msg) 383 { 384 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); 385 txbuf[1] = (msg->address >> 8) & 0xff; 386 txbuf[2] = msg->address & 0xff; 387 txbuf[3] = msg->size - 1; 388 } 389 390 static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg) 391 { 392 /* 393 * If we're trying to send the HDCP Aksv, we need to set a the Aksv 394 * select bit to inform the hardware to send the Aksv after our header 395 * since we can't access that data from software. 396 */ 397 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE && 398 msg->address == DP_AUX_HDCP_AKSV) 399 return DP_AUX_CH_CTL_AUX_AKSV_SELECT; 400 401 return 0; 402 } 403 404 static ssize_t 405 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 406 { 407 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 408 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 409 u8 txbuf[20], rxbuf[20]; 410 size_t txsize, rxsize; 411 u32 flags = intel_dp_aux_xfer_flags(msg); 412 int ret; 413 414 intel_dp_aux_header(txbuf, msg); 415 416 switch (msg->request & ~DP_AUX_I2C_MOT) { 417 case DP_AUX_NATIVE_WRITE: 418 case DP_AUX_I2C_WRITE: 419 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 420 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 421 rxsize = 2; /* 0 or 1 data bytes */ 422 423 if (drm_WARN_ON(&i915->drm, txsize > 20)) 424 return -E2BIG; 425 426 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size); 427 428 if (msg->buffer) 429 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 430 431 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 432 rxbuf, rxsize, flags); 433 if (ret > 0) { 434 msg->reply = rxbuf[0] >> 4; 435 436 if (ret > 1) { 437 /* Number of bytes written in a short write. */ 438 ret = clamp_t(int, rxbuf[1], 0, msg->size); 439 } else { 440 /* Return payload size. */ 441 ret = msg->size; 442 } 443 } 444 break; 445 446 case DP_AUX_NATIVE_READ: 447 case DP_AUX_I2C_READ: 448 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 449 rxsize = msg->size + 1; 450 451 if (drm_WARN_ON(&i915->drm, rxsize > 20)) 452 return -E2BIG; 453 454 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 455 rxbuf, rxsize, flags); 456 if (ret > 0) { 457 msg->reply = rxbuf[0] >> 4; 458 /* 459 * Assume happy day, and copy the data. The caller is 460 * expected to check msg->reply before touching it. 461 * 462 * Return payload size. 463 */ 464 ret--; 465 memcpy(msg->buffer, rxbuf + 1, ret); 466 } 467 break; 468 469 default: 470 ret = -EINVAL; 471 break; 472 } 473 474 return ret; 475 } 476 477 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) 478 { 479 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 480 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 481 enum aux_ch aux_ch = dig_port->aux_ch; 482 483 switch (aux_ch) { 484 case AUX_CH_B: 485 case AUX_CH_C: 486 case AUX_CH_D: 487 return DP_AUX_CH_CTL(aux_ch); 488 default: 489 MISSING_CASE(aux_ch); 490 return DP_AUX_CH_CTL(AUX_CH_B); 491 } 492 } 493 494 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) 495 { 496 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 497 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 498 enum aux_ch aux_ch = dig_port->aux_ch; 499 500 switch (aux_ch) { 501 case AUX_CH_B: 502 case AUX_CH_C: 503 case AUX_CH_D: 504 return DP_AUX_CH_DATA(aux_ch, index); 505 default: 506 MISSING_CASE(aux_ch); 507 return DP_AUX_CH_DATA(AUX_CH_B, index); 508 } 509 } 510 511 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) 512 { 513 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 514 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 515 enum aux_ch aux_ch = dig_port->aux_ch; 516 517 switch (aux_ch) { 518 case AUX_CH_A: 519 return DP_AUX_CH_CTL(aux_ch); 520 case AUX_CH_B: 521 case AUX_CH_C: 522 case AUX_CH_D: 523 return PCH_DP_AUX_CH_CTL(aux_ch); 524 default: 525 MISSING_CASE(aux_ch); 526 return DP_AUX_CH_CTL(AUX_CH_A); 527 } 528 } 529 530 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) 531 { 532 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 533 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 534 enum aux_ch aux_ch = dig_port->aux_ch; 535 536 switch (aux_ch) { 537 case AUX_CH_A: 538 return DP_AUX_CH_DATA(aux_ch, index); 539 case AUX_CH_B: 540 case AUX_CH_C: 541 case AUX_CH_D: 542 return PCH_DP_AUX_CH_DATA(aux_ch, index); 543 default: 544 MISSING_CASE(aux_ch); 545 return DP_AUX_CH_DATA(AUX_CH_A, index); 546 } 547 } 548 549 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) 550 { 551 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 552 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 553 enum aux_ch aux_ch = dig_port->aux_ch; 554 555 switch (aux_ch) { 556 case AUX_CH_A: 557 case AUX_CH_B: 558 case AUX_CH_C: 559 case AUX_CH_D: 560 case AUX_CH_E: 561 case AUX_CH_F: 562 return DP_AUX_CH_CTL(aux_ch); 563 default: 564 MISSING_CASE(aux_ch); 565 return DP_AUX_CH_CTL(AUX_CH_A); 566 } 567 } 568 569 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) 570 { 571 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 572 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 573 enum aux_ch aux_ch = dig_port->aux_ch; 574 575 switch (aux_ch) { 576 case AUX_CH_A: 577 case AUX_CH_B: 578 case AUX_CH_C: 579 case AUX_CH_D: 580 case AUX_CH_E: 581 case AUX_CH_F: 582 return DP_AUX_CH_DATA(aux_ch, index); 583 default: 584 MISSING_CASE(aux_ch); 585 return DP_AUX_CH_DATA(AUX_CH_A, index); 586 } 587 } 588 589 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) 590 { 591 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 592 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 593 enum aux_ch aux_ch = dig_port->aux_ch; 594 595 switch (aux_ch) { 596 case AUX_CH_A: 597 case AUX_CH_B: 598 case AUX_CH_C: 599 case AUX_CH_USBC1: 600 case AUX_CH_USBC2: 601 case AUX_CH_USBC3: 602 case AUX_CH_USBC4: 603 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 604 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 605 return DP_AUX_CH_CTL(aux_ch); 606 default: 607 MISSING_CASE(aux_ch); 608 return DP_AUX_CH_CTL(AUX_CH_A); 609 } 610 } 611 612 static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) 613 { 614 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 615 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 616 enum aux_ch aux_ch = dig_port->aux_ch; 617 618 switch (aux_ch) { 619 case AUX_CH_A: 620 case AUX_CH_B: 621 case AUX_CH_C: 622 case AUX_CH_USBC1: 623 case AUX_CH_USBC2: 624 case AUX_CH_USBC3: 625 case AUX_CH_USBC4: 626 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 627 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 628 return DP_AUX_CH_DATA(aux_ch, index); 629 default: 630 MISSING_CASE(aux_ch); 631 return DP_AUX_CH_DATA(AUX_CH_A, index); 632 } 633 } 634 635 static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) 636 { 637 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 638 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 639 enum aux_ch aux_ch = dig_port->aux_ch; 640 641 switch (aux_ch) { 642 case AUX_CH_A: 643 case AUX_CH_B: 644 case AUX_CH_USBC1: 645 case AUX_CH_USBC2: 646 case AUX_CH_USBC3: 647 case AUX_CH_USBC4: 648 return XELPDP_DP_AUX_CH_CTL(aux_ch); 649 default: 650 MISSING_CASE(aux_ch); 651 return XELPDP_DP_AUX_CH_CTL(AUX_CH_A); 652 } 653 } 654 655 static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index) 656 { 657 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 658 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 659 enum aux_ch aux_ch = dig_port->aux_ch; 660 661 switch (aux_ch) { 662 case AUX_CH_A: 663 case AUX_CH_B: 664 case AUX_CH_USBC1: 665 case AUX_CH_USBC2: 666 case AUX_CH_USBC3: 667 case AUX_CH_USBC4: 668 return XELPDP_DP_AUX_CH_DATA(aux_ch, index); 669 default: 670 MISSING_CASE(aux_ch); 671 return XELPDP_DP_AUX_CH_DATA(AUX_CH_A, index); 672 } 673 } 674 675 void intel_dp_aux_fini(struct intel_dp *intel_dp) 676 { 677 if (cpu_latency_qos_request_active(&intel_dp->pm_qos)) 678 cpu_latency_qos_remove_request(&intel_dp->pm_qos); 679 680 kfree(intel_dp->aux.name); 681 } 682 683 void intel_dp_aux_init(struct intel_dp *intel_dp) 684 { 685 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 686 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 687 struct intel_encoder *encoder = &dig_port->base; 688 enum aux_ch aux_ch = dig_port->aux_ch; 689 690 if (DISPLAY_VER(dev_priv) >= 14) { 691 intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg; 692 intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg; 693 } else if (DISPLAY_VER(dev_priv) >= 12) { 694 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg; 695 intel_dp->aux_ch_data_reg = tgl_aux_data_reg; 696 } else if (DISPLAY_VER(dev_priv) >= 9) { 697 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; 698 intel_dp->aux_ch_data_reg = skl_aux_data_reg; 699 } else if (HAS_PCH_SPLIT(dev_priv)) { 700 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; 701 intel_dp->aux_ch_data_reg = ilk_aux_data_reg; 702 } else { 703 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; 704 intel_dp->aux_ch_data_reg = g4x_aux_data_reg; 705 } 706 707 if (DISPLAY_VER(dev_priv) >= 9) 708 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; 709 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 710 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 711 else if (HAS_PCH_SPLIT(dev_priv)) 712 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 713 else 714 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; 715 716 if (DISPLAY_VER(dev_priv) >= 9) 717 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; 718 else 719 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; 720 721 intel_dp->aux.drm_dev = &dev_priv->drm; 722 drm_dp_aux_init(&intel_dp->aux); 723 724 /* Failure to allocate our preferred name is not critical */ 725 if (DISPLAY_VER(dev_priv) >= 13 && aux_ch >= AUX_CH_D_XELPD) 726 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s", 727 aux_ch_name(aux_ch - AUX_CH_D_XELPD + AUX_CH_D), 728 encoder->base.name); 729 else if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1) 730 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s", 731 aux_ch - AUX_CH_USBC1 + '1', 732 encoder->base.name); 733 else 734 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s", 735 aux_ch_name(aux_ch), 736 encoder->base.name); 737 738 intel_dp->aux.transfer = intel_dp_aux_transfer; 739 cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 740 } 741 742 static enum aux_ch default_aux_ch(struct intel_encoder *encoder) 743 { 744 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 745 746 /* SKL has DDI E but no AUX E */ 747 if (DISPLAY_VER(i915) == 9 && encoder->port == PORT_E) 748 return AUX_CH_A; 749 750 return (enum aux_ch)encoder->port; 751 } 752 753 enum aux_ch intel_dp_aux_ch(struct intel_encoder *encoder) 754 { 755 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 756 enum aux_ch aux_ch; 757 758 aux_ch = intel_bios_dp_aux_ch(encoder->devdata); 759 if (aux_ch != AUX_CH_NONE) { 760 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] using AUX %c (VBT)\n", 761 encoder->base.base.id, encoder->base.name, 762 aux_ch_name(aux_ch)); 763 return aux_ch; 764 } 765 766 aux_ch = default_aux_ch(encoder); 767 768 drm_dbg_kms(&i915->drm, 769 "[ENCODER:%d:%s] using AUX %c (platform default)\n", 770 encoder->base.base.id, encoder->base.name, 771 aux_ch_name(aux_ch)); 772 773 return aux_ch; 774 } 775