1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2020-2021 Intel Corporation 4 */ 5 6 #include "i915_drv.h" 7 #include "i915_reg.h" 8 #include "i915_trace.h" 9 #include "intel_bios.h" 10 #include "intel_de.h" 11 #include "intel_display_types.h" 12 #include "intel_dp_aux.h" 13 #include "intel_pps.h" 14 #include "intel_tc.h" 15 16 static u32 intel_dp_aux_pack(const u8 *src, int src_bytes) 17 { 18 int i; 19 u32 v = 0; 20 21 if (src_bytes > 4) 22 src_bytes = 4; 23 for (i = 0; i < src_bytes; i++) 24 v |= ((u32)src[i]) << ((3 - i) * 8); 25 return v; 26 } 27 28 static void intel_dp_aux_unpack(u32 src, u8 *dst, int dst_bytes) 29 { 30 int i; 31 32 if (dst_bytes > 4) 33 dst_bytes = 4; 34 for (i = 0; i < dst_bytes; i++) 35 dst[i] = src >> ((3 - i) * 8); 36 } 37 38 static u32 39 intel_dp_aux_wait_done(struct intel_dp *intel_dp) 40 { 41 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 42 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 43 const unsigned int timeout_ms = 10; 44 u32 status; 45 int ret; 46 47 ret = __intel_de_wait_for_register(i915, ch_ctl, 48 DP_AUX_CH_CTL_SEND_BUSY, 0, 49 2, timeout_ms, &status); 50 51 if (ret == -ETIMEDOUT) 52 drm_err(&i915->drm, 53 "%s: did not complete or timeout within %ums (status 0x%08x)\n", 54 intel_dp->aux.name, timeout_ms, status); 55 56 return status; 57 } 58 59 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 60 { 61 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 62 63 if (index) 64 return 0; 65 66 /* 67 * The clock divider is based off the hrawclk, and would like to run at 68 * 2MHz. So, take the hrawclk value and divide by 2000 and use that 69 */ 70 return DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq, 2000); 71 } 72 73 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 74 { 75 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 76 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 77 u32 freq; 78 79 if (index) 80 return 0; 81 82 /* 83 * The clock divider is based off the cdclk or PCH rawclk, and would 84 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and 85 * divide by 2000 and use that 86 */ 87 if (dig_port->aux_ch == AUX_CH_A) 88 freq = dev_priv->display.cdclk.hw.cdclk; 89 else 90 freq = RUNTIME_INFO(dev_priv)->rawclk_freq; 91 return DIV_ROUND_CLOSEST(freq, 2000); 92 } 93 94 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 95 { 96 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 97 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 98 99 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) { 100 /* Workaround for non-ULT HSW */ 101 switch (index) { 102 case 0: return 63; 103 case 1: return 72; 104 default: return 0; 105 } 106 } 107 108 return ilk_get_aux_clock_divider(intel_dp, index); 109 } 110 111 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 112 { 113 /* 114 * SKL doesn't need us to program the AUX clock divider (Hardware will 115 * derive the clock from CDCLK automatically). We still implement the 116 * get_aux_clock_divider vfunc to plug-in into the existing code. 117 */ 118 return index ? 0 : 1; 119 } 120 121 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, 122 int send_bytes, 123 u32 aux_clock_divider) 124 { 125 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 126 struct drm_i915_private *dev_priv = 127 to_i915(dig_port->base.base.dev); 128 u32 timeout; 129 130 /* Max timeout value on G4x-BDW: 1.6ms */ 131 if (IS_BROADWELL(dev_priv)) 132 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 133 else 134 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 135 136 return DP_AUX_CH_CTL_SEND_BUSY | 137 DP_AUX_CH_CTL_DONE | 138 DP_AUX_CH_CTL_INTERRUPT | 139 DP_AUX_CH_CTL_TIME_OUT_ERROR | 140 timeout | 141 DP_AUX_CH_CTL_RECEIVE_ERROR | 142 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 143 (3 << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 144 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 145 } 146 147 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, 148 int send_bytes, 149 u32 unused) 150 { 151 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 152 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 153 u32 ret; 154 155 /* 156 * Max timeout values: 157 * SKL-GLK: 1.6ms 158 * ICL+: 4ms 159 */ 160 ret = DP_AUX_CH_CTL_SEND_BUSY | 161 DP_AUX_CH_CTL_DONE | 162 DP_AUX_CH_CTL_INTERRUPT | 163 DP_AUX_CH_CTL_TIME_OUT_ERROR | 164 DP_AUX_CH_CTL_TIME_OUT_MAX | 165 DP_AUX_CH_CTL_RECEIVE_ERROR | 166 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 167 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | 168 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); 169 170 if (intel_tc_port_in_tbt_alt_mode(dig_port)) 171 ret |= DP_AUX_CH_CTL_TBT_IO; 172 173 /* 174 * Power request bit is already set during aux power well enable. 175 * Preserve the bit across aux transactions. 176 */ 177 if (DISPLAY_VER(i915) >= 14) 178 ret |= XELPDP_DP_AUX_CH_CTL_POWER_REQUEST; 179 180 return ret; 181 } 182 183 static int 184 intel_dp_aux_xfer(struct intel_dp *intel_dp, 185 const u8 *send, int send_bytes, 186 u8 *recv, int recv_size, 187 u32 aux_send_ctl_flags) 188 { 189 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 190 struct drm_i915_private *i915 = 191 to_i915(dig_port->base.base.dev); 192 enum phy phy = intel_port_to_phy(i915, dig_port->base.port); 193 bool is_tc_port = intel_phy_is_tc(i915, phy); 194 i915_reg_t ch_ctl, ch_data[5]; 195 u32 aux_clock_divider; 196 enum intel_display_power_domain aux_domain; 197 intel_wakeref_t aux_wakeref; 198 intel_wakeref_t pps_wakeref; 199 int i, ret, recv_bytes; 200 int try, clock = 0; 201 u32 status; 202 bool vdd; 203 204 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 205 for (i = 0; i < ARRAY_SIZE(ch_data); i++) 206 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); 207 208 if (is_tc_port) { 209 intel_tc_port_lock(dig_port); 210 /* 211 * Abort transfers on a disconnected port as required by 212 * DP 1.4a link CTS 4.2.1.5, also avoiding the long AUX 213 * timeouts that would otherwise happen. 214 * TODO: abort the transfer on non-TC ports as well. 215 */ 216 if (!intel_tc_port_connected_locked(&dig_port->base)) { 217 ret = -ENXIO; 218 goto out_unlock; 219 } 220 } 221 222 aux_domain = intel_aux_power_domain(dig_port); 223 224 aux_wakeref = intel_display_power_get(i915, aux_domain); 225 pps_wakeref = intel_pps_lock(intel_dp); 226 227 /* 228 * We will be called with VDD already enabled for dpcd/edid/oui reads. 229 * In such cases we want to leave VDD enabled and it's up to upper layers 230 * to turn it off. But for eg. i2c-dev access we need to turn it on/off 231 * ourselves. 232 */ 233 vdd = intel_pps_vdd_on_unlocked(intel_dp); 234 235 /* 236 * dp aux is extremely sensitive to irq latency, hence request the 237 * lowest possible wakeup latency and so prevent the cpu from going into 238 * deep sleep states. 239 */ 240 cpu_latency_qos_update_request(&intel_dp->pm_qos, 0); 241 242 intel_pps_check_power_unlocked(intel_dp); 243 244 /* Try to wait for any previous AUX channel activity */ 245 for (try = 0; try < 3; try++) { 246 status = intel_de_read_notrace(i915, ch_ctl); 247 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 248 break; 249 msleep(1); 250 } 251 /* just trace the final value */ 252 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); 253 254 if (try == 3) { 255 const u32 status = intel_de_read(i915, ch_ctl); 256 257 if (status != intel_dp->aux_busy_last_status) { 258 drm_WARN(&i915->drm, 1, 259 "%s: not started (status 0x%08x)\n", 260 intel_dp->aux.name, status); 261 intel_dp->aux_busy_last_status = status; 262 } 263 264 ret = -EBUSY; 265 goto out; 266 } 267 268 /* Only 5 data registers! */ 269 if (drm_WARN_ON(&i915->drm, send_bytes > 20 || recv_size > 20)) { 270 ret = -E2BIG; 271 goto out; 272 } 273 274 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 275 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 276 send_bytes, 277 aux_clock_divider); 278 279 send_ctl |= aux_send_ctl_flags; 280 281 /* Must try at least 3 times according to DP spec */ 282 for (try = 0; try < 5; try++) { 283 /* Load the send data into the aux channel data registers */ 284 for (i = 0; i < send_bytes; i += 4) 285 intel_de_write(i915, ch_data[i >> 2], 286 intel_dp_aux_pack(send + i, 287 send_bytes - i)); 288 289 /* Send the command and wait for it to complete */ 290 intel_de_write(i915, ch_ctl, send_ctl); 291 292 status = intel_dp_aux_wait_done(intel_dp); 293 294 /* Clear done status and any errors */ 295 intel_de_write(i915, ch_ctl, 296 status | DP_AUX_CH_CTL_DONE | 297 DP_AUX_CH_CTL_TIME_OUT_ERROR | 298 DP_AUX_CH_CTL_RECEIVE_ERROR); 299 300 /* 301 * DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 302 * 400us delay required for errors and timeouts 303 * Timeout errors from the HW already meet this 304 * requirement so skip to next iteration 305 */ 306 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) 307 continue; 308 309 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 310 usleep_range(400, 500); 311 continue; 312 } 313 if (status & DP_AUX_CH_CTL_DONE) 314 goto done; 315 } 316 } 317 318 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 319 drm_err(&i915->drm, "%s: not done (status 0x%08x)\n", 320 intel_dp->aux.name, status); 321 ret = -EBUSY; 322 goto out; 323 } 324 325 done: 326 /* 327 * Check for timeout or receive error. Timeouts occur when the sink is 328 * not connected. 329 */ 330 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 331 drm_err(&i915->drm, "%s: receive error (status 0x%08x)\n", 332 intel_dp->aux.name, status); 333 ret = -EIO; 334 goto out; 335 } 336 337 /* 338 * Timeouts occur when the device isn't connected, so they're "normal" 339 * -- don't fill the kernel log with these 340 */ 341 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 342 drm_dbg_kms(&i915->drm, "%s: timeout (status 0x%08x)\n", 343 intel_dp->aux.name, status); 344 ret = -ETIMEDOUT; 345 goto out; 346 } 347 348 /* Unload any bytes sent back from the other side */ 349 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 350 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 351 352 /* 353 * By BSpec: "Message sizes of 0 or >20 are not allowed." 354 * We have no idea of what happened so we return -EBUSY so 355 * drm layer takes care for the necessary retries. 356 */ 357 if (recv_bytes == 0 || recv_bytes > 20) { 358 drm_dbg_kms(&i915->drm, 359 "%s: Forbidden recv_bytes = %d on aux transaction\n", 360 intel_dp->aux.name, recv_bytes); 361 ret = -EBUSY; 362 goto out; 363 } 364 365 if (recv_bytes > recv_size) 366 recv_bytes = recv_size; 367 368 for (i = 0; i < recv_bytes; i += 4) 369 intel_dp_aux_unpack(intel_de_read(i915, ch_data[i >> 2]), 370 recv + i, recv_bytes - i); 371 372 ret = recv_bytes; 373 out: 374 cpu_latency_qos_update_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 375 376 if (vdd) 377 intel_pps_vdd_off_unlocked(intel_dp, false); 378 379 intel_pps_unlock(intel_dp, pps_wakeref); 380 intel_display_power_put_async(i915, aux_domain, aux_wakeref); 381 out_unlock: 382 if (is_tc_port) 383 intel_tc_port_unlock(dig_port); 384 385 return ret; 386 } 387 388 #define BARE_ADDRESS_SIZE 3 389 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 390 391 static void 392 intel_dp_aux_header(u8 txbuf[HEADER_SIZE], 393 const struct drm_dp_aux_msg *msg) 394 { 395 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); 396 txbuf[1] = (msg->address >> 8) & 0xff; 397 txbuf[2] = msg->address & 0xff; 398 txbuf[3] = msg->size - 1; 399 } 400 401 static u32 intel_dp_aux_xfer_flags(const struct drm_dp_aux_msg *msg) 402 { 403 /* 404 * If we're trying to send the HDCP Aksv, we need to set a the Aksv 405 * select bit to inform the hardware to send the Aksv after our header 406 * since we can't access that data from software. 407 */ 408 if ((msg->request & ~DP_AUX_I2C_MOT) == DP_AUX_NATIVE_WRITE && 409 msg->address == DP_AUX_HDCP_AKSV) 410 return DP_AUX_CH_CTL_AUX_AKSV_SELECT; 411 412 return 0; 413 } 414 415 static ssize_t 416 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 417 { 418 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 419 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 420 u8 txbuf[20], rxbuf[20]; 421 size_t txsize, rxsize; 422 u32 flags = intel_dp_aux_xfer_flags(msg); 423 int ret; 424 425 intel_dp_aux_header(txbuf, msg); 426 427 switch (msg->request & ~DP_AUX_I2C_MOT) { 428 case DP_AUX_NATIVE_WRITE: 429 case DP_AUX_I2C_WRITE: 430 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 431 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 432 rxsize = 2; /* 0 or 1 data bytes */ 433 434 if (drm_WARN_ON(&i915->drm, txsize > 20)) 435 return -E2BIG; 436 437 drm_WARN_ON(&i915->drm, !msg->buffer != !msg->size); 438 439 if (msg->buffer) 440 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 441 442 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 443 rxbuf, rxsize, flags); 444 if (ret > 0) { 445 msg->reply = rxbuf[0] >> 4; 446 447 if (ret > 1) { 448 /* Number of bytes written in a short write. */ 449 ret = clamp_t(int, rxbuf[1], 0, msg->size); 450 } else { 451 /* Return payload size. */ 452 ret = msg->size; 453 } 454 } 455 break; 456 457 case DP_AUX_NATIVE_READ: 458 case DP_AUX_I2C_READ: 459 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 460 rxsize = msg->size + 1; 461 462 if (drm_WARN_ON(&i915->drm, rxsize > 20)) 463 return -E2BIG; 464 465 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 466 rxbuf, rxsize, flags); 467 if (ret > 0) { 468 msg->reply = rxbuf[0] >> 4; 469 /* 470 * Assume happy day, and copy the data. The caller is 471 * expected to check msg->reply before touching it. 472 * 473 * Return payload size. 474 */ 475 ret--; 476 memcpy(msg->buffer, rxbuf + 1, ret); 477 } 478 break; 479 480 default: 481 ret = -EINVAL; 482 break; 483 } 484 485 return ret; 486 } 487 488 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) 489 { 490 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 491 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 492 enum aux_ch aux_ch = dig_port->aux_ch; 493 494 switch (aux_ch) { 495 case AUX_CH_B: 496 case AUX_CH_C: 497 case AUX_CH_D: 498 return DP_AUX_CH_CTL(aux_ch); 499 default: 500 MISSING_CASE(aux_ch); 501 return DP_AUX_CH_CTL(AUX_CH_B); 502 } 503 } 504 505 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) 506 { 507 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 508 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 509 enum aux_ch aux_ch = dig_port->aux_ch; 510 511 switch (aux_ch) { 512 case AUX_CH_B: 513 case AUX_CH_C: 514 case AUX_CH_D: 515 return DP_AUX_CH_DATA(aux_ch, index); 516 default: 517 MISSING_CASE(aux_ch); 518 return DP_AUX_CH_DATA(AUX_CH_B, index); 519 } 520 } 521 522 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) 523 { 524 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 525 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 526 enum aux_ch aux_ch = dig_port->aux_ch; 527 528 switch (aux_ch) { 529 case AUX_CH_A: 530 return DP_AUX_CH_CTL(aux_ch); 531 case AUX_CH_B: 532 case AUX_CH_C: 533 case AUX_CH_D: 534 return PCH_DP_AUX_CH_CTL(aux_ch); 535 default: 536 MISSING_CASE(aux_ch); 537 return DP_AUX_CH_CTL(AUX_CH_A); 538 } 539 } 540 541 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) 542 { 543 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 544 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 545 enum aux_ch aux_ch = dig_port->aux_ch; 546 547 switch (aux_ch) { 548 case AUX_CH_A: 549 return DP_AUX_CH_DATA(aux_ch, index); 550 case AUX_CH_B: 551 case AUX_CH_C: 552 case AUX_CH_D: 553 return PCH_DP_AUX_CH_DATA(aux_ch, index); 554 default: 555 MISSING_CASE(aux_ch); 556 return DP_AUX_CH_DATA(AUX_CH_A, index); 557 } 558 } 559 560 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) 561 { 562 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 563 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 564 enum aux_ch aux_ch = dig_port->aux_ch; 565 566 switch (aux_ch) { 567 case AUX_CH_A: 568 case AUX_CH_B: 569 case AUX_CH_C: 570 case AUX_CH_D: 571 case AUX_CH_E: 572 case AUX_CH_F: 573 return DP_AUX_CH_CTL(aux_ch); 574 default: 575 MISSING_CASE(aux_ch); 576 return DP_AUX_CH_CTL(AUX_CH_A); 577 } 578 } 579 580 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) 581 { 582 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 583 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 584 enum aux_ch aux_ch = dig_port->aux_ch; 585 586 switch (aux_ch) { 587 case AUX_CH_A: 588 case AUX_CH_B: 589 case AUX_CH_C: 590 case AUX_CH_D: 591 case AUX_CH_E: 592 case AUX_CH_F: 593 return DP_AUX_CH_DATA(aux_ch, index); 594 default: 595 MISSING_CASE(aux_ch); 596 return DP_AUX_CH_DATA(AUX_CH_A, index); 597 } 598 } 599 600 static i915_reg_t tgl_aux_ctl_reg(struct intel_dp *intel_dp) 601 { 602 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 603 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 604 enum aux_ch aux_ch = dig_port->aux_ch; 605 606 switch (aux_ch) { 607 case AUX_CH_A: 608 case AUX_CH_B: 609 case AUX_CH_C: 610 case AUX_CH_USBC1: 611 case AUX_CH_USBC2: 612 case AUX_CH_USBC3: 613 case AUX_CH_USBC4: 614 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 615 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 616 return DP_AUX_CH_CTL(aux_ch); 617 default: 618 MISSING_CASE(aux_ch); 619 return DP_AUX_CH_CTL(AUX_CH_A); 620 } 621 } 622 623 static i915_reg_t tgl_aux_data_reg(struct intel_dp *intel_dp, int index) 624 { 625 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 626 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 627 enum aux_ch aux_ch = dig_port->aux_ch; 628 629 switch (aux_ch) { 630 case AUX_CH_A: 631 case AUX_CH_B: 632 case AUX_CH_C: 633 case AUX_CH_USBC1: 634 case AUX_CH_USBC2: 635 case AUX_CH_USBC3: 636 case AUX_CH_USBC4: 637 case AUX_CH_USBC5: /* aka AUX_CH_D_XELPD */ 638 case AUX_CH_USBC6: /* aka AUX_CH_E_XELPD */ 639 return DP_AUX_CH_DATA(aux_ch, index); 640 default: 641 MISSING_CASE(aux_ch); 642 return DP_AUX_CH_DATA(AUX_CH_A, index); 643 } 644 } 645 646 static i915_reg_t xelpdp_aux_ctl_reg(struct intel_dp *intel_dp) 647 { 648 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 649 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 650 enum aux_ch aux_ch = dig_port->aux_ch; 651 652 switch (aux_ch) { 653 case AUX_CH_A: 654 case AUX_CH_B: 655 case AUX_CH_USBC1: 656 case AUX_CH_USBC2: 657 case AUX_CH_USBC3: 658 case AUX_CH_USBC4: 659 return XELPDP_DP_AUX_CH_CTL(aux_ch); 660 default: 661 MISSING_CASE(aux_ch); 662 return XELPDP_DP_AUX_CH_CTL(AUX_CH_A); 663 } 664 } 665 666 static i915_reg_t xelpdp_aux_data_reg(struct intel_dp *intel_dp, int index) 667 { 668 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 669 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 670 enum aux_ch aux_ch = dig_port->aux_ch; 671 672 switch (aux_ch) { 673 case AUX_CH_A: 674 case AUX_CH_B: 675 case AUX_CH_USBC1: 676 case AUX_CH_USBC2: 677 case AUX_CH_USBC3: 678 case AUX_CH_USBC4: 679 return XELPDP_DP_AUX_CH_DATA(aux_ch, index); 680 default: 681 MISSING_CASE(aux_ch); 682 return XELPDP_DP_AUX_CH_DATA(AUX_CH_A, index); 683 } 684 } 685 686 void intel_dp_aux_fini(struct intel_dp *intel_dp) 687 { 688 if (cpu_latency_qos_request_active(&intel_dp->pm_qos)) 689 cpu_latency_qos_remove_request(&intel_dp->pm_qos); 690 691 kfree(intel_dp->aux.name); 692 } 693 694 void intel_dp_aux_init(struct intel_dp *intel_dp) 695 { 696 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 697 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 698 struct intel_encoder *encoder = &dig_port->base; 699 enum aux_ch aux_ch = dig_port->aux_ch; 700 701 if (DISPLAY_VER(dev_priv) >= 14) { 702 intel_dp->aux_ch_ctl_reg = xelpdp_aux_ctl_reg; 703 intel_dp->aux_ch_data_reg = xelpdp_aux_data_reg; 704 } else if (DISPLAY_VER(dev_priv) >= 12) { 705 intel_dp->aux_ch_ctl_reg = tgl_aux_ctl_reg; 706 intel_dp->aux_ch_data_reg = tgl_aux_data_reg; 707 } else if (DISPLAY_VER(dev_priv) >= 9) { 708 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; 709 intel_dp->aux_ch_data_reg = skl_aux_data_reg; 710 } else if (HAS_PCH_SPLIT(dev_priv)) { 711 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; 712 intel_dp->aux_ch_data_reg = ilk_aux_data_reg; 713 } else { 714 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; 715 intel_dp->aux_ch_data_reg = g4x_aux_data_reg; 716 } 717 718 if (DISPLAY_VER(dev_priv) >= 9) 719 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; 720 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 721 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 722 else if (HAS_PCH_SPLIT(dev_priv)) 723 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 724 else 725 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; 726 727 if (DISPLAY_VER(dev_priv) >= 9) 728 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; 729 else 730 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; 731 732 intel_dp->aux.drm_dev = &dev_priv->drm; 733 drm_dp_aux_init(&intel_dp->aux); 734 735 /* Failure to allocate our preferred name is not critical */ 736 if (DISPLAY_VER(dev_priv) >= 13 && aux_ch >= AUX_CH_D_XELPD) 737 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s", 738 aux_ch_name(aux_ch - AUX_CH_D_XELPD + AUX_CH_D), 739 encoder->base.name); 740 else if (DISPLAY_VER(dev_priv) >= 12 && aux_ch >= AUX_CH_USBC1) 741 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX USBC%c/%s", 742 aux_ch - AUX_CH_USBC1 + '1', 743 encoder->base.name); 744 else 745 intel_dp->aux.name = kasprintf(GFP_KERNEL, "AUX %c/%s", 746 aux_ch_name(aux_ch), 747 encoder->base.name); 748 749 intel_dp->aux.transfer = intel_dp_aux_transfer; 750 cpu_latency_qos_add_request(&intel_dp->pm_qos, PM_QOS_DEFAULT_VALUE); 751 } 752 753 static enum aux_ch default_aux_ch(struct intel_encoder *encoder) 754 { 755 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 756 757 /* SKL has DDI E but no AUX E */ 758 if (DISPLAY_VER(i915) == 9 && encoder->port == PORT_E) 759 return AUX_CH_A; 760 761 return (enum aux_ch)encoder->port; 762 } 763 764 enum aux_ch intel_dp_aux_ch(struct intel_encoder *encoder) 765 { 766 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 767 enum aux_ch aux_ch; 768 769 aux_ch = intel_bios_dp_aux_ch(encoder->devdata); 770 if (aux_ch != AUX_CH_NONE) { 771 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] using AUX %c (VBT)\n", 772 encoder->base.base.id, encoder->base.name, 773 aux_ch_name(aux_ch)); 774 return aux_ch; 775 } 776 777 aux_ch = default_aux_ch(encoder); 778 779 drm_dbg_kms(&i915->drm, 780 "[ENCODER:%d:%s] using AUX %c (platform default)\n", 781 encoder->base.base.id, encoder->base.name, 782 aux_ch_name(aux_ch)); 783 784 return aux_ch; 785 } 786