1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2019 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DP_H__ 7 #define __INTEL_DP_H__ 8 9 #include <linux/types.h> 10 11 #include "i915_reg.h" 12 13 enum pipe; 14 enum port; 15 struct drm_connector_state; 16 struct drm_encoder; 17 struct drm_i915_private; 18 struct drm_modeset_acquire_ctx; 19 struct intel_connector; 20 struct intel_crtc_state; 21 struct intel_digital_port; 22 struct intel_dp; 23 struct intel_encoder; 24 25 struct link_config_limits { 26 int min_clock, max_clock; 27 int min_lane_count, max_lane_count; 28 int min_bpp, max_bpp; 29 }; 30 31 void intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, 32 struct intel_crtc_state *pipe_config, 33 struct link_config_limits *limits); 34 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, 35 const struct drm_connector_state *conn_state); 36 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state); 37 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, 38 i915_reg_t dp_reg, enum port port, 39 enum pipe *pipe); 40 bool intel_dp_init(struct drm_i915_private *dev_priv, i915_reg_t output_reg, 41 enum port port); 42 bool intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 43 struct intel_connector *intel_connector); 44 void intel_dp_set_link_params(struct intel_dp *intel_dp, 45 int link_rate, u8 lane_count, 46 bool link_mst); 47 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, 48 int link_rate, u8 lane_count); 49 int intel_dp_retrain_link(struct intel_encoder *encoder, 50 struct drm_modeset_acquire_ctx *ctx); 51 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode); 52 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, 53 const struct intel_crtc_state *crtc_state, 54 bool enable); 55 void intel_dp_encoder_reset(struct drm_encoder *encoder); 56 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder); 57 void intel_dp_encoder_flush_work(struct drm_encoder *encoder); 58 int intel_dp_compute_config(struct intel_encoder *encoder, 59 struct intel_crtc_state *pipe_config, 60 struct drm_connector_state *conn_state); 61 bool intel_dp_is_edp(struct intel_dp *intel_dp); 62 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); 63 enum irqreturn intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, 64 bool long_hpd); 65 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, 66 const struct drm_connector_state *conn_state); 67 void intel_edp_backlight_off(const struct drm_connector_state *conn_state); 68 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); 69 void intel_edp_panel_on(struct intel_dp *intel_dp); 70 void intel_edp_panel_off(struct intel_dp *intel_dp); 71 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv); 72 void intel_dp_mst_resume(struct drm_i915_private *dev_priv); 73 int intel_dp_max_link_rate(struct intel_dp *intel_dp); 74 int intel_dp_max_lane_count(struct intel_dp *intel_dp); 75 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate); 76 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv); 77 u32 intel_dp_pack_aux(const u8 *src, int src_bytes); 78 79 void intel_edp_drrs_enable(struct intel_dp *intel_dp, 80 const struct intel_crtc_state *crtc_state); 81 void intel_edp_drrs_disable(struct intel_dp *intel_dp, 82 const struct intel_crtc_state *crtc_state); 83 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, 84 unsigned int frontbuffer_bits); 85 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, 86 unsigned int frontbuffer_bits); 87 88 void 89 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 90 u8 dp_train_pat); 91 void 92 intel_dp_set_signal_levels(struct intel_dp *intel_dp); 93 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp); 94 u8 95 intel_dp_voltage_max(struct intel_dp *intel_dp); 96 u8 97 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing); 98 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 99 u8 *link_bw, u8 *rate_select); 100 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp); 101 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp); 102 bool 103 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 *link_status); 104 105 bool intel_dp_read_dpcd(struct intel_dp *intel_dp); 106 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp); 107 int intel_dp_link_required(int pixel_clock, int bpp); 108 int intel_dp_max_data_rate(int max_link_clock, int max_lanes); 109 bool intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, 110 const struct drm_connector_state *conn_state); 111 void intel_dp_vsc_enable(struct intel_dp *intel_dp, 112 const struct intel_crtc_state *crtc_state, 113 const struct drm_connector_state *conn_state); 114 void intel_dp_hdr_metadata_enable(struct intel_dp *intel_dp, 115 const struct intel_crtc_state *crtc_state, 116 const struct drm_connector_state *conn_state); 117 bool intel_digital_port_connected(struct intel_encoder *encoder); 118 119 static inline unsigned int intel_dp_unused_lane_mask(int lane_count) 120 { 121 return ~((1 << lane_count) - 1) & 0xf; 122 } 123 124 u32 intel_dp_mode_to_fec_clock(u32 mode_clock); 125 126 #endif /* __INTEL_DP_H__ */ 127