1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28 #include <linux/export.h> 29 #include <linux/i2c.h> 30 #include <linux/notifier.h> 31 #include <linux/slab.h> 32 #include <linux/types.h> 33 34 #include <asm/byteorder.h> 35 36 #include <drm/drm_atomic_helper.h> 37 #include <drm/drm_crtc.h> 38 #include <drm/drm_dp_helper.h> 39 #include <drm/drm_edid.h> 40 #include <drm/drm_probe_helper.h> 41 42 #include "g4x_dp.h" 43 #include "i915_debugfs.h" 44 #include "i915_drv.h" 45 #include "intel_atomic.h" 46 #include "intel_audio.h" 47 #include "intel_connector.h" 48 #include "intel_ddi.h" 49 #include "intel_de.h" 50 #include "intel_display_types.h" 51 #include "intel_dp.h" 52 #include "intel_dp_aux.h" 53 #include "intel_dp_hdcp.h" 54 #include "intel_dp_link_training.h" 55 #include "intel_dp_mst.h" 56 #include "intel_dpio_phy.h" 57 #include "intel_dpll.h" 58 #include "intel_fifo_underrun.h" 59 #include "intel_hdcp.h" 60 #include "intel_hdmi.h" 61 #include "intel_hotplug.h" 62 #include "intel_lspcon.h" 63 #include "intel_lvds.h" 64 #include "intel_panel.h" 65 #include "intel_pps.h" 66 #include "intel_psr.h" 67 #include "intel_sideband.h" 68 #include "intel_tc.h" 69 #include "intel_vdsc.h" 70 #include "intel_vrr.h" 71 72 #define DP_DPRX_ESI_LEN 14 73 74 /* DP DSC throughput values used for slice count calculations KPixels/s */ 75 #define DP_DSC_PEAK_PIXEL_RATE 2720000 76 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 77 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 78 79 /* DP DSC FEC Overhead factor = 1/(0.972261) */ 80 #define DP_DSC_FEC_OVERHEAD_FACTOR 972261 81 82 /* Compliance test status bits */ 83 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 84 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) 85 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) 86 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) 87 88 89 /* Constants for DP DSC configurations */ 90 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; 91 92 /* With Single pipe configuration, HW is capable of supporting maximum 93 * of 4 slices per line. 94 */ 95 static const u8 valid_dsc_slicecount[] = {1, 2, 4}; 96 97 /** 98 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) 99 * @intel_dp: DP struct 100 * 101 * If a CPU or PCH DP output is attached to an eDP panel, this function 102 * will return true, and false otherwise. 103 */ 104 bool intel_dp_is_edp(struct intel_dp *intel_dp) 105 { 106 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 107 108 return dig_port->base.type == INTEL_OUTPUT_EDP; 109 } 110 111 static void intel_dp_unset_edid(struct intel_dp *intel_dp); 112 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); 113 114 /* update sink rates from dpcd */ 115 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) 116 { 117 static const int dp_rates[] = { 118 162000, 270000, 540000, 810000 119 }; 120 int i, max_rate; 121 int max_lttpr_rate; 122 123 if (drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CAN_DO_MAX_LINK_RATE_3_24_GBPS)) { 124 /* Needed, e.g., for Apple MBP 2017, 15 inch eDP Retina panel */ 125 static const int quirk_rates[] = { 162000, 270000, 324000 }; 126 127 memcpy(intel_dp->sink_rates, quirk_rates, sizeof(quirk_rates)); 128 intel_dp->num_sink_rates = ARRAY_SIZE(quirk_rates); 129 130 return; 131 } 132 133 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); 134 max_lttpr_rate = drm_dp_lttpr_max_link_rate(intel_dp->lttpr_common_caps); 135 if (max_lttpr_rate) 136 max_rate = min(max_rate, max_lttpr_rate); 137 138 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) { 139 if (dp_rates[i] > max_rate) 140 break; 141 intel_dp->sink_rates[i] = dp_rates[i]; 142 } 143 144 intel_dp->num_sink_rates = i; 145 } 146 147 /* Get length of rates array potentially limited by max_rate. */ 148 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) 149 { 150 int i; 151 152 /* Limit results by potentially reduced max rate */ 153 for (i = 0; i < len; i++) { 154 if (rates[len - i - 1] <= max_rate) 155 return len - i; 156 } 157 158 return 0; 159 } 160 161 /* Get length of common rates array potentially limited by max_rate. */ 162 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, 163 int max_rate) 164 { 165 return intel_dp_rate_limit_len(intel_dp->common_rates, 166 intel_dp->num_common_rates, max_rate); 167 } 168 169 /* Theoretical max between source and sink */ 170 static int intel_dp_max_common_rate(struct intel_dp *intel_dp) 171 { 172 return intel_dp->common_rates[intel_dp->num_common_rates - 1]; 173 } 174 175 /* Theoretical max between source and sink */ 176 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) 177 { 178 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 179 int source_max = dig_port->max_lanes; 180 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd); 181 int fia_max = intel_tc_port_fia_max_lane_count(dig_port); 182 int lttpr_max = drm_dp_lttpr_max_lane_count(intel_dp->lttpr_common_caps); 183 184 if (lttpr_max) 185 sink_max = min(sink_max, lttpr_max); 186 187 return min3(source_max, sink_max, fia_max); 188 } 189 190 int intel_dp_max_lane_count(struct intel_dp *intel_dp) 191 { 192 return intel_dp->max_link_lane_count; 193 } 194 195 int 196 intel_dp_link_required(int pixel_clock, int bpp) 197 { 198 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ 199 return DIV_ROUND_UP(pixel_clock * bpp, 8); 200 } 201 202 int 203 intel_dp_max_data_rate(int max_link_clock, int max_lanes) 204 { 205 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the 206 * link rate that is generally expressed in Gbps. Since, 8 bits of data 207 * is transmitted every LS_Clk per lane, there is no need to account for 208 * the channel encoding that is done in the PHY layer here. 209 */ 210 211 return max_link_clock * max_lanes; 212 } 213 214 bool intel_dp_can_bigjoiner(struct intel_dp *intel_dp) 215 { 216 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 217 struct intel_encoder *encoder = &intel_dig_port->base; 218 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 219 220 return DISPLAY_VER(dev_priv) >= 12 || 221 (DISPLAY_VER(dev_priv) == 11 && 222 encoder->port != PORT_A); 223 } 224 225 static int icl_max_source_rate(struct intel_dp *intel_dp) 226 { 227 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 228 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 229 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 230 231 if (intel_phy_is_combo(dev_priv, phy) && 232 !intel_dp_is_edp(intel_dp)) 233 return 540000; 234 235 return 810000; 236 } 237 238 static int ehl_max_source_rate(struct intel_dp *intel_dp) 239 { 240 if (intel_dp_is_edp(intel_dp)) 241 return 540000; 242 243 return 810000; 244 } 245 246 static void 247 intel_dp_set_source_rates(struct intel_dp *intel_dp) 248 { 249 /* The values must be in increasing order */ 250 static const int icl_rates[] = { 251 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000 252 }; 253 static const int bxt_rates[] = { 254 162000, 216000, 243000, 270000, 324000, 432000, 540000 255 }; 256 static const int skl_rates[] = { 257 162000, 216000, 270000, 324000, 432000, 540000 258 }; 259 static const int hsw_rates[] = { 260 162000, 270000, 540000 261 }; 262 static const int g4x_rates[] = { 263 162000, 270000 264 }; 265 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 266 struct intel_encoder *encoder = &dig_port->base; 267 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 268 const int *source_rates; 269 int size, max_rate = 0, vbt_max_rate; 270 271 /* This should only be done once */ 272 drm_WARN_ON(&dev_priv->drm, 273 intel_dp->source_rates || intel_dp->num_source_rates); 274 275 if (DISPLAY_VER(dev_priv) >= 11) { 276 source_rates = icl_rates; 277 size = ARRAY_SIZE(icl_rates); 278 if (IS_JSL_EHL(dev_priv)) 279 max_rate = ehl_max_source_rate(intel_dp); 280 else 281 max_rate = icl_max_source_rate(intel_dp); 282 } else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) { 283 source_rates = bxt_rates; 284 size = ARRAY_SIZE(bxt_rates); 285 } else if (DISPLAY_VER(dev_priv) == 9) { 286 source_rates = skl_rates; 287 size = ARRAY_SIZE(skl_rates); 288 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || 289 IS_BROADWELL(dev_priv)) { 290 source_rates = hsw_rates; 291 size = ARRAY_SIZE(hsw_rates); 292 } else { 293 source_rates = g4x_rates; 294 size = ARRAY_SIZE(g4x_rates); 295 } 296 297 vbt_max_rate = intel_bios_dp_max_link_rate(encoder); 298 if (max_rate && vbt_max_rate) 299 max_rate = min(max_rate, vbt_max_rate); 300 else if (vbt_max_rate) 301 max_rate = vbt_max_rate; 302 303 if (max_rate) 304 size = intel_dp_rate_limit_len(source_rates, size, max_rate); 305 306 intel_dp->source_rates = source_rates; 307 intel_dp->num_source_rates = size; 308 } 309 310 static int intersect_rates(const int *source_rates, int source_len, 311 const int *sink_rates, int sink_len, 312 int *common_rates) 313 { 314 int i = 0, j = 0, k = 0; 315 316 while (i < source_len && j < sink_len) { 317 if (source_rates[i] == sink_rates[j]) { 318 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) 319 return k; 320 common_rates[k] = source_rates[i]; 321 ++k; 322 ++i; 323 ++j; 324 } else if (source_rates[i] < sink_rates[j]) { 325 ++i; 326 } else { 327 ++j; 328 } 329 } 330 return k; 331 } 332 333 /* return index of rate in rates array, or -1 if not found */ 334 static int intel_dp_rate_index(const int *rates, int len, int rate) 335 { 336 int i; 337 338 for (i = 0; i < len; i++) 339 if (rate == rates[i]) 340 return i; 341 342 return -1; 343 } 344 345 static void intel_dp_set_common_rates(struct intel_dp *intel_dp) 346 { 347 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 348 349 drm_WARN_ON(&i915->drm, 350 !intel_dp->num_source_rates || !intel_dp->num_sink_rates); 351 352 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, 353 intel_dp->num_source_rates, 354 intel_dp->sink_rates, 355 intel_dp->num_sink_rates, 356 intel_dp->common_rates); 357 358 /* Paranoia, there should always be something in common. */ 359 if (drm_WARN_ON(&i915->drm, intel_dp->num_common_rates == 0)) { 360 intel_dp->common_rates[0] = 162000; 361 intel_dp->num_common_rates = 1; 362 } 363 } 364 365 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, 366 u8 lane_count) 367 { 368 /* 369 * FIXME: we need to synchronize the current link parameters with 370 * hardware readout. Currently fast link training doesn't work on 371 * boot-up. 372 */ 373 if (link_rate == 0 || 374 link_rate > intel_dp->max_link_rate) 375 return false; 376 377 if (lane_count == 0 || 378 lane_count > intel_dp_max_lane_count(intel_dp)) 379 return false; 380 381 return true; 382 } 383 384 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, 385 int link_rate, 386 u8 lane_count) 387 { 388 const struct drm_display_mode *fixed_mode = 389 intel_dp->attached_connector->panel.fixed_mode; 390 int mode_rate, max_rate; 391 392 mode_rate = intel_dp_link_required(fixed_mode->clock, 18); 393 max_rate = intel_dp_max_data_rate(link_rate, lane_count); 394 if (mode_rate > max_rate) 395 return false; 396 397 return true; 398 } 399 400 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, 401 int link_rate, u8 lane_count) 402 { 403 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 404 int index; 405 406 /* 407 * TODO: Enable fallback on MST links once MST link compute can handle 408 * the fallback params. 409 */ 410 if (intel_dp->is_mst) { 411 drm_err(&i915->drm, "Link Training Unsuccessful\n"); 412 return -1; 413 } 414 415 if (intel_dp_is_edp(intel_dp) && !intel_dp->use_max_params) { 416 drm_dbg_kms(&i915->drm, 417 "Retrying Link training for eDP with max parameters\n"); 418 intel_dp->use_max_params = true; 419 return 0; 420 } 421 422 index = intel_dp_rate_index(intel_dp->common_rates, 423 intel_dp->num_common_rates, 424 link_rate); 425 if (index > 0) { 426 if (intel_dp_is_edp(intel_dp) && 427 !intel_dp_can_link_train_fallback_for_edp(intel_dp, 428 intel_dp->common_rates[index - 1], 429 lane_count)) { 430 drm_dbg_kms(&i915->drm, 431 "Retrying Link training for eDP with same parameters\n"); 432 return 0; 433 } 434 intel_dp->max_link_rate = intel_dp->common_rates[index - 1]; 435 intel_dp->max_link_lane_count = lane_count; 436 } else if (lane_count > 1) { 437 if (intel_dp_is_edp(intel_dp) && 438 !intel_dp_can_link_train_fallback_for_edp(intel_dp, 439 intel_dp_max_common_rate(intel_dp), 440 lane_count >> 1)) { 441 drm_dbg_kms(&i915->drm, 442 "Retrying Link training for eDP with same parameters\n"); 443 return 0; 444 } 445 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); 446 intel_dp->max_link_lane_count = lane_count >> 1; 447 } else { 448 drm_err(&i915->drm, "Link Training Unsuccessful\n"); 449 return -1; 450 } 451 452 return 0; 453 } 454 455 u32 intel_dp_mode_to_fec_clock(u32 mode_clock) 456 { 457 return div_u64(mul_u32_u32(mode_clock, 1000000U), 458 DP_DSC_FEC_OVERHEAD_FACTOR); 459 } 460 461 static int 462 small_joiner_ram_size_bits(struct drm_i915_private *i915) 463 { 464 if (DISPLAY_VER(i915) >= 11) 465 return 7680 * 8; 466 else 467 return 6144 * 8; 468 } 469 470 static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, 471 u32 link_clock, u32 lane_count, 472 u32 mode_clock, u32 mode_hdisplay, 473 bool bigjoiner, 474 u32 pipe_bpp) 475 { 476 u32 bits_per_pixel, max_bpp_small_joiner_ram; 477 int i; 478 479 /* 480 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* 481 * (LinkSymbolClock)* 8 * (TimeSlotsPerMTP) 482 * for SST -> TimeSlotsPerMTP is 1, 483 * for MST -> TimeSlotsPerMTP has to be calculated 484 */ 485 bits_per_pixel = (link_clock * lane_count * 8) / 486 intel_dp_mode_to_fec_clock(mode_clock); 487 drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel); 488 489 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ 490 max_bpp_small_joiner_ram = small_joiner_ram_size_bits(i915) / 491 mode_hdisplay; 492 493 if (bigjoiner) 494 max_bpp_small_joiner_ram *= 2; 495 496 drm_dbg_kms(&i915->drm, "Max small joiner bpp: %u\n", 497 max_bpp_small_joiner_ram); 498 499 /* 500 * Greatest allowed DSC BPP = MIN (output BPP from available Link BW 501 * check, output bpp from small joiner RAM check) 502 */ 503 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram); 504 505 if (bigjoiner) { 506 u32 max_bpp_bigjoiner = 507 i915->max_cdclk_freq * 48 / 508 intel_dp_mode_to_fec_clock(mode_clock); 509 510 DRM_DEBUG_KMS("Max big joiner bpp: %u\n", max_bpp_bigjoiner); 511 bits_per_pixel = min(bits_per_pixel, max_bpp_bigjoiner); 512 } 513 514 /* Error out if the max bpp is less than smallest allowed valid bpp */ 515 if (bits_per_pixel < valid_dsc_bpp[0]) { 516 drm_dbg_kms(&i915->drm, "Unsupported BPP %u, min %u\n", 517 bits_per_pixel, valid_dsc_bpp[0]); 518 return 0; 519 } 520 521 /* From XE_LPD onwards we support from bpc upto uncompressed bpp-1 BPPs */ 522 if (DISPLAY_VER(i915) >= 13) { 523 bits_per_pixel = min(bits_per_pixel, pipe_bpp - 1); 524 } else { 525 /* Find the nearest match in the array of known BPPs from VESA */ 526 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { 527 if (bits_per_pixel < valid_dsc_bpp[i + 1]) 528 break; 529 } 530 bits_per_pixel = valid_dsc_bpp[i]; 531 } 532 533 /* 534 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11, 535 * fractional part is 0 536 */ 537 return bits_per_pixel << 4; 538 } 539 540 static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, 541 int mode_clock, int mode_hdisplay, 542 bool bigjoiner) 543 { 544 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 545 u8 min_slice_count, i; 546 int max_slice_width; 547 548 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE) 549 min_slice_count = DIV_ROUND_UP(mode_clock, 550 DP_DSC_MAX_ENC_THROUGHPUT_0); 551 else 552 min_slice_count = DIV_ROUND_UP(mode_clock, 553 DP_DSC_MAX_ENC_THROUGHPUT_1); 554 555 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd); 556 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { 557 drm_dbg_kms(&i915->drm, 558 "Unsupported slice width %d by DP DSC Sink device\n", 559 max_slice_width); 560 return 0; 561 } 562 /* Also take into account max slice width */ 563 min_slice_count = max_t(u8, min_slice_count, 564 DIV_ROUND_UP(mode_hdisplay, 565 max_slice_width)); 566 567 /* Find the closest match to the valid slice count values */ 568 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { 569 u8 test_slice_count = valid_dsc_slicecount[i] << bigjoiner; 570 571 if (test_slice_count > 572 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, false)) 573 break; 574 575 /* big joiner needs small joiner to be enabled */ 576 if (bigjoiner && test_slice_count < 4) 577 continue; 578 579 if (min_slice_count <= test_slice_count) 580 return test_slice_count; 581 } 582 583 drm_dbg_kms(&i915->drm, "Unsupported Slice Count %d\n", 584 min_slice_count); 585 return 0; 586 } 587 588 static enum intel_output_format 589 intel_dp_output_format(struct drm_connector *connector, 590 const struct drm_display_mode *mode) 591 { 592 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 593 const struct drm_display_info *info = &connector->display_info; 594 595 if (!connector->ycbcr_420_allowed || 596 !drm_mode_is_420_only(info, mode)) 597 return INTEL_OUTPUT_FORMAT_RGB; 598 599 if (intel_dp->dfp.rgb_to_ycbcr && 600 intel_dp->dfp.ycbcr_444_to_420) 601 return INTEL_OUTPUT_FORMAT_RGB; 602 603 if (intel_dp->dfp.ycbcr_444_to_420) 604 return INTEL_OUTPUT_FORMAT_YCBCR444; 605 else 606 return INTEL_OUTPUT_FORMAT_YCBCR420; 607 } 608 609 int intel_dp_min_bpp(enum intel_output_format output_format) 610 { 611 if (output_format == INTEL_OUTPUT_FORMAT_RGB) 612 return 6 * 3; 613 else 614 return 8 * 3; 615 } 616 617 static int intel_dp_output_bpp(enum intel_output_format output_format, int bpp) 618 { 619 /* 620 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output 621 * format of the number of bytes per pixel will be half the number 622 * of bytes of RGB pixel. 623 */ 624 if (output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 625 bpp /= 2; 626 627 return bpp; 628 } 629 630 static int 631 intel_dp_mode_min_output_bpp(struct drm_connector *connector, 632 const struct drm_display_mode *mode) 633 { 634 enum intel_output_format output_format = 635 intel_dp_output_format(connector, mode); 636 637 return intel_dp_output_bpp(output_format, intel_dp_min_bpp(output_format)); 638 } 639 640 static bool intel_dp_hdisplay_bad(struct drm_i915_private *dev_priv, 641 int hdisplay) 642 { 643 /* 644 * Older platforms don't like hdisplay==4096 with DP. 645 * 646 * On ILK/SNB/IVB the pipe seems to be somewhat running (scanline 647 * and frame counter increment), but we don't get vblank interrupts, 648 * and the pipe underruns immediately. The link also doesn't seem 649 * to get trained properly. 650 * 651 * On CHV the vblank interrupts don't seem to disappear but 652 * otherwise the symptoms are similar. 653 * 654 * TODO: confirm the behaviour on HSW+ 655 */ 656 return hdisplay == 4096 && !HAS_DDI(dev_priv); 657 } 658 659 static enum drm_mode_status 660 intel_dp_mode_valid_downstream(struct intel_connector *connector, 661 const struct drm_display_mode *mode, 662 int target_clock) 663 { 664 struct intel_dp *intel_dp = intel_attached_dp(connector); 665 const struct drm_display_info *info = &connector->base.display_info; 666 int tmds_clock; 667 668 /* If PCON supports FRL MODE, check FRL bandwidth constraints */ 669 if (intel_dp->dfp.pcon_max_frl_bw) { 670 int target_bw; 671 int max_frl_bw; 672 int bpp = intel_dp_mode_min_output_bpp(&connector->base, mode); 673 674 target_bw = bpp * target_clock; 675 676 max_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 677 678 /* converting bw from Gbps to Kbps*/ 679 max_frl_bw = max_frl_bw * 1000000; 680 681 if (target_bw > max_frl_bw) 682 return MODE_CLOCK_HIGH; 683 684 return MODE_OK; 685 } 686 687 if (intel_dp->dfp.max_dotclock && 688 target_clock > intel_dp->dfp.max_dotclock) 689 return MODE_CLOCK_HIGH; 690 691 /* Assume 8bpc for the DP++/HDMI/DVI TMDS clock check */ 692 tmds_clock = target_clock; 693 if (drm_mode_is_420_only(info, mode)) 694 tmds_clock /= 2; 695 696 if (intel_dp->dfp.min_tmds_clock && 697 tmds_clock < intel_dp->dfp.min_tmds_clock) 698 return MODE_CLOCK_LOW; 699 if (intel_dp->dfp.max_tmds_clock && 700 tmds_clock > intel_dp->dfp.max_tmds_clock) 701 return MODE_CLOCK_HIGH; 702 703 return MODE_OK; 704 } 705 706 static enum drm_mode_status 707 intel_dp_mode_valid(struct drm_connector *connector, 708 struct drm_display_mode *mode) 709 { 710 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 711 struct intel_connector *intel_connector = to_intel_connector(connector); 712 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 713 struct drm_i915_private *dev_priv = to_i915(connector->dev); 714 int target_clock = mode->clock; 715 int max_rate, mode_rate, max_lanes, max_link_clock; 716 int max_dotclk = dev_priv->max_dotclk_freq; 717 u16 dsc_max_output_bpp = 0; 718 u8 dsc_slice_count = 0; 719 enum drm_mode_status status; 720 bool dsc = false, bigjoiner = false; 721 722 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 723 return MODE_NO_DBLESCAN; 724 725 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 726 return MODE_H_ILLEGAL; 727 728 if (intel_dp_is_edp(intel_dp) && fixed_mode) { 729 if (mode->hdisplay != fixed_mode->hdisplay) 730 return MODE_PANEL; 731 732 if (mode->vdisplay != fixed_mode->vdisplay) 733 return MODE_PANEL; 734 735 target_clock = fixed_mode->clock; 736 } 737 738 if (mode->clock < 10000) 739 return MODE_CLOCK_LOW; 740 741 if ((target_clock > max_dotclk || mode->hdisplay > 5120) && 742 intel_dp_can_bigjoiner(intel_dp)) { 743 bigjoiner = true; 744 max_dotclk *= 2; 745 } 746 if (target_clock > max_dotclk) 747 return MODE_CLOCK_HIGH; 748 749 max_link_clock = intel_dp_max_link_rate(intel_dp); 750 max_lanes = intel_dp_max_lane_count(intel_dp); 751 752 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 753 mode_rate = intel_dp_link_required(target_clock, 754 intel_dp_mode_min_output_bpp(connector, mode)); 755 756 if (intel_dp_hdisplay_bad(dev_priv, mode->hdisplay)) 757 return MODE_H_ILLEGAL; 758 759 /* 760 * Output bpp is stored in 6.4 format so right shift by 4 to get the 761 * integer value since we support only integer values of bpp. 762 */ 763 if (DISPLAY_VER(dev_priv) >= 10 && 764 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { 765 /* 766 * TBD pass the connector BPC, 767 * for now U8_MAX so that max BPC on that platform would be picked 768 */ 769 int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); 770 771 if (intel_dp_is_edp(intel_dp)) { 772 dsc_max_output_bpp = 773 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; 774 dsc_slice_count = 775 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, 776 true); 777 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { 778 dsc_max_output_bpp = 779 intel_dp_dsc_get_output_bpp(dev_priv, 780 max_link_clock, 781 max_lanes, 782 target_clock, 783 mode->hdisplay, 784 bigjoiner, 785 pipe_bpp) >> 4; 786 dsc_slice_count = 787 intel_dp_dsc_get_slice_count(intel_dp, 788 target_clock, 789 mode->hdisplay, 790 bigjoiner); 791 } 792 793 dsc = dsc_max_output_bpp && dsc_slice_count; 794 } 795 796 /* 797 * Big joiner configuration needs DSC for TGL which is not true for 798 * XE_LPD where uncompressed joiner is supported. 799 */ 800 if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc) 801 return MODE_CLOCK_HIGH; 802 803 if (mode_rate > max_rate && !dsc) 804 return MODE_CLOCK_HIGH; 805 806 status = intel_dp_mode_valid_downstream(intel_connector, 807 mode, target_clock); 808 if (status != MODE_OK) 809 return status; 810 811 return intel_mode_valid_max_plane_size(dev_priv, mode, bigjoiner); 812 } 813 814 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) 815 { 816 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; 817 818 return max_rate >= 540000; 819 } 820 821 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp) 822 { 823 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; 824 825 return max_rate >= 810000; 826 } 827 828 static void snprintf_int_array(char *str, size_t len, 829 const int *array, int nelem) 830 { 831 int i; 832 833 str[0] = '\0'; 834 835 for (i = 0; i < nelem; i++) { 836 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); 837 if (r >= len) 838 return; 839 str += r; 840 len -= r; 841 } 842 } 843 844 static void intel_dp_print_rates(struct intel_dp *intel_dp) 845 { 846 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 847 char str[128]; /* FIXME: too big for stack? */ 848 849 if (!drm_debug_enabled(DRM_UT_KMS)) 850 return; 851 852 snprintf_int_array(str, sizeof(str), 853 intel_dp->source_rates, intel_dp->num_source_rates); 854 drm_dbg_kms(&i915->drm, "source rates: %s\n", str); 855 856 snprintf_int_array(str, sizeof(str), 857 intel_dp->sink_rates, intel_dp->num_sink_rates); 858 drm_dbg_kms(&i915->drm, "sink rates: %s\n", str); 859 860 snprintf_int_array(str, sizeof(str), 861 intel_dp->common_rates, intel_dp->num_common_rates); 862 drm_dbg_kms(&i915->drm, "common rates: %s\n", str); 863 } 864 865 int 866 intel_dp_max_link_rate(struct intel_dp *intel_dp) 867 { 868 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 869 int len; 870 871 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate); 872 if (drm_WARN_ON(&i915->drm, len <= 0)) 873 return 162000; 874 875 return intel_dp->common_rates[len - 1]; 876 } 877 878 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) 879 { 880 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 881 int i = intel_dp_rate_index(intel_dp->sink_rates, 882 intel_dp->num_sink_rates, rate); 883 884 if (drm_WARN_ON(&i915->drm, i < 0)) 885 i = 0; 886 887 return i; 888 } 889 890 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 891 u8 *link_bw, u8 *rate_select) 892 { 893 /* eDP 1.4 rate select method. */ 894 if (intel_dp->use_rate_select) { 895 *link_bw = 0; 896 *rate_select = 897 intel_dp_rate_select(intel_dp, port_clock); 898 } else { 899 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); 900 *rate_select = 0; 901 } 902 } 903 904 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, 905 const struct intel_crtc_state *pipe_config) 906 { 907 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 908 909 /* On TGL, FEC is supported on all Pipes */ 910 if (DISPLAY_VER(dev_priv) >= 12) 911 return true; 912 913 if (DISPLAY_VER(dev_priv) == 11 && pipe_config->cpu_transcoder != TRANSCODER_A) 914 return true; 915 916 return false; 917 } 918 919 static bool intel_dp_supports_fec(struct intel_dp *intel_dp, 920 const struct intel_crtc_state *pipe_config) 921 { 922 return intel_dp_source_supports_fec(intel_dp, pipe_config) && 923 drm_dp_sink_supports_fec(intel_dp->fec_capable); 924 } 925 926 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, 927 const struct intel_crtc_state *crtc_state) 928 { 929 if (intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP) && !crtc_state->fec_enable) 930 return false; 931 932 return intel_dsc_source_support(crtc_state) && 933 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd); 934 } 935 936 static bool intel_dp_hdmi_ycbcr420(struct intel_dp *intel_dp, 937 const struct intel_crtc_state *crtc_state) 938 { 939 return crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420 || 940 (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 && 941 intel_dp->dfp.ycbcr_444_to_420); 942 } 943 944 static int intel_dp_hdmi_tmds_clock(struct intel_dp *intel_dp, 945 const struct intel_crtc_state *crtc_state, int bpc) 946 { 947 int clock = crtc_state->hw.adjusted_mode.crtc_clock * bpc / 8; 948 949 if (intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) 950 clock /= 2; 951 952 return clock; 953 } 954 955 static bool intel_dp_hdmi_tmds_clock_valid(struct intel_dp *intel_dp, 956 const struct intel_crtc_state *crtc_state, int bpc) 957 { 958 int tmds_clock = intel_dp_hdmi_tmds_clock(intel_dp, crtc_state, bpc); 959 960 if (intel_dp->dfp.min_tmds_clock && 961 tmds_clock < intel_dp->dfp.min_tmds_clock) 962 return false; 963 964 if (intel_dp->dfp.max_tmds_clock && 965 tmds_clock > intel_dp->dfp.max_tmds_clock) 966 return false; 967 968 return true; 969 } 970 971 static bool intel_dp_hdmi_deep_color_possible(struct intel_dp *intel_dp, 972 const struct intel_crtc_state *crtc_state, 973 int bpc) 974 { 975 976 return intel_hdmi_deep_color_possible(crtc_state, bpc, 977 intel_dp->has_hdmi_sink, 978 intel_dp_hdmi_ycbcr420(intel_dp, crtc_state)) && 979 intel_dp_hdmi_tmds_clock_valid(intel_dp, crtc_state, bpc); 980 } 981 982 static int intel_dp_max_bpp(struct intel_dp *intel_dp, 983 const struct intel_crtc_state *crtc_state) 984 { 985 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 986 struct intel_connector *intel_connector = intel_dp->attached_connector; 987 int bpp, bpc; 988 989 bpc = crtc_state->pipe_bpp / 3; 990 991 if (intel_dp->dfp.max_bpc) 992 bpc = min_t(int, bpc, intel_dp->dfp.max_bpc); 993 994 if (intel_dp->dfp.min_tmds_clock) { 995 for (; bpc >= 10; bpc -= 2) { 996 if (intel_dp_hdmi_deep_color_possible(intel_dp, crtc_state, bpc)) 997 break; 998 } 999 } 1000 1001 bpp = bpc * 3; 1002 if (intel_dp_is_edp(intel_dp)) { 1003 /* Get bpp from vbt only for panels that dont have bpp in edid */ 1004 if (intel_connector->base.display_info.bpc == 0 && 1005 dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) { 1006 drm_dbg_kms(&dev_priv->drm, 1007 "clamping bpp for eDP panel to BIOS-provided %i\n", 1008 dev_priv->vbt.edp.bpp); 1009 bpp = dev_priv->vbt.edp.bpp; 1010 } 1011 } 1012 1013 return bpp; 1014 } 1015 1016 /* Adjust link config limits based on compliance test requests. */ 1017 void 1018 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, 1019 struct intel_crtc_state *pipe_config, 1020 struct link_config_limits *limits) 1021 { 1022 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1023 1024 /* For DP Compliance we override the computed bpp for the pipe */ 1025 if (intel_dp->compliance.test_data.bpc != 0) { 1026 int bpp = 3 * intel_dp->compliance.test_data.bpc; 1027 1028 limits->min_bpp = limits->max_bpp = bpp; 1029 pipe_config->dither_force_disable = bpp == 6 * 3; 1030 1031 drm_dbg_kms(&i915->drm, "Setting pipe_bpp to %d\n", bpp); 1032 } 1033 1034 /* Use values requested by Compliance Test Request */ 1035 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { 1036 int index; 1037 1038 /* Validate the compliance test data since max values 1039 * might have changed due to link train fallback. 1040 */ 1041 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, 1042 intel_dp->compliance.test_lane_count)) { 1043 index = intel_dp_rate_index(intel_dp->common_rates, 1044 intel_dp->num_common_rates, 1045 intel_dp->compliance.test_link_rate); 1046 if (index >= 0) 1047 limits->min_clock = limits->max_clock = index; 1048 limits->min_lane_count = limits->max_lane_count = 1049 intel_dp->compliance.test_lane_count; 1050 } 1051 } 1052 } 1053 1054 /* Optimize link config in order: max bpp, min clock, min lanes */ 1055 static int 1056 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, 1057 struct intel_crtc_state *pipe_config, 1058 const struct link_config_limits *limits) 1059 { 1060 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1061 int bpp, clock, lane_count; 1062 int mode_rate, link_clock, link_avail; 1063 1064 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { 1065 int output_bpp = intel_dp_output_bpp(pipe_config->output_format, bpp); 1066 1067 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 1068 output_bpp); 1069 1070 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) { 1071 for (lane_count = limits->min_lane_count; 1072 lane_count <= limits->max_lane_count; 1073 lane_count <<= 1) { 1074 link_clock = intel_dp->common_rates[clock]; 1075 link_avail = intel_dp_max_data_rate(link_clock, 1076 lane_count); 1077 1078 if (mode_rate <= link_avail) { 1079 pipe_config->lane_count = lane_count; 1080 pipe_config->pipe_bpp = bpp; 1081 pipe_config->port_clock = link_clock; 1082 1083 return 0; 1084 } 1085 } 1086 } 1087 } 1088 1089 return -EINVAL; 1090 } 1091 1092 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) 1093 { 1094 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1095 int i, num_bpc; 1096 u8 dsc_bpc[3] = {0}; 1097 u8 dsc_max_bpc; 1098 1099 /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ 1100 if (DISPLAY_VER(i915) >= 12) 1101 dsc_max_bpc = min_t(u8, 12, max_req_bpc); 1102 else 1103 dsc_max_bpc = min_t(u8, 10, max_req_bpc); 1104 1105 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, 1106 dsc_bpc); 1107 for (i = 0; i < num_bpc; i++) { 1108 if (dsc_max_bpc >= dsc_bpc[i]) 1109 return dsc_bpc[i] * 3; 1110 } 1111 1112 return 0; 1113 } 1114 1115 #define DSC_SUPPORTED_VERSION_MIN 1 1116 1117 static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, 1118 struct intel_crtc_state *crtc_state) 1119 { 1120 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1121 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1122 struct drm_dsc_config *vdsc_cfg = &crtc_state->dsc.config; 1123 u8 line_buf_depth; 1124 int ret; 1125 1126 /* 1127 * RC_MODEL_SIZE is currently a constant across all configurations. 1128 * 1129 * FIXME: Look into using sink defined DPCD DP_DSC_RC_BUF_BLK_SIZE and 1130 * DP_DSC_RC_BUF_SIZE for this. 1131 */ 1132 vdsc_cfg->rc_model_size = DSC_RC_MODEL_SIZE_CONST; 1133 1134 /* 1135 * Slice Height of 8 works for all currently available panels. So start 1136 * with that if pic_height is an integral multiple of 8. Eventually add 1137 * logic to try multiple slice heights. 1138 */ 1139 if (vdsc_cfg->pic_height % 8 == 0) 1140 vdsc_cfg->slice_height = 8; 1141 else if (vdsc_cfg->pic_height % 4 == 0) 1142 vdsc_cfg->slice_height = 4; 1143 else 1144 vdsc_cfg->slice_height = 2; 1145 1146 ret = intel_dsc_compute_params(encoder, crtc_state); 1147 if (ret) 1148 return ret; 1149 1150 vdsc_cfg->dsc_version_major = 1151 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & 1152 DP_DSC_MAJOR_MASK) >> DP_DSC_MAJOR_SHIFT; 1153 vdsc_cfg->dsc_version_minor = 1154 min(DSC_SUPPORTED_VERSION_MIN, 1155 (intel_dp->dsc_dpcd[DP_DSC_REV - DP_DSC_SUPPORT] & 1156 DP_DSC_MINOR_MASK) >> DP_DSC_MINOR_SHIFT); 1157 1158 vdsc_cfg->convert_rgb = intel_dp->dsc_dpcd[DP_DSC_DEC_COLOR_FORMAT_CAP - DP_DSC_SUPPORT] & 1159 DP_DSC_RGB; 1160 1161 line_buf_depth = drm_dp_dsc_sink_line_buf_depth(intel_dp->dsc_dpcd); 1162 if (!line_buf_depth) { 1163 drm_dbg_kms(&i915->drm, 1164 "DSC Sink Line Buffer Depth invalid\n"); 1165 return -EINVAL; 1166 } 1167 1168 if (vdsc_cfg->dsc_version_minor == 2) 1169 vdsc_cfg->line_buf_depth = (line_buf_depth == DSC_1_2_MAX_LINEBUF_DEPTH_BITS) ? 1170 DSC_1_2_MAX_LINEBUF_DEPTH_VAL : line_buf_depth; 1171 else 1172 vdsc_cfg->line_buf_depth = (line_buf_depth > DSC_1_1_MAX_LINEBUF_DEPTH_BITS) ? 1173 DSC_1_1_MAX_LINEBUF_DEPTH_BITS : line_buf_depth; 1174 1175 vdsc_cfg->block_pred_enable = 1176 intel_dp->dsc_dpcd[DP_DSC_BLK_PREDICTION_SUPPORT - DP_DSC_SUPPORT] & 1177 DP_DSC_BLK_PREDICTION_IS_SUPPORTED; 1178 1179 return drm_dsc_compute_rc_parameters(vdsc_cfg); 1180 } 1181 1182 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 1183 struct intel_crtc_state *pipe_config, 1184 struct drm_connector_state *conn_state, 1185 struct link_config_limits *limits) 1186 { 1187 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1188 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 1189 const struct drm_display_mode *adjusted_mode = 1190 &pipe_config->hw.adjusted_mode; 1191 int pipe_bpp; 1192 int ret; 1193 1194 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && 1195 intel_dp_supports_fec(intel_dp, pipe_config); 1196 1197 if (!intel_dp_supports_dsc(intel_dp, pipe_config)) 1198 return -EINVAL; 1199 1200 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, conn_state->max_requested_bpc); 1201 1202 /* Min Input BPC for ICL+ is 8 */ 1203 if (pipe_bpp < 8 * 3) { 1204 drm_dbg_kms(&dev_priv->drm, 1205 "No DSC support for less than 8bpc\n"); 1206 return -EINVAL; 1207 } 1208 1209 /* 1210 * For now enable DSC for max bpp, max link rate, max lane count. 1211 * Optimize this later for the minimum possible link rate/lane count 1212 * with DSC enabled for the requested mode. 1213 */ 1214 pipe_config->pipe_bpp = pipe_bpp; 1215 pipe_config->port_clock = intel_dp->common_rates[limits->max_clock]; 1216 pipe_config->lane_count = limits->max_lane_count; 1217 1218 if (intel_dp_is_edp(intel_dp)) { 1219 pipe_config->dsc.compressed_bpp = 1220 min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4, 1221 pipe_config->pipe_bpp); 1222 pipe_config->dsc.slice_count = 1223 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, 1224 true); 1225 } else { 1226 u16 dsc_max_output_bpp; 1227 u8 dsc_dp_slice_count; 1228 1229 dsc_max_output_bpp = 1230 intel_dp_dsc_get_output_bpp(dev_priv, 1231 pipe_config->port_clock, 1232 pipe_config->lane_count, 1233 adjusted_mode->crtc_clock, 1234 adjusted_mode->crtc_hdisplay, 1235 pipe_config->bigjoiner, 1236 pipe_bpp); 1237 dsc_dp_slice_count = 1238 intel_dp_dsc_get_slice_count(intel_dp, 1239 adjusted_mode->crtc_clock, 1240 adjusted_mode->crtc_hdisplay, 1241 pipe_config->bigjoiner); 1242 if (!dsc_max_output_bpp || !dsc_dp_slice_count) { 1243 drm_dbg_kms(&dev_priv->drm, 1244 "Compressed BPP/Slice Count not supported\n"); 1245 return -EINVAL; 1246 } 1247 pipe_config->dsc.compressed_bpp = min_t(u16, 1248 dsc_max_output_bpp >> 4, 1249 pipe_config->pipe_bpp); 1250 pipe_config->dsc.slice_count = dsc_dp_slice_count; 1251 } 1252 1253 /* As of today we support DSC for only RGB */ 1254 if (intel_dp->force_dsc_bpp) { 1255 if (intel_dp->force_dsc_bpp >= 8 && 1256 intel_dp->force_dsc_bpp < pipe_bpp) { 1257 drm_dbg_kms(&dev_priv->drm, 1258 "DSC BPP forced to %d", 1259 intel_dp->force_dsc_bpp); 1260 pipe_config->dsc.compressed_bpp = 1261 intel_dp->force_dsc_bpp; 1262 } else { 1263 drm_dbg_kms(&dev_priv->drm, 1264 "Invalid DSC BPP %d", 1265 intel_dp->force_dsc_bpp); 1266 } 1267 } 1268 1269 /* 1270 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate 1271 * is greater than the maximum Cdclock and if slice count is even 1272 * then we need to use 2 VDSC instances. 1273 */ 1274 if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq || 1275 pipe_config->bigjoiner) { 1276 if (pipe_config->dsc.slice_count < 2) { 1277 drm_dbg_kms(&dev_priv->drm, 1278 "Cannot split stream to use 2 VDSC instances\n"); 1279 return -EINVAL; 1280 } 1281 1282 pipe_config->dsc.dsc_split = true; 1283 } 1284 1285 ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config); 1286 if (ret < 0) { 1287 drm_dbg_kms(&dev_priv->drm, 1288 "Cannot compute valid DSC parameters for Input Bpp = %d " 1289 "Compressed BPP = %d\n", 1290 pipe_config->pipe_bpp, 1291 pipe_config->dsc.compressed_bpp); 1292 return ret; 1293 } 1294 1295 pipe_config->dsc.compression_enable = true; 1296 drm_dbg_kms(&dev_priv->drm, "DP DSC computed with Input Bpp = %d " 1297 "Compressed Bpp = %d Slice Count = %d\n", 1298 pipe_config->pipe_bpp, 1299 pipe_config->dsc.compressed_bpp, 1300 pipe_config->dsc.slice_count); 1301 1302 return 0; 1303 } 1304 1305 static int 1306 intel_dp_compute_link_config(struct intel_encoder *encoder, 1307 struct intel_crtc_state *pipe_config, 1308 struct drm_connector_state *conn_state) 1309 { 1310 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1311 const struct drm_display_mode *adjusted_mode = 1312 &pipe_config->hw.adjusted_mode; 1313 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1314 struct link_config_limits limits; 1315 int common_len; 1316 int ret; 1317 1318 common_len = intel_dp_common_len_rate_limit(intel_dp, 1319 intel_dp->max_link_rate); 1320 1321 /* No common link rates between source and sink */ 1322 drm_WARN_ON(encoder->base.dev, common_len <= 0); 1323 1324 limits.min_clock = 0; 1325 limits.max_clock = common_len - 1; 1326 1327 limits.min_lane_count = 1; 1328 limits.max_lane_count = intel_dp_max_lane_count(intel_dp); 1329 1330 limits.min_bpp = intel_dp_min_bpp(pipe_config->output_format); 1331 limits.max_bpp = intel_dp_max_bpp(intel_dp, pipe_config); 1332 1333 if (intel_dp->use_max_params) { 1334 /* 1335 * Use the maximum clock and number of lanes the eDP panel 1336 * advertizes being capable of in case the initial fast 1337 * optimal params failed us. The panels are generally 1338 * designed to support only a single clock and lane 1339 * configuration, and typically on older panels these 1340 * values correspond to the native resolution of the panel. 1341 */ 1342 limits.min_lane_count = limits.max_lane_count; 1343 limits.min_clock = limits.max_clock; 1344 } 1345 1346 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); 1347 1348 drm_dbg_kms(&i915->drm, "DP link computation with max lane count %i " 1349 "max rate %d max bpp %d pixel clock %iKHz\n", 1350 limits.max_lane_count, 1351 intel_dp->common_rates[limits.max_clock], 1352 limits.max_bpp, adjusted_mode->crtc_clock); 1353 1354 if ((adjusted_mode->crtc_clock > i915->max_dotclk_freq || 1355 adjusted_mode->crtc_hdisplay > 5120) && 1356 intel_dp_can_bigjoiner(intel_dp)) 1357 pipe_config->bigjoiner = true; 1358 1359 /* 1360 * Optimize for slow and wide for everything, because there are some 1361 * eDP 1.3 and 1.4 panels don't work well with fast and narrow. 1362 */ 1363 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits); 1364 1365 /* 1366 * Pipe joiner needs compression upto display12 due to BW limitation. DG2 1367 * onwards pipe joiner can be enabled without compression. 1368 */ 1369 drm_dbg_kms(&i915->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); 1370 if (ret || intel_dp->force_dsc_en || (DISPLAY_VER(i915) < 13 && 1371 pipe_config->bigjoiner)) { 1372 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, 1373 conn_state, &limits); 1374 if (ret < 0) 1375 return ret; 1376 } 1377 1378 if (pipe_config->dsc.compression_enable) { 1379 drm_dbg_kms(&i915->drm, 1380 "DP lane count %d clock %d Input bpp %d Compressed bpp %d\n", 1381 pipe_config->lane_count, pipe_config->port_clock, 1382 pipe_config->pipe_bpp, 1383 pipe_config->dsc.compressed_bpp); 1384 1385 drm_dbg_kms(&i915->drm, 1386 "DP link rate required %i available %i\n", 1387 intel_dp_link_required(adjusted_mode->crtc_clock, 1388 pipe_config->dsc.compressed_bpp), 1389 intel_dp_max_data_rate(pipe_config->port_clock, 1390 pipe_config->lane_count)); 1391 } else { 1392 drm_dbg_kms(&i915->drm, "DP lane count %d clock %d bpp %d\n", 1393 pipe_config->lane_count, pipe_config->port_clock, 1394 pipe_config->pipe_bpp); 1395 1396 drm_dbg_kms(&i915->drm, 1397 "DP link rate required %i available %i\n", 1398 intel_dp_link_required(adjusted_mode->crtc_clock, 1399 pipe_config->pipe_bpp), 1400 intel_dp_max_data_rate(pipe_config->port_clock, 1401 pipe_config->lane_count)); 1402 } 1403 return 0; 1404 } 1405 1406 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, 1407 const struct drm_connector_state *conn_state) 1408 { 1409 const struct intel_digital_connector_state *intel_conn_state = 1410 to_intel_digital_connector_state(conn_state); 1411 const struct drm_display_mode *adjusted_mode = 1412 &crtc_state->hw.adjusted_mode; 1413 1414 /* 1415 * Our YCbCr output is always limited range. 1416 * crtc_state->limited_color_range only applies to RGB, 1417 * and it must never be set for YCbCr or we risk setting 1418 * some conflicting bits in PIPECONF which will mess up 1419 * the colors on the monitor. 1420 */ 1421 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_RGB) 1422 return false; 1423 1424 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 1425 /* 1426 * See: 1427 * CEA-861-E - 5.1 Default Encoding Parameters 1428 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 1429 */ 1430 return crtc_state->pipe_bpp != 18 && 1431 drm_default_rgb_quant_range(adjusted_mode) == 1432 HDMI_QUANTIZATION_RANGE_LIMITED; 1433 } else { 1434 return intel_conn_state->broadcast_rgb == 1435 INTEL_BROADCAST_RGB_LIMITED; 1436 } 1437 } 1438 1439 static bool intel_dp_port_has_audio(struct drm_i915_private *dev_priv, 1440 enum port port) 1441 { 1442 if (IS_G4X(dev_priv)) 1443 return false; 1444 if (DISPLAY_VER(dev_priv) < 12 && port == PORT_A) 1445 return false; 1446 1447 return true; 1448 } 1449 1450 static void intel_dp_compute_vsc_colorimetry(const struct intel_crtc_state *crtc_state, 1451 const struct drm_connector_state *conn_state, 1452 struct drm_dp_vsc_sdp *vsc) 1453 { 1454 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 1455 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 1456 1457 /* 1458 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 1459 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ 1460 * Colorimetry Format indication. 1461 */ 1462 vsc->revision = 0x5; 1463 vsc->length = 0x13; 1464 1465 /* DP 1.4a spec, Table 2-120 */ 1466 switch (crtc_state->output_format) { 1467 case INTEL_OUTPUT_FORMAT_YCBCR444: 1468 vsc->pixelformat = DP_PIXELFORMAT_YUV444; 1469 break; 1470 case INTEL_OUTPUT_FORMAT_YCBCR420: 1471 vsc->pixelformat = DP_PIXELFORMAT_YUV420; 1472 break; 1473 case INTEL_OUTPUT_FORMAT_RGB: 1474 default: 1475 vsc->pixelformat = DP_PIXELFORMAT_RGB; 1476 } 1477 1478 switch (conn_state->colorspace) { 1479 case DRM_MODE_COLORIMETRY_BT709_YCC: 1480 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 1481 break; 1482 case DRM_MODE_COLORIMETRY_XVYCC_601: 1483 vsc->colorimetry = DP_COLORIMETRY_XVYCC_601; 1484 break; 1485 case DRM_MODE_COLORIMETRY_XVYCC_709: 1486 vsc->colorimetry = DP_COLORIMETRY_XVYCC_709; 1487 break; 1488 case DRM_MODE_COLORIMETRY_SYCC_601: 1489 vsc->colorimetry = DP_COLORIMETRY_SYCC_601; 1490 break; 1491 case DRM_MODE_COLORIMETRY_OPYCC_601: 1492 vsc->colorimetry = DP_COLORIMETRY_OPYCC_601; 1493 break; 1494 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 1495 vsc->colorimetry = DP_COLORIMETRY_BT2020_CYCC; 1496 break; 1497 case DRM_MODE_COLORIMETRY_BT2020_RGB: 1498 vsc->colorimetry = DP_COLORIMETRY_BT2020_RGB; 1499 break; 1500 case DRM_MODE_COLORIMETRY_BT2020_YCC: 1501 vsc->colorimetry = DP_COLORIMETRY_BT2020_YCC; 1502 break; 1503 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_D65: 1504 case DRM_MODE_COLORIMETRY_DCI_P3_RGB_THEATER: 1505 vsc->colorimetry = DP_COLORIMETRY_DCI_P3_RGB; 1506 break; 1507 default: 1508 /* 1509 * RGB->YCBCR color conversion uses the BT.709 1510 * color space. 1511 */ 1512 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1513 vsc->colorimetry = DP_COLORIMETRY_BT709_YCC; 1514 else 1515 vsc->colorimetry = DP_COLORIMETRY_DEFAULT; 1516 break; 1517 } 1518 1519 vsc->bpc = crtc_state->pipe_bpp / 3; 1520 1521 /* only RGB pixelformat supports 6 bpc */ 1522 drm_WARN_ON(&dev_priv->drm, 1523 vsc->bpc == 6 && vsc->pixelformat != DP_PIXELFORMAT_RGB); 1524 1525 /* all YCbCr are always limited range */ 1526 vsc->dynamic_range = DP_DYNAMIC_RANGE_CTA; 1527 vsc->content_type = DP_CONTENT_TYPE_NOT_DEFINED; 1528 } 1529 1530 static void intel_dp_compute_vsc_sdp(struct intel_dp *intel_dp, 1531 struct intel_crtc_state *crtc_state, 1532 const struct drm_connector_state *conn_state) 1533 { 1534 struct drm_dp_vsc_sdp *vsc = &crtc_state->infoframes.vsc; 1535 1536 /* When a crtc state has PSR, VSC SDP will be handled by PSR routine */ 1537 if (crtc_state->has_psr) 1538 return; 1539 1540 if (!intel_dp_needs_vsc_sdp(crtc_state, conn_state)) 1541 return; 1542 1543 crtc_state->infoframes.enable |= intel_hdmi_infoframe_enable(DP_SDP_VSC); 1544 vsc->sdp_type = DP_SDP_VSC; 1545 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, 1546 &crtc_state->infoframes.vsc); 1547 } 1548 1549 void intel_dp_compute_psr_vsc_sdp(struct intel_dp *intel_dp, 1550 const struct intel_crtc_state *crtc_state, 1551 const struct drm_connector_state *conn_state, 1552 struct drm_dp_vsc_sdp *vsc) 1553 { 1554 vsc->sdp_type = DP_SDP_VSC; 1555 1556 if (intel_dp->psr.psr2_enabled) { 1557 if (intel_dp->psr.colorimetry_support && 1558 intel_dp_needs_vsc_sdp(crtc_state, conn_state)) { 1559 /* [PSR2, +Colorimetry] */ 1560 intel_dp_compute_vsc_colorimetry(crtc_state, conn_state, 1561 vsc); 1562 } else { 1563 /* 1564 * [PSR2, -Colorimetry] 1565 * Prepare VSC Header for SU as per eDP 1.4 spec, Table 6-11 1566 * 3D stereo + PSR/PSR2 + Y-coordinate. 1567 */ 1568 vsc->revision = 0x4; 1569 vsc->length = 0xe; 1570 } 1571 } else { 1572 /* 1573 * [PSR1] 1574 * Prepare VSC Header for SU as per DP 1.4 spec, Table 2-118 1575 * VSC SDP supporting 3D stereo + PSR (applies to eDP v1.3 or 1576 * higher). 1577 */ 1578 vsc->revision = 0x2; 1579 vsc->length = 0x8; 1580 } 1581 } 1582 1583 static void 1584 intel_dp_compute_hdr_metadata_infoframe_sdp(struct intel_dp *intel_dp, 1585 struct intel_crtc_state *crtc_state, 1586 const struct drm_connector_state *conn_state) 1587 { 1588 int ret; 1589 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1590 struct hdmi_drm_infoframe *drm_infoframe = &crtc_state->infoframes.drm.drm; 1591 1592 if (!conn_state->hdr_output_metadata) 1593 return; 1594 1595 ret = drm_hdmi_infoframe_set_hdr_metadata(drm_infoframe, conn_state); 1596 1597 if (ret) { 1598 drm_dbg_kms(&dev_priv->drm, "couldn't set HDR metadata in infoframe\n"); 1599 return; 1600 } 1601 1602 crtc_state->infoframes.enable |= 1603 intel_hdmi_infoframe_enable(HDMI_PACKET_TYPE_GAMUT_METADATA); 1604 } 1605 1606 static void 1607 intel_dp_drrs_compute_config(struct intel_dp *intel_dp, 1608 struct intel_crtc_state *pipe_config, 1609 int output_bpp, bool constant_n) 1610 { 1611 struct intel_connector *intel_connector = intel_dp->attached_connector; 1612 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1613 int pixel_clock; 1614 1615 if (pipe_config->vrr.enable) 1616 return; 1617 1618 /* 1619 * DRRS and PSR can't be enable together, so giving preference to PSR 1620 * as it allows more power-savings by complete shutting down display, 1621 * so to guarantee this, intel_dp_drrs_compute_config() must be called 1622 * after intel_psr_compute_config(). 1623 */ 1624 if (pipe_config->has_psr) 1625 return; 1626 1627 if (!intel_connector->panel.downclock_mode || 1628 dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT) 1629 return; 1630 1631 pipe_config->has_drrs = true; 1632 1633 pixel_clock = intel_connector->panel.downclock_mode->clock; 1634 if (pipe_config->splitter.enable) 1635 pixel_clock /= pipe_config->splitter.link_count; 1636 1637 intel_link_compute_m_n(output_bpp, pipe_config->lane_count, pixel_clock, 1638 pipe_config->port_clock, &pipe_config->dp_m2_n2, 1639 constant_n, pipe_config->fec_enable); 1640 1641 /* FIXME: abstract this better */ 1642 if (pipe_config->splitter.enable) 1643 pipe_config->dp_m2_n2.gmch_m *= pipe_config->splitter.link_count; 1644 } 1645 1646 int 1647 intel_dp_compute_config(struct intel_encoder *encoder, 1648 struct intel_crtc_state *pipe_config, 1649 struct drm_connector_state *conn_state) 1650 { 1651 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1652 struct drm_display_mode *adjusted_mode = &pipe_config->hw.adjusted_mode; 1653 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1654 enum port port = encoder->port; 1655 struct intel_connector *intel_connector = intel_dp->attached_connector; 1656 struct intel_digital_connector_state *intel_conn_state = 1657 to_intel_digital_connector_state(conn_state); 1658 bool constant_n = drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_CONSTANT_N); 1659 int ret = 0, output_bpp; 1660 1661 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) 1662 pipe_config->has_pch_encoder = true; 1663 1664 pipe_config->output_format = intel_dp_output_format(&intel_connector->base, 1665 adjusted_mode); 1666 1667 if (pipe_config->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) { 1668 ret = intel_pch_panel_fitting(pipe_config, conn_state); 1669 if (ret) 1670 return ret; 1671 } 1672 1673 if (!intel_dp_port_has_audio(dev_priv, port)) 1674 pipe_config->has_audio = false; 1675 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 1676 pipe_config->has_audio = intel_dp->has_audio; 1677 else 1678 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; 1679 1680 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 1681 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 1682 adjusted_mode); 1683 1684 if (HAS_GMCH(dev_priv)) 1685 ret = intel_gmch_panel_fitting(pipe_config, conn_state); 1686 else 1687 ret = intel_pch_panel_fitting(pipe_config, conn_state); 1688 if (ret) 1689 return ret; 1690 } 1691 1692 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 1693 return -EINVAL; 1694 1695 if (HAS_GMCH(dev_priv) && 1696 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 1697 return -EINVAL; 1698 1699 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 1700 return -EINVAL; 1701 1702 if (intel_dp_hdisplay_bad(dev_priv, adjusted_mode->crtc_hdisplay)) 1703 return -EINVAL; 1704 1705 ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state); 1706 if (ret < 0) 1707 return ret; 1708 1709 pipe_config->limited_color_range = 1710 intel_dp_limited_color_range(pipe_config, conn_state); 1711 1712 if (pipe_config->dsc.compression_enable) 1713 output_bpp = pipe_config->dsc.compressed_bpp; 1714 else 1715 output_bpp = intel_dp_output_bpp(pipe_config->output_format, 1716 pipe_config->pipe_bpp); 1717 1718 if (intel_dp->mso_link_count) { 1719 int n = intel_dp->mso_link_count; 1720 int overlap = intel_dp->mso_pixel_overlap; 1721 1722 pipe_config->splitter.enable = true; 1723 pipe_config->splitter.link_count = n; 1724 pipe_config->splitter.pixel_overlap = overlap; 1725 1726 drm_dbg_kms(&dev_priv->drm, "MSO link count %d, pixel overlap %d\n", 1727 n, overlap); 1728 1729 adjusted_mode->crtc_hdisplay = adjusted_mode->crtc_hdisplay / n + overlap; 1730 adjusted_mode->crtc_hblank_start = adjusted_mode->crtc_hblank_start / n + overlap; 1731 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_end / n + overlap; 1732 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hsync_start / n + overlap; 1733 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_end / n + overlap; 1734 adjusted_mode->crtc_htotal = adjusted_mode->crtc_htotal / n + overlap; 1735 adjusted_mode->crtc_clock /= n; 1736 } 1737 1738 intel_link_compute_m_n(output_bpp, 1739 pipe_config->lane_count, 1740 adjusted_mode->crtc_clock, 1741 pipe_config->port_clock, 1742 &pipe_config->dp_m_n, 1743 constant_n, pipe_config->fec_enable); 1744 1745 /* FIXME: abstract this better */ 1746 if (pipe_config->splitter.enable) 1747 pipe_config->dp_m_n.gmch_m *= pipe_config->splitter.link_count; 1748 1749 if (!HAS_DDI(dev_priv)) 1750 g4x_dp_set_clock(encoder, pipe_config); 1751 1752 intel_vrr_compute_config(pipe_config, conn_state); 1753 intel_psr_compute_config(intel_dp, pipe_config); 1754 intel_dp_drrs_compute_config(intel_dp, pipe_config, output_bpp, 1755 constant_n); 1756 intel_dp_compute_vsc_sdp(intel_dp, pipe_config, conn_state); 1757 intel_dp_compute_hdr_metadata_infoframe_sdp(intel_dp, pipe_config, conn_state); 1758 1759 return 0; 1760 } 1761 1762 void intel_dp_set_link_params(struct intel_dp *intel_dp, 1763 int link_rate, int lane_count) 1764 { 1765 intel_dp->link_trained = false; 1766 intel_dp->link_rate = link_rate; 1767 intel_dp->lane_count = lane_count; 1768 } 1769 1770 /* Enable backlight PWM and backlight PP control. */ 1771 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, 1772 const struct drm_connector_state *conn_state) 1773 { 1774 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(conn_state->best_encoder)); 1775 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1776 1777 if (!intel_dp_is_edp(intel_dp)) 1778 return; 1779 1780 drm_dbg_kms(&i915->drm, "\n"); 1781 1782 intel_panel_enable_backlight(crtc_state, conn_state); 1783 intel_pps_backlight_on(intel_dp); 1784 } 1785 1786 /* Disable backlight PP control and backlight PWM. */ 1787 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) 1788 { 1789 struct intel_dp *intel_dp = enc_to_intel_dp(to_intel_encoder(old_conn_state->best_encoder)); 1790 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1791 1792 if (!intel_dp_is_edp(intel_dp)) 1793 return; 1794 1795 drm_dbg_kms(&i915->drm, "\n"); 1796 1797 intel_pps_backlight_off(intel_dp); 1798 intel_panel_disable_backlight(old_conn_state); 1799 } 1800 1801 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) 1802 { 1803 /* 1804 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus 1805 * be capable of signalling downstream hpd with a long pulse. 1806 * Whether or not that means D3 is safe to use is not clear, 1807 * but let's assume so until proven otherwise. 1808 * 1809 * FIXME should really check all downstream ports... 1810 */ 1811 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && 1812 drm_dp_is_branch(intel_dp->dpcd) && 1813 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; 1814 } 1815 1816 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, 1817 const struct intel_crtc_state *crtc_state, 1818 bool enable) 1819 { 1820 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1821 int ret; 1822 1823 if (!crtc_state->dsc.compression_enable) 1824 return; 1825 1826 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, 1827 enable ? DP_DECOMPRESSION_EN : 0); 1828 if (ret < 0) 1829 drm_dbg_kms(&i915->drm, 1830 "Failed to %s sink decompression state\n", 1831 enabledisable(enable)); 1832 } 1833 1834 static void 1835 intel_edp_init_source_oui(struct intel_dp *intel_dp, bool careful) 1836 { 1837 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1838 u8 oui[] = { 0x00, 0xaa, 0x01 }; 1839 u8 buf[3] = { 0 }; 1840 1841 /* 1842 * During driver init, we want to be careful and avoid changing the source OUI if it's 1843 * already set to what we want, so as to avoid clearing any state by accident 1844 */ 1845 if (careful) { 1846 if (drm_dp_dpcd_read(&intel_dp->aux, DP_SOURCE_OUI, buf, sizeof(buf)) < 0) 1847 drm_err(&i915->drm, "Failed to read source OUI\n"); 1848 1849 if (memcmp(oui, buf, sizeof(oui)) == 0) 1850 return; 1851 } 1852 1853 if (drm_dp_dpcd_write(&intel_dp->aux, DP_SOURCE_OUI, oui, sizeof(oui)) < 0) 1854 drm_err(&i915->drm, "Failed to write source OUI\n"); 1855 } 1856 1857 /* If the device supports it, try to set the power state appropriately */ 1858 void intel_dp_set_power(struct intel_dp *intel_dp, u8 mode) 1859 { 1860 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 1861 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1862 int ret, i; 1863 1864 /* Should have a valid DPCD by this point */ 1865 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 1866 return; 1867 1868 if (mode != DP_SET_POWER_D0) { 1869 if (downstream_hpd_needs_d0(intel_dp)) 1870 return; 1871 1872 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 1873 } else { 1874 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); 1875 1876 lspcon_resume(dp_to_dig_port(intel_dp)); 1877 1878 /* Write the source OUI as early as possible */ 1879 if (intel_dp_is_edp(intel_dp)) 1880 intel_edp_init_source_oui(intel_dp, false); 1881 1882 /* 1883 * When turning on, we need to retry for 1ms to give the sink 1884 * time to wake up. 1885 */ 1886 for (i = 0; i < 3; i++) { 1887 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, mode); 1888 if (ret == 1) 1889 break; 1890 msleep(1); 1891 } 1892 1893 if (ret == 1 && lspcon->active) 1894 lspcon_wait_pcon_mode(lspcon); 1895 } 1896 1897 if (ret != 1) 1898 drm_dbg_kms(&i915->drm, "[ENCODER:%d:%s] Set power to %s failed\n", 1899 encoder->base.base.id, encoder->base.name, 1900 mode == DP_SET_POWER_D0 ? "D0" : "D3"); 1901 } 1902 1903 static bool 1904 intel_dp_get_dpcd(struct intel_dp *intel_dp); 1905 1906 /** 1907 * intel_dp_sync_state - sync the encoder state during init/resume 1908 * @encoder: intel encoder to sync 1909 * @crtc_state: state for the CRTC connected to the encoder 1910 * 1911 * Sync any state stored in the encoder wrt. HW state during driver init 1912 * and system resume. 1913 */ 1914 void intel_dp_sync_state(struct intel_encoder *encoder, 1915 const struct intel_crtc_state *crtc_state) 1916 { 1917 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1918 1919 /* 1920 * Don't clobber DPCD if it's been already read out during output 1921 * setup (eDP) or detect. 1922 */ 1923 if (intel_dp->dpcd[DP_DPCD_REV] == 0) 1924 intel_dp_get_dpcd(intel_dp); 1925 1926 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); 1927 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); 1928 } 1929 1930 bool intel_dp_initial_fastset_check(struct intel_encoder *encoder, 1931 struct intel_crtc_state *crtc_state) 1932 { 1933 struct drm_i915_private *i915 = to_i915(encoder->base.dev); 1934 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 1935 1936 /* 1937 * If BIOS has set an unsupported or non-standard link rate for some 1938 * reason force an encoder recompute and full modeset. 1939 */ 1940 if (intel_dp_rate_index(intel_dp->source_rates, intel_dp->num_source_rates, 1941 crtc_state->port_clock) < 0) { 1942 drm_dbg_kms(&i915->drm, "Forcing full modeset due to unsupported link rate\n"); 1943 crtc_state->uapi.connectors_changed = true; 1944 return false; 1945 } 1946 1947 /* 1948 * FIXME hack to force full modeset when DSC is being used. 1949 * 1950 * As long as we do not have full state readout and config comparison 1951 * of crtc_state->dsc, we have no way to ensure reliable fastset. 1952 * Remove once we have readout for DSC. 1953 */ 1954 if (crtc_state->dsc.compression_enable) { 1955 drm_dbg_kms(&i915->drm, "Forcing full modeset due to DSC being enabled\n"); 1956 crtc_state->uapi.mode_changed = true; 1957 return false; 1958 } 1959 1960 if (CAN_PSR(intel_dp)) { 1961 drm_dbg_kms(&i915->drm, "Forcing full modeset to compute PSR state\n"); 1962 crtc_state->uapi.mode_changed = true; 1963 return false; 1964 } 1965 1966 return true; 1967 } 1968 1969 static void intel_dp_get_pcon_dsc_cap(struct intel_dp *intel_dp) 1970 { 1971 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1972 1973 /* Clear the cached register set to avoid using stale values */ 1974 1975 memset(intel_dp->pcon_dsc_dpcd, 0, sizeof(intel_dp->pcon_dsc_dpcd)); 1976 1977 if (drm_dp_dpcd_read(&intel_dp->aux, DP_PCON_DSC_ENCODER, 1978 intel_dp->pcon_dsc_dpcd, 1979 sizeof(intel_dp->pcon_dsc_dpcd)) < 0) 1980 drm_err(&i915->drm, "Failed to read DPCD register 0x%x\n", 1981 DP_PCON_DSC_ENCODER); 1982 1983 drm_dbg_kms(&i915->drm, "PCON ENCODER DSC DPCD: %*ph\n", 1984 (int)sizeof(intel_dp->pcon_dsc_dpcd), intel_dp->pcon_dsc_dpcd); 1985 } 1986 1987 static int intel_dp_pcon_get_frl_mask(u8 frl_bw_mask) 1988 { 1989 int bw_gbps[] = {9, 18, 24, 32, 40, 48}; 1990 int i; 1991 1992 for (i = ARRAY_SIZE(bw_gbps) - 1; i >= 0; i--) { 1993 if (frl_bw_mask & (1 << i)) 1994 return bw_gbps[i]; 1995 } 1996 return 0; 1997 } 1998 1999 static int intel_dp_pcon_set_frl_mask(int max_frl) 2000 { 2001 switch (max_frl) { 2002 case 48: 2003 return DP_PCON_FRL_BW_MASK_48GBPS; 2004 case 40: 2005 return DP_PCON_FRL_BW_MASK_40GBPS; 2006 case 32: 2007 return DP_PCON_FRL_BW_MASK_32GBPS; 2008 case 24: 2009 return DP_PCON_FRL_BW_MASK_24GBPS; 2010 case 18: 2011 return DP_PCON_FRL_BW_MASK_18GBPS; 2012 case 9: 2013 return DP_PCON_FRL_BW_MASK_9GBPS; 2014 } 2015 2016 return 0; 2017 } 2018 2019 static int intel_dp_hdmi_sink_max_frl(struct intel_dp *intel_dp) 2020 { 2021 struct intel_connector *intel_connector = intel_dp->attached_connector; 2022 struct drm_connector *connector = &intel_connector->base; 2023 int max_frl_rate; 2024 int max_lanes, rate_per_lane; 2025 int max_dsc_lanes, dsc_rate_per_lane; 2026 2027 max_lanes = connector->display_info.hdmi.max_lanes; 2028 rate_per_lane = connector->display_info.hdmi.max_frl_rate_per_lane; 2029 max_frl_rate = max_lanes * rate_per_lane; 2030 2031 if (connector->display_info.hdmi.dsc_cap.v_1p2) { 2032 max_dsc_lanes = connector->display_info.hdmi.dsc_cap.max_lanes; 2033 dsc_rate_per_lane = connector->display_info.hdmi.dsc_cap.max_frl_rate_per_lane; 2034 if (max_dsc_lanes && dsc_rate_per_lane) 2035 max_frl_rate = min(max_frl_rate, max_dsc_lanes * dsc_rate_per_lane); 2036 } 2037 2038 return max_frl_rate; 2039 } 2040 2041 static int intel_dp_pcon_start_frl_training(struct intel_dp *intel_dp) 2042 { 2043 #define TIMEOUT_FRL_READY_MS 500 2044 #define TIMEOUT_HDMI_LINK_ACTIVE_MS 1000 2045 2046 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2047 int max_frl_bw, max_pcon_frl_bw, max_edid_frl_bw, ret; 2048 u8 max_frl_bw_mask = 0, frl_trained_mask; 2049 bool is_active; 2050 2051 ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux); 2052 if (ret < 0) 2053 return ret; 2054 2055 max_pcon_frl_bw = intel_dp->dfp.pcon_max_frl_bw; 2056 drm_dbg(&i915->drm, "PCON max rate = %d Gbps\n", max_pcon_frl_bw); 2057 2058 max_edid_frl_bw = intel_dp_hdmi_sink_max_frl(intel_dp); 2059 drm_dbg(&i915->drm, "Sink max rate from EDID = %d Gbps\n", max_edid_frl_bw); 2060 2061 max_frl_bw = min(max_edid_frl_bw, max_pcon_frl_bw); 2062 2063 if (max_frl_bw <= 0) 2064 return -EINVAL; 2065 2066 ret = drm_dp_pcon_frl_prepare(&intel_dp->aux, false); 2067 if (ret < 0) 2068 return ret; 2069 /* Wait for PCON to be FRL Ready */ 2070 wait_for(is_active = drm_dp_pcon_is_frl_ready(&intel_dp->aux) == true, TIMEOUT_FRL_READY_MS); 2071 2072 if (!is_active) 2073 return -ETIMEDOUT; 2074 2075 max_frl_bw_mask = intel_dp_pcon_set_frl_mask(max_frl_bw); 2076 ret = drm_dp_pcon_frl_configure_1(&intel_dp->aux, max_frl_bw, 2077 DP_PCON_ENABLE_SEQUENTIAL_LINK); 2078 if (ret < 0) 2079 return ret; 2080 ret = drm_dp_pcon_frl_configure_2(&intel_dp->aux, max_frl_bw_mask, 2081 DP_PCON_FRL_LINK_TRAIN_NORMAL); 2082 if (ret < 0) 2083 return ret; 2084 ret = drm_dp_pcon_frl_enable(&intel_dp->aux); 2085 if (ret < 0) 2086 return ret; 2087 /* 2088 * Wait for FRL to be completed 2089 * Check if the HDMI Link is up and active. 2090 */ 2091 wait_for(is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux) == true, TIMEOUT_HDMI_LINK_ACTIVE_MS); 2092 2093 if (!is_active) 2094 return -ETIMEDOUT; 2095 2096 /* Verify HDMI Link configuration shows FRL Mode */ 2097 if (drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, &frl_trained_mask) != 2098 DP_PCON_HDMI_MODE_FRL) { 2099 drm_dbg(&i915->drm, "HDMI couldn't be trained in FRL Mode\n"); 2100 return -EINVAL; 2101 } 2102 drm_dbg(&i915->drm, "MAX_FRL_MASK = %u, FRL_TRAINED_MASK = %u\n", max_frl_bw_mask, frl_trained_mask); 2103 2104 intel_dp->frl.trained_rate_gbps = intel_dp_pcon_get_frl_mask(frl_trained_mask); 2105 intel_dp->frl.is_trained = true; 2106 drm_dbg(&i915->drm, "FRL trained with : %d Gbps\n", intel_dp->frl.trained_rate_gbps); 2107 2108 return 0; 2109 } 2110 2111 static bool intel_dp_is_hdmi_2_1_sink(struct intel_dp *intel_dp) 2112 { 2113 if (drm_dp_is_branch(intel_dp->dpcd) && 2114 intel_dp->has_hdmi_sink && 2115 intel_dp_hdmi_sink_max_frl(intel_dp) > 0) 2116 return true; 2117 2118 return false; 2119 } 2120 2121 void intel_dp_check_frl_training(struct intel_dp *intel_dp) 2122 { 2123 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2124 2125 /* 2126 * Always go for FRL training if: 2127 * -PCON supports SRC_CTL_MODE (VESA DP2.0-HDMI2.1 PCON Spec Draft-1 Sec-7) 2128 * -sink is HDMI2.1 2129 */ 2130 if (!(intel_dp->downstream_ports[2] & DP_PCON_SOURCE_CTL_MODE) || 2131 !intel_dp_is_hdmi_2_1_sink(intel_dp) || 2132 intel_dp->frl.is_trained) 2133 return; 2134 2135 if (intel_dp_pcon_start_frl_training(intel_dp) < 0) { 2136 int ret, mode; 2137 2138 drm_dbg(&dev_priv->drm, "Couldn't set FRL mode, continuing with TMDS mode\n"); 2139 ret = drm_dp_pcon_reset_frl_config(&intel_dp->aux); 2140 mode = drm_dp_pcon_hdmi_link_mode(&intel_dp->aux, NULL); 2141 2142 if (ret < 0 || mode != DP_PCON_HDMI_MODE_TMDS) 2143 drm_dbg(&dev_priv->drm, "Issue with PCON, cannot set TMDS mode\n"); 2144 } else { 2145 drm_dbg(&dev_priv->drm, "FRL training Completed\n"); 2146 } 2147 } 2148 2149 static int 2150 intel_dp_pcon_dsc_enc_slice_height(const struct intel_crtc_state *crtc_state) 2151 { 2152 int vactive = crtc_state->hw.adjusted_mode.vdisplay; 2153 2154 return intel_hdmi_dsc_get_slice_height(vactive); 2155 } 2156 2157 static int 2158 intel_dp_pcon_dsc_enc_slices(struct intel_dp *intel_dp, 2159 const struct intel_crtc_state *crtc_state) 2160 { 2161 struct intel_connector *intel_connector = intel_dp->attached_connector; 2162 struct drm_connector *connector = &intel_connector->base; 2163 int hdmi_throughput = connector->display_info.hdmi.dsc_cap.clk_per_slice; 2164 int hdmi_max_slices = connector->display_info.hdmi.dsc_cap.max_slices; 2165 int pcon_max_slices = drm_dp_pcon_dsc_max_slices(intel_dp->pcon_dsc_dpcd); 2166 int pcon_max_slice_width = drm_dp_pcon_dsc_max_slice_width(intel_dp->pcon_dsc_dpcd); 2167 2168 return intel_hdmi_dsc_get_num_slices(crtc_state, pcon_max_slices, 2169 pcon_max_slice_width, 2170 hdmi_max_slices, hdmi_throughput); 2171 } 2172 2173 static int 2174 intel_dp_pcon_dsc_enc_bpp(struct intel_dp *intel_dp, 2175 const struct intel_crtc_state *crtc_state, 2176 int num_slices, int slice_width) 2177 { 2178 struct intel_connector *intel_connector = intel_dp->attached_connector; 2179 struct drm_connector *connector = &intel_connector->base; 2180 int output_format = crtc_state->output_format; 2181 bool hdmi_all_bpp = connector->display_info.hdmi.dsc_cap.all_bpp; 2182 int pcon_fractional_bpp = drm_dp_pcon_dsc_bpp_incr(intel_dp->pcon_dsc_dpcd); 2183 int hdmi_max_chunk_bytes = 2184 connector->display_info.hdmi.dsc_cap.total_chunk_kbytes * 1024; 2185 2186 return intel_hdmi_dsc_get_bpp(pcon_fractional_bpp, slice_width, 2187 num_slices, output_format, hdmi_all_bpp, 2188 hdmi_max_chunk_bytes); 2189 } 2190 2191 void 2192 intel_dp_pcon_dsc_configure(struct intel_dp *intel_dp, 2193 const struct intel_crtc_state *crtc_state) 2194 { 2195 u8 pps_param[6]; 2196 int slice_height; 2197 int slice_width; 2198 int num_slices; 2199 int bits_per_pixel; 2200 int ret; 2201 struct intel_connector *intel_connector = intel_dp->attached_connector; 2202 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2203 struct drm_connector *connector; 2204 bool hdmi_is_dsc_1_2; 2205 2206 if (!intel_dp_is_hdmi_2_1_sink(intel_dp)) 2207 return; 2208 2209 if (!intel_connector) 2210 return; 2211 connector = &intel_connector->base; 2212 hdmi_is_dsc_1_2 = connector->display_info.hdmi.dsc_cap.v_1p2; 2213 2214 if (!drm_dp_pcon_enc_is_dsc_1_2(intel_dp->pcon_dsc_dpcd) || 2215 !hdmi_is_dsc_1_2) 2216 return; 2217 2218 slice_height = intel_dp_pcon_dsc_enc_slice_height(crtc_state); 2219 if (!slice_height) 2220 return; 2221 2222 num_slices = intel_dp_pcon_dsc_enc_slices(intel_dp, crtc_state); 2223 if (!num_slices) 2224 return; 2225 2226 slice_width = DIV_ROUND_UP(crtc_state->hw.adjusted_mode.hdisplay, 2227 num_slices); 2228 2229 bits_per_pixel = intel_dp_pcon_dsc_enc_bpp(intel_dp, crtc_state, 2230 num_slices, slice_width); 2231 if (!bits_per_pixel) 2232 return; 2233 2234 pps_param[0] = slice_height & 0xFF; 2235 pps_param[1] = slice_height >> 8; 2236 pps_param[2] = slice_width & 0xFF; 2237 pps_param[3] = slice_width >> 8; 2238 pps_param[4] = bits_per_pixel & 0xFF; 2239 pps_param[5] = (bits_per_pixel >> 8) & 0x3; 2240 2241 ret = drm_dp_pcon_pps_override_param(&intel_dp->aux, pps_param); 2242 if (ret < 0) 2243 drm_dbg_kms(&i915->drm, "Failed to set pcon DSC\n"); 2244 } 2245 2246 void intel_dp_configure_protocol_converter(struct intel_dp *intel_dp, 2247 const struct intel_crtc_state *crtc_state) 2248 { 2249 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2250 u8 tmp; 2251 2252 if (intel_dp->dpcd[DP_DPCD_REV] < 0x13) 2253 return; 2254 2255 if (!drm_dp_is_branch(intel_dp->dpcd)) 2256 return; 2257 2258 tmp = intel_dp->has_hdmi_sink ? 2259 DP_HDMI_DVI_OUTPUT_CONFIG : 0; 2260 2261 if (drm_dp_dpcd_writeb(&intel_dp->aux, 2262 DP_PROTOCOL_CONVERTER_CONTROL_0, tmp) != 1) 2263 drm_dbg_kms(&i915->drm, "Failed to %s protocol converter HDMI mode\n", 2264 enabledisable(intel_dp->has_hdmi_sink)); 2265 2266 tmp = crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR444 && 2267 intel_dp->dfp.ycbcr_444_to_420 ? DP_CONVERSION_TO_YCBCR420_ENABLE : 0; 2268 2269 if (drm_dp_dpcd_writeb(&intel_dp->aux, 2270 DP_PROTOCOL_CONVERTER_CONTROL_1, tmp) != 1) 2271 drm_dbg_kms(&i915->drm, 2272 "Failed to %s protocol converter YCbCr 4:2:0 conversion mode\n", 2273 enabledisable(intel_dp->dfp.ycbcr_444_to_420)); 2274 2275 tmp = 0; 2276 if (intel_dp->dfp.rgb_to_ycbcr) { 2277 bool bt2020, bt709; 2278 2279 /* 2280 * FIXME: Currently if userspace selects BT2020 or BT709, but PCON supports only 2281 * RGB->YCbCr for BT601 colorspace, we go ahead with BT601, as default. 2282 * 2283 */ 2284 tmp = DP_CONVERSION_BT601_RGB_YCBCR_ENABLE; 2285 2286 bt2020 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, 2287 intel_dp->downstream_ports, 2288 DP_DS_HDMI_BT2020_RGB_YCBCR_CONV); 2289 bt709 = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, 2290 intel_dp->downstream_ports, 2291 DP_DS_HDMI_BT709_RGB_YCBCR_CONV); 2292 switch (crtc_state->infoframes.vsc.colorimetry) { 2293 case DP_COLORIMETRY_BT2020_RGB: 2294 case DP_COLORIMETRY_BT2020_YCC: 2295 if (bt2020) 2296 tmp = DP_CONVERSION_BT2020_RGB_YCBCR_ENABLE; 2297 break; 2298 case DP_COLORIMETRY_BT709_YCC: 2299 case DP_COLORIMETRY_XVYCC_709: 2300 if (bt709) 2301 tmp = DP_CONVERSION_BT709_RGB_YCBCR_ENABLE; 2302 break; 2303 default: 2304 break; 2305 } 2306 } 2307 2308 if (drm_dp_pcon_convert_rgb_to_ycbcr(&intel_dp->aux, tmp) < 0) 2309 drm_dbg_kms(&i915->drm, 2310 "Failed to %s protocol converter RGB->YCbCr conversion mode\n", 2311 enabledisable(tmp)); 2312 } 2313 2314 2315 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) 2316 { 2317 u8 dprx = 0; 2318 2319 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 2320 &dprx) != 1) 2321 return false; 2322 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; 2323 } 2324 2325 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) 2326 { 2327 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2328 2329 /* 2330 * Clear the cached register set to avoid using stale values 2331 * for the sinks that do not support DSC. 2332 */ 2333 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); 2334 2335 /* Clear fec_capable to avoid using stale values */ 2336 intel_dp->fec_capable = 0; 2337 2338 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */ 2339 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 || 2340 intel_dp->edp_dpcd[0] >= DP_EDP_14) { 2341 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT, 2342 intel_dp->dsc_dpcd, 2343 sizeof(intel_dp->dsc_dpcd)) < 0) 2344 drm_err(&i915->drm, 2345 "Failed to read DPCD register 0x%x\n", 2346 DP_DSC_SUPPORT); 2347 2348 drm_dbg_kms(&i915->drm, "DSC DPCD: %*ph\n", 2349 (int)sizeof(intel_dp->dsc_dpcd), 2350 intel_dp->dsc_dpcd); 2351 2352 /* FEC is supported only on DP 1.4 */ 2353 if (!intel_dp_is_edp(intel_dp) && 2354 drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY, 2355 &intel_dp->fec_capable) < 0) 2356 drm_err(&i915->drm, 2357 "Failed to read FEC DPCD register\n"); 2358 2359 drm_dbg_kms(&i915->drm, "FEC CAPABILITY: %x\n", 2360 intel_dp->fec_capable); 2361 } 2362 } 2363 2364 static void intel_edp_mso_mode_fixup(struct intel_connector *connector, 2365 struct drm_display_mode *mode) 2366 { 2367 struct intel_dp *intel_dp = intel_attached_dp(connector); 2368 struct drm_i915_private *i915 = to_i915(connector->base.dev); 2369 int n = intel_dp->mso_link_count; 2370 int overlap = intel_dp->mso_pixel_overlap; 2371 2372 if (!mode || !n) 2373 return; 2374 2375 mode->hdisplay = (mode->hdisplay - overlap) * n; 2376 mode->hsync_start = (mode->hsync_start - overlap) * n; 2377 mode->hsync_end = (mode->hsync_end - overlap) * n; 2378 mode->htotal = (mode->htotal - overlap) * n; 2379 mode->clock *= n; 2380 2381 drm_mode_set_name(mode); 2382 2383 drm_dbg_kms(&i915->drm, 2384 "[CONNECTOR:%d:%s] using generated MSO mode: ", 2385 connector->base.base.id, connector->base.name); 2386 drm_mode_debug_printmodeline(mode); 2387 } 2388 2389 static void intel_edp_mso_init(struct intel_dp *intel_dp) 2390 { 2391 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2392 u8 mso; 2393 2394 if (intel_dp->edp_dpcd[0] < DP_EDP_14) 2395 return; 2396 2397 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_EDP_MSO_LINK_CAPABILITIES, &mso) != 1) { 2398 drm_err(&i915->drm, "Failed to read MSO cap\n"); 2399 return; 2400 } 2401 2402 /* Valid configurations are SST or MSO 2x1, 2x2, 4x1 */ 2403 mso &= DP_EDP_MSO_NUMBER_OF_LINKS_MASK; 2404 if (mso % 2 || mso > drm_dp_max_lane_count(intel_dp->dpcd)) { 2405 drm_err(&i915->drm, "Invalid MSO link count cap %u\n", mso); 2406 mso = 0; 2407 } 2408 2409 if (mso) { 2410 drm_dbg_kms(&i915->drm, "Sink MSO %ux%u configuration\n", 2411 mso, drm_dp_max_lane_count(intel_dp->dpcd) / mso); 2412 if (!HAS_MSO(i915)) { 2413 drm_err(&i915->drm, "No source MSO support, disabling\n"); 2414 mso = 0; 2415 } 2416 } 2417 2418 intel_dp->mso_link_count = mso; 2419 intel_dp->mso_pixel_overlap = 0; /* FIXME: read from DisplayID v2.0 */ 2420 } 2421 2422 static bool 2423 intel_edp_init_dpcd(struct intel_dp *intel_dp) 2424 { 2425 struct drm_i915_private *dev_priv = 2426 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 2427 2428 /* this function is meant to be called only once */ 2429 drm_WARN_ON(&dev_priv->drm, intel_dp->dpcd[DP_DPCD_REV] != 0); 2430 2431 if (drm_dp_read_dpcd_caps(&intel_dp->aux, intel_dp->dpcd) != 0) 2432 return false; 2433 2434 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 2435 drm_dp_is_branch(intel_dp->dpcd)); 2436 2437 /* 2438 * Read the eDP display control registers. 2439 * 2440 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in 2441 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it 2442 * set, but require eDP 1.4+ detection (e.g. for supported link rates 2443 * method). The display control registers should read zero if they're 2444 * not supported anyway. 2445 */ 2446 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, 2447 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == 2448 sizeof(intel_dp->edp_dpcd)) { 2449 drm_dbg_kms(&dev_priv->drm, "eDP DPCD: %*ph\n", 2450 (int)sizeof(intel_dp->edp_dpcd), 2451 intel_dp->edp_dpcd); 2452 2453 intel_dp->use_max_params = intel_dp->edp_dpcd[0] < DP_EDP_14; 2454 } 2455 2456 /* 2457 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks 2458 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] 2459 */ 2460 intel_psr_init_dpcd(intel_dp); 2461 2462 /* Read the eDP 1.4+ supported link rates. */ 2463 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { 2464 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 2465 int i; 2466 2467 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 2468 sink_rates, sizeof(sink_rates)); 2469 2470 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 2471 int val = le16_to_cpu(sink_rates[i]); 2472 2473 if (val == 0) 2474 break; 2475 2476 /* Value read multiplied by 200kHz gives the per-lane 2477 * link rate in kHz. The source rates are, however, 2478 * stored in terms of LS_Clk kHz. The full conversion 2479 * back to symbols is 2480 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) 2481 */ 2482 intel_dp->sink_rates[i] = (val * 200) / 10; 2483 } 2484 intel_dp->num_sink_rates = i; 2485 } 2486 2487 /* 2488 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available, 2489 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise. 2490 */ 2491 if (intel_dp->num_sink_rates) 2492 intel_dp->use_rate_select = true; 2493 else 2494 intel_dp_set_sink_rates(intel_dp); 2495 2496 intel_dp_set_common_rates(intel_dp); 2497 2498 /* Read the eDP DSC DPCD registers */ 2499 if (DISPLAY_VER(dev_priv) >= 10) 2500 intel_dp_get_dsc_sink_cap(intel_dp); 2501 2502 /* 2503 * If needed, program our source OUI so we can make various Intel-specific AUX services 2504 * available (such as HDR backlight controls) 2505 */ 2506 intel_edp_init_source_oui(intel_dp, true); 2507 2508 intel_edp_mso_init(intel_dp); 2509 2510 return true; 2511 } 2512 2513 static bool 2514 intel_dp_has_sink_count(struct intel_dp *intel_dp) 2515 { 2516 if (!intel_dp->attached_connector) 2517 return false; 2518 2519 return drm_dp_read_sink_count_cap(&intel_dp->attached_connector->base, 2520 intel_dp->dpcd, 2521 &intel_dp->desc); 2522 } 2523 2524 static bool 2525 intel_dp_get_dpcd(struct intel_dp *intel_dp) 2526 { 2527 int ret; 2528 2529 if (intel_dp_init_lttpr_and_dprx_caps(intel_dp) < 0) 2530 return false; 2531 2532 /* 2533 * Don't clobber cached eDP rates. Also skip re-reading 2534 * the OUI/ID since we know it won't change. 2535 */ 2536 if (!intel_dp_is_edp(intel_dp)) { 2537 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 2538 drm_dp_is_branch(intel_dp->dpcd)); 2539 2540 intel_dp_set_sink_rates(intel_dp); 2541 intel_dp_set_common_rates(intel_dp); 2542 } 2543 2544 if (intel_dp_has_sink_count(intel_dp)) { 2545 ret = drm_dp_read_sink_count(&intel_dp->aux); 2546 if (ret < 0) 2547 return false; 2548 2549 /* 2550 * Sink count can change between short pulse hpd hence 2551 * a member variable in intel_dp will track any changes 2552 * between short pulse interrupts. 2553 */ 2554 intel_dp->sink_count = ret; 2555 2556 /* 2557 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that 2558 * a dongle is present but no display. Unless we require to know 2559 * if a dongle is present or not, we don't need to update 2560 * downstream port information. So, an early return here saves 2561 * time from performing other operations which are not required. 2562 */ 2563 if (!intel_dp->sink_count) 2564 return false; 2565 } 2566 2567 return drm_dp_read_downstream_info(&intel_dp->aux, intel_dp->dpcd, 2568 intel_dp->downstream_ports) == 0; 2569 } 2570 2571 static bool 2572 intel_dp_can_mst(struct intel_dp *intel_dp) 2573 { 2574 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2575 2576 return i915->params.enable_dp_mst && 2577 intel_dp->can_mst && 2578 drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); 2579 } 2580 2581 static void 2582 intel_dp_configure_mst(struct intel_dp *intel_dp) 2583 { 2584 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 2585 struct intel_encoder *encoder = 2586 &dp_to_dig_port(intel_dp)->base; 2587 bool sink_can_mst = drm_dp_read_mst_cap(&intel_dp->aux, intel_dp->dpcd); 2588 2589 drm_dbg_kms(&i915->drm, 2590 "[ENCODER:%d:%s] MST support: port: %s, sink: %s, modparam: %s\n", 2591 encoder->base.base.id, encoder->base.name, 2592 yesno(intel_dp->can_mst), yesno(sink_can_mst), 2593 yesno(i915->params.enable_dp_mst)); 2594 2595 if (!intel_dp->can_mst) 2596 return; 2597 2598 intel_dp->is_mst = sink_can_mst && 2599 i915->params.enable_dp_mst; 2600 2601 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 2602 intel_dp->is_mst); 2603 } 2604 2605 static bool 2606 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) 2607 { 2608 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, 2609 sink_irq_vector, DP_DPRX_ESI_LEN) == 2610 DP_DPRX_ESI_LEN; 2611 } 2612 2613 bool 2614 intel_dp_needs_vsc_sdp(const struct intel_crtc_state *crtc_state, 2615 const struct drm_connector_state *conn_state) 2616 { 2617 /* 2618 * As per DP 1.4a spec section 2.2.4.3 [MSA Field for Indication 2619 * of Color Encoding Format and Content Color Gamut], in order to 2620 * sending YCBCR 420 or HDR BT.2020 signals we should use DP VSC SDP. 2621 */ 2622 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 2623 return true; 2624 2625 switch (conn_state->colorspace) { 2626 case DRM_MODE_COLORIMETRY_SYCC_601: 2627 case DRM_MODE_COLORIMETRY_OPYCC_601: 2628 case DRM_MODE_COLORIMETRY_BT2020_YCC: 2629 case DRM_MODE_COLORIMETRY_BT2020_RGB: 2630 case DRM_MODE_COLORIMETRY_BT2020_CYCC: 2631 return true; 2632 default: 2633 break; 2634 } 2635 2636 return false; 2637 } 2638 2639 static ssize_t intel_dp_vsc_sdp_pack(const struct drm_dp_vsc_sdp *vsc, 2640 struct dp_sdp *sdp, size_t size) 2641 { 2642 size_t length = sizeof(struct dp_sdp); 2643 2644 if (size < length) 2645 return -ENOSPC; 2646 2647 memset(sdp, 0, size); 2648 2649 /* 2650 * Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 2651 * VSC SDP Header Bytes 2652 */ 2653 sdp->sdp_header.HB0 = 0; /* Secondary-Data Packet ID = 0 */ 2654 sdp->sdp_header.HB1 = vsc->sdp_type; /* Secondary-data Packet Type */ 2655 sdp->sdp_header.HB2 = vsc->revision; /* Revision Number */ 2656 sdp->sdp_header.HB3 = vsc->length; /* Number of Valid Data Bytes */ 2657 2658 /* 2659 * Only revision 0x5 supports Pixel Encoding/Colorimetry Format as 2660 * per DP 1.4a spec. 2661 */ 2662 if (vsc->revision != 0x5) 2663 goto out; 2664 2665 /* VSC SDP Payload for DB16 through DB18 */ 2666 /* Pixel Encoding and Colorimetry Formats */ 2667 sdp->db[16] = (vsc->pixelformat & 0xf) << 4; /* DB16[7:4] */ 2668 sdp->db[16] |= vsc->colorimetry & 0xf; /* DB16[3:0] */ 2669 2670 switch (vsc->bpc) { 2671 case 6: 2672 /* 6bpc: 0x0 */ 2673 break; 2674 case 8: 2675 sdp->db[17] = 0x1; /* DB17[3:0] */ 2676 break; 2677 case 10: 2678 sdp->db[17] = 0x2; 2679 break; 2680 case 12: 2681 sdp->db[17] = 0x3; 2682 break; 2683 case 16: 2684 sdp->db[17] = 0x4; 2685 break; 2686 default: 2687 MISSING_CASE(vsc->bpc); 2688 break; 2689 } 2690 /* Dynamic Range and Component Bit Depth */ 2691 if (vsc->dynamic_range == DP_DYNAMIC_RANGE_CTA) 2692 sdp->db[17] |= 0x80; /* DB17[7] */ 2693 2694 /* Content Type */ 2695 sdp->db[18] = vsc->content_type & 0x7; 2696 2697 out: 2698 return length; 2699 } 2700 2701 static ssize_t 2702 intel_dp_hdr_metadata_infoframe_sdp_pack(const struct hdmi_drm_infoframe *drm_infoframe, 2703 struct dp_sdp *sdp, 2704 size_t size) 2705 { 2706 size_t length = sizeof(struct dp_sdp); 2707 const int infoframe_size = HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE; 2708 unsigned char buf[HDMI_INFOFRAME_HEADER_SIZE + HDMI_DRM_INFOFRAME_SIZE]; 2709 ssize_t len; 2710 2711 if (size < length) 2712 return -ENOSPC; 2713 2714 memset(sdp, 0, size); 2715 2716 len = hdmi_drm_infoframe_pack_only(drm_infoframe, buf, sizeof(buf)); 2717 if (len < 0) { 2718 DRM_DEBUG_KMS("buffer size is smaller than hdr metadata infoframe\n"); 2719 return -ENOSPC; 2720 } 2721 2722 if (len != infoframe_size) { 2723 DRM_DEBUG_KMS("wrong static hdr metadata size\n"); 2724 return -ENOSPC; 2725 } 2726 2727 /* 2728 * Set up the infoframe sdp packet for HDR static metadata. 2729 * Prepare VSC Header for SU as per DP 1.4a spec, 2730 * Table 2-100 and Table 2-101 2731 */ 2732 2733 /* Secondary-Data Packet ID, 00h for non-Audio INFOFRAME */ 2734 sdp->sdp_header.HB0 = 0; 2735 /* 2736 * Packet Type 80h + Non-audio INFOFRAME Type value 2737 * HDMI_INFOFRAME_TYPE_DRM: 0x87 2738 * - 80h + Non-audio INFOFRAME Type value 2739 * - InfoFrame Type: 0x07 2740 * [CTA-861-G Table-42 Dynamic Range and Mastering InfoFrame] 2741 */ 2742 sdp->sdp_header.HB1 = drm_infoframe->type; 2743 /* 2744 * Least Significant Eight Bits of (Data Byte Count – 1) 2745 * infoframe_size - 1 2746 */ 2747 sdp->sdp_header.HB2 = 0x1D; 2748 /* INFOFRAME SDP Version Number */ 2749 sdp->sdp_header.HB3 = (0x13 << 2); 2750 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 2751 sdp->db[0] = drm_infoframe->version; 2752 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 2753 sdp->db[1] = drm_infoframe->length; 2754 /* 2755 * Copy HDMI_DRM_INFOFRAME_SIZE size from a buffer after 2756 * HDMI_INFOFRAME_HEADER_SIZE 2757 */ 2758 BUILD_BUG_ON(sizeof(sdp->db) < HDMI_DRM_INFOFRAME_SIZE + 2); 2759 memcpy(&sdp->db[2], &buf[HDMI_INFOFRAME_HEADER_SIZE], 2760 HDMI_DRM_INFOFRAME_SIZE); 2761 2762 /* 2763 * Size of DP infoframe sdp packet for HDR static metadata consists of 2764 * - DP SDP Header(struct dp_sdp_header): 4 bytes 2765 * - Two Data Blocks: 2 bytes 2766 * CTA Header Byte2 (INFOFRAME Version Number) 2767 * CTA Header Byte3 (Length of INFOFRAME) 2768 * - HDMI_DRM_INFOFRAME_SIZE: 26 bytes 2769 * 2770 * Prior to GEN11's GMP register size is identical to DP HDR static metadata 2771 * infoframe size. But GEN11+ has larger than that size, write_infoframe 2772 * will pad rest of the size. 2773 */ 2774 return sizeof(struct dp_sdp_header) + 2 + HDMI_DRM_INFOFRAME_SIZE; 2775 } 2776 2777 static void intel_write_dp_sdp(struct intel_encoder *encoder, 2778 const struct intel_crtc_state *crtc_state, 2779 unsigned int type) 2780 { 2781 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2782 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2783 struct dp_sdp sdp = {}; 2784 ssize_t len; 2785 2786 if ((crtc_state->infoframes.enable & 2787 intel_hdmi_infoframe_enable(type)) == 0) 2788 return; 2789 2790 switch (type) { 2791 case DP_SDP_VSC: 2792 len = intel_dp_vsc_sdp_pack(&crtc_state->infoframes.vsc, &sdp, 2793 sizeof(sdp)); 2794 break; 2795 case HDMI_PACKET_TYPE_GAMUT_METADATA: 2796 len = intel_dp_hdr_metadata_infoframe_sdp_pack(&crtc_state->infoframes.drm.drm, 2797 &sdp, sizeof(sdp)); 2798 break; 2799 default: 2800 MISSING_CASE(type); 2801 return; 2802 } 2803 2804 if (drm_WARN_ON(&dev_priv->drm, len < 0)) 2805 return; 2806 2807 dig_port->write_infoframe(encoder, crtc_state, type, &sdp, len); 2808 } 2809 2810 void intel_write_dp_vsc_sdp(struct intel_encoder *encoder, 2811 const struct intel_crtc_state *crtc_state, 2812 struct drm_dp_vsc_sdp *vsc) 2813 { 2814 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2815 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2816 struct dp_sdp sdp = {}; 2817 ssize_t len; 2818 2819 len = intel_dp_vsc_sdp_pack(vsc, &sdp, sizeof(sdp)); 2820 2821 if (drm_WARN_ON(&dev_priv->drm, len < 0)) 2822 return; 2823 2824 dig_port->write_infoframe(encoder, crtc_state, DP_SDP_VSC, 2825 &sdp, len); 2826 } 2827 2828 void intel_dp_set_infoframes(struct intel_encoder *encoder, 2829 bool enable, 2830 const struct intel_crtc_state *crtc_state, 2831 const struct drm_connector_state *conn_state) 2832 { 2833 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2834 i915_reg_t reg = HSW_TVIDEO_DIP_CTL(crtc_state->cpu_transcoder); 2835 u32 dip_enable = VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_GCP_HSW | 2836 VIDEO_DIP_ENABLE_VS_HSW | VIDEO_DIP_ENABLE_GMP_HSW | 2837 VIDEO_DIP_ENABLE_SPD_HSW | VIDEO_DIP_ENABLE_DRM_GLK; 2838 u32 val = intel_de_read(dev_priv, reg) & ~dip_enable; 2839 2840 /* TODO: Add DSC case (DIP_ENABLE_PPS) */ 2841 /* When PSR is enabled, this routine doesn't disable VSC DIP */ 2842 if (!crtc_state->has_psr) 2843 val &= ~VIDEO_DIP_ENABLE_VSC_HSW; 2844 2845 intel_de_write(dev_priv, reg, val); 2846 intel_de_posting_read(dev_priv, reg); 2847 2848 if (!enable) 2849 return; 2850 2851 /* When PSR is enabled, VSC SDP is handled by PSR routine */ 2852 if (!crtc_state->has_psr) 2853 intel_write_dp_sdp(encoder, crtc_state, DP_SDP_VSC); 2854 2855 intel_write_dp_sdp(encoder, crtc_state, HDMI_PACKET_TYPE_GAMUT_METADATA); 2856 } 2857 2858 static int intel_dp_vsc_sdp_unpack(struct drm_dp_vsc_sdp *vsc, 2859 const void *buffer, size_t size) 2860 { 2861 const struct dp_sdp *sdp = buffer; 2862 2863 if (size < sizeof(struct dp_sdp)) 2864 return -EINVAL; 2865 2866 memset(vsc, 0, sizeof(*vsc)); 2867 2868 if (sdp->sdp_header.HB0 != 0) 2869 return -EINVAL; 2870 2871 if (sdp->sdp_header.HB1 != DP_SDP_VSC) 2872 return -EINVAL; 2873 2874 vsc->sdp_type = sdp->sdp_header.HB1; 2875 vsc->revision = sdp->sdp_header.HB2; 2876 vsc->length = sdp->sdp_header.HB3; 2877 2878 if ((sdp->sdp_header.HB2 == 0x2 && sdp->sdp_header.HB3 == 0x8) || 2879 (sdp->sdp_header.HB2 == 0x4 && sdp->sdp_header.HB3 == 0xe)) { 2880 /* 2881 * - HB2 = 0x2, HB3 = 0x8 2882 * VSC SDP supporting 3D stereo + PSR 2883 * - HB2 = 0x4, HB3 = 0xe 2884 * VSC SDP supporting 3D stereo + PSR2 with Y-coordinate of 2885 * first scan line of the SU region (applies to eDP v1.4b 2886 * and higher). 2887 */ 2888 return 0; 2889 } else if (sdp->sdp_header.HB2 == 0x5 && sdp->sdp_header.HB3 == 0x13) { 2890 /* 2891 * - HB2 = 0x5, HB3 = 0x13 2892 * VSC SDP supporting 3D stereo + PSR2 + Pixel Encoding/Colorimetry 2893 * Format. 2894 */ 2895 vsc->pixelformat = (sdp->db[16] >> 4) & 0xf; 2896 vsc->colorimetry = sdp->db[16] & 0xf; 2897 vsc->dynamic_range = (sdp->db[17] >> 7) & 0x1; 2898 2899 switch (sdp->db[17] & 0x7) { 2900 case 0x0: 2901 vsc->bpc = 6; 2902 break; 2903 case 0x1: 2904 vsc->bpc = 8; 2905 break; 2906 case 0x2: 2907 vsc->bpc = 10; 2908 break; 2909 case 0x3: 2910 vsc->bpc = 12; 2911 break; 2912 case 0x4: 2913 vsc->bpc = 16; 2914 break; 2915 default: 2916 MISSING_CASE(sdp->db[17] & 0x7); 2917 return -EINVAL; 2918 } 2919 2920 vsc->content_type = sdp->db[18] & 0x7; 2921 } else { 2922 return -EINVAL; 2923 } 2924 2925 return 0; 2926 } 2927 2928 static int 2929 intel_dp_hdr_metadata_infoframe_sdp_unpack(struct hdmi_drm_infoframe *drm_infoframe, 2930 const void *buffer, size_t size) 2931 { 2932 int ret; 2933 2934 const struct dp_sdp *sdp = buffer; 2935 2936 if (size < sizeof(struct dp_sdp)) 2937 return -EINVAL; 2938 2939 if (sdp->sdp_header.HB0 != 0) 2940 return -EINVAL; 2941 2942 if (sdp->sdp_header.HB1 != HDMI_INFOFRAME_TYPE_DRM) 2943 return -EINVAL; 2944 2945 /* 2946 * Least Significant Eight Bits of (Data Byte Count – 1) 2947 * 1Dh (i.e., Data Byte Count = 30 bytes). 2948 */ 2949 if (sdp->sdp_header.HB2 != 0x1D) 2950 return -EINVAL; 2951 2952 /* Most Significant Two Bits of (Data Byte Count – 1), Clear to 00b. */ 2953 if ((sdp->sdp_header.HB3 & 0x3) != 0) 2954 return -EINVAL; 2955 2956 /* INFOFRAME SDP Version Number */ 2957 if (((sdp->sdp_header.HB3 >> 2) & 0x3f) != 0x13) 2958 return -EINVAL; 2959 2960 /* CTA Header Byte 2 (INFOFRAME Version Number) */ 2961 if (sdp->db[0] != 1) 2962 return -EINVAL; 2963 2964 /* CTA Header Byte 3 (Length of INFOFRAME): HDMI_DRM_INFOFRAME_SIZE */ 2965 if (sdp->db[1] != HDMI_DRM_INFOFRAME_SIZE) 2966 return -EINVAL; 2967 2968 ret = hdmi_drm_infoframe_unpack_only(drm_infoframe, &sdp->db[2], 2969 HDMI_DRM_INFOFRAME_SIZE); 2970 2971 return ret; 2972 } 2973 2974 static void intel_read_dp_vsc_sdp(struct intel_encoder *encoder, 2975 struct intel_crtc_state *crtc_state, 2976 struct drm_dp_vsc_sdp *vsc) 2977 { 2978 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 2979 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2980 unsigned int type = DP_SDP_VSC; 2981 struct dp_sdp sdp = {}; 2982 int ret; 2983 2984 /* When PSR is enabled, VSC SDP is handled by PSR routine */ 2985 if (crtc_state->has_psr) 2986 return; 2987 2988 if ((crtc_state->infoframes.enable & 2989 intel_hdmi_infoframe_enable(type)) == 0) 2990 return; 2991 2992 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, sizeof(sdp)); 2993 2994 ret = intel_dp_vsc_sdp_unpack(vsc, &sdp, sizeof(sdp)); 2995 2996 if (ret) 2997 drm_dbg_kms(&dev_priv->drm, "Failed to unpack DP VSC SDP\n"); 2998 } 2999 3000 static void intel_read_dp_hdr_metadata_infoframe_sdp(struct intel_encoder *encoder, 3001 struct intel_crtc_state *crtc_state, 3002 struct hdmi_drm_infoframe *drm_infoframe) 3003 { 3004 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 3005 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3006 unsigned int type = HDMI_PACKET_TYPE_GAMUT_METADATA; 3007 struct dp_sdp sdp = {}; 3008 int ret; 3009 3010 if ((crtc_state->infoframes.enable & 3011 intel_hdmi_infoframe_enable(type)) == 0) 3012 return; 3013 3014 dig_port->read_infoframe(encoder, crtc_state, type, &sdp, 3015 sizeof(sdp)); 3016 3017 ret = intel_dp_hdr_metadata_infoframe_sdp_unpack(drm_infoframe, &sdp, 3018 sizeof(sdp)); 3019 3020 if (ret) 3021 drm_dbg_kms(&dev_priv->drm, 3022 "Failed to unpack DP HDR Metadata Infoframe SDP\n"); 3023 } 3024 3025 void intel_read_dp_sdp(struct intel_encoder *encoder, 3026 struct intel_crtc_state *crtc_state, 3027 unsigned int type) 3028 { 3029 switch (type) { 3030 case DP_SDP_VSC: 3031 intel_read_dp_vsc_sdp(encoder, crtc_state, 3032 &crtc_state->infoframes.vsc); 3033 break; 3034 case HDMI_PACKET_TYPE_GAMUT_METADATA: 3035 intel_read_dp_hdr_metadata_infoframe_sdp(encoder, crtc_state, 3036 &crtc_state->infoframes.drm.drm); 3037 break; 3038 default: 3039 MISSING_CASE(type); 3040 break; 3041 } 3042 } 3043 3044 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp) 3045 { 3046 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3047 int status = 0; 3048 int test_link_rate; 3049 u8 test_lane_count, test_link_bw; 3050 /* (DP CTS 1.2) 3051 * 4.3.1.11 3052 */ 3053 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */ 3054 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT, 3055 &test_lane_count); 3056 3057 if (status <= 0) { 3058 drm_dbg_kms(&i915->drm, "Lane count read failed\n"); 3059 return DP_TEST_NAK; 3060 } 3061 test_lane_count &= DP_MAX_LANE_COUNT_MASK; 3062 3063 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, 3064 &test_link_bw); 3065 if (status <= 0) { 3066 drm_dbg_kms(&i915->drm, "Link Rate read failed\n"); 3067 return DP_TEST_NAK; 3068 } 3069 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); 3070 3071 /* Validate the requested link rate and lane count */ 3072 if (!intel_dp_link_params_valid(intel_dp, test_link_rate, 3073 test_lane_count)) 3074 return DP_TEST_NAK; 3075 3076 intel_dp->compliance.test_lane_count = test_lane_count; 3077 intel_dp->compliance.test_link_rate = test_link_rate; 3078 3079 return DP_TEST_ACK; 3080 } 3081 3082 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) 3083 { 3084 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3085 u8 test_pattern; 3086 u8 test_misc; 3087 __be16 h_width, v_height; 3088 int status = 0; 3089 3090 /* Read the TEST_PATTERN (DP CTS 3.1.5) */ 3091 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN, 3092 &test_pattern); 3093 if (status <= 0) { 3094 drm_dbg_kms(&i915->drm, "Test pattern read failed\n"); 3095 return DP_TEST_NAK; 3096 } 3097 if (test_pattern != DP_COLOR_RAMP) 3098 return DP_TEST_NAK; 3099 3100 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, 3101 &h_width, 2); 3102 if (status <= 0) { 3103 drm_dbg_kms(&i915->drm, "H Width read failed\n"); 3104 return DP_TEST_NAK; 3105 } 3106 3107 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, 3108 &v_height, 2); 3109 if (status <= 0) { 3110 drm_dbg_kms(&i915->drm, "V Height read failed\n"); 3111 return DP_TEST_NAK; 3112 } 3113 3114 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0, 3115 &test_misc); 3116 if (status <= 0) { 3117 drm_dbg_kms(&i915->drm, "TEST MISC read failed\n"); 3118 return DP_TEST_NAK; 3119 } 3120 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB) 3121 return DP_TEST_NAK; 3122 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA) 3123 return DP_TEST_NAK; 3124 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) { 3125 case DP_TEST_BIT_DEPTH_6: 3126 intel_dp->compliance.test_data.bpc = 6; 3127 break; 3128 case DP_TEST_BIT_DEPTH_8: 3129 intel_dp->compliance.test_data.bpc = 8; 3130 break; 3131 default: 3132 return DP_TEST_NAK; 3133 } 3134 3135 intel_dp->compliance.test_data.video_pattern = test_pattern; 3136 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width); 3137 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height); 3138 /* Set test active flag here so userspace doesn't interrupt things */ 3139 intel_dp->compliance.test_active = true; 3140 3141 return DP_TEST_ACK; 3142 } 3143 3144 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp) 3145 { 3146 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3147 u8 test_result = DP_TEST_ACK; 3148 struct intel_connector *intel_connector = intel_dp->attached_connector; 3149 struct drm_connector *connector = &intel_connector->base; 3150 3151 if (intel_connector->detect_edid == NULL || 3152 connector->edid_corrupt || 3153 intel_dp->aux.i2c_defer_count > 6) { 3154 /* Check EDID read for NACKs, DEFERs and corruption 3155 * (DP CTS 1.2 Core r1.1) 3156 * 4.2.2.4 : Failed EDID read, I2C_NAK 3157 * 4.2.2.5 : Failed EDID read, I2C_DEFER 3158 * 4.2.2.6 : EDID corruption detected 3159 * Use failsafe mode for all cases 3160 */ 3161 if (intel_dp->aux.i2c_nack_count > 0 || 3162 intel_dp->aux.i2c_defer_count > 0) 3163 drm_dbg_kms(&i915->drm, 3164 "EDID read had %d NACKs, %d DEFERs\n", 3165 intel_dp->aux.i2c_nack_count, 3166 intel_dp->aux.i2c_defer_count); 3167 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; 3168 } else { 3169 struct edid *block = intel_connector->detect_edid; 3170 3171 /* We have to write the checksum 3172 * of the last block read 3173 */ 3174 block += intel_connector->detect_edid->extensions; 3175 3176 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM, 3177 block->checksum) <= 0) 3178 drm_dbg_kms(&i915->drm, 3179 "Failed to write EDID checksum\n"); 3180 3181 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; 3182 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; 3183 } 3184 3185 /* Set test active flag here so userspace doesn't interrupt things */ 3186 intel_dp->compliance.test_active = true; 3187 3188 return test_result; 3189 } 3190 3191 static void intel_dp_phy_pattern_update(struct intel_dp *intel_dp, 3192 const struct intel_crtc_state *crtc_state) 3193 { 3194 struct drm_i915_private *dev_priv = 3195 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 3196 struct drm_dp_phy_test_params *data = 3197 &intel_dp->compliance.test_data.phytest; 3198 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 3199 enum pipe pipe = crtc->pipe; 3200 u32 pattern_val; 3201 3202 switch (data->phy_pattern) { 3203 case DP_PHY_TEST_PATTERN_NONE: 3204 DRM_DEBUG_KMS("Disable Phy Test Pattern\n"); 3205 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 0x0); 3206 break; 3207 case DP_PHY_TEST_PATTERN_D10_2: 3208 DRM_DEBUG_KMS("Set D10.2 Phy Test Pattern\n"); 3209 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 3210 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_D10_2); 3211 break; 3212 case DP_PHY_TEST_PATTERN_ERROR_COUNT: 3213 DRM_DEBUG_KMS("Set Error Count Phy Test Pattern\n"); 3214 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 3215 DDI_DP_COMP_CTL_ENABLE | 3216 DDI_DP_COMP_CTL_SCRAMBLED_0); 3217 break; 3218 case DP_PHY_TEST_PATTERN_PRBS7: 3219 DRM_DEBUG_KMS("Set PRBS7 Phy Test Pattern\n"); 3220 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 3221 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_PRBS7); 3222 break; 3223 case DP_PHY_TEST_PATTERN_80BIT_CUSTOM: 3224 /* 3225 * FIXME: Ideally pattern should come from DPCD 0x250. As 3226 * current firmware of DPR-100 could not set it, so hardcoding 3227 * now for complaince test. 3228 */ 3229 DRM_DEBUG_KMS("Set 80Bit Custom Phy Test Pattern 0x3e0f83e0 0x0f83e0f8 0x0000f83e\n"); 3230 pattern_val = 0x3e0f83e0; 3231 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 0), pattern_val); 3232 pattern_val = 0x0f83e0f8; 3233 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 1), pattern_val); 3234 pattern_val = 0x0000f83e; 3235 intel_de_write(dev_priv, DDI_DP_COMP_PAT(pipe, 2), pattern_val); 3236 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 3237 DDI_DP_COMP_CTL_ENABLE | 3238 DDI_DP_COMP_CTL_CUSTOM80); 3239 break; 3240 case DP_PHY_TEST_PATTERN_CP2520: 3241 /* 3242 * FIXME: Ideally pattern should come from DPCD 0x24A. As 3243 * current firmware of DPR-100 could not set it, so hardcoding 3244 * now for complaince test. 3245 */ 3246 DRM_DEBUG_KMS("Set HBR2 compliance Phy Test Pattern\n"); 3247 pattern_val = 0xFB; 3248 intel_de_write(dev_priv, DDI_DP_COMP_CTL(pipe), 3249 DDI_DP_COMP_CTL_ENABLE | DDI_DP_COMP_CTL_HBR2 | 3250 pattern_val); 3251 break; 3252 default: 3253 WARN(1, "Invalid Phy Test Pattern\n"); 3254 } 3255 } 3256 3257 static void 3258 intel_dp_autotest_phy_ddi_disable(struct intel_dp *intel_dp, 3259 const struct intel_crtc_state *crtc_state) 3260 { 3261 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3262 struct drm_device *dev = dig_port->base.base.dev; 3263 struct drm_i915_private *dev_priv = to_i915(dev); 3264 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 3265 enum pipe pipe = crtc->pipe; 3266 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; 3267 3268 trans_ddi_func_ctl_value = intel_de_read(dev_priv, 3269 TRANS_DDI_FUNC_CTL(pipe)); 3270 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); 3271 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); 3272 3273 trans_ddi_func_ctl_value &= ~(TRANS_DDI_FUNC_ENABLE | 3274 TGL_TRANS_DDI_PORT_MASK); 3275 trans_conf_value &= ~PIPECONF_ENABLE; 3276 dp_tp_ctl_value &= ~DP_TP_CTL_ENABLE; 3277 3278 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); 3279 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), 3280 trans_ddi_func_ctl_value); 3281 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); 3282 } 3283 3284 static void 3285 intel_dp_autotest_phy_ddi_enable(struct intel_dp *intel_dp, 3286 const struct intel_crtc_state *crtc_state) 3287 { 3288 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3289 struct drm_device *dev = dig_port->base.base.dev; 3290 struct drm_i915_private *dev_priv = to_i915(dev); 3291 enum port port = dig_port->base.port; 3292 struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc); 3293 enum pipe pipe = crtc->pipe; 3294 u32 trans_ddi_func_ctl_value, trans_conf_value, dp_tp_ctl_value; 3295 3296 trans_ddi_func_ctl_value = intel_de_read(dev_priv, 3297 TRANS_DDI_FUNC_CTL(pipe)); 3298 trans_conf_value = intel_de_read(dev_priv, PIPECONF(pipe)); 3299 dp_tp_ctl_value = intel_de_read(dev_priv, TGL_DP_TP_CTL(pipe)); 3300 3301 trans_ddi_func_ctl_value |= TRANS_DDI_FUNC_ENABLE | 3302 TGL_TRANS_DDI_SELECT_PORT(port); 3303 trans_conf_value |= PIPECONF_ENABLE; 3304 dp_tp_ctl_value |= DP_TP_CTL_ENABLE; 3305 3306 intel_de_write(dev_priv, PIPECONF(pipe), trans_conf_value); 3307 intel_de_write(dev_priv, TGL_DP_TP_CTL(pipe), dp_tp_ctl_value); 3308 intel_de_write(dev_priv, TRANS_DDI_FUNC_CTL(pipe), 3309 trans_ddi_func_ctl_value); 3310 } 3311 3312 static void intel_dp_process_phy_request(struct intel_dp *intel_dp, 3313 const struct intel_crtc_state *crtc_state) 3314 { 3315 struct drm_dp_phy_test_params *data = 3316 &intel_dp->compliance.test_data.phytest; 3317 u8 link_status[DP_LINK_STATUS_SIZE]; 3318 3319 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, 3320 link_status) < 0) { 3321 DRM_DEBUG_KMS("failed to get link status\n"); 3322 return; 3323 } 3324 3325 /* retrieve vswing & pre-emphasis setting */ 3326 intel_dp_get_adjust_train(intel_dp, crtc_state, DP_PHY_DPRX, 3327 link_status); 3328 3329 intel_dp_autotest_phy_ddi_disable(intel_dp, crtc_state); 3330 3331 intel_dp_set_signal_levels(intel_dp, crtc_state, DP_PHY_DPRX); 3332 3333 intel_dp_phy_pattern_update(intel_dp, crtc_state); 3334 3335 intel_dp_autotest_phy_ddi_enable(intel_dp, crtc_state); 3336 3337 drm_dp_dpcd_write(&intel_dp->aux, DP_TRAINING_LANE0_SET, 3338 intel_dp->train_set, crtc_state->lane_count); 3339 3340 drm_dp_set_phy_test_pattern(&intel_dp->aux, data, 3341 link_status[DP_DPCD_REV]); 3342 } 3343 3344 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) 3345 { 3346 struct drm_dp_phy_test_params *data = 3347 &intel_dp->compliance.test_data.phytest; 3348 3349 if (drm_dp_get_phy_test_pattern(&intel_dp->aux, data)) { 3350 DRM_DEBUG_KMS("DP Phy Test pattern AUX read failure\n"); 3351 return DP_TEST_NAK; 3352 } 3353 3354 /* Set test active flag here so userspace doesn't interrupt things */ 3355 intel_dp->compliance.test_active = true; 3356 3357 return DP_TEST_ACK; 3358 } 3359 3360 static void intel_dp_handle_test_request(struct intel_dp *intel_dp) 3361 { 3362 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3363 u8 response = DP_TEST_NAK; 3364 u8 request = 0; 3365 int status; 3366 3367 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request); 3368 if (status <= 0) { 3369 drm_dbg_kms(&i915->drm, 3370 "Could not read test request from sink\n"); 3371 goto update_status; 3372 } 3373 3374 switch (request) { 3375 case DP_TEST_LINK_TRAINING: 3376 drm_dbg_kms(&i915->drm, "LINK_TRAINING test requested\n"); 3377 response = intel_dp_autotest_link_training(intel_dp); 3378 break; 3379 case DP_TEST_LINK_VIDEO_PATTERN: 3380 drm_dbg_kms(&i915->drm, "TEST_PATTERN test requested\n"); 3381 response = intel_dp_autotest_video_pattern(intel_dp); 3382 break; 3383 case DP_TEST_LINK_EDID_READ: 3384 drm_dbg_kms(&i915->drm, "EDID test requested\n"); 3385 response = intel_dp_autotest_edid(intel_dp); 3386 break; 3387 case DP_TEST_LINK_PHY_TEST_PATTERN: 3388 drm_dbg_kms(&i915->drm, "PHY_PATTERN test requested\n"); 3389 response = intel_dp_autotest_phy_pattern(intel_dp); 3390 break; 3391 default: 3392 drm_dbg_kms(&i915->drm, "Invalid test request '%02x'\n", 3393 request); 3394 break; 3395 } 3396 3397 if (response & DP_TEST_ACK) 3398 intel_dp->compliance.test_type = request; 3399 3400 update_status: 3401 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response); 3402 if (status <= 0) 3403 drm_dbg_kms(&i915->drm, 3404 "Could not write test response to sink\n"); 3405 } 3406 3407 static void 3408 intel_dp_mst_hpd_irq(struct intel_dp *intel_dp, u8 *esi, bool *handled) 3409 { 3410 drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, handled); 3411 3412 if (esi[1] & DP_CP_IRQ) { 3413 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 3414 *handled = true; 3415 } 3416 } 3417 3418 /** 3419 * intel_dp_check_mst_status - service any pending MST interrupts, check link status 3420 * @intel_dp: Intel DP struct 3421 * 3422 * Read any pending MST interrupts, call MST core to handle these and ack the 3423 * interrupts. Check if the main and AUX link state is ok. 3424 * 3425 * Returns: 3426 * - %true if pending interrupts were serviced (or no interrupts were 3427 * pending) w/o detecting an error condition. 3428 * - %false if an error condition - like AUX failure or a loss of link - is 3429 * detected, which needs servicing from the hotplug work. 3430 */ 3431 static bool 3432 intel_dp_check_mst_status(struct intel_dp *intel_dp) 3433 { 3434 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3435 bool link_ok = true; 3436 3437 drm_WARN_ON_ONCE(&i915->drm, intel_dp->active_mst_links < 0); 3438 3439 for (;;) { 3440 /* 3441 * The +2 is because DP_DPRX_ESI_LEN is 14, but we then 3442 * pass in "esi+10" to drm_dp_channel_eq_ok(), which 3443 * takes a 6-byte array. So we actually need 16 bytes 3444 * here. 3445 * 3446 * Somebody who knows what the limits actually are 3447 * should check this, but for now this is at least 3448 * harmless and avoids a valid compiler warning about 3449 * using more of the array than we have allocated. 3450 */ 3451 u8 esi[DP_DPRX_ESI_LEN+2] = {}; 3452 bool handled; 3453 int retry; 3454 3455 if (!intel_dp_get_sink_irq_esi(intel_dp, esi)) { 3456 drm_dbg_kms(&i915->drm, 3457 "failed to get ESI - device may have failed\n"); 3458 link_ok = false; 3459 3460 break; 3461 } 3462 3463 /* check link status - esi[10] = 0x200c */ 3464 if (intel_dp->active_mst_links > 0 && link_ok && 3465 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { 3466 drm_dbg_kms(&i915->drm, 3467 "channel EQ not ok, retraining\n"); 3468 link_ok = false; 3469 } 3470 3471 drm_dbg_kms(&i915->drm, "got esi %3ph\n", esi); 3472 3473 intel_dp_mst_hpd_irq(intel_dp, esi, &handled); 3474 3475 if (!handled) 3476 break; 3477 3478 for (retry = 0; retry < 3; retry++) { 3479 int wret; 3480 3481 wret = drm_dp_dpcd_write(&intel_dp->aux, 3482 DP_SINK_COUNT_ESI+1, 3483 &esi[1], 3); 3484 if (wret == 3) 3485 break; 3486 } 3487 } 3488 3489 return link_ok; 3490 } 3491 3492 static void 3493 intel_dp_handle_hdmi_link_status_change(struct intel_dp *intel_dp) 3494 { 3495 bool is_active; 3496 u8 buf = 0; 3497 3498 is_active = drm_dp_pcon_hdmi_link_active(&intel_dp->aux); 3499 if (intel_dp->frl.is_trained && !is_active) { 3500 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, &buf) < 0) 3501 return; 3502 3503 buf &= ~DP_PCON_ENABLE_HDMI_LINK; 3504 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_PCON_HDMI_LINK_CONFIG_1, buf) < 0) 3505 return; 3506 3507 drm_dp_pcon_hdmi_frl_link_error_count(&intel_dp->aux, &intel_dp->attached_connector->base); 3508 3509 /* Restart FRL training or fall back to TMDS mode */ 3510 intel_dp_check_frl_training(intel_dp); 3511 } 3512 } 3513 3514 static bool 3515 intel_dp_needs_link_retrain(struct intel_dp *intel_dp) 3516 { 3517 u8 link_status[DP_LINK_STATUS_SIZE]; 3518 3519 if (!intel_dp->link_trained) 3520 return false; 3521 3522 /* 3523 * While PSR source HW is enabled, it will control main-link sending 3524 * frames, enabling and disabling it so trying to do a retrain will fail 3525 * as the link would or not be on or it could mix training patterns 3526 * and frame data at the same time causing retrain to fail. 3527 * Also when exiting PSR, HW will retrain the link anyways fixing 3528 * any link status error. 3529 */ 3530 if (intel_psr_enabled(intel_dp)) 3531 return false; 3532 3533 if (drm_dp_dpcd_read_phy_link_status(&intel_dp->aux, DP_PHY_DPRX, 3534 link_status) < 0) 3535 return false; 3536 3537 /* 3538 * Validate the cached values of intel_dp->link_rate and 3539 * intel_dp->lane_count before attempting to retrain. 3540 * 3541 * FIXME would be nice to user the crtc state here, but since 3542 * we need to call this from the short HPD handler that seems 3543 * a bit hard. 3544 */ 3545 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, 3546 intel_dp->lane_count)) 3547 return false; 3548 3549 /* Retrain if Channel EQ or CR not ok */ 3550 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); 3551 } 3552 3553 static bool intel_dp_has_connector(struct intel_dp *intel_dp, 3554 const struct drm_connector_state *conn_state) 3555 { 3556 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3557 struct intel_encoder *encoder; 3558 enum pipe pipe; 3559 3560 if (!conn_state->best_encoder) 3561 return false; 3562 3563 /* SST */ 3564 encoder = &dp_to_dig_port(intel_dp)->base; 3565 if (conn_state->best_encoder == &encoder->base) 3566 return true; 3567 3568 /* MST */ 3569 for_each_pipe(i915, pipe) { 3570 encoder = &intel_dp->mst_encoders[pipe]->base; 3571 if (conn_state->best_encoder == &encoder->base) 3572 return true; 3573 } 3574 3575 return false; 3576 } 3577 3578 static int intel_dp_prep_link_retrain(struct intel_dp *intel_dp, 3579 struct drm_modeset_acquire_ctx *ctx, 3580 u32 *crtc_mask) 3581 { 3582 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3583 struct drm_connector_list_iter conn_iter; 3584 struct intel_connector *connector; 3585 int ret = 0; 3586 3587 *crtc_mask = 0; 3588 3589 if (!intel_dp_needs_link_retrain(intel_dp)) 3590 return 0; 3591 3592 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 3593 for_each_intel_connector_iter(connector, &conn_iter) { 3594 struct drm_connector_state *conn_state = 3595 connector->base.state; 3596 struct intel_crtc_state *crtc_state; 3597 struct intel_crtc *crtc; 3598 3599 if (!intel_dp_has_connector(intel_dp, conn_state)) 3600 continue; 3601 3602 crtc = to_intel_crtc(conn_state->crtc); 3603 if (!crtc) 3604 continue; 3605 3606 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 3607 if (ret) 3608 break; 3609 3610 crtc_state = to_intel_crtc_state(crtc->base.state); 3611 3612 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state)); 3613 3614 if (!crtc_state->hw.active) 3615 continue; 3616 3617 if (conn_state->commit && 3618 !try_wait_for_completion(&conn_state->commit->hw_done)) 3619 continue; 3620 3621 *crtc_mask |= drm_crtc_mask(&crtc->base); 3622 } 3623 drm_connector_list_iter_end(&conn_iter); 3624 3625 if (!intel_dp_needs_link_retrain(intel_dp)) 3626 *crtc_mask = 0; 3627 3628 return ret; 3629 } 3630 3631 static bool intel_dp_is_connected(struct intel_dp *intel_dp) 3632 { 3633 struct intel_connector *connector = intel_dp->attached_connector; 3634 3635 return connector->base.status == connector_status_connected || 3636 intel_dp->is_mst; 3637 } 3638 3639 int intel_dp_retrain_link(struct intel_encoder *encoder, 3640 struct drm_modeset_acquire_ctx *ctx) 3641 { 3642 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3643 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3644 struct intel_crtc *crtc; 3645 u32 crtc_mask; 3646 int ret; 3647 3648 if (!intel_dp_is_connected(intel_dp)) 3649 return 0; 3650 3651 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 3652 ctx); 3653 if (ret) 3654 return ret; 3655 3656 ret = intel_dp_prep_link_retrain(intel_dp, ctx, &crtc_mask); 3657 if (ret) 3658 return ret; 3659 3660 if (crtc_mask == 0) 3661 return 0; 3662 3663 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] retraining link\n", 3664 encoder->base.base.id, encoder->base.name); 3665 3666 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) { 3667 const struct intel_crtc_state *crtc_state = 3668 to_intel_crtc_state(crtc->base.state); 3669 3670 /* Suppress underruns caused by re-training */ 3671 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 3672 if (crtc_state->has_pch_encoder) 3673 intel_set_pch_fifo_underrun_reporting(dev_priv, 3674 intel_crtc_pch_transcoder(crtc), false); 3675 } 3676 3677 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) { 3678 const struct intel_crtc_state *crtc_state = 3679 to_intel_crtc_state(crtc->base.state); 3680 3681 /* retrain on the MST master transcoder */ 3682 if (DISPLAY_VER(dev_priv) >= 12 && 3683 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && 3684 !intel_dp_mst_is_master_trans(crtc_state)) 3685 continue; 3686 3687 intel_dp_check_frl_training(intel_dp); 3688 intel_dp_pcon_dsc_configure(intel_dp, crtc_state); 3689 intel_dp_start_link_train(intel_dp, crtc_state); 3690 intel_dp_stop_link_train(intel_dp, crtc_state); 3691 break; 3692 } 3693 3694 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) { 3695 const struct intel_crtc_state *crtc_state = 3696 to_intel_crtc_state(crtc->base.state); 3697 3698 /* Keep underrun reporting disabled until things are stable */ 3699 intel_wait_for_vblank(dev_priv, crtc->pipe); 3700 3701 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 3702 if (crtc_state->has_pch_encoder) 3703 intel_set_pch_fifo_underrun_reporting(dev_priv, 3704 intel_crtc_pch_transcoder(crtc), true); 3705 } 3706 3707 return 0; 3708 } 3709 3710 static int intel_dp_prep_phy_test(struct intel_dp *intel_dp, 3711 struct drm_modeset_acquire_ctx *ctx, 3712 u32 *crtc_mask) 3713 { 3714 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3715 struct drm_connector_list_iter conn_iter; 3716 struct intel_connector *connector; 3717 int ret = 0; 3718 3719 *crtc_mask = 0; 3720 3721 drm_connector_list_iter_begin(&i915->drm, &conn_iter); 3722 for_each_intel_connector_iter(connector, &conn_iter) { 3723 struct drm_connector_state *conn_state = 3724 connector->base.state; 3725 struct intel_crtc_state *crtc_state; 3726 struct intel_crtc *crtc; 3727 3728 if (!intel_dp_has_connector(intel_dp, conn_state)) 3729 continue; 3730 3731 crtc = to_intel_crtc(conn_state->crtc); 3732 if (!crtc) 3733 continue; 3734 3735 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 3736 if (ret) 3737 break; 3738 3739 crtc_state = to_intel_crtc_state(crtc->base.state); 3740 3741 drm_WARN_ON(&i915->drm, !intel_crtc_has_dp_encoder(crtc_state)); 3742 3743 if (!crtc_state->hw.active) 3744 continue; 3745 3746 if (conn_state->commit && 3747 !try_wait_for_completion(&conn_state->commit->hw_done)) 3748 continue; 3749 3750 *crtc_mask |= drm_crtc_mask(&crtc->base); 3751 } 3752 drm_connector_list_iter_end(&conn_iter); 3753 3754 return ret; 3755 } 3756 3757 static int intel_dp_do_phy_test(struct intel_encoder *encoder, 3758 struct drm_modeset_acquire_ctx *ctx) 3759 { 3760 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3761 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 3762 struct intel_crtc *crtc; 3763 u32 crtc_mask; 3764 int ret; 3765 3766 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 3767 ctx); 3768 if (ret) 3769 return ret; 3770 3771 ret = intel_dp_prep_phy_test(intel_dp, ctx, &crtc_mask); 3772 if (ret) 3773 return ret; 3774 3775 if (crtc_mask == 0) 3776 return 0; 3777 3778 drm_dbg_kms(&dev_priv->drm, "[ENCODER:%d:%s] PHY test\n", 3779 encoder->base.base.id, encoder->base.name); 3780 3781 for_each_intel_crtc_mask(&dev_priv->drm, crtc, crtc_mask) { 3782 const struct intel_crtc_state *crtc_state = 3783 to_intel_crtc_state(crtc->base.state); 3784 3785 /* test on the MST master transcoder */ 3786 if (DISPLAY_VER(dev_priv) >= 12 && 3787 intel_crtc_has_type(crtc_state, INTEL_OUTPUT_DP_MST) && 3788 !intel_dp_mst_is_master_trans(crtc_state)) 3789 continue; 3790 3791 intel_dp_process_phy_request(intel_dp, crtc_state); 3792 break; 3793 } 3794 3795 return 0; 3796 } 3797 3798 void intel_dp_phy_test(struct intel_encoder *encoder) 3799 { 3800 struct drm_modeset_acquire_ctx ctx; 3801 int ret; 3802 3803 drm_modeset_acquire_init(&ctx, 0); 3804 3805 for (;;) { 3806 ret = intel_dp_do_phy_test(encoder, &ctx); 3807 3808 if (ret == -EDEADLK) { 3809 drm_modeset_backoff(&ctx); 3810 continue; 3811 } 3812 3813 break; 3814 } 3815 3816 drm_modeset_drop_locks(&ctx); 3817 drm_modeset_acquire_fini(&ctx); 3818 drm_WARN(encoder->base.dev, ret, 3819 "Acquiring modeset locks failed with %i\n", ret); 3820 } 3821 3822 static void intel_dp_check_device_service_irq(struct intel_dp *intel_dp) 3823 { 3824 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3825 u8 val; 3826 3827 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 3828 return; 3829 3830 if (drm_dp_dpcd_readb(&intel_dp->aux, 3831 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val) 3832 return; 3833 3834 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val); 3835 3836 if (val & DP_AUTOMATED_TEST_REQUEST) 3837 intel_dp_handle_test_request(intel_dp); 3838 3839 if (val & DP_CP_IRQ) 3840 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 3841 3842 if (val & DP_SINK_SPECIFIC_IRQ) 3843 drm_dbg_kms(&i915->drm, "Sink specific irq unhandled\n"); 3844 } 3845 3846 static void intel_dp_check_link_service_irq(struct intel_dp *intel_dp) 3847 { 3848 u8 val; 3849 3850 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 3851 return; 3852 3853 if (drm_dp_dpcd_readb(&intel_dp->aux, 3854 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, &val) != 1 || !val) 3855 return; 3856 3857 if (drm_dp_dpcd_writeb(&intel_dp->aux, 3858 DP_LINK_SERVICE_IRQ_VECTOR_ESI0, val) != 1) 3859 return; 3860 3861 if (val & HDMI_LINK_STATUS_CHANGED) 3862 intel_dp_handle_hdmi_link_status_change(intel_dp); 3863 } 3864 3865 /* 3866 * According to DP spec 3867 * 5.1.2: 3868 * 1. Read DPCD 3869 * 2. Configure link according to Receiver Capabilities 3870 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 3871 * 4. Check link status on receipt of hot-plug interrupt 3872 * 3873 * intel_dp_short_pulse - handles short pulse interrupts 3874 * when full detection is not required. 3875 * Returns %true if short pulse is handled and full detection 3876 * is NOT required and %false otherwise. 3877 */ 3878 static bool 3879 intel_dp_short_pulse(struct intel_dp *intel_dp) 3880 { 3881 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3882 u8 old_sink_count = intel_dp->sink_count; 3883 bool ret; 3884 3885 /* 3886 * Clearing compliance test variables to allow capturing 3887 * of values for next automated test request. 3888 */ 3889 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); 3890 3891 /* 3892 * Now read the DPCD to see if it's actually running 3893 * If the current value of sink count doesn't match with 3894 * the value that was stored earlier or dpcd read failed 3895 * we need to do full detection 3896 */ 3897 ret = intel_dp_get_dpcd(intel_dp); 3898 3899 if ((old_sink_count != intel_dp->sink_count) || !ret) { 3900 /* No need to proceed if we are going to do full detect */ 3901 return false; 3902 } 3903 3904 intel_dp_check_device_service_irq(intel_dp); 3905 intel_dp_check_link_service_irq(intel_dp); 3906 3907 /* Handle CEC interrupts, if any */ 3908 drm_dp_cec_irq(&intel_dp->aux); 3909 3910 /* defer to the hotplug work for link retraining if needed */ 3911 if (intel_dp_needs_link_retrain(intel_dp)) 3912 return false; 3913 3914 intel_psr_short_pulse(intel_dp); 3915 3916 switch (intel_dp->compliance.test_type) { 3917 case DP_TEST_LINK_TRAINING: 3918 drm_dbg_kms(&dev_priv->drm, 3919 "Link Training Compliance Test requested\n"); 3920 /* Send a Hotplug Uevent to userspace to start modeset */ 3921 drm_kms_helper_hotplug_event(&dev_priv->drm); 3922 break; 3923 case DP_TEST_LINK_PHY_TEST_PATTERN: 3924 drm_dbg_kms(&dev_priv->drm, 3925 "PHY test pattern Compliance Test requested\n"); 3926 /* 3927 * Schedule long hpd to do the test 3928 * 3929 * FIXME get rid of the ad-hoc phy test modeset code 3930 * and properly incorporate it into the normal modeset. 3931 */ 3932 return false; 3933 } 3934 3935 return true; 3936 } 3937 3938 /* XXX this is probably wrong for multiple downstream ports */ 3939 static enum drm_connector_status 3940 intel_dp_detect_dpcd(struct intel_dp *intel_dp) 3941 { 3942 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 3943 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 3944 u8 *dpcd = intel_dp->dpcd; 3945 u8 type; 3946 3947 if (drm_WARN_ON(&i915->drm, intel_dp_is_edp(intel_dp))) 3948 return connector_status_connected; 3949 3950 lspcon_resume(dig_port); 3951 3952 if (!intel_dp_get_dpcd(intel_dp)) 3953 return connector_status_disconnected; 3954 3955 /* if there's no downstream port, we're done */ 3956 if (!drm_dp_is_branch(dpcd)) 3957 return connector_status_connected; 3958 3959 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 3960 if (intel_dp_has_sink_count(intel_dp) && 3961 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 3962 return intel_dp->sink_count ? 3963 connector_status_connected : connector_status_disconnected; 3964 } 3965 3966 if (intel_dp_can_mst(intel_dp)) 3967 return connector_status_connected; 3968 3969 /* If no HPD, poke DDC gently */ 3970 if (drm_probe_ddc(&intel_dp->aux.ddc)) 3971 return connector_status_connected; 3972 3973 /* Well we tried, say unknown for unreliable port types */ 3974 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 3975 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 3976 if (type == DP_DS_PORT_TYPE_VGA || 3977 type == DP_DS_PORT_TYPE_NON_EDID) 3978 return connector_status_unknown; 3979 } else { 3980 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 3981 DP_DWN_STRM_PORT_TYPE_MASK; 3982 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 3983 type == DP_DWN_STRM_PORT_TYPE_OTHER) 3984 return connector_status_unknown; 3985 } 3986 3987 /* Anything else is out of spec, warn and ignore */ 3988 drm_dbg_kms(&i915->drm, "Broken DP branch device, ignoring\n"); 3989 return connector_status_disconnected; 3990 } 3991 3992 static enum drm_connector_status 3993 edp_detect(struct intel_dp *intel_dp) 3994 { 3995 return connector_status_connected; 3996 } 3997 3998 /* 3999 * intel_digital_port_connected - is the specified port connected? 4000 * @encoder: intel_encoder 4001 * 4002 * In cases where there's a connector physically connected but it can't be used 4003 * by our hardware we also return false, since the rest of the driver should 4004 * pretty much treat the port as disconnected. This is relevant for type-C 4005 * (starting on ICL) where there's ownership involved. 4006 * 4007 * Return %true if port is connected, %false otherwise. 4008 */ 4009 bool intel_digital_port_connected(struct intel_encoder *encoder) 4010 { 4011 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4012 struct intel_digital_port *dig_port = enc_to_dig_port(encoder); 4013 bool is_connected = false; 4014 intel_wakeref_t wakeref; 4015 4016 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) 4017 is_connected = dig_port->connected(encoder); 4018 4019 return is_connected; 4020 } 4021 4022 static struct edid * 4023 intel_dp_get_edid(struct intel_dp *intel_dp) 4024 { 4025 struct intel_connector *intel_connector = intel_dp->attached_connector; 4026 4027 /* use cached edid if we have one */ 4028 if (intel_connector->edid) { 4029 /* invalid edid */ 4030 if (IS_ERR(intel_connector->edid)) 4031 return NULL; 4032 4033 return drm_edid_duplicate(intel_connector->edid); 4034 } else 4035 return drm_get_edid(&intel_connector->base, 4036 &intel_dp->aux.ddc); 4037 } 4038 4039 static void 4040 intel_dp_update_dfp(struct intel_dp *intel_dp, 4041 const struct edid *edid) 4042 { 4043 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4044 struct intel_connector *connector = intel_dp->attached_connector; 4045 4046 intel_dp->dfp.max_bpc = 4047 drm_dp_downstream_max_bpc(intel_dp->dpcd, 4048 intel_dp->downstream_ports, edid); 4049 4050 intel_dp->dfp.max_dotclock = 4051 drm_dp_downstream_max_dotclock(intel_dp->dpcd, 4052 intel_dp->downstream_ports); 4053 4054 intel_dp->dfp.min_tmds_clock = 4055 drm_dp_downstream_min_tmds_clock(intel_dp->dpcd, 4056 intel_dp->downstream_ports, 4057 edid); 4058 intel_dp->dfp.max_tmds_clock = 4059 drm_dp_downstream_max_tmds_clock(intel_dp->dpcd, 4060 intel_dp->downstream_ports, 4061 edid); 4062 4063 intel_dp->dfp.pcon_max_frl_bw = 4064 drm_dp_get_pcon_max_frl_bw(intel_dp->dpcd, 4065 intel_dp->downstream_ports); 4066 4067 drm_dbg_kms(&i915->drm, 4068 "[CONNECTOR:%d:%s] DFP max bpc %d, max dotclock %d, TMDS clock %d-%d, PCON Max FRL BW %dGbps\n", 4069 connector->base.base.id, connector->base.name, 4070 intel_dp->dfp.max_bpc, 4071 intel_dp->dfp.max_dotclock, 4072 intel_dp->dfp.min_tmds_clock, 4073 intel_dp->dfp.max_tmds_clock, 4074 intel_dp->dfp.pcon_max_frl_bw); 4075 4076 intel_dp_get_pcon_dsc_cap(intel_dp); 4077 } 4078 4079 static void 4080 intel_dp_update_420(struct intel_dp *intel_dp) 4081 { 4082 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 4083 struct intel_connector *connector = intel_dp->attached_connector; 4084 bool is_branch, ycbcr_420_passthrough, ycbcr_444_to_420, rgb_to_ycbcr; 4085 4086 /* No YCbCr output support on gmch platforms */ 4087 if (HAS_GMCH(i915)) 4088 return; 4089 4090 /* 4091 * ILK doesn't seem capable of DP YCbCr output. The 4092 * displayed image is severly corrupted. SNB+ is fine. 4093 */ 4094 if (IS_IRONLAKE(i915)) 4095 return; 4096 4097 is_branch = drm_dp_is_branch(intel_dp->dpcd); 4098 ycbcr_420_passthrough = 4099 drm_dp_downstream_420_passthrough(intel_dp->dpcd, 4100 intel_dp->downstream_ports); 4101 /* on-board LSPCON always assumed to support 4:4:4->4:2:0 conversion */ 4102 ycbcr_444_to_420 = 4103 dp_to_dig_port(intel_dp)->lspcon.active || 4104 drm_dp_downstream_444_to_420_conversion(intel_dp->dpcd, 4105 intel_dp->downstream_ports); 4106 rgb_to_ycbcr = drm_dp_downstream_rgb_to_ycbcr_conversion(intel_dp->dpcd, 4107 intel_dp->downstream_ports, 4108 DP_DS_HDMI_BT601_RGB_YCBCR_CONV | 4109 DP_DS_HDMI_BT709_RGB_YCBCR_CONV | 4110 DP_DS_HDMI_BT2020_RGB_YCBCR_CONV); 4111 4112 if (DISPLAY_VER(i915) >= 11) { 4113 /* Let PCON convert from RGB->YCbCr if possible */ 4114 if (is_branch && rgb_to_ycbcr && ycbcr_444_to_420) { 4115 intel_dp->dfp.rgb_to_ycbcr = true; 4116 intel_dp->dfp.ycbcr_444_to_420 = true; 4117 connector->base.ycbcr_420_allowed = true; 4118 } else { 4119 /* Prefer 4:2:0 passthrough over 4:4:4->4:2:0 conversion */ 4120 intel_dp->dfp.ycbcr_444_to_420 = 4121 ycbcr_444_to_420 && !ycbcr_420_passthrough; 4122 4123 connector->base.ycbcr_420_allowed = 4124 !is_branch || ycbcr_444_to_420 || ycbcr_420_passthrough; 4125 } 4126 } else { 4127 /* 4:4:4->4:2:0 conversion is the only way */ 4128 intel_dp->dfp.ycbcr_444_to_420 = ycbcr_444_to_420; 4129 4130 connector->base.ycbcr_420_allowed = ycbcr_444_to_420; 4131 } 4132 4133 drm_dbg_kms(&i915->drm, 4134 "[CONNECTOR:%d:%s] RGB->YcbCr conversion? %s, YCbCr 4:2:0 allowed? %s, YCbCr 4:4:4->4:2:0 conversion? %s\n", 4135 connector->base.base.id, connector->base.name, 4136 yesno(intel_dp->dfp.rgb_to_ycbcr), 4137 yesno(connector->base.ycbcr_420_allowed), 4138 yesno(intel_dp->dfp.ycbcr_444_to_420)); 4139 } 4140 4141 static void 4142 intel_dp_set_edid(struct intel_dp *intel_dp) 4143 { 4144 struct intel_connector *connector = intel_dp->attached_connector; 4145 struct edid *edid; 4146 4147 intel_dp_unset_edid(intel_dp); 4148 edid = intel_dp_get_edid(intel_dp); 4149 connector->detect_edid = edid; 4150 4151 intel_dp_update_dfp(intel_dp, edid); 4152 intel_dp_update_420(intel_dp); 4153 4154 if (edid && edid->input & DRM_EDID_INPUT_DIGITAL) { 4155 intel_dp->has_hdmi_sink = drm_detect_hdmi_monitor(edid); 4156 intel_dp->has_audio = drm_detect_monitor_audio(edid); 4157 } 4158 4159 drm_dp_cec_set_edid(&intel_dp->aux, edid); 4160 } 4161 4162 static void 4163 intel_dp_unset_edid(struct intel_dp *intel_dp) 4164 { 4165 struct intel_connector *connector = intel_dp->attached_connector; 4166 4167 drm_dp_cec_unset_edid(&intel_dp->aux); 4168 kfree(connector->detect_edid); 4169 connector->detect_edid = NULL; 4170 4171 intel_dp->has_hdmi_sink = false; 4172 intel_dp->has_audio = false; 4173 4174 intel_dp->dfp.max_bpc = 0; 4175 intel_dp->dfp.max_dotclock = 0; 4176 intel_dp->dfp.min_tmds_clock = 0; 4177 intel_dp->dfp.max_tmds_clock = 0; 4178 4179 intel_dp->dfp.pcon_max_frl_bw = 0; 4180 4181 intel_dp->dfp.ycbcr_444_to_420 = false; 4182 connector->base.ycbcr_420_allowed = false; 4183 } 4184 4185 static int 4186 intel_dp_detect(struct drm_connector *connector, 4187 struct drm_modeset_acquire_ctx *ctx, 4188 bool force) 4189 { 4190 struct drm_i915_private *dev_priv = to_i915(connector->dev); 4191 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 4192 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4193 struct intel_encoder *encoder = &dig_port->base; 4194 enum drm_connector_status status; 4195 4196 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 4197 connector->base.id, connector->name); 4198 drm_WARN_ON(&dev_priv->drm, 4199 !drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 4200 4201 if (!INTEL_DISPLAY_ENABLED(dev_priv)) 4202 return connector_status_disconnected; 4203 4204 /* Can't disconnect eDP */ 4205 if (intel_dp_is_edp(intel_dp)) 4206 status = edp_detect(intel_dp); 4207 else if (intel_digital_port_connected(encoder)) 4208 status = intel_dp_detect_dpcd(intel_dp); 4209 else 4210 status = connector_status_disconnected; 4211 4212 if (status == connector_status_disconnected) { 4213 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); 4214 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); 4215 4216 if (intel_dp->is_mst) { 4217 drm_dbg_kms(&dev_priv->drm, 4218 "MST device may have disappeared %d vs %d\n", 4219 intel_dp->is_mst, 4220 intel_dp->mst_mgr.mst_state); 4221 intel_dp->is_mst = false; 4222 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 4223 intel_dp->is_mst); 4224 } 4225 4226 goto out; 4227 } 4228 4229 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ 4230 if (DISPLAY_VER(dev_priv) >= 11) 4231 intel_dp_get_dsc_sink_cap(intel_dp); 4232 4233 intel_dp_configure_mst(intel_dp); 4234 4235 /* 4236 * TODO: Reset link params when switching to MST mode, until MST 4237 * supports link training fallback params. 4238 */ 4239 if (intel_dp->reset_link_params || intel_dp->is_mst) { 4240 /* Initial max link lane count */ 4241 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); 4242 4243 /* Initial max link rate */ 4244 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); 4245 4246 intel_dp->reset_link_params = false; 4247 } 4248 4249 intel_dp_print_rates(intel_dp); 4250 4251 if (intel_dp->is_mst) { 4252 /* 4253 * If we are in MST mode then this connector 4254 * won't appear connected or have anything 4255 * with EDID on it 4256 */ 4257 status = connector_status_disconnected; 4258 goto out; 4259 } 4260 4261 /* 4262 * Some external monitors do not signal loss of link synchronization 4263 * with an IRQ_HPD, so force a link status check. 4264 */ 4265 if (!intel_dp_is_edp(intel_dp)) { 4266 int ret; 4267 4268 ret = intel_dp_retrain_link(encoder, ctx); 4269 if (ret) 4270 return ret; 4271 } 4272 4273 /* 4274 * Clearing NACK and defer counts to get their exact values 4275 * while reading EDID which are required by Compliance tests 4276 * 4.2.2.4 and 4.2.2.5 4277 */ 4278 intel_dp->aux.i2c_nack_count = 0; 4279 intel_dp->aux.i2c_defer_count = 0; 4280 4281 intel_dp_set_edid(intel_dp); 4282 if (intel_dp_is_edp(intel_dp) || 4283 to_intel_connector(connector)->detect_edid) 4284 status = connector_status_connected; 4285 4286 intel_dp_check_device_service_irq(intel_dp); 4287 4288 out: 4289 if (status != connector_status_connected && !intel_dp->is_mst) 4290 intel_dp_unset_edid(intel_dp); 4291 4292 /* 4293 * Make sure the refs for power wells enabled during detect are 4294 * dropped to avoid a new detect cycle triggered by HPD polling. 4295 */ 4296 intel_display_power_flush_work(dev_priv); 4297 4298 if (!intel_dp_is_edp(intel_dp)) 4299 drm_dp_set_subconnector_property(connector, 4300 status, 4301 intel_dp->dpcd, 4302 intel_dp->downstream_ports); 4303 return status; 4304 } 4305 4306 static void 4307 intel_dp_force(struct drm_connector *connector) 4308 { 4309 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 4310 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4311 struct intel_encoder *intel_encoder = &dig_port->base; 4312 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 4313 enum intel_display_power_domain aux_domain = 4314 intel_aux_power_domain(dig_port); 4315 intel_wakeref_t wakeref; 4316 4317 drm_dbg_kms(&dev_priv->drm, "[CONNECTOR:%d:%s]\n", 4318 connector->base.id, connector->name); 4319 intel_dp_unset_edid(intel_dp); 4320 4321 if (connector->status != connector_status_connected) 4322 return; 4323 4324 wakeref = intel_display_power_get(dev_priv, aux_domain); 4325 4326 intel_dp_set_edid(intel_dp); 4327 4328 intel_display_power_put(dev_priv, aux_domain, wakeref); 4329 } 4330 4331 static int intel_dp_get_modes(struct drm_connector *connector) 4332 { 4333 struct intel_connector *intel_connector = to_intel_connector(connector); 4334 struct edid *edid; 4335 int num_modes = 0; 4336 4337 edid = intel_connector->detect_edid; 4338 if (edid) { 4339 num_modes = intel_connector_update_modes(connector, edid); 4340 4341 if (intel_vrr_is_capable(connector)) 4342 drm_connector_set_vrr_capable_property(connector, 4343 true); 4344 } 4345 4346 /* Also add fixed mode, which may or may not be present in EDID */ 4347 if (intel_dp_is_edp(intel_attached_dp(intel_connector)) && 4348 intel_connector->panel.fixed_mode) { 4349 struct drm_display_mode *mode; 4350 4351 mode = drm_mode_duplicate(connector->dev, 4352 intel_connector->panel.fixed_mode); 4353 if (mode) { 4354 drm_mode_probed_add(connector, mode); 4355 num_modes++; 4356 } 4357 } 4358 4359 if (num_modes) 4360 return num_modes; 4361 4362 if (!edid) { 4363 struct intel_dp *intel_dp = intel_attached_dp(intel_connector); 4364 struct drm_display_mode *mode; 4365 4366 mode = drm_dp_downstream_mode(connector->dev, 4367 intel_dp->dpcd, 4368 intel_dp->downstream_ports); 4369 if (mode) { 4370 drm_mode_probed_add(connector, mode); 4371 num_modes++; 4372 } 4373 } 4374 4375 return num_modes; 4376 } 4377 4378 static int 4379 intel_dp_connector_register(struct drm_connector *connector) 4380 { 4381 struct drm_i915_private *i915 = to_i915(connector->dev); 4382 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 4383 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 4384 struct intel_lspcon *lspcon = &dig_port->lspcon; 4385 int ret; 4386 4387 ret = intel_connector_register(connector); 4388 if (ret) 4389 return ret; 4390 4391 drm_dbg_kms(&i915->drm, "registering %s bus for %s\n", 4392 intel_dp->aux.name, connector->kdev->kobj.name); 4393 4394 intel_dp->aux.dev = connector->kdev; 4395 ret = drm_dp_aux_register(&intel_dp->aux); 4396 if (!ret) 4397 drm_dp_cec_register_connector(&intel_dp->aux, connector); 4398 4399 if (!intel_bios_is_lspcon_present(i915, dig_port->base.port)) 4400 return ret; 4401 4402 /* 4403 * ToDo: Clean this up to handle lspcon init and resume more 4404 * efficiently and streamlined. 4405 */ 4406 if (lspcon_init(dig_port)) { 4407 lspcon_detect_hdr_capability(lspcon); 4408 if (lspcon->hdr_supported) 4409 drm_object_attach_property(&connector->base, 4410 connector->dev->mode_config.hdr_output_metadata_property, 4411 0); 4412 } 4413 4414 return ret; 4415 } 4416 4417 static void 4418 intel_dp_connector_unregister(struct drm_connector *connector) 4419 { 4420 struct intel_dp *intel_dp = intel_attached_dp(to_intel_connector(connector)); 4421 4422 drm_dp_cec_unregister_connector(&intel_dp->aux); 4423 drm_dp_aux_unregister(&intel_dp->aux); 4424 intel_connector_unregister(connector); 4425 } 4426 4427 void intel_dp_encoder_flush_work(struct drm_encoder *encoder) 4428 { 4429 struct intel_digital_port *dig_port = enc_to_dig_port(to_intel_encoder(encoder)); 4430 struct intel_dp *intel_dp = &dig_port->dp; 4431 4432 intel_dp_mst_encoder_cleanup(dig_port); 4433 4434 intel_pps_vdd_off_sync(intel_dp); 4435 4436 intel_dp_aux_fini(intel_dp); 4437 } 4438 4439 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) 4440 { 4441 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); 4442 4443 intel_pps_vdd_off_sync(intel_dp); 4444 } 4445 4446 void intel_dp_encoder_shutdown(struct intel_encoder *intel_encoder) 4447 { 4448 struct intel_dp *intel_dp = enc_to_intel_dp(intel_encoder); 4449 4450 intel_pps_wait_power_cycle(intel_dp); 4451 } 4452 4453 static int intel_modeset_tile_group(struct intel_atomic_state *state, 4454 int tile_group_id) 4455 { 4456 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 4457 struct drm_connector_list_iter conn_iter; 4458 struct drm_connector *connector; 4459 int ret = 0; 4460 4461 drm_connector_list_iter_begin(&dev_priv->drm, &conn_iter); 4462 drm_for_each_connector_iter(connector, &conn_iter) { 4463 struct drm_connector_state *conn_state; 4464 struct intel_crtc_state *crtc_state; 4465 struct intel_crtc *crtc; 4466 4467 if (!connector->has_tile || 4468 connector->tile_group->id != tile_group_id) 4469 continue; 4470 4471 conn_state = drm_atomic_get_connector_state(&state->base, 4472 connector); 4473 if (IS_ERR(conn_state)) { 4474 ret = PTR_ERR(conn_state); 4475 break; 4476 } 4477 4478 crtc = to_intel_crtc(conn_state->crtc); 4479 4480 if (!crtc) 4481 continue; 4482 4483 crtc_state = intel_atomic_get_new_crtc_state(state, crtc); 4484 crtc_state->uapi.mode_changed = true; 4485 4486 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 4487 if (ret) 4488 break; 4489 } 4490 drm_connector_list_iter_end(&conn_iter); 4491 4492 return ret; 4493 } 4494 4495 static int intel_modeset_affected_transcoders(struct intel_atomic_state *state, u8 transcoders) 4496 { 4497 struct drm_i915_private *dev_priv = to_i915(state->base.dev); 4498 struct intel_crtc *crtc; 4499 4500 if (transcoders == 0) 4501 return 0; 4502 4503 for_each_intel_crtc(&dev_priv->drm, crtc) { 4504 struct intel_crtc_state *crtc_state; 4505 int ret; 4506 4507 crtc_state = intel_atomic_get_crtc_state(&state->base, crtc); 4508 if (IS_ERR(crtc_state)) 4509 return PTR_ERR(crtc_state); 4510 4511 if (!crtc_state->hw.enable) 4512 continue; 4513 4514 if (!(transcoders & BIT(crtc_state->cpu_transcoder))) 4515 continue; 4516 4517 crtc_state->uapi.mode_changed = true; 4518 4519 ret = drm_atomic_add_affected_connectors(&state->base, &crtc->base); 4520 if (ret) 4521 return ret; 4522 4523 ret = drm_atomic_add_affected_planes(&state->base, &crtc->base); 4524 if (ret) 4525 return ret; 4526 4527 transcoders &= ~BIT(crtc_state->cpu_transcoder); 4528 } 4529 4530 drm_WARN_ON(&dev_priv->drm, transcoders != 0); 4531 4532 return 0; 4533 } 4534 4535 static int intel_modeset_synced_crtcs(struct intel_atomic_state *state, 4536 struct drm_connector *connector) 4537 { 4538 const struct drm_connector_state *old_conn_state = 4539 drm_atomic_get_old_connector_state(&state->base, connector); 4540 const struct intel_crtc_state *old_crtc_state; 4541 struct intel_crtc *crtc; 4542 u8 transcoders; 4543 4544 crtc = to_intel_crtc(old_conn_state->crtc); 4545 if (!crtc) 4546 return 0; 4547 4548 old_crtc_state = intel_atomic_get_old_crtc_state(state, crtc); 4549 4550 if (!old_crtc_state->hw.active) 4551 return 0; 4552 4553 transcoders = old_crtc_state->sync_mode_slaves_mask; 4554 if (old_crtc_state->master_transcoder != INVALID_TRANSCODER) 4555 transcoders |= BIT(old_crtc_state->master_transcoder); 4556 4557 return intel_modeset_affected_transcoders(state, 4558 transcoders); 4559 } 4560 4561 static int intel_dp_connector_atomic_check(struct drm_connector *conn, 4562 struct drm_atomic_state *_state) 4563 { 4564 struct drm_i915_private *dev_priv = to_i915(conn->dev); 4565 struct intel_atomic_state *state = to_intel_atomic_state(_state); 4566 int ret; 4567 4568 ret = intel_digital_connector_atomic_check(conn, &state->base); 4569 if (ret) 4570 return ret; 4571 4572 /* 4573 * We don't enable port sync on BDW due to missing w/as and 4574 * due to not having adjusted the modeset sequence appropriately. 4575 */ 4576 if (DISPLAY_VER(dev_priv) < 9) 4577 return 0; 4578 4579 if (!intel_connector_needs_modeset(state, conn)) 4580 return 0; 4581 4582 if (conn->has_tile) { 4583 ret = intel_modeset_tile_group(state, conn->tile_group->id); 4584 if (ret) 4585 return ret; 4586 } 4587 4588 return intel_modeset_synced_crtcs(state, conn); 4589 } 4590 4591 static const struct drm_connector_funcs intel_dp_connector_funcs = { 4592 .force = intel_dp_force, 4593 .fill_modes = drm_helper_probe_single_connector_modes, 4594 .atomic_get_property = intel_digital_connector_atomic_get_property, 4595 .atomic_set_property = intel_digital_connector_atomic_set_property, 4596 .late_register = intel_dp_connector_register, 4597 .early_unregister = intel_dp_connector_unregister, 4598 .destroy = intel_connector_destroy, 4599 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 4600 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 4601 }; 4602 4603 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 4604 .detect_ctx = intel_dp_detect, 4605 .get_modes = intel_dp_get_modes, 4606 .mode_valid = intel_dp_mode_valid, 4607 .atomic_check = intel_dp_connector_atomic_check, 4608 }; 4609 4610 enum irqreturn 4611 intel_dp_hpd_pulse(struct intel_digital_port *dig_port, bool long_hpd) 4612 { 4613 struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev); 4614 struct intel_dp *intel_dp = &dig_port->dp; 4615 4616 if (dig_port->base.type == INTEL_OUTPUT_EDP && 4617 (long_hpd || !intel_pps_have_power(intel_dp))) { 4618 /* 4619 * vdd off can generate a long/short pulse on eDP which 4620 * would require vdd on to handle it, and thus we 4621 * would end up in an endless cycle of 4622 * "vdd off -> long/short hpd -> vdd on -> detect -> vdd off -> ..." 4623 */ 4624 drm_dbg_kms(&i915->drm, 4625 "ignoring %s hpd on eDP [ENCODER:%d:%s]\n", 4626 long_hpd ? "long" : "short", 4627 dig_port->base.base.base.id, 4628 dig_port->base.base.name); 4629 return IRQ_HANDLED; 4630 } 4631 4632 drm_dbg_kms(&i915->drm, "got hpd irq on [ENCODER:%d:%s] - %s\n", 4633 dig_port->base.base.base.id, 4634 dig_port->base.base.name, 4635 long_hpd ? "long" : "short"); 4636 4637 if (long_hpd) { 4638 intel_dp->reset_link_params = true; 4639 return IRQ_NONE; 4640 } 4641 4642 if (intel_dp->is_mst) { 4643 if (!intel_dp_check_mst_status(intel_dp)) 4644 return IRQ_NONE; 4645 } else if (!intel_dp_short_pulse(intel_dp)) { 4646 return IRQ_NONE; 4647 } 4648 4649 return IRQ_HANDLED; 4650 } 4651 4652 /* check the VBT to see whether the eDP is on another port */ 4653 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port) 4654 { 4655 /* 4656 * eDP not supported on g4x. so bail out early just 4657 * for a bit extra safety in case the VBT is bonkers. 4658 */ 4659 if (DISPLAY_VER(dev_priv) < 5) 4660 return false; 4661 4662 if (DISPLAY_VER(dev_priv) < 9 && port == PORT_A) 4663 return true; 4664 4665 return intel_bios_is_port_edp(dev_priv, port); 4666 } 4667 4668 static void 4669 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 4670 { 4671 struct drm_i915_private *dev_priv = to_i915(connector->dev); 4672 enum port port = dp_to_dig_port(intel_dp)->base.port; 4673 4674 if (!intel_dp_is_edp(intel_dp)) 4675 drm_connector_attach_dp_subconnector_property(connector); 4676 4677 if (!IS_G4X(dev_priv) && port != PORT_A) 4678 intel_attach_force_audio_property(connector); 4679 4680 intel_attach_broadcast_rgb_property(connector); 4681 if (HAS_GMCH(dev_priv)) 4682 drm_connector_attach_max_bpc_property(connector, 6, 10); 4683 else if (DISPLAY_VER(dev_priv) >= 5) 4684 drm_connector_attach_max_bpc_property(connector, 6, 12); 4685 4686 /* Register HDMI colorspace for case of lspcon */ 4687 if (intel_bios_is_lspcon_present(dev_priv, port)) { 4688 drm_connector_attach_content_type_property(connector); 4689 intel_attach_hdmi_colorspace_property(connector); 4690 } else { 4691 intel_attach_dp_colorspace_property(connector); 4692 } 4693 4694 if (IS_GEMINILAKE(dev_priv) || DISPLAY_VER(dev_priv) >= 11) 4695 drm_object_attach_property(&connector->base, 4696 connector->dev->mode_config.hdr_output_metadata_property, 4697 0); 4698 4699 if (intel_dp_is_edp(intel_dp)) { 4700 u32 allowed_scalers; 4701 4702 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); 4703 if (!HAS_GMCH(dev_priv)) 4704 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); 4705 4706 drm_connector_attach_scaling_mode_property(connector, allowed_scalers); 4707 4708 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; 4709 4710 } 4711 4712 if (HAS_VRR(dev_priv)) 4713 drm_connector_attach_vrr_capable_property(connector); 4714 } 4715 4716 /** 4717 * intel_dp_set_drrs_state - program registers for RR switch to take effect 4718 * @dev_priv: i915 device 4719 * @crtc_state: a pointer to the active intel_crtc_state 4720 * @refresh_rate: RR to be programmed 4721 * 4722 * This function gets called when refresh rate (RR) has to be changed from 4723 * one frequency to another. Switches can be between high and low RR 4724 * supported by the panel or to any other RR based on media playback (in 4725 * this case, RR value needs to be passed from user space). 4726 * 4727 * The caller of this function needs to take a lock on dev_priv->drrs. 4728 */ 4729 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, 4730 const struct intel_crtc_state *crtc_state, 4731 int refresh_rate) 4732 { 4733 struct intel_dp *intel_dp = dev_priv->drrs.dp; 4734 struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); 4735 enum drrs_refresh_rate_type index = DRRS_HIGH_RR; 4736 4737 if (refresh_rate <= 0) { 4738 drm_dbg_kms(&dev_priv->drm, 4739 "Refresh rate should be positive non-zero.\n"); 4740 return; 4741 } 4742 4743 if (intel_dp == NULL) { 4744 drm_dbg_kms(&dev_priv->drm, "DRRS not supported.\n"); 4745 return; 4746 } 4747 4748 if (!crtc) { 4749 drm_dbg_kms(&dev_priv->drm, 4750 "DRRS: intel_crtc not initialized\n"); 4751 return; 4752 } 4753 4754 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { 4755 drm_dbg_kms(&dev_priv->drm, "Only Seamless DRRS supported.\n"); 4756 return; 4757 } 4758 4759 if (drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode) == 4760 refresh_rate) 4761 index = DRRS_LOW_RR; 4762 4763 if (index == dev_priv->drrs.refresh_rate_type) { 4764 drm_dbg_kms(&dev_priv->drm, 4765 "DRRS requested for previously set RR...ignoring\n"); 4766 return; 4767 } 4768 4769 if (!crtc_state->hw.active) { 4770 drm_dbg_kms(&dev_priv->drm, 4771 "eDP encoder disabled. CRTC not Active\n"); 4772 return; 4773 } 4774 4775 if (DISPLAY_VER(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { 4776 switch (index) { 4777 case DRRS_HIGH_RR: 4778 intel_dp_set_m_n(crtc_state, M1_N1); 4779 break; 4780 case DRRS_LOW_RR: 4781 intel_dp_set_m_n(crtc_state, M2_N2); 4782 break; 4783 case DRRS_MAX_RR: 4784 default: 4785 drm_err(&dev_priv->drm, 4786 "Unsupported refreshrate type\n"); 4787 } 4788 } else if (DISPLAY_VER(dev_priv) > 6) { 4789 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); 4790 u32 val; 4791 4792 val = intel_de_read(dev_priv, reg); 4793 if (index > DRRS_HIGH_RR) { 4794 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4795 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; 4796 else 4797 val |= PIPECONF_EDP_RR_MODE_SWITCH; 4798 } else { 4799 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 4800 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; 4801 else 4802 val &= ~PIPECONF_EDP_RR_MODE_SWITCH; 4803 } 4804 intel_de_write(dev_priv, reg, val); 4805 } 4806 4807 dev_priv->drrs.refresh_rate_type = index; 4808 4809 drm_dbg_kms(&dev_priv->drm, "eDP Refresh Rate set to : %dHz\n", 4810 refresh_rate); 4811 } 4812 4813 static void 4814 intel_edp_drrs_enable_locked(struct intel_dp *intel_dp) 4815 { 4816 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 4817 4818 dev_priv->drrs.busy_frontbuffer_bits = 0; 4819 dev_priv->drrs.dp = intel_dp; 4820 } 4821 4822 /** 4823 * intel_edp_drrs_enable - init drrs struct if supported 4824 * @intel_dp: DP struct 4825 * @crtc_state: A pointer to the active crtc state. 4826 * 4827 * Initializes frontbuffer_bits and drrs.dp 4828 */ 4829 void intel_edp_drrs_enable(struct intel_dp *intel_dp, 4830 const struct intel_crtc_state *crtc_state) 4831 { 4832 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 4833 4834 if (!crtc_state->has_drrs) 4835 return; 4836 4837 drm_dbg_kms(&dev_priv->drm, "Enabling DRRS\n"); 4838 4839 mutex_lock(&dev_priv->drrs.mutex); 4840 4841 if (dev_priv->drrs.dp) { 4842 drm_warn(&dev_priv->drm, "DRRS already enabled\n"); 4843 goto unlock; 4844 } 4845 4846 intel_edp_drrs_enable_locked(intel_dp); 4847 4848 unlock: 4849 mutex_unlock(&dev_priv->drrs.mutex); 4850 } 4851 4852 static void 4853 intel_edp_drrs_disable_locked(struct intel_dp *intel_dp, 4854 const struct intel_crtc_state *crtc_state) 4855 { 4856 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 4857 4858 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) { 4859 int refresh; 4860 4861 refresh = drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode); 4862 intel_dp_set_drrs_state(dev_priv, crtc_state, refresh); 4863 } 4864 4865 dev_priv->drrs.dp = NULL; 4866 } 4867 4868 /** 4869 * intel_edp_drrs_disable - Disable DRRS 4870 * @intel_dp: DP struct 4871 * @old_crtc_state: Pointer to old crtc_state. 4872 * 4873 */ 4874 void intel_edp_drrs_disable(struct intel_dp *intel_dp, 4875 const struct intel_crtc_state *old_crtc_state) 4876 { 4877 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 4878 4879 if (!old_crtc_state->has_drrs) 4880 return; 4881 4882 mutex_lock(&dev_priv->drrs.mutex); 4883 if (!dev_priv->drrs.dp) { 4884 mutex_unlock(&dev_priv->drrs.mutex); 4885 return; 4886 } 4887 4888 intel_edp_drrs_disable_locked(intel_dp, old_crtc_state); 4889 mutex_unlock(&dev_priv->drrs.mutex); 4890 4891 cancel_delayed_work_sync(&dev_priv->drrs.work); 4892 } 4893 4894 /** 4895 * intel_edp_drrs_update - Update DRRS state 4896 * @intel_dp: Intel DP 4897 * @crtc_state: new CRTC state 4898 * 4899 * This function will update DRRS states, disabling or enabling DRRS when 4900 * executing fastsets. For full modeset, intel_edp_drrs_disable() and 4901 * intel_edp_drrs_enable() should be called instead. 4902 */ 4903 void 4904 intel_edp_drrs_update(struct intel_dp *intel_dp, 4905 const struct intel_crtc_state *crtc_state) 4906 { 4907 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 4908 4909 if (dev_priv->drrs.type != SEAMLESS_DRRS_SUPPORT) 4910 return; 4911 4912 mutex_lock(&dev_priv->drrs.mutex); 4913 4914 /* New state matches current one? */ 4915 if (crtc_state->has_drrs == !!dev_priv->drrs.dp) 4916 goto unlock; 4917 4918 if (crtc_state->has_drrs) 4919 intel_edp_drrs_enable_locked(intel_dp); 4920 else 4921 intel_edp_drrs_disable_locked(intel_dp, crtc_state); 4922 4923 unlock: 4924 mutex_unlock(&dev_priv->drrs.mutex); 4925 } 4926 4927 static void intel_edp_drrs_downclock_work(struct work_struct *work) 4928 { 4929 struct drm_i915_private *dev_priv = 4930 container_of(work, typeof(*dev_priv), drrs.work.work); 4931 struct intel_dp *intel_dp; 4932 4933 mutex_lock(&dev_priv->drrs.mutex); 4934 4935 intel_dp = dev_priv->drrs.dp; 4936 4937 if (!intel_dp) 4938 goto unlock; 4939 4940 /* 4941 * The delayed work can race with an invalidate hence we need to 4942 * recheck. 4943 */ 4944 4945 if (dev_priv->drrs.busy_frontbuffer_bits) 4946 goto unlock; 4947 4948 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) { 4949 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 4950 4951 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, 4952 drm_mode_vrefresh(intel_dp->attached_connector->panel.downclock_mode)); 4953 } 4954 4955 unlock: 4956 mutex_unlock(&dev_priv->drrs.mutex); 4957 } 4958 4959 /** 4960 * intel_edp_drrs_invalidate - Disable Idleness DRRS 4961 * @dev_priv: i915 device 4962 * @frontbuffer_bits: frontbuffer plane tracking bits 4963 * 4964 * This function gets called everytime rendering on the given planes start. 4965 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). 4966 * 4967 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 4968 */ 4969 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, 4970 unsigned int frontbuffer_bits) 4971 { 4972 struct intel_dp *intel_dp; 4973 struct drm_crtc *crtc; 4974 enum pipe pipe; 4975 4976 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) 4977 return; 4978 4979 cancel_delayed_work(&dev_priv->drrs.work); 4980 4981 mutex_lock(&dev_priv->drrs.mutex); 4982 4983 intel_dp = dev_priv->drrs.dp; 4984 if (!intel_dp) { 4985 mutex_unlock(&dev_priv->drrs.mutex); 4986 return; 4987 } 4988 4989 crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 4990 pipe = to_intel_crtc(crtc)->pipe; 4991 4992 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 4993 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; 4994 4995 /* invalidate means busy screen hence upclock */ 4996 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 4997 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, 4998 drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode)); 4999 5000 mutex_unlock(&dev_priv->drrs.mutex); 5001 } 5002 5003 /** 5004 * intel_edp_drrs_flush - Restart Idleness DRRS 5005 * @dev_priv: i915 device 5006 * @frontbuffer_bits: frontbuffer plane tracking bits 5007 * 5008 * This function gets called every time rendering on the given planes has 5009 * completed or flip on a crtc is completed. So DRRS should be upclocked 5010 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, 5011 * if no other planes are dirty. 5012 * 5013 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 5014 */ 5015 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, 5016 unsigned int frontbuffer_bits) 5017 { 5018 struct intel_dp *intel_dp; 5019 struct drm_crtc *crtc; 5020 enum pipe pipe; 5021 5022 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) 5023 return; 5024 5025 cancel_delayed_work(&dev_priv->drrs.work); 5026 5027 mutex_lock(&dev_priv->drrs.mutex); 5028 5029 intel_dp = dev_priv->drrs.dp; 5030 if (!intel_dp) { 5031 mutex_unlock(&dev_priv->drrs.mutex); 5032 return; 5033 } 5034 5035 crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 5036 pipe = to_intel_crtc(crtc)->pipe; 5037 5038 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 5039 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; 5040 5041 /* flush means busy screen hence upclock */ 5042 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 5043 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, 5044 drm_mode_vrefresh(intel_dp->attached_connector->panel.fixed_mode)); 5045 5046 /* 5047 * flush also means no more activity hence schedule downclock, if all 5048 * other fbs are quiescent too 5049 */ 5050 if (!dev_priv->drrs.busy_frontbuffer_bits) 5051 schedule_delayed_work(&dev_priv->drrs.work, 5052 msecs_to_jiffies(1000)); 5053 mutex_unlock(&dev_priv->drrs.mutex); 5054 } 5055 5056 /** 5057 * DOC: Display Refresh Rate Switching (DRRS) 5058 * 5059 * Display Refresh Rate Switching (DRRS) is a power conservation feature 5060 * which enables swtching between low and high refresh rates, 5061 * dynamically, based on the usage scenario. This feature is applicable 5062 * for internal panels. 5063 * 5064 * Indication that the panel supports DRRS is given by the panel EDID, which 5065 * would list multiple refresh rates for one resolution. 5066 * 5067 * DRRS is of 2 types - static and seamless. 5068 * Static DRRS involves changing refresh rate (RR) by doing a full modeset 5069 * (may appear as a blink on screen) and is used in dock-undock scenario. 5070 * Seamless DRRS involves changing RR without any visual effect to the user 5071 * and can be used during normal system usage. This is done by programming 5072 * certain registers. 5073 * 5074 * Support for static/seamless DRRS may be indicated in the VBT based on 5075 * inputs from the panel spec. 5076 * 5077 * DRRS saves power by switching to low RR based on usage scenarios. 5078 * 5079 * The implementation is based on frontbuffer tracking implementation. When 5080 * there is a disturbance on the screen triggered by user activity or a periodic 5081 * system activity, DRRS is disabled (RR is changed to high RR). When there is 5082 * no movement on screen, after a timeout of 1 second, a switch to low RR is 5083 * made. 5084 * 5085 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() 5086 * and intel_edp_drrs_flush() are called. 5087 * 5088 * DRRS can be further extended to support other internal panels and also 5089 * the scenario of video playback wherein RR is set based on the rate 5090 * requested by userspace. 5091 */ 5092 5093 /** 5094 * intel_dp_drrs_init - Init basic DRRS work and mutex. 5095 * @connector: eDP connector 5096 * @fixed_mode: preferred mode of panel 5097 * 5098 * This function is called only once at driver load to initialize basic 5099 * DRRS stuff. 5100 * 5101 * Returns: 5102 * Downclock mode if panel supports it, else return NULL. 5103 * DRRS support is determined by the presence of downclock mode (apart 5104 * from VBT setting). 5105 */ 5106 static struct drm_display_mode * 5107 intel_dp_drrs_init(struct intel_connector *connector, 5108 struct drm_display_mode *fixed_mode) 5109 { 5110 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 5111 struct drm_display_mode *downclock_mode = NULL; 5112 5113 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); 5114 mutex_init(&dev_priv->drrs.mutex); 5115 5116 if (DISPLAY_VER(dev_priv) <= 6) { 5117 drm_dbg_kms(&dev_priv->drm, 5118 "DRRS supported for Gen7 and above\n"); 5119 return NULL; 5120 } 5121 5122 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { 5123 drm_dbg_kms(&dev_priv->drm, "VBT doesn't support DRRS\n"); 5124 return NULL; 5125 } 5126 5127 downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode); 5128 if (!downclock_mode) { 5129 drm_dbg_kms(&dev_priv->drm, 5130 "Downclock mode is not found. DRRS not supported\n"); 5131 return NULL; 5132 } 5133 5134 dev_priv->drrs.type = dev_priv->vbt.drrs_type; 5135 5136 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; 5137 drm_dbg_kms(&dev_priv->drm, 5138 "seamless DRRS supported for eDP panel.\n"); 5139 return downclock_mode; 5140 } 5141 5142 static bool intel_edp_init_connector(struct intel_dp *intel_dp, 5143 struct intel_connector *intel_connector) 5144 { 5145 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 5146 struct drm_device *dev = &dev_priv->drm; 5147 struct drm_connector *connector = &intel_connector->base; 5148 struct drm_display_mode *fixed_mode = NULL; 5149 struct drm_display_mode *downclock_mode = NULL; 5150 bool has_dpcd; 5151 enum pipe pipe = INVALID_PIPE; 5152 struct edid *edid; 5153 5154 if (!intel_dp_is_edp(intel_dp)) 5155 return true; 5156 5157 /* 5158 * On IBX/CPT we may get here with LVDS already registered. Since the 5159 * driver uses the only internal power sequencer available for both 5160 * eDP and LVDS bail out early in this case to prevent interfering 5161 * with an already powered-on LVDS power sequencer. 5162 */ 5163 if (intel_get_lvds_encoder(dev_priv)) { 5164 drm_WARN_ON(dev, 5165 !(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); 5166 drm_info(&dev_priv->drm, 5167 "LVDS was detected, not registering eDP\n"); 5168 5169 return false; 5170 } 5171 5172 intel_pps_init(intel_dp); 5173 5174 /* Cache DPCD and EDID for edp. */ 5175 has_dpcd = intel_edp_init_dpcd(intel_dp); 5176 5177 if (!has_dpcd) { 5178 /* if this fails, presume the device is a ghost */ 5179 drm_info(&dev_priv->drm, 5180 "failed to retrieve link info, disabling eDP\n"); 5181 goto out_vdd_off; 5182 } 5183 5184 mutex_lock(&dev->mode_config.mutex); 5185 edid = drm_get_edid(connector, &intel_dp->aux.ddc); 5186 if (edid) { 5187 if (drm_add_edid_modes(connector, edid)) { 5188 drm_connector_update_edid_property(connector, edid); 5189 } else { 5190 kfree(edid); 5191 edid = ERR_PTR(-EINVAL); 5192 } 5193 } else { 5194 edid = ERR_PTR(-ENOENT); 5195 } 5196 intel_connector->edid = edid; 5197 5198 fixed_mode = intel_panel_edid_fixed_mode(intel_connector); 5199 if (fixed_mode) 5200 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode); 5201 5202 /* multiply the mode clock and horizontal timings for MSO */ 5203 intel_edp_mso_mode_fixup(intel_connector, fixed_mode); 5204 intel_edp_mso_mode_fixup(intel_connector, downclock_mode); 5205 5206 /* fallback to VBT if available for eDP */ 5207 if (!fixed_mode) 5208 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 5209 mutex_unlock(&dev->mode_config.mutex); 5210 5211 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 5212 /* 5213 * Figure out the current pipe for the initial backlight setup. 5214 * If the current pipe isn't valid, try the PPS pipe, and if that 5215 * fails just assume pipe A. 5216 */ 5217 pipe = vlv_active_pipe(intel_dp); 5218 5219 if (pipe != PIPE_A && pipe != PIPE_B) 5220 pipe = intel_dp->pps.pps_pipe; 5221 5222 if (pipe != PIPE_A && pipe != PIPE_B) 5223 pipe = PIPE_A; 5224 5225 drm_dbg_kms(&dev_priv->drm, 5226 "using pipe %c for initial backlight setup\n", 5227 pipe_name(pipe)); 5228 } 5229 5230 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 5231 if (!(dev_priv->quirks & QUIRK_NO_PPS_BACKLIGHT_POWER_HOOK)) 5232 intel_connector->panel.backlight.power = intel_pps_backlight_power; 5233 intel_panel_setup_backlight(connector, pipe); 5234 5235 if (fixed_mode) { 5236 drm_connector_set_panel_orientation_with_quirk(connector, 5237 dev_priv->vbt.orientation, 5238 fixed_mode->hdisplay, fixed_mode->vdisplay); 5239 } 5240 5241 return true; 5242 5243 out_vdd_off: 5244 intel_pps_vdd_off_sync(intel_dp); 5245 5246 return false; 5247 } 5248 5249 static void intel_dp_modeset_retry_work_fn(struct work_struct *work) 5250 { 5251 struct intel_connector *intel_connector; 5252 struct drm_connector *connector; 5253 5254 intel_connector = container_of(work, typeof(*intel_connector), 5255 modeset_retry_work); 5256 connector = &intel_connector->base; 5257 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, 5258 connector->name); 5259 5260 /* Grab the locks before changing connector property*/ 5261 mutex_lock(&connector->dev->mode_config.mutex); 5262 /* Set connector link status to BAD and send a Uevent to notify 5263 * userspace to do a modeset. 5264 */ 5265 drm_connector_set_link_status_property(connector, 5266 DRM_MODE_LINK_STATUS_BAD); 5267 mutex_unlock(&connector->dev->mode_config.mutex); 5268 /* Send Hotplug uevent so userspace can reprobe */ 5269 drm_kms_helper_hotplug_event(connector->dev); 5270 } 5271 5272 bool 5273 intel_dp_init_connector(struct intel_digital_port *dig_port, 5274 struct intel_connector *intel_connector) 5275 { 5276 struct drm_connector *connector = &intel_connector->base; 5277 struct intel_dp *intel_dp = &dig_port->dp; 5278 struct intel_encoder *intel_encoder = &dig_port->base; 5279 struct drm_device *dev = intel_encoder->base.dev; 5280 struct drm_i915_private *dev_priv = to_i915(dev); 5281 enum port port = intel_encoder->port; 5282 enum phy phy = intel_port_to_phy(dev_priv, port); 5283 int type; 5284 5285 /* Initialize the work for modeset in case of link train failure */ 5286 INIT_WORK(&intel_connector->modeset_retry_work, 5287 intel_dp_modeset_retry_work_fn); 5288 5289 if (drm_WARN(dev, dig_port->max_lanes < 1, 5290 "Not enough lanes (%d) for DP on [ENCODER:%d:%s]\n", 5291 dig_port->max_lanes, intel_encoder->base.base.id, 5292 intel_encoder->base.name)) 5293 return false; 5294 5295 intel_dp_set_source_rates(intel_dp); 5296 5297 intel_dp->reset_link_params = true; 5298 intel_dp->pps.pps_pipe = INVALID_PIPE; 5299 intel_dp->pps.active_pipe = INVALID_PIPE; 5300 5301 /* Preserve the current hw state. */ 5302 intel_dp->DP = intel_de_read(dev_priv, intel_dp->output_reg); 5303 intel_dp->attached_connector = intel_connector; 5304 5305 if (intel_dp_is_port_edp(dev_priv, port)) { 5306 /* 5307 * Currently we don't support eDP on TypeC ports, although in 5308 * theory it could work on TypeC legacy ports. 5309 */ 5310 drm_WARN_ON(dev, intel_phy_is_tc(dev_priv, phy)); 5311 type = DRM_MODE_CONNECTOR_eDP; 5312 } else { 5313 type = DRM_MODE_CONNECTOR_DisplayPort; 5314 } 5315 5316 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 5317 intel_dp->pps.active_pipe = vlv_active_pipe(intel_dp); 5318 5319 /* 5320 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 5321 * for DP the encoder type can be set by the caller to 5322 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 5323 */ 5324 if (type == DRM_MODE_CONNECTOR_eDP) 5325 intel_encoder->type = INTEL_OUTPUT_EDP; 5326 5327 /* eDP only on port B and/or C on vlv/chv */ 5328 if (drm_WARN_ON(dev, (IS_VALLEYVIEW(dev_priv) || 5329 IS_CHERRYVIEW(dev_priv)) && 5330 intel_dp_is_edp(intel_dp) && 5331 port != PORT_B && port != PORT_C)) 5332 return false; 5333 5334 drm_dbg_kms(&dev_priv->drm, 5335 "Adding %s connector on [ENCODER:%d:%s]\n", 5336 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 5337 intel_encoder->base.base.id, intel_encoder->base.name); 5338 5339 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 5340 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 5341 5342 if (!HAS_GMCH(dev_priv)) 5343 connector->interlace_allowed = true; 5344 connector->doublescan_allowed = 0; 5345 5346 intel_connector->polled = DRM_CONNECTOR_POLL_HPD; 5347 5348 intel_dp_aux_init(intel_dp); 5349 5350 intel_connector_attach_encoder(intel_connector, intel_encoder); 5351 5352 if (HAS_DDI(dev_priv)) 5353 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 5354 else 5355 intel_connector->get_hw_state = intel_connector_get_hw_state; 5356 5357 /* init MST on ports that can support it */ 5358 intel_dp_mst_encoder_init(dig_port, 5359 intel_connector->base.base.id); 5360 5361 if (!intel_edp_init_connector(intel_dp, intel_connector)) { 5362 intel_dp_aux_fini(intel_dp); 5363 intel_dp_mst_encoder_cleanup(dig_port); 5364 goto fail; 5365 } 5366 5367 intel_dp_add_properties(intel_dp, connector); 5368 5369 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) { 5370 int ret = intel_dp_hdcp_init(dig_port, intel_connector); 5371 if (ret) 5372 drm_dbg_kms(&dev_priv->drm, 5373 "HDCP init failed, skipping.\n"); 5374 } 5375 5376 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 5377 * 0xd. Failure to do so will result in spurious interrupts being 5378 * generated on the port when a cable is not attached. 5379 */ 5380 if (IS_G45(dev_priv)) { 5381 u32 temp = intel_de_read(dev_priv, PEG_BAND_GAP_DATA); 5382 intel_de_write(dev_priv, PEG_BAND_GAP_DATA, 5383 (temp & ~0xf) | 0xd); 5384 } 5385 5386 intel_dp->frl.is_trained = false; 5387 intel_dp->frl.trained_rate_gbps = 0; 5388 5389 intel_psr_init(intel_dp); 5390 5391 return true; 5392 5393 fail: 5394 drm_connector_cleanup(connector); 5395 5396 return false; 5397 } 5398 5399 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv) 5400 { 5401 struct intel_encoder *encoder; 5402 5403 if (!HAS_DISPLAY(dev_priv)) 5404 return; 5405 5406 for_each_intel_encoder(&dev_priv->drm, encoder) { 5407 struct intel_dp *intel_dp; 5408 5409 if (encoder->type != INTEL_OUTPUT_DDI) 5410 continue; 5411 5412 intel_dp = enc_to_intel_dp(encoder); 5413 5414 if (!intel_dp->can_mst) 5415 continue; 5416 5417 if (intel_dp->is_mst) 5418 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr); 5419 } 5420 } 5421 5422 void intel_dp_mst_resume(struct drm_i915_private *dev_priv) 5423 { 5424 struct intel_encoder *encoder; 5425 5426 if (!HAS_DISPLAY(dev_priv)) 5427 return; 5428 5429 for_each_intel_encoder(&dev_priv->drm, encoder) { 5430 struct intel_dp *intel_dp; 5431 int ret; 5432 5433 if (encoder->type != INTEL_OUTPUT_DDI) 5434 continue; 5435 5436 intel_dp = enc_to_intel_dp(encoder); 5437 5438 if (!intel_dp->can_mst) 5439 continue; 5440 5441 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr, 5442 true); 5443 if (ret) { 5444 intel_dp->is_mst = false; 5445 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 5446 false); 5447 } 5448 } 5449 } 5450