1 /* 2 * Copyright © 2008 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 * Authors: 24 * Keith Packard <keithp@keithp.com> 25 * 26 */ 27 28 #include <linux/export.h> 29 #include <linux/i2c.h> 30 #include <linux/notifier.h> 31 #include <linux/reboot.h> 32 #include <linux/slab.h> 33 #include <linux/types.h> 34 35 #include <asm/byteorder.h> 36 37 #include <drm/drm_atomic_helper.h> 38 #include <drm/drm_crtc.h> 39 #include <drm/drm_dp_helper.h> 40 #include <drm/drm_edid.h> 41 #include <drm/drm_hdcp.h> 42 #include <drm/drm_probe_helper.h> 43 #include <drm/i915_drm.h> 44 45 #include "i915_debugfs.h" 46 #include "i915_drv.h" 47 #include "intel_atomic.h" 48 #include "intel_audio.h" 49 #include "intel_connector.h" 50 #include "intel_ddi.h" 51 #include "intel_dp.h" 52 #include "intel_dp_link_training.h" 53 #include "intel_dp_mst.h" 54 #include "intel_dpio_phy.h" 55 #include "intel_drv.h" 56 #include "intel_fifo_underrun.h" 57 #include "intel_hdcp.h" 58 #include "intel_hdmi.h" 59 #include "intel_hotplug.h" 60 #include "intel_lspcon.h" 61 #include "intel_lvds.h" 62 #include "intel_panel.h" 63 #include "intel_psr.h" 64 #include "intel_sideband.h" 65 #include "intel_tc.h" 66 #include "intel_vdsc.h" 67 68 #define DP_DPRX_ESI_LEN 14 69 70 /* DP DSC small joiner has 2 FIFOs each of 640 x 6 bytes */ 71 #define DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER 61440 72 #define DP_DSC_MIN_SUPPORTED_BPC 8 73 #define DP_DSC_MAX_SUPPORTED_BPC 10 74 75 /* DP DSC throughput values used for slice count calculations KPixels/s */ 76 #define DP_DSC_PEAK_PIXEL_RATE 2720000 77 #define DP_DSC_MAX_ENC_THROUGHPUT_0 340000 78 #define DP_DSC_MAX_ENC_THROUGHPUT_1 400000 79 80 /* DP DSC FEC Overhead factor = (100 - 2.4)/100 */ 81 #define DP_DSC_FEC_OVERHEAD_FACTOR 976 82 83 /* Compliance test status bits */ 84 #define INTEL_DP_RESOLUTION_SHIFT_MASK 0 85 #define INTEL_DP_RESOLUTION_PREFERRED (1 << INTEL_DP_RESOLUTION_SHIFT_MASK) 86 #define INTEL_DP_RESOLUTION_STANDARD (2 << INTEL_DP_RESOLUTION_SHIFT_MASK) 87 #define INTEL_DP_RESOLUTION_FAILSAFE (3 << INTEL_DP_RESOLUTION_SHIFT_MASK) 88 89 struct dp_link_dpll { 90 int clock; 91 struct dpll dpll; 92 }; 93 94 static const struct dp_link_dpll g4x_dpll[] = { 95 { 162000, 96 { .p1 = 2, .p2 = 10, .n = 2, .m1 = 23, .m2 = 8 } }, 97 { 270000, 98 { .p1 = 1, .p2 = 10, .n = 1, .m1 = 14, .m2 = 2 } } 99 }; 100 101 static const struct dp_link_dpll pch_dpll[] = { 102 { 162000, 103 { .p1 = 2, .p2 = 10, .n = 1, .m1 = 12, .m2 = 9 } }, 104 { 270000, 105 { .p1 = 1, .p2 = 10, .n = 2, .m1 = 14, .m2 = 8 } } 106 }; 107 108 static const struct dp_link_dpll vlv_dpll[] = { 109 { 162000, 110 { .p1 = 3, .p2 = 2, .n = 5, .m1 = 3, .m2 = 81 } }, 111 { 270000, 112 { .p1 = 2, .p2 = 2, .n = 1, .m1 = 2, .m2 = 27 } } 113 }; 114 115 /* 116 * CHV supports eDP 1.4 that have more link rates. 117 * Below only provides the fixed rate but exclude variable rate. 118 */ 119 static const struct dp_link_dpll chv_dpll[] = { 120 /* 121 * CHV requires to program fractional division for m2. 122 * m2 is stored in fixed point format using formula below 123 * (m2_int << 22) | m2_fraction 124 */ 125 { 162000, /* m2_int = 32, m2_fraction = 1677722 */ 126 { .p1 = 4, .p2 = 2, .n = 1, .m1 = 2, .m2 = 0x819999a } }, 127 { 270000, /* m2_int = 27, m2_fraction = 0 */ 128 { .p1 = 4, .p2 = 1, .n = 1, .m1 = 2, .m2 = 0x6c00000 } }, 129 }; 130 131 /* Constants for DP DSC configurations */ 132 static const u8 valid_dsc_bpp[] = {6, 8, 10, 12, 15}; 133 134 /* With Single pipe configuration, HW is capable of supporting maximum 135 * of 4 slices per line. 136 */ 137 static const u8 valid_dsc_slicecount[] = {1, 2, 4}; 138 139 /** 140 * intel_dp_is_edp - is the given port attached to an eDP panel (either CPU or PCH) 141 * @intel_dp: DP struct 142 * 143 * If a CPU or PCH DP output is attached to an eDP panel, this function 144 * will return true, and false otherwise. 145 */ 146 bool intel_dp_is_edp(struct intel_dp *intel_dp) 147 { 148 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 149 150 return intel_dig_port->base.type == INTEL_OUTPUT_EDP; 151 } 152 153 static struct intel_dp *intel_attached_dp(struct drm_connector *connector) 154 { 155 return enc_to_intel_dp(&intel_attached_encoder(connector)->base); 156 } 157 158 static void intel_dp_link_down(struct intel_encoder *encoder, 159 const struct intel_crtc_state *old_crtc_state); 160 static bool edp_panel_vdd_on(struct intel_dp *intel_dp); 161 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); 162 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, 163 const struct intel_crtc_state *crtc_state); 164 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, 165 enum pipe pipe); 166 static void intel_dp_unset_edid(struct intel_dp *intel_dp); 167 168 /* update sink rates from dpcd */ 169 static void intel_dp_set_sink_rates(struct intel_dp *intel_dp) 170 { 171 static const int dp_rates[] = { 172 162000, 270000, 540000, 810000 173 }; 174 int i, max_rate; 175 176 max_rate = drm_dp_bw_code_to_link_rate(intel_dp->dpcd[DP_MAX_LINK_RATE]); 177 178 for (i = 0; i < ARRAY_SIZE(dp_rates); i++) { 179 if (dp_rates[i] > max_rate) 180 break; 181 intel_dp->sink_rates[i] = dp_rates[i]; 182 } 183 184 intel_dp->num_sink_rates = i; 185 } 186 187 /* Get length of rates array potentially limited by max_rate. */ 188 static int intel_dp_rate_limit_len(const int *rates, int len, int max_rate) 189 { 190 int i; 191 192 /* Limit results by potentially reduced max rate */ 193 for (i = 0; i < len; i++) { 194 if (rates[len - i - 1] <= max_rate) 195 return len - i; 196 } 197 198 return 0; 199 } 200 201 /* Get length of common rates array potentially limited by max_rate. */ 202 static int intel_dp_common_len_rate_limit(const struct intel_dp *intel_dp, 203 int max_rate) 204 { 205 return intel_dp_rate_limit_len(intel_dp->common_rates, 206 intel_dp->num_common_rates, max_rate); 207 } 208 209 /* Theoretical max between source and sink */ 210 static int intel_dp_max_common_rate(struct intel_dp *intel_dp) 211 { 212 return intel_dp->common_rates[intel_dp->num_common_rates - 1]; 213 } 214 215 /* Theoretical max between source and sink */ 216 static int intel_dp_max_common_lane_count(struct intel_dp *intel_dp) 217 { 218 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 219 int source_max = intel_dig_port->max_lanes; 220 int sink_max = drm_dp_max_lane_count(intel_dp->dpcd); 221 int fia_max = intel_tc_port_fia_max_lane_count(intel_dig_port); 222 223 return min3(source_max, sink_max, fia_max); 224 } 225 226 int intel_dp_max_lane_count(struct intel_dp *intel_dp) 227 { 228 return intel_dp->max_link_lane_count; 229 } 230 231 int 232 intel_dp_link_required(int pixel_clock, int bpp) 233 { 234 /* pixel_clock is in kHz, divide bpp by 8 for bit to Byte conversion */ 235 return DIV_ROUND_UP(pixel_clock * bpp, 8); 236 } 237 238 int 239 intel_dp_max_data_rate(int max_link_clock, int max_lanes) 240 { 241 /* max_link_clock is the link symbol clock (LS_Clk) in kHz and not the 242 * link rate that is generally expressed in Gbps. Since, 8 bits of data 243 * is transmitted every LS_Clk per lane, there is no need to account for 244 * the channel encoding that is done in the PHY layer here. 245 */ 246 247 return max_link_clock * max_lanes; 248 } 249 250 static int 251 intel_dp_downstream_max_dotclock(struct intel_dp *intel_dp) 252 { 253 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 254 struct intel_encoder *encoder = &intel_dig_port->base; 255 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 256 int max_dotclk = dev_priv->max_dotclk_freq; 257 int ds_max_dotclk; 258 259 int type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 260 261 if (type != DP_DS_PORT_TYPE_VGA) 262 return max_dotclk; 263 264 ds_max_dotclk = drm_dp_downstream_max_clock(intel_dp->dpcd, 265 intel_dp->downstream_ports); 266 267 if (ds_max_dotclk != 0) 268 max_dotclk = min(max_dotclk, ds_max_dotclk); 269 270 return max_dotclk; 271 } 272 273 static int cnl_max_source_rate(struct intel_dp *intel_dp) 274 { 275 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 276 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 277 enum port port = dig_port->base.port; 278 279 u32 voltage = I915_READ(CNL_PORT_COMP_DW3) & VOLTAGE_INFO_MASK; 280 281 /* Low voltage SKUs are limited to max of 5.4G */ 282 if (voltage == VOLTAGE_INFO_0_85V) 283 return 540000; 284 285 /* For this SKU 8.1G is supported in all ports */ 286 if (IS_CNL_WITH_PORT_F(dev_priv)) 287 return 810000; 288 289 /* For other SKUs, max rate on ports A and D is 5.4G */ 290 if (port == PORT_A || port == PORT_D) 291 return 540000; 292 293 return 810000; 294 } 295 296 static int icl_max_source_rate(struct intel_dp *intel_dp) 297 { 298 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 299 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 300 enum phy phy = intel_port_to_phy(dev_priv, dig_port->base.port); 301 302 if (intel_phy_is_combo(dev_priv, phy) && 303 !IS_ELKHARTLAKE(dev_priv) && 304 !intel_dp_is_edp(intel_dp)) 305 return 540000; 306 307 return 810000; 308 } 309 310 static void 311 intel_dp_set_source_rates(struct intel_dp *intel_dp) 312 { 313 /* The values must be in increasing order */ 314 static const int cnl_rates[] = { 315 162000, 216000, 270000, 324000, 432000, 540000, 648000, 810000 316 }; 317 static const int bxt_rates[] = { 318 162000, 216000, 243000, 270000, 324000, 432000, 540000 319 }; 320 static const int skl_rates[] = { 321 162000, 216000, 270000, 324000, 432000, 540000 322 }; 323 static const int hsw_rates[] = { 324 162000, 270000, 540000 325 }; 326 static const int g4x_rates[] = { 327 162000, 270000 328 }; 329 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 330 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 331 const struct ddi_vbt_port_info *info = 332 &dev_priv->vbt.ddi_port_info[dig_port->base.port]; 333 const int *source_rates; 334 int size, max_rate = 0, vbt_max_rate = info->dp_max_link_rate; 335 336 /* This should only be done once */ 337 WARN_ON(intel_dp->source_rates || intel_dp->num_source_rates); 338 339 if (INTEL_GEN(dev_priv) >= 10) { 340 source_rates = cnl_rates; 341 size = ARRAY_SIZE(cnl_rates); 342 if (IS_GEN(dev_priv, 10)) 343 max_rate = cnl_max_source_rate(intel_dp); 344 else 345 max_rate = icl_max_source_rate(intel_dp); 346 } else if (IS_GEN9_LP(dev_priv)) { 347 source_rates = bxt_rates; 348 size = ARRAY_SIZE(bxt_rates); 349 } else if (IS_GEN9_BC(dev_priv)) { 350 source_rates = skl_rates; 351 size = ARRAY_SIZE(skl_rates); 352 } else if ((IS_HASWELL(dev_priv) && !IS_HSW_ULX(dev_priv)) || 353 IS_BROADWELL(dev_priv)) { 354 source_rates = hsw_rates; 355 size = ARRAY_SIZE(hsw_rates); 356 } else { 357 source_rates = g4x_rates; 358 size = ARRAY_SIZE(g4x_rates); 359 } 360 361 if (max_rate && vbt_max_rate) 362 max_rate = min(max_rate, vbt_max_rate); 363 else if (vbt_max_rate) 364 max_rate = vbt_max_rate; 365 366 if (max_rate) 367 size = intel_dp_rate_limit_len(source_rates, size, max_rate); 368 369 intel_dp->source_rates = source_rates; 370 intel_dp->num_source_rates = size; 371 } 372 373 static int intersect_rates(const int *source_rates, int source_len, 374 const int *sink_rates, int sink_len, 375 int *common_rates) 376 { 377 int i = 0, j = 0, k = 0; 378 379 while (i < source_len && j < sink_len) { 380 if (source_rates[i] == sink_rates[j]) { 381 if (WARN_ON(k >= DP_MAX_SUPPORTED_RATES)) 382 return k; 383 common_rates[k] = source_rates[i]; 384 ++k; 385 ++i; 386 ++j; 387 } else if (source_rates[i] < sink_rates[j]) { 388 ++i; 389 } else { 390 ++j; 391 } 392 } 393 return k; 394 } 395 396 /* return index of rate in rates array, or -1 if not found */ 397 static int intel_dp_rate_index(const int *rates, int len, int rate) 398 { 399 int i; 400 401 for (i = 0; i < len; i++) 402 if (rate == rates[i]) 403 return i; 404 405 return -1; 406 } 407 408 static void intel_dp_set_common_rates(struct intel_dp *intel_dp) 409 { 410 WARN_ON(!intel_dp->num_source_rates || !intel_dp->num_sink_rates); 411 412 intel_dp->num_common_rates = intersect_rates(intel_dp->source_rates, 413 intel_dp->num_source_rates, 414 intel_dp->sink_rates, 415 intel_dp->num_sink_rates, 416 intel_dp->common_rates); 417 418 /* Paranoia, there should always be something in common. */ 419 if (WARN_ON(intel_dp->num_common_rates == 0)) { 420 intel_dp->common_rates[0] = 162000; 421 intel_dp->num_common_rates = 1; 422 } 423 } 424 425 static bool intel_dp_link_params_valid(struct intel_dp *intel_dp, int link_rate, 426 u8 lane_count) 427 { 428 /* 429 * FIXME: we need to synchronize the current link parameters with 430 * hardware readout. Currently fast link training doesn't work on 431 * boot-up. 432 */ 433 if (link_rate == 0 || 434 link_rate > intel_dp->max_link_rate) 435 return false; 436 437 if (lane_count == 0 || 438 lane_count > intel_dp_max_lane_count(intel_dp)) 439 return false; 440 441 return true; 442 } 443 444 static bool intel_dp_can_link_train_fallback_for_edp(struct intel_dp *intel_dp, 445 int link_rate, 446 u8 lane_count) 447 { 448 const struct drm_display_mode *fixed_mode = 449 intel_dp->attached_connector->panel.fixed_mode; 450 int mode_rate, max_rate; 451 452 mode_rate = intel_dp_link_required(fixed_mode->clock, 18); 453 max_rate = intel_dp_max_data_rate(link_rate, lane_count); 454 if (mode_rate > max_rate) 455 return false; 456 457 return true; 458 } 459 460 int intel_dp_get_link_train_fallback_values(struct intel_dp *intel_dp, 461 int link_rate, u8 lane_count) 462 { 463 int index; 464 465 index = intel_dp_rate_index(intel_dp->common_rates, 466 intel_dp->num_common_rates, 467 link_rate); 468 if (index > 0) { 469 if (intel_dp_is_edp(intel_dp) && 470 !intel_dp_can_link_train_fallback_for_edp(intel_dp, 471 intel_dp->common_rates[index - 1], 472 lane_count)) { 473 DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n"); 474 return 0; 475 } 476 intel_dp->max_link_rate = intel_dp->common_rates[index - 1]; 477 intel_dp->max_link_lane_count = lane_count; 478 } else if (lane_count > 1) { 479 if (intel_dp_is_edp(intel_dp) && 480 !intel_dp_can_link_train_fallback_for_edp(intel_dp, 481 intel_dp_max_common_rate(intel_dp), 482 lane_count >> 1)) { 483 DRM_DEBUG_KMS("Retrying Link training for eDP with same parameters\n"); 484 return 0; 485 } 486 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); 487 intel_dp->max_link_lane_count = lane_count >> 1; 488 } else { 489 DRM_ERROR("Link Training Unsuccessful\n"); 490 return -1; 491 } 492 493 return 0; 494 } 495 496 static enum drm_mode_status 497 intel_dp_mode_valid(struct drm_connector *connector, 498 struct drm_display_mode *mode) 499 { 500 struct intel_dp *intel_dp = intel_attached_dp(connector); 501 struct intel_connector *intel_connector = to_intel_connector(connector); 502 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; 503 struct drm_i915_private *dev_priv = to_i915(connector->dev); 504 int target_clock = mode->clock; 505 int max_rate, mode_rate, max_lanes, max_link_clock; 506 int max_dotclk; 507 u16 dsc_max_output_bpp = 0; 508 u8 dsc_slice_count = 0; 509 510 if (mode->flags & DRM_MODE_FLAG_DBLSCAN) 511 return MODE_NO_DBLESCAN; 512 513 max_dotclk = intel_dp_downstream_max_dotclock(intel_dp); 514 515 if (intel_dp_is_edp(intel_dp) && fixed_mode) { 516 if (mode->hdisplay > fixed_mode->hdisplay) 517 return MODE_PANEL; 518 519 if (mode->vdisplay > fixed_mode->vdisplay) 520 return MODE_PANEL; 521 522 target_clock = fixed_mode->clock; 523 } 524 525 max_link_clock = intel_dp_max_link_rate(intel_dp); 526 max_lanes = intel_dp_max_lane_count(intel_dp); 527 528 max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); 529 mode_rate = intel_dp_link_required(target_clock, 18); 530 531 /* 532 * Output bpp is stored in 6.4 format so right shift by 4 to get the 533 * integer value since we support only integer values of bpp. 534 */ 535 if ((INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) && 536 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { 537 if (intel_dp_is_edp(intel_dp)) { 538 dsc_max_output_bpp = 539 drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4; 540 dsc_slice_count = 541 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, 542 true); 543 } else if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { 544 dsc_max_output_bpp = 545 intel_dp_dsc_get_output_bpp(max_link_clock, 546 max_lanes, 547 target_clock, 548 mode->hdisplay) >> 4; 549 dsc_slice_count = 550 intel_dp_dsc_get_slice_count(intel_dp, 551 target_clock, 552 mode->hdisplay); 553 } 554 } 555 556 if ((mode_rate > max_rate && !(dsc_max_output_bpp && dsc_slice_count)) || 557 target_clock > max_dotclk) 558 return MODE_CLOCK_HIGH; 559 560 if (mode->clock < 10000) 561 return MODE_CLOCK_LOW; 562 563 if (mode->flags & DRM_MODE_FLAG_DBLCLK) 564 return MODE_H_ILLEGAL; 565 566 return MODE_OK; 567 } 568 569 u32 intel_dp_pack_aux(const u8 *src, int src_bytes) 570 { 571 int i; 572 u32 v = 0; 573 574 if (src_bytes > 4) 575 src_bytes = 4; 576 for (i = 0; i < src_bytes; i++) 577 v |= ((u32)src[i]) << ((3 - i) * 8); 578 return v; 579 } 580 581 static void intel_dp_unpack_aux(u32 src, u8 *dst, int dst_bytes) 582 { 583 int i; 584 if (dst_bytes > 4) 585 dst_bytes = 4; 586 for (i = 0; i < dst_bytes; i++) 587 dst[i] = src >> ((3-i) * 8); 588 } 589 590 static void 591 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp); 592 static void 593 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, 594 bool force_disable_vdd); 595 static void 596 intel_dp_pps_init(struct intel_dp *intel_dp); 597 598 static intel_wakeref_t 599 pps_lock(struct intel_dp *intel_dp) 600 { 601 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 602 intel_wakeref_t wakeref; 603 604 /* 605 * See intel_power_sequencer_reset() why we need 606 * a power domain reference here. 607 */ 608 wakeref = intel_display_power_get(dev_priv, 609 intel_aux_power_domain(dp_to_dig_port(intel_dp))); 610 611 mutex_lock(&dev_priv->pps_mutex); 612 613 return wakeref; 614 } 615 616 static intel_wakeref_t 617 pps_unlock(struct intel_dp *intel_dp, intel_wakeref_t wakeref) 618 { 619 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 620 621 mutex_unlock(&dev_priv->pps_mutex); 622 intel_display_power_put(dev_priv, 623 intel_aux_power_domain(dp_to_dig_port(intel_dp)), 624 wakeref); 625 return 0; 626 } 627 628 #define with_pps_lock(dp, wf) \ 629 for ((wf) = pps_lock(dp); (wf); (wf) = pps_unlock((dp), (wf))) 630 631 static void 632 vlv_power_sequencer_kick(struct intel_dp *intel_dp) 633 { 634 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 635 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 636 enum pipe pipe = intel_dp->pps_pipe; 637 bool pll_enabled, release_cl_override = false; 638 enum dpio_phy phy = DPIO_PHY(pipe); 639 enum dpio_channel ch = vlv_pipe_to_channel(pipe); 640 u32 DP; 641 642 if (WARN(I915_READ(intel_dp->output_reg) & DP_PORT_EN, 643 "skipping pipe %c power sequencer kick due to port %c being active\n", 644 pipe_name(pipe), port_name(intel_dig_port->base.port))) 645 return; 646 647 DRM_DEBUG_KMS("kicking pipe %c power sequencer for port %c\n", 648 pipe_name(pipe), port_name(intel_dig_port->base.port)); 649 650 /* Preserve the BIOS-computed detected bit. This is 651 * supposed to be read-only. 652 */ 653 DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 654 DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 655 DP |= DP_PORT_WIDTH(1); 656 DP |= DP_LINK_TRAIN_PAT_1; 657 658 if (IS_CHERRYVIEW(dev_priv)) 659 DP |= DP_PIPE_SEL_CHV(pipe); 660 else 661 DP |= DP_PIPE_SEL(pipe); 662 663 pll_enabled = I915_READ(DPLL(pipe)) & DPLL_VCO_ENABLE; 664 665 /* 666 * The DPLL for the pipe must be enabled for this to work. 667 * So enable temporarily it if it's not already enabled. 668 */ 669 if (!pll_enabled) { 670 release_cl_override = IS_CHERRYVIEW(dev_priv) && 671 !chv_phy_powergate_ch(dev_priv, phy, ch, true); 672 673 if (vlv_force_pll_on(dev_priv, pipe, IS_CHERRYVIEW(dev_priv) ? 674 &chv_dpll[0].dpll : &vlv_dpll[0].dpll)) { 675 DRM_ERROR("Failed to force on pll for pipe %c!\n", 676 pipe_name(pipe)); 677 return; 678 } 679 } 680 681 /* 682 * Similar magic as in intel_dp_enable_port(). 683 * We _must_ do this port enable + disable trick 684 * to make this power sequencer lock onto the port. 685 * Otherwise even VDD force bit won't work. 686 */ 687 I915_WRITE(intel_dp->output_reg, DP); 688 POSTING_READ(intel_dp->output_reg); 689 690 I915_WRITE(intel_dp->output_reg, DP | DP_PORT_EN); 691 POSTING_READ(intel_dp->output_reg); 692 693 I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); 694 POSTING_READ(intel_dp->output_reg); 695 696 if (!pll_enabled) { 697 vlv_force_pll_off(dev_priv, pipe); 698 699 if (release_cl_override) 700 chv_phy_powergate_ch(dev_priv, phy, ch, false); 701 } 702 } 703 704 static enum pipe vlv_find_free_pps(struct drm_i915_private *dev_priv) 705 { 706 struct intel_encoder *encoder; 707 unsigned int pipes = (1 << PIPE_A) | (1 << PIPE_B); 708 709 /* 710 * We don't have power sequencer currently. 711 * Pick one that's not used by other ports. 712 */ 713 for_each_intel_dp(&dev_priv->drm, encoder) { 714 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 715 716 if (encoder->type == INTEL_OUTPUT_EDP) { 717 WARN_ON(intel_dp->active_pipe != INVALID_PIPE && 718 intel_dp->active_pipe != intel_dp->pps_pipe); 719 720 if (intel_dp->pps_pipe != INVALID_PIPE) 721 pipes &= ~(1 << intel_dp->pps_pipe); 722 } else { 723 WARN_ON(intel_dp->pps_pipe != INVALID_PIPE); 724 725 if (intel_dp->active_pipe != INVALID_PIPE) 726 pipes &= ~(1 << intel_dp->active_pipe); 727 } 728 } 729 730 if (pipes == 0) 731 return INVALID_PIPE; 732 733 return ffs(pipes) - 1; 734 } 735 736 static enum pipe 737 vlv_power_sequencer_pipe(struct intel_dp *intel_dp) 738 { 739 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 740 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 741 enum pipe pipe; 742 743 lockdep_assert_held(&dev_priv->pps_mutex); 744 745 /* We should never land here with regular DP ports */ 746 WARN_ON(!intel_dp_is_edp(intel_dp)); 747 748 WARN_ON(intel_dp->active_pipe != INVALID_PIPE && 749 intel_dp->active_pipe != intel_dp->pps_pipe); 750 751 if (intel_dp->pps_pipe != INVALID_PIPE) 752 return intel_dp->pps_pipe; 753 754 pipe = vlv_find_free_pps(dev_priv); 755 756 /* 757 * Didn't find one. This should not happen since there 758 * are two power sequencers and up to two eDP ports. 759 */ 760 if (WARN_ON(pipe == INVALID_PIPE)) 761 pipe = PIPE_A; 762 763 vlv_steal_power_sequencer(dev_priv, pipe); 764 intel_dp->pps_pipe = pipe; 765 766 DRM_DEBUG_KMS("picked pipe %c power sequencer for port %c\n", 767 pipe_name(intel_dp->pps_pipe), 768 port_name(intel_dig_port->base.port)); 769 770 /* init power sequencer on this pipe and port */ 771 intel_dp_init_panel_power_sequencer(intel_dp); 772 intel_dp_init_panel_power_sequencer_registers(intel_dp, true); 773 774 /* 775 * Even vdd force doesn't work until we've made 776 * the power sequencer lock in on the port. 777 */ 778 vlv_power_sequencer_kick(intel_dp); 779 780 return intel_dp->pps_pipe; 781 } 782 783 static int 784 bxt_power_sequencer_idx(struct intel_dp *intel_dp) 785 { 786 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 787 int backlight_controller = dev_priv->vbt.backlight.controller; 788 789 lockdep_assert_held(&dev_priv->pps_mutex); 790 791 /* We should never land here with regular DP ports */ 792 WARN_ON(!intel_dp_is_edp(intel_dp)); 793 794 if (!intel_dp->pps_reset) 795 return backlight_controller; 796 797 intel_dp->pps_reset = false; 798 799 /* 800 * Only the HW needs to be reprogrammed, the SW state is fixed and 801 * has been setup during connector init. 802 */ 803 intel_dp_init_panel_power_sequencer_registers(intel_dp, false); 804 805 return backlight_controller; 806 } 807 808 typedef bool (*vlv_pipe_check)(struct drm_i915_private *dev_priv, 809 enum pipe pipe); 810 811 static bool vlv_pipe_has_pp_on(struct drm_i915_private *dev_priv, 812 enum pipe pipe) 813 { 814 return I915_READ(PP_STATUS(pipe)) & PP_ON; 815 } 816 817 static bool vlv_pipe_has_vdd_on(struct drm_i915_private *dev_priv, 818 enum pipe pipe) 819 { 820 return I915_READ(PP_CONTROL(pipe)) & EDP_FORCE_VDD; 821 } 822 823 static bool vlv_pipe_any(struct drm_i915_private *dev_priv, 824 enum pipe pipe) 825 { 826 return true; 827 } 828 829 static enum pipe 830 vlv_initial_pps_pipe(struct drm_i915_private *dev_priv, 831 enum port port, 832 vlv_pipe_check pipe_check) 833 { 834 enum pipe pipe; 835 836 for (pipe = PIPE_A; pipe <= PIPE_B; pipe++) { 837 u32 port_sel = I915_READ(PP_ON_DELAYS(pipe)) & 838 PANEL_PORT_SELECT_MASK; 839 840 if (port_sel != PANEL_PORT_SELECT_VLV(port)) 841 continue; 842 843 if (!pipe_check(dev_priv, pipe)) 844 continue; 845 846 return pipe; 847 } 848 849 return INVALID_PIPE; 850 } 851 852 static void 853 vlv_initial_power_sequencer_setup(struct intel_dp *intel_dp) 854 { 855 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 856 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 857 enum port port = intel_dig_port->base.port; 858 859 lockdep_assert_held(&dev_priv->pps_mutex); 860 861 /* try to find a pipe with this port selected */ 862 /* first pick one where the panel is on */ 863 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, 864 vlv_pipe_has_pp_on); 865 /* didn't find one? pick one where vdd is on */ 866 if (intel_dp->pps_pipe == INVALID_PIPE) 867 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, 868 vlv_pipe_has_vdd_on); 869 /* didn't find one? pick one with just the correct port */ 870 if (intel_dp->pps_pipe == INVALID_PIPE) 871 intel_dp->pps_pipe = vlv_initial_pps_pipe(dev_priv, port, 872 vlv_pipe_any); 873 874 /* didn't find one? just let vlv_power_sequencer_pipe() pick one when needed */ 875 if (intel_dp->pps_pipe == INVALID_PIPE) { 876 DRM_DEBUG_KMS("no initial power sequencer for port %c\n", 877 port_name(port)); 878 return; 879 } 880 881 DRM_DEBUG_KMS("initial power sequencer for port %c: pipe %c\n", 882 port_name(port), pipe_name(intel_dp->pps_pipe)); 883 884 intel_dp_init_panel_power_sequencer(intel_dp); 885 intel_dp_init_panel_power_sequencer_registers(intel_dp, false); 886 } 887 888 void intel_power_sequencer_reset(struct drm_i915_private *dev_priv) 889 { 890 struct intel_encoder *encoder; 891 892 if (WARN_ON(!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && 893 !IS_GEN9_LP(dev_priv))) 894 return; 895 896 /* 897 * We can't grab pps_mutex here due to deadlock with power_domain 898 * mutex when power_domain functions are called while holding pps_mutex. 899 * That also means that in order to use pps_pipe the code needs to 900 * hold both a power domain reference and pps_mutex, and the power domain 901 * reference get/put must be done while _not_ holding pps_mutex. 902 * pps_{lock,unlock}() do these steps in the correct order, so one 903 * should use them always. 904 */ 905 906 for_each_intel_dp(&dev_priv->drm, encoder) { 907 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 908 909 WARN_ON(intel_dp->active_pipe != INVALID_PIPE); 910 911 if (encoder->type != INTEL_OUTPUT_EDP) 912 continue; 913 914 if (IS_GEN9_LP(dev_priv)) 915 intel_dp->pps_reset = true; 916 else 917 intel_dp->pps_pipe = INVALID_PIPE; 918 } 919 } 920 921 struct pps_registers { 922 i915_reg_t pp_ctrl; 923 i915_reg_t pp_stat; 924 i915_reg_t pp_on; 925 i915_reg_t pp_off; 926 i915_reg_t pp_div; 927 }; 928 929 static void intel_pps_get_registers(struct intel_dp *intel_dp, 930 struct pps_registers *regs) 931 { 932 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 933 int pps_idx = 0; 934 935 memset(regs, 0, sizeof(*regs)); 936 937 if (IS_GEN9_LP(dev_priv)) 938 pps_idx = bxt_power_sequencer_idx(intel_dp); 939 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 940 pps_idx = vlv_power_sequencer_pipe(intel_dp); 941 942 regs->pp_ctrl = PP_CONTROL(pps_idx); 943 regs->pp_stat = PP_STATUS(pps_idx); 944 regs->pp_on = PP_ON_DELAYS(pps_idx); 945 regs->pp_off = PP_OFF_DELAYS(pps_idx); 946 947 /* Cycle delay moved from PP_DIVISOR to PP_CONTROL */ 948 if (IS_GEN9_LP(dev_priv) || INTEL_PCH_TYPE(dev_priv) >= PCH_CNP) 949 regs->pp_div = INVALID_MMIO_REG; 950 else 951 regs->pp_div = PP_DIVISOR(pps_idx); 952 } 953 954 static i915_reg_t 955 _pp_ctrl_reg(struct intel_dp *intel_dp) 956 { 957 struct pps_registers regs; 958 959 intel_pps_get_registers(intel_dp, ®s); 960 961 return regs.pp_ctrl; 962 } 963 964 static i915_reg_t 965 _pp_stat_reg(struct intel_dp *intel_dp) 966 { 967 struct pps_registers regs; 968 969 intel_pps_get_registers(intel_dp, ®s); 970 971 return regs.pp_stat; 972 } 973 974 /* Reboot notifier handler to shutdown panel power to guarantee T12 timing 975 This function only applicable when panel PM state is not to be tracked */ 976 static int edp_notify_handler(struct notifier_block *this, unsigned long code, 977 void *unused) 978 { 979 struct intel_dp *intel_dp = container_of(this, typeof(* intel_dp), 980 edp_notifier); 981 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 982 intel_wakeref_t wakeref; 983 984 if (!intel_dp_is_edp(intel_dp) || code != SYS_RESTART) 985 return 0; 986 987 with_pps_lock(intel_dp, wakeref) { 988 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 989 enum pipe pipe = vlv_power_sequencer_pipe(intel_dp); 990 i915_reg_t pp_ctrl_reg, pp_div_reg; 991 u32 pp_div; 992 993 pp_ctrl_reg = PP_CONTROL(pipe); 994 pp_div_reg = PP_DIVISOR(pipe); 995 pp_div = I915_READ(pp_div_reg); 996 pp_div &= PP_REFERENCE_DIVIDER_MASK; 997 998 /* 0x1F write to PP_DIV_REG sets max cycle delay */ 999 I915_WRITE(pp_div_reg, pp_div | 0x1F); 1000 I915_WRITE(pp_ctrl_reg, PANEL_UNLOCK_REGS); 1001 msleep(intel_dp->panel_power_cycle_delay); 1002 } 1003 } 1004 1005 return 0; 1006 } 1007 1008 static bool edp_have_panel_power(struct intel_dp *intel_dp) 1009 { 1010 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1011 1012 lockdep_assert_held(&dev_priv->pps_mutex); 1013 1014 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1015 intel_dp->pps_pipe == INVALID_PIPE) 1016 return false; 1017 1018 return (I915_READ(_pp_stat_reg(intel_dp)) & PP_ON) != 0; 1019 } 1020 1021 static bool edp_have_panel_vdd(struct intel_dp *intel_dp) 1022 { 1023 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1024 1025 lockdep_assert_held(&dev_priv->pps_mutex); 1026 1027 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 1028 intel_dp->pps_pipe == INVALID_PIPE) 1029 return false; 1030 1031 return I915_READ(_pp_ctrl_reg(intel_dp)) & EDP_FORCE_VDD; 1032 } 1033 1034 static void 1035 intel_dp_check_edp(struct intel_dp *intel_dp) 1036 { 1037 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1038 1039 if (!intel_dp_is_edp(intel_dp)) 1040 return; 1041 1042 if (!edp_have_panel_power(intel_dp) && !edp_have_panel_vdd(intel_dp)) { 1043 WARN(1, "eDP powered off while attempting aux channel communication.\n"); 1044 DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", 1045 I915_READ(_pp_stat_reg(intel_dp)), 1046 I915_READ(_pp_ctrl_reg(intel_dp))); 1047 } 1048 } 1049 1050 static u32 1051 intel_dp_aux_wait_done(struct intel_dp *intel_dp) 1052 { 1053 struct drm_i915_private *i915 = dp_to_i915(intel_dp); 1054 i915_reg_t ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 1055 u32 status; 1056 bool done; 1057 1058 #define C (((status = intel_uncore_read_notrace(&i915->uncore, ch_ctl)) & DP_AUX_CH_CTL_SEND_BUSY) == 0) 1059 done = wait_event_timeout(i915->gmbus_wait_queue, C, 1060 msecs_to_jiffies_timeout(10)); 1061 1062 /* just trace the final value */ 1063 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); 1064 1065 if (!done) 1066 DRM_ERROR("dp aux hw did not signal timeout!\n"); 1067 #undef C 1068 1069 return status; 1070 } 1071 1072 static u32 g4x_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 1073 { 1074 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1075 1076 if (index) 1077 return 0; 1078 1079 /* 1080 * The clock divider is based off the hrawclk, and would like to run at 1081 * 2MHz. So, take the hrawclk value and divide by 2000 and use that 1082 */ 1083 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); 1084 } 1085 1086 static u32 ilk_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 1087 { 1088 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1089 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1090 1091 if (index) 1092 return 0; 1093 1094 /* 1095 * The clock divider is based off the cdclk or PCH rawclk, and would 1096 * like to run at 2MHz. So, take the cdclk or PCH rawclk value and 1097 * divide by 2000 and use that 1098 */ 1099 if (dig_port->aux_ch == AUX_CH_A) 1100 return DIV_ROUND_CLOSEST(dev_priv->cdclk.hw.cdclk, 2000); 1101 else 1102 return DIV_ROUND_CLOSEST(dev_priv->rawclk_freq, 2000); 1103 } 1104 1105 static u32 hsw_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 1106 { 1107 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1108 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1109 1110 if (dig_port->aux_ch != AUX_CH_A && HAS_PCH_LPT_H(dev_priv)) { 1111 /* Workaround for non-ULT HSW */ 1112 switch (index) { 1113 case 0: return 63; 1114 case 1: return 72; 1115 default: return 0; 1116 } 1117 } 1118 1119 return ilk_get_aux_clock_divider(intel_dp, index); 1120 } 1121 1122 static u32 skl_get_aux_clock_divider(struct intel_dp *intel_dp, int index) 1123 { 1124 /* 1125 * SKL doesn't need us to program the AUX clock divider (Hardware will 1126 * derive the clock from CDCLK automatically). We still implement the 1127 * get_aux_clock_divider vfunc to plug-in into the existing code. 1128 */ 1129 return index ? 0 : 1; 1130 } 1131 1132 static u32 g4x_get_aux_send_ctl(struct intel_dp *intel_dp, 1133 int send_bytes, 1134 u32 aux_clock_divider) 1135 { 1136 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1137 struct drm_i915_private *dev_priv = 1138 to_i915(intel_dig_port->base.base.dev); 1139 u32 precharge, timeout; 1140 1141 if (IS_GEN(dev_priv, 6)) 1142 precharge = 3; 1143 else 1144 precharge = 5; 1145 1146 if (IS_BROADWELL(dev_priv)) 1147 timeout = DP_AUX_CH_CTL_TIME_OUT_600us; 1148 else 1149 timeout = DP_AUX_CH_CTL_TIME_OUT_400us; 1150 1151 return DP_AUX_CH_CTL_SEND_BUSY | 1152 DP_AUX_CH_CTL_DONE | 1153 DP_AUX_CH_CTL_INTERRUPT | 1154 DP_AUX_CH_CTL_TIME_OUT_ERROR | 1155 timeout | 1156 DP_AUX_CH_CTL_RECEIVE_ERROR | 1157 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 1158 (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | 1159 (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT); 1160 } 1161 1162 static u32 skl_get_aux_send_ctl(struct intel_dp *intel_dp, 1163 int send_bytes, 1164 u32 unused) 1165 { 1166 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1167 u32 ret; 1168 1169 ret = DP_AUX_CH_CTL_SEND_BUSY | 1170 DP_AUX_CH_CTL_DONE | 1171 DP_AUX_CH_CTL_INTERRUPT | 1172 DP_AUX_CH_CTL_TIME_OUT_ERROR | 1173 DP_AUX_CH_CTL_TIME_OUT_MAX | 1174 DP_AUX_CH_CTL_RECEIVE_ERROR | 1175 (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | 1176 DP_AUX_CH_CTL_FW_SYNC_PULSE_SKL(32) | 1177 DP_AUX_CH_CTL_SYNC_PULSE_SKL(32); 1178 1179 if (intel_dig_port->tc_mode == TC_PORT_TBT_ALT) 1180 ret |= DP_AUX_CH_CTL_TBT_IO; 1181 1182 return ret; 1183 } 1184 1185 static int 1186 intel_dp_aux_xfer(struct intel_dp *intel_dp, 1187 const u8 *send, int send_bytes, 1188 u8 *recv, int recv_size, 1189 u32 aux_send_ctl_flags) 1190 { 1191 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 1192 struct drm_i915_private *i915 = 1193 to_i915(intel_dig_port->base.base.dev); 1194 struct intel_uncore *uncore = &i915->uncore; 1195 enum phy phy = intel_port_to_phy(i915, intel_dig_port->base.port); 1196 bool is_tc_port = intel_phy_is_tc(i915, phy); 1197 i915_reg_t ch_ctl, ch_data[5]; 1198 u32 aux_clock_divider; 1199 enum intel_display_power_domain aux_domain = 1200 intel_aux_power_domain(intel_dig_port); 1201 intel_wakeref_t aux_wakeref; 1202 intel_wakeref_t pps_wakeref; 1203 int i, ret, recv_bytes; 1204 int try, clock = 0; 1205 u32 status; 1206 bool vdd; 1207 1208 ch_ctl = intel_dp->aux_ch_ctl_reg(intel_dp); 1209 for (i = 0; i < ARRAY_SIZE(ch_data); i++) 1210 ch_data[i] = intel_dp->aux_ch_data_reg(intel_dp, i); 1211 1212 if (is_tc_port) 1213 intel_tc_port_lock(intel_dig_port); 1214 1215 aux_wakeref = intel_display_power_get(i915, aux_domain); 1216 pps_wakeref = pps_lock(intel_dp); 1217 1218 /* 1219 * We will be called with VDD already enabled for dpcd/edid/oui reads. 1220 * In such cases we want to leave VDD enabled and it's up to upper layers 1221 * to turn it off. But for eg. i2c-dev access we need to turn it on/off 1222 * ourselves. 1223 */ 1224 vdd = edp_panel_vdd_on(intel_dp); 1225 1226 /* dp aux is extremely sensitive to irq latency, hence request the 1227 * lowest possible wakeup latency and so prevent the cpu from going into 1228 * deep sleep states. 1229 */ 1230 pm_qos_update_request(&i915->pm_qos, 0); 1231 1232 intel_dp_check_edp(intel_dp); 1233 1234 /* Try to wait for any previous AUX channel activity */ 1235 for (try = 0; try < 3; try++) { 1236 status = intel_uncore_read_notrace(uncore, ch_ctl); 1237 if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) 1238 break; 1239 msleep(1); 1240 } 1241 /* just trace the final value */ 1242 trace_i915_reg_rw(false, ch_ctl, status, sizeof(status), true); 1243 1244 if (try == 3) { 1245 static u32 last_status = -1; 1246 const u32 status = intel_uncore_read(uncore, ch_ctl); 1247 1248 if (status != last_status) { 1249 WARN(1, "dp_aux_ch not started status 0x%08x\n", 1250 status); 1251 last_status = status; 1252 } 1253 1254 ret = -EBUSY; 1255 goto out; 1256 } 1257 1258 /* Only 5 data registers! */ 1259 if (WARN_ON(send_bytes > 20 || recv_size > 20)) { 1260 ret = -E2BIG; 1261 goto out; 1262 } 1263 1264 while ((aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, clock++))) { 1265 u32 send_ctl = intel_dp->get_aux_send_ctl(intel_dp, 1266 send_bytes, 1267 aux_clock_divider); 1268 1269 send_ctl |= aux_send_ctl_flags; 1270 1271 /* Must try at least 3 times according to DP spec */ 1272 for (try = 0; try < 5; try++) { 1273 /* Load the send data into the aux channel data registers */ 1274 for (i = 0; i < send_bytes; i += 4) 1275 intel_uncore_write(uncore, 1276 ch_data[i >> 2], 1277 intel_dp_pack_aux(send + i, 1278 send_bytes - i)); 1279 1280 /* Send the command and wait for it to complete */ 1281 intel_uncore_write(uncore, ch_ctl, send_ctl); 1282 1283 status = intel_dp_aux_wait_done(intel_dp); 1284 1285 /* Clear done status and any errors */ 1286 intel_uncore_write(uncore, 1287 ch_ctl, 1288 status | 1289 DP_AUX_CH_CTL_DONE | 1290 DP_AUX_CH_CTL_TIME_OUT_ERROR | 1291 DP_AUX_CH_CTL_RECEIVE_ERROR); 1292 1293 /* DP CTS 1.2 Core Rev 1.1, 4.2.1.1 & 4.2.1.2 1294 * 400us delay required for errors and timeouts 1295 * Timeout errors from the HW already meet this 1296 * requirement so skip to next iteration 1297 */ 1298 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) 1299 continue; 1300 1301 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 1302 usleep_range(400, 500); 1303 continue; 1304 } 1305 if (status & DP_AUX_CH_CTL_DONE) 1306 goto done; 1307 } 1308 } 1309 1310 if ((status & DP_AUX_CH_CTL_DONE) == 0) { 1311 DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); 1312 ret = -EBUSY; 1313 goto out; 1314 } 1315 1316 done: 1317 /* Check for timeout or receive error. 1318 * Timeouts occur when the sink is not connected 1319 */ 1320 if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { 1321 DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); 1322 ret = -EIO; 1323 goto out; 1324 } 1325 1326 /* Timeouts occur when the device isn't connected, so they're 1327 * "normal" -- don't fill the kernel log with these */ 1328 if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { 1329 DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); 1330 ret = -ETIMEDOUT; 1331 goto out; 1332 } 1333 1334 /* Unload any bytes sent back from the other side */ 1335 recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> 1336 DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); 1337 1338 /* 1339 * By BSpec: "Message sizes of 0 or >20 are not allowed." 1340 * We have no idea of what happened so we return -EBUSY so 1341 * drm layer takes care for the necessary retries. 1342 */ 1343 if (recv_bytes == 0 || recv_bytes > 20) { 1344 DRM_DEBUG_KMS("Forbidden recv_bytes = %d on aux transaction\n", 1345 recv_bytes); 1346 ret = -EBUSY; 1347 goto out; 1348 } 1349 1350 if (recv_bytes > recv_size) 1351 recv_bytes = recv_size; 1352 1353 for (i = 0; i < recv_bytes; i += 4) 1354 intel_dp_unpack_aux(intel_uncore_read(uncore, ch_data[i >> 2]), 1355 recv + i, recv_bytes - i); 1356 1357 ret = recv_bytes; 1358 out: 1359 pm_qos_update_request(&i915->pm_qos, PM_QOS_DEFAULT_VALUE); 1360 1361 if (vdd) 1362 edp_panel_vdd_off(intel_dp, false); 1363 1364 pps_unlock(intel_dp, pps_wakeref); 1365 intel_display_power_put_async(i915, aux_domain, aux_wakeref); 1366 1367 if (is_tc_port) 1368 intel_tc_port_unlock(intel_dig_port); 1369 1370 return ret; 1371 } 1372 1373 #define BARE_ADDRESS_SIZE 3 1374 #define HEADER_SIZE (BARE_ADDRESS_SIZE + 1) 1375 1376 static void 1377 intel_dp_aux_header(u8 txbuf[HEADER_SIZE], 1378 const struct drm_dp_aux_msg *msg) 1379 { 1380 txbuf[0] = (msg->request << 4) | ((msg->address >> 16) & 0xf); 1381 txbuf[1] = (msg->address >> 8) & 0xff; 1382 txbuf[2] = msg->address & 0xff; 1383 txbuf[3] = msg->size - 1; 1384 } 1385 1386 static ssize_t 1387 intel_dp_aux_transfer(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg) 1388 { 1389 struct intel_dp *intel_dp = container_of(aux, struct intel_dp, aux); 1390 u8 txbuf[20], rxbuf[20]; 1391 size_t txsize, rxsize; 1392 int ret; 1393 1394 intel_dp_aux_header(txbuf, msg); 1395 1396 switch (msg->request & ~DP_AUX_I2C_MOT) { 1397 case DP_AUX_NATIVE_WRITE: 1398 case DP_AUX_I2C_WRITE: 1399 case DP_AUX_I2C_WRITE_STATUS_UPDATE: 1400 txsize = msg->size ? HEADER_SIZE + msg->size : BARE_ADDRESS_SIZE; 1401 rxsize = 2; /* 0 or 1 data bytes */ 1402 1403 if (WARN_ON(txsize > 20)) 1404 return -E2BIG; 1405 1406 WARN_ON(!msg->buffer != !msg->size); 1407 1408 if (msg->buffer) 1409 memcpy(txbuf + HEADER_SIZE, msg->buffer, msg->size); 1410 1411 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 1412 rxbuf, rxsize, 0); 1413 if (ret > 0) { 1414 msg->reply = rxbuf[0] >> 4; 1415 1416 if (ret > 1) { 1417 /* Number of bytes written in a short write. */ 1418 ret = clamp_t(int, rxbuf[1], 0, msg->size); 1419 } else { 1420 /* Return payload size. */ 1421 ret = msg->size; 1422 } 1423 } 1424 break; 1425 1426 case DP_AUX_NATIVE_READ: 1427 case DP_AUX_I2C_READ: 1428 txsize = msg->size ? HEADER_SIZE : BARE_ADDRESS_SIZE; 1429 rxsize = msg->size + 1; 1430 1431 if (WARN_ON(rxsize > 20)) 1432 return -E2BIG; 1433 1434 ret = intel_dp_aux_xfer(intel_dp, txbuf, txsize, 1435 rxbuf, rxsize, 0); 1436 if (ret > 0) { 1437 msg->reply = rxbuf[0] >> 4; 1438 /* 1439 * Assume happy day, and copy the data. The caller is 1440 * expected to check msg->reply before touching it. 1441 * 1442 * Return payload size. 1443 */ 1444 ret--; 1445 memcpy(msg->buffer, rxbuf + 1, ret); 1446 } 1447 break; 1448 1449 default: 1450 ret = -EINVAL; 1451 break; 1452 } 1453 1454 return ret; 1455 } 1456 1457 1458 static i915_reg_t g4x_aux_ctl_reg(struct intel_dp *intel_dp) 1459 { 1460 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1461 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1462 enum aux_ch aux_ch = dig_port->aux_ch; 1463 1464 switch (aux_ch) { 1465 case AUX_CH_B: 1466 case AUX_CH_C: 1467 case AUX_CH_D: 1468 return DP_AUX_CH_CTL(aux_ch); 1469 default: 1470 MISSING_CASE(aux_ch); 1471 return DP_AUX_CH_CTL(AUX_CH_B); 1472 } 1473 } 1474 1475 static i915_reg_t g4x_aux_data_reg(struct intel_dp *intel_dp, int index) 1476 { 1477 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1478 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1479 enum aux_ch aux_ch = dig_port->aux_ch; 1480 1481 switch (aux_ch) { 1482 case AUX_CH_B: 1483 case AUX_CH_C: 1484 case AUX_CH_D: 1485 return DP_AUX_CH_DATA(aux_ch, index); 1486 default: 1487 MISSING_CASE(aux_ch); 1488 return DP_AUX_CH_DATA(AUX_CH_B, index); 1489 } 1490 } 1491 1492 static i915_reg_t ilk_aux_ctl_reg(struct intel_dp *intel_dp) 1493 { 1494 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1495 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1496 enum aux_ch aux_ch = dig_port->aux_ch; 1497 1498 switch (aux_ch) { 1499 case AUX_CH_A: 1500 return DP_AUX_CH_CTL(aux_ch); 1501 case AUX_CH_B: 1502 case AUX_CH_C: 1503 case AUX_CH_D: 1504 return PCH_DP_AUX_CH_CTL(aux_ch); 1505 default: 1506 MISSING_CASE(aux_ch); 1507 return DP_AUX_CH_CTL(AUX_CH_A); 1508 } 1509 } 1510 1511 static i915_reg_t ilk_aux_data_reg(struct intel_dp *intel_dp, int index) 1512 { 1513 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1514 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1515 enum aux_ch aux_ch = dig_port->aux_ch; 1516 1517 switch (aux_ch) { 1518 case AUX_CH_A: 1519 return DP_AUX_CH_DATA(aux_ch, index); 1520 case AUX_CH_B: 1521 case AUX_CH_C: 1522 case AUX_CH_D: 1523 return PCH_DP_AUX_CH_DATA(aux_ch, index); 1524 default: 1525 MISSING_CASE(aux_ch); 1526 return DP_AUX_CH_DATA(AUX_CH_A, index); 1527 } 1528 } 1529 1530 static i915_reg_t skl_aux_ctl_reg(struct intel_dp *intel_dp) 1531 { 1532 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1533 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1534 enum aux_ch aux_ch = dig_port->aux_ch; 1535 1536 switch (aux_ch) { 1537 case AUX_CH_A: 1538 case AUX_CH_B: 1539 case AUX_CH_C: 1540 case AUX_CH_D: 1541 case AUX_CH_E: 1542 case AUX_CH_F: 1543 return DP_AUX_CH_CTL(aux_ch); 1544 default: 1545 MISSING_CASE(aux_ch); 1546 return DP_AUX_CH_CTL(AUX_CH_A); 1547 } 1548 } 1549 1550 static i915_reg_t skl_aux_data_reg(struct intel_dp *intel_dp, int index) 1551 { 1552 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1553 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1554 enum aux_ch aux_ch = dig_port->aux_ch; 1555 1556 switch (aux_ch) { 1557 case AUX_CH_A: 1558 case AUX_CH_B: 1559 case AUX_CH_C: 1560 case AUX_CH_D: 1561 case AUX_CH_E: 1562 case AUX_CH_F: 1563 return DP_AUX_CH_DATA(aux_ch, index); 1564 default: 1565 MISSING_CASE(aux_ch); 1566 return DP_AUX_CH_DATA(AUX_CH_A, index); 1567 } 1568 } 1569 1570 static void 1571 intel_dp_aux_fini(struct intel_dp *intel_dp) 1572 { 1573 kfree(intel_dp->aux.name); 1574 } 1575 1576 static void 1577 intel_dp_aux_init(struct intel_dp *intel_dp) 1578 { 1579 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1580 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1581 struct intel_encoder *encoder = &dig_port->base; 1582 1583 if (INTEL_GEN(dev_priv) >= 9) { 1584 intel_dp->aux_ch_ctl_reg = skl_aux_ctl_reg; 1585 intel_dp->aux_ch_data_reg = skl_aux_data_reg; 1586 } else if (HAS_PCH_SPLIT(dev_priv)) { 1587 intel_dp->aux_ch_ctl_reg = ilk_aux_ctl_reg; 1588 intel_dp->aux_ch_data_reg = ilk_aux_data_reg; 1589 } else { 1590 intel_dp->aux_ch_ctl_reg = g4x_aux_ctl_reg; 1591 intel_dp->aux_ch_data_reg = g4x_aux_data_reg; 1592 } 1593 1594 if (INTEL_GEN(dev_priv) >= 9) 1595 intel_dp->get_aux_clock_divider = skl_get_aux_clock_divider; 1596 else if (IS_BROADWELL(dev_priv) || IS_HASWELL(dev_priv)) 1597 intel_dp->get_aux_clock_divider = hsw_get_aux_clock_divider; 1598 else if (HAS_PCH_SPLIT(dev_priv)) 1599 intel_dp->get_aux_clock_divider = ilk_get_aux_clock_divider; 1600 else 1601 intel_dp->get_aux_clock_divider = g4x_get_aux_clock_divider; 1602 1603 if (INTEL_GEN(dev_priv) >= 9) 1604 intel_dp->get_aux_send_ctl = skl_get_aux_send_ctl; 1605 else 1606 intel_dp->get_aux_send_ctl = g4x_get_aux_send_ctl; 1607 1608 drm_dp_aux_init(&intel_dp->aux); 1609 1610 /* Failure to allocate our preferred name is not critical */ 1611 intel_dp->aux.name = kasprintf(GFP_KERNEL, "DPDDC-%c", 1612 port_name(encoder->port)); 1613 intel_dp->aux.transfer = intel_dp_aux_transfer; 1614 } 1615 1616 bool intel_dp_source_supports_hbr2(struct intel_dp *intel_dp) 1617 { 1618 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; 1619 1620 return max_rate >= 540000; 1621 } 1622 1623 bool intel_dp_source_supports_hbr3(struct intel_dp *intel_dp) 1624 { 1625 int max_rate = intel_dp->source_rates[intel_dp->num_source_rates - 1]; 1626 1627 return max_rate >= 810000; 1628 } 1629 1630 static void 1631 intel_dp_set_clock(struct intel_encoder *encoder, 1632 struct intel_crtc_state *pipe_config) 1633 { 1634 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 1635 const struct dp_link_dpll *divisor = NULL; 1636 int i, count = 0; 1637 1638 if (IS_G4X(dev_priv)) { 1639 divisor = g4x_dpll; 1640 count = ARRAY_SIZE(g4x_dpll); 1641 } else if (HAS_PCH_SPLIT(dev_priv)) { 1642 divisor = pch_dpll; 1643 count = ARRAY_SIZE(pch_dpll); 1644 } else if (IS_CHERRYVIEW(dev_priv)) { 1645 divisor = chv_dpll; 1646 count = ARRAY_SIZE(chv_dpll); 1647 } else if (IS_VALLEYVIEW(dev_priv)) { 1648 divisor = vlv_dpll; 1649 count = ARRAY_SIZE(vlv_dpll); 1650 } 1651 1652 if (divisor && count) { 1653 for (i = 0; i < count; i++) { 1654 if (pipe_config->port_clock == divisor[i].clock) { 1655 pipe_config->dpll = divisor[i].dpll; 1656 pipe_config->clock_set = true; 1657 break; 1658 } 1659 } 1660 } 1661 } 1662 1663 static void snprintf_int_array(char *str, size_t len, 1664 const int *array, int nelem) 1665 { 1666 int i; 1667 1668 str[0] = '\0'; 1669 1670 for (i = 0; i < nelem; i++) { 1671 int r = snprintf(str, len, "%s%d", i ? ", " : "", array[i]); 1672 if (r >= len) 1673 return; 1674 str += r; 1675 len -= r; 1676 } 1677 } 1678 1679 static void intel_dp_print_rates(struct intel_dp *intel_dp) 1680 { 1681 char str[128]; /* FIXME: too big for stack? */ 1682 1683 if ((drm_debug & DRM_UT_KMS) == 0) 1684 return; 1685 1686 snprintf_int_array(str, sizeof(str), 1687 intel_dp->source_rates, intel_dp->num_source_rates); 1688 DRM_DEBUG_KMS("source rates: %s\n", str); 1689 1690 snprintf_int_array(str, sizeof(str), 1691 intel_dp->sink_rates, intel_dp->num_sink_rates); 1692 DRM_DEBUG_KMS("sink rates: %s\n", str); 1693 1694 snprintf_int_array(str, sizeof(str), 1695 intel_dp->common_rates, intel_dp->num_common_rates); 1696 DRM_DEBUG_KMS("common rates: %s\n", str); 1697 } 1698 1699 int 1700 intel_dp_max_link_rate(struct intel_dp *intel_dp) 1701 { 1702 int len; 1703 1704 len = intel_dp_common_len_rate_limit(intel_dp, intel_dp->max_link_rate); 1705 if (WARN_ON(len <= 0)) 1706 return 162000; 1707 1708 return intel_dp->common_rates[len - 1]; 1709 } 1710 1711 int intel_dp_rate_select(struct intel_dp *intel_dp, int rate) 1712 { 1713 int i = intel_dp_rate_index(intel_dp->sink_rates, 1714 intel_dp->num_sink_rates, rate); 1715 1716 if (WARN_ON(i < 0)) 1717 i = 0; 1718 1719 return i; 1720 } 1721 1722 void intel_dp_compute_rate(struct intel_dp *intel_dp, int port_clock, 1723 u8 *link_bw, u8 *rate_select) 1724 { 1725 /* eDP 1.4 rate select method. */ 1726 if (intel_dp->use_rate_select) { 1727 *link_bw = 0; 1728 *rate_select = 1729 intel_dp_rate_select(intel_dp, port_clock); 1730 } else { 1731 *link_bw = drm_dp_link_rate_to_bw_code(port_clock); 1732 *rate_select = 0; 1733 } 1734 } 1735 1736 static bool intel_dp_source_supports_fec(struct intel_dp *intel_dp, 1737 const struct intel_crtc_state *pipe_config) 1738 { 1739 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1740 1741 return INTEL_GEN(dev_priv) >= 11 && 1742 pipe_config->cpu_transcoder != TRANSCODER_A; 1743 } 1744 1745 static bool intel_dp_supports_fec(struct intel_dp *intel_dp, 1746 const struct intel_crtc_state *pipe_config) 1747 { 1748 return intel_dp_source_supports_fec(intel_dp, pipe_config) && 1749 drm_dp_sink_supports_fec(intel_dp->fec_capable); 1750 } 1751 1752 static bool intel_dp_source_supports_dsc(struct intel_dp *intel_dp, 1753 const struct intel_crtc_state *pipe_config) 1754 { 1755 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1756 1757 return INTEL_GEN(dev_priv) >= 10 && 1758 pipe_config->cpu_transcoder != TRANSCODER_A; 1759 } 1760 1761 static bool intel_dp_supports_dsc(struct intel_dp *intel_dp, 1762 const struct intel_crtc_state *pipe_config) 1763 { 1764 if (!intel_dp_is_edp(intel_dp) && !pipe_config->fec_enable) 1765 return false; 1766 1767 return intel_dp_source_supports_dsc(intel_dp, pipe_config) && 1768 drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd); 1769 } 1770 1771 static int intel_dp_compute_bpp(struct intel_dp *intel_dp, 1772 struct intel_crtc_state *pipe_config) 1773 { 1774 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 1775 struct intel_connector *intel_connector = intel_dp->attached_connector; 1776 int bpp, bpc; 1777 1778 bpp = pipe_config->pipe_bpp; 1779 bpc = drm_dp_downstream_max_bpc(intel_dp->dpcd, intel_dp->downstream_ports); 1780 1781 if (bpc > 0) 1782 bpp = min(bpp, 3*bpc); 1783 1784 if (intel_dp_is_edp(intel_dp)) { 1785 /* Get bpp from vbt only for panels that dont have bpp in edid */ 1786 if (intel_connector->base.display_info.bpc == 0 && 1787 dev_priv->vbt.edp.bpp && dev_priv->vbt.edp.bpp < bpp) { 1788 DRM_DEBUG_KMS("clamping bpp for eDP panel to BIOS-provided %i\n", 1789 dev_priv->vbt.edp.bpp); 1790 bpp = dev_priv->vbt.edp.bpp; 1791 } 1792 } 1793 1794 return bpp; 1795 } 1796 1797 /* Adjust link config limits based on compliance test requests. */ 1798 void 1799 intel_dp_adjust_compliance_config(struct intel_dp *intel_dp, 1800 struct intel_crtc_state *pipe_config, 1801 struct link_config_limits *limits) 1802 { 1803 /* For DP Compliance we override the computed bpp for the pipe */ 1804 if (intel_dp->compliance.test_data.bpc != 0) { 1805 int bpp = 3 * intel_dp->compliance.test_data.bpc; 1806 1807 limits->min_bpp = limits->max_bpp = bpp; 1808 pipe_config->dither_force_disable = bpp == 6 * 3; 1809 1810 DRM_DEBUG_KMS("Setting pipe_bpp to %d\n", bpp); 1811 } 1812 1813 /* Use values requested by Compliance Test Request */ 1814 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { 1815 int index; 1816 1817 /* Validate the compliance test data since max values 1818 * might have changed due to link train fallback. 1819 */ 1820 if (intel_dp_link_params_valid(intel_dp, intel_dp->compliance.test_link_rate, 1821 intel_dp->compliance.test_lane_count)) { 1822 index = intel_dp_rate_index(intel_dp->common_rates, 1823 intel_dp->num_common_rates, 1824 intel_dp->compliance.test_link_rate); 1825 if (index >= 0) 1826 limits->min_clock = limits->max_clock = index; 1827 limits->min_lane_count = limits->max_lane_count = 1828 intel_dp->compliance.test_lane_count; 1829 } 1830 } 1831 } 1832 1833 static int intel_dp_output_bpp(const struct intel_crtc_state *crtc_state, int bpp) 1834 { 1835 /* 1836 * bpp value was assumed to RGB format. And YCbCr 4:2:0 output 1837 * format of the number of bytes per pixel will be half the number 1838 * of bytes of RGB pixel. 1839 */ 1840 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_YCBCR420) 1841 bpp /= 2; 1842 1843 return bpp; 1844 } 1845 1846 /* Optimize link config in order: max bpp, min clock, min lanes */ 1847 static int 1848 intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, 1849 struct intel_crtc_state *pipe_config, 1850 const struct link_config_limits *limits) 1851 { 1852 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1853 int bpp, clock, lane_count; 1854 int mode_rate, link_clock, link_avail; 1855 1856 for (bpp = limits->max_bpp; bpp >= limits->min_bpp; bpp -= 2 * 3) { 1857 int output_bpp = intel_dp_output_bpp(pipe_config, bpp); 1858 1859 mode_rate = intel_dp_link_required(adjusted_mode->crtc_clock, 1860 output_bpp); 1861 1862 for (clock = limits->min_clock; clock <= limits->max_clock; clock++) { 1863 for (lane_count = limits->min_lane_count; 1864 lane_count <= limits->max_lane_count; 1865 lane_count <<= 1) { 1866 link_clock = intel_dp->common_rates[clock]; 1867 link_avail = intel_dp_max_data_rate(link_clock, 1868 lane_count); 1869 1870 if (mode_rate <= link_avail) { 1871 pipe_config->lane_count = lane_count; 1872 pipe_config->pipe_bpp = bpp; 1873 pipe_config->port_clock = link_clock; 1874 1875 return 0; 1876 } 1877 } 1878 } 1879 } 1880 1881 return -EINVAL; 1882 } 1883 1884 static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc) 1885 { 1886 int i, num_bpc; 1887 u8 dsc_bpc[3] = {0}; 1888 1889 num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, 1890 dsc_bpc); 1891 for (i = 0; i < num_bpc; i++) { 1892 if (dsc_max_bpc >= dsc_bpc[i]) 1893 return dsc_bpc[i] * 3; 1894 } 1895 1896 return 0; 1897 } 1898 1899 static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, 1900 struct intel_crtc_state *pipe_config, 1901 struct drm_connector_state *conn_state, 1902 struct link_config_limits *limits) 1903 { 1904 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 1905 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 1906 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 1907 u8 dsc_max_bpc; 1908 int pipe_bpp; 1909 int ret; 1910 1911 pipe_config->fec_enable = !intel_dp_is_edp(intel_dp) && 1912 intel_dp_supports_fec(intel_dp, pipe_config); 1913 1914 if (!intel_dp_supports_dsc(intel_dp, pipe_config)) 1915 return -EINVAL; 1916 1917 dsc_max_bpc = min_t(u8, DP_DSC_MAX_SUPPORTED_BPC, 1918 conn_state->max_requested_bpc); 1919 1920 pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, dsc_max_bpc); 1921 if (pipe_bpp < DP_DSC_MIN_SUPPORTED_BPC * 3) { 1922 DRM_DEBUG_KMS("No DSC support for less than 8bpc\n"); 1923 return -EINVAL; 1924 } 1925 1926 /* 1927 * For now enable DSC for max bpp, max link rate, max lane count. 1928 * Optimize this later for the minimum possible link rate/lane count 1929 * with DSC enabled for the requested mode. 1930 */ 1931 pipe_config->pipe_bpp = pipe_bpp; 1932 pipe_config->port_clock = intel_dp->common_rates[limits->max_clock]; 1933 pipe_config->lane_count = limits->max_lane_count; 1934 1935 if (intel_dp_is_edp(intel_dp)) { 1936 pipe_config->dsc_params.compressed_bpp = 1937 min_t(u16, drm_edp_dsc_sink_output_bpp(intel_dp->dsc_dpcd) >> 4, 1938 pipe_config->pipe_bpp); 1939 pipe_config->dsc_params.slice_count = 1940 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, 1941 true); 1942 } else { 1943 u16 dsc_max_output_bpp; 1944 u8 dsc_dp_slice_count; 1945 1946 dsc_max_output_bpp = 1947 intel_dp_dsc_get_output_bpp(pipe_config->port_clock, 1948 pipe_config->lane_count, 1949 adjusted_mode->crtc_clock, 1950 adjusted_mode->crtc_hdisplay); 1951 dsc_dp_slice_count = 1952 intel_dp_dsc_get_slice_count(intel_dp, 1953 adjusted_mode->crtc_clock, 1954 adjusted_mode->crtc_hdisplay); 1955 if (!dsc_max_output_bpp || !dsc_dp_slice_count) { 1956 DRM_DEBUG_KMS("Compressed BPP/Slice Count not supported\n"); 1957 return -EINVAL; 1958 } 1959 pipe_config->dsc_params.compressed_bpp = min_t(u16, 1960 dsc_max_output_bpp >> 4, 1961 pipe_config->pipe_bpp); 1962 pipe_config->dsc_params.slice_count = dsc_dp_slice_count; 1963 } 1964 /* 1965 * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate 1966 * is greater than the maximum Cdclock and if slice count is even 1967 * then we need to use 2 VDSC instances. 1968 */ 1969 if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) { 1970 if (pipe_config->dsc_params.slice_count > 1) { 1971 pipe_config->dsc_params.dsc_split = true; 1972 } else { 1973 DRM_DEBUG_KMS("Cannot split stream to use 2 VDSC instances\n"); 1974 return -EINVAL; 1975 } 1976 } 1977 1978 ret = intel_dp_compute_dsc_params(intel_dp, pipe_config); 1979 if (ret < 0) { 1980 DRM_DEBUG_KMS("Cannot compute valid DSC parameters for Input Bpp = %d " 1981 "Compressed BPP = %d\n", 1982 pipe_config->pipe_bpp, 1983 pipe_config->dsc_params.compressed_bpp); 1984 return ret; 1985 } 1986 1987 pipe_config->dsc_params.compression_enable = true; 1988 DRM_DEBUG_KMS("DP DSC computed with Input Bpp = %d " 1989 "Compressed Bpp = %d Slice Count = %d\n", 1990 pipe_config->pipe_bpp, 1991 pipe_config->dsc_params.compressed_bpp, 1992 pipe_config->dsc_params.slice_count); 1993 1994 return 0; 1995 } 1996 1997 int intel_dp_min_bpp(const struct intel_crtc_state *crtc_state) 1998 { 1999 if (crtc_state->output_format == INTEL_OUTPUT_FORMAT_RGB) 2000 return 6 * 3; 2001 else 2002 return 8 * 3; 2003 } 2004 2005 static int 2006 intel_dp_compute_link_config(struct intel_encoder *encoder, 2007 struct intel_crtc_state *pipe_config, 2008 struct drm_connector_state *conn_state) 2009 { 2010 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 2011 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2012 struct link_config_limits limits; 2013 int common_len; 2014 int ret; 2015 2016 common_len = intel_dp_common_len_rate_limit(intel_dp, 2017 intel_dp->max_link_rate); 2018 2019 /* No common link rates between source and sink */ 2020 WARN_ON(common_len <= 0); 2021 2022 limits.min_clock = 0; 2023 limits.max_clock = common_len - 1; 2024 2025 limits.min_lane_count = 1; 2026 limits.max_lane_count = intel_dp_max_lane_count(intel_dp); 2027 2028 limits.min_bpp = intel_dp_min_bpp(pipe_config); 2029 limits.max_bpp = intel_dp_compute_bpp(intel_dp, pipe_config); 2030 2031 if (intel_dp_is_edp(intel_dp)) { 2032 /* 2033 * Use the maximum clock and number of lanes the eDP panel 2034 * advertizes being capable of. The panels are generally 2035 * designed to support only a single clock and lane 2036 * configuration, and typically these values correspond to the 2037 * native resolution of the panel. 2038 */ 2039 limits.min_lane_count = limits.max_lane_count; 2040 limits.min_clock = limits.max_clock; 2041 } 2042 2043 intel_dp_adjust_compliance_config(intel_dp, pipe_config, &limits); 2044 2045 DRM_DEBUG_KMS("DP link computation with max lane count %i " 2046 "max rate %d max bpp %d pixel clock %iKHz\n", 2047 limits.max_lane_count, 2048 intel_dp->common_rates[limits.max_clock], 2049 limits.max_bpp, adjusted_mode->crtc_clock); 2050 2051 /* 2052 * Optimize for slow and wide. This is the place to add alternative 2053 * optimization policy. 2054 */ 2055 ret = intel_dp_compute_link_config_wide(intel_dp, pipe_config, &limits); 2056 2057 /* enable compression if the mode doesn't fit available BW */ 2058 DRM_DEBUG_KMS("Force DSC en = %d\n", intel_dp->force_dsc_en); 2059 if (ret || intel_dp->force_dsc_en) { 2060 ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, 2061 conn_state, &limits); 2062 if (ret < 0) 2063 return ret; 2064 } 2065 2066 if (pipe_config->dsc_params.compression_enable) { 2067 DRM_DEBUG_KMS("DP lane count %d clock %d Input bpp %d Compressed bpp %d\n", 2068 pipe_config->lane_count, pipe_config->port_clock, 2069 pipe_config->pipe_bpp, 2070 pipe_config->dsc_params.compressed_bpp); 2071 2072 DRM_DEBUG_KMS("DP link rate required %i available %i\n", 2073 intel_dp_link_required(adjusted_mode->crtc_clock, 2074 pipe_config->dsc_params.compressed_bpp), 2075 intel_dp_max_data_rate(pipe_config->port_clock, 2076 pipe_config->lane_count)); 2077 } else { 2078 DRM_DEBUG_KMS("DP lane count %d clock %d bpp %d\n", 2079 pipe_config->lane_count, pipe_config->port_clock, 2080 pipe_config->pipe_bpp); 2081 2082 DRM_DEBUG_KMS("DP link rate required %i available %i\n", 2083 intel_dp_link_required(adjusted_mode->crtc_clock, 2084 pipe_config->pipe_bpp), 2085 intel_dp_max_data_rate(pipe_config->port_clock, 2086 pipe_config->lane_count)); 2087 } 2088 return 0; 2089 } 2090 2091 static int 2092 intel_dp_ycbcr420_config(struct intel_dp *intel_dp, 2093 struct drm_connector *connector, 2094 struct intel_crtc_state *crtc_state) 2095 { 2096 const struct drm_display_info *info = &connector->display_info; 2097 const struct drm_display_mode *adjusted_mode = 2098 &crtc_state->base.adjusted_mode; 2099 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 2100 int ret; 2101 2102 if (!drm_mode_is_420_only(info, adjusted_mode) || 2103 !intel_dp_get_colorimetry_status(intel_dp) || 2104 !connector->ycbcr_420_allowed) 2105 return 0; 2106 2107 crtc_state->output_format = INTEL_OUTPUT_FORMAT_YCBCR420; 2108 2109 /* YCBCR 420 output conversion needs a scaler */ 2110 ret = skl_update_scaler_crtc(crtc_state); 2111 if (ret) { 2112 DRM_DEBUG_KMS("Scaler allocation for output failed\n"); 2113 return ret; 2114 } 2115 2116 intel_pch_panel_fitting(crtc, crtc_state, DRM_MODE_SCALE_FULLSCREEN); 2117 2118 return 0; 2119 } 2120 2121 bool intel_dp_limited_color_range(const struct intel_crtc_state *crtc_state, 2122 const struct drm_connector_state *conn_state) 2123 { 2124 const struct intel_digital_connector_state *intel_conn_state = 2125 to_intel_digital_connector_state(conn_state); 2126 const struct drm_display_mode *adjusted_mode = 2127 &crtc_state->base.adjusted_mode; 2128 2129 if (intel_conn_state->broadcast_rgb == INTEL_BROADCAST_RGB_AUTO) { 2130 /* 2131 * See: 2132 * CEA-861-E - 5.1 Default Encoding Parameters 2133 * VESA DisplayPort Ver.1.2a - 5.1.1.1 Video Colorimetry 2134 */ 2135 return crtc_state->pipe_bpp != 18 && 2136 drm_default_rgb_quant_range(adjusted_mode) == 2137 HDMI_QUANTIZATION_RANGE_LIMITED; 2138 } else { 2139 return intel_conn_state->broadcast_rgb == 2140 INTEL_BROADCAST_RGB_LIMITED; 2141 } 2142 } 2143 2144 int 2145 intel_dp_compute_config(struct intel_encoder *encoder, 2146 struct intel_crtc_state *pipe_config, 2147 struct drm_connector_state *conn_state) 2148 { 2149 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2150 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 2151 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2152 struct intel_lspcon *lspcon = enc_to_intel_lspcon(&encoder->base); 2153 enum port port = encoder->port; 2154 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); 2155 struct intel_connector *intel_connector = intel_dp->attached_connector; 2156 struct intel_digital_connector_state *intel_conn_state = 2157 to_intel_digital_connector_state(conn_state); 2158 bool constant_n = drm_dp_has_quirk(&intel_dp->desc, 2159 DP_DPCD_QUIRK_CONSTANT_N); 2160 int ret = 0, output_bpp; 2161 2162 if (HAS_PCH_SPLIT(dev_priv) && !HAS_DDI(dev_priv) && port != PORT_A) 2163 pipe_config->has_pch_encoder = true; 2164 2165 pipe_config->output_format = INTEL_OUTPUT_FORMAT_RGB; 2166 if (lspcon->active) 2167 lspcon_ycbcr420_config(&intel_connector->base, pipe_config); 2168 else 2169 ret = intel_dp_ycbcr420_config(intel_dp, &intel_connector->base, 2170 pipe_config); 2171 2172 if (ret) 2173 return ret; 2174 2175 pipe_config->has_drrs = false; 2176 if (IS_G4X(dev_priv) || port == PORT_A) 2177 pipe_config->has_audio = false; 2178 else if (intel_conn_state->force_audio == HDMI_AUDIO_AUTO) 2179 pipe_config->has_audio = intel_dp->has_audio; 2180 else 2181 pipe_config->has_audio = intel_conn_state->force_audio == HDMI_AUDIO_ON; 2182 2183 if (intel_dp_is_edp(intel_dp) && intel_connector->panel.fixed_mode) { 2184 intel_fixed_panel_mode(intel_connector->panel.fixed_mode, 2185 adjusted_mode); 2186 2187 if (INTEL_GEN(dev_priv) >= 9) { 2188 ret = skl_update_scaler_crtc(pipe_config); 2189 if (ret) 2190 return ret; 2191 } 2192 2193 if (HAS_GMCH(dev_priv)) 2194 intel_gmch_panel_fitting(intel_crtc, pipe_config, 2195 conn_state->scaling_mode); 2196 else 2197 intel_pch_panel_fitting(intel_crtc, pipe_config, 2198 conn_state->scaling_mode); 2199 } 2200 2201 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN) 2202 return -EINVAL; 2203 2204 if (HAS_GMCH(dev_priv) && 2205 adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) 2206 return -EINVAL; 2207 2208 if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) 2209 return -EINVAL; 2210 2211 ret = intel_dp_compute_link_config(encoder, pipe_config, conn_state); 2212 if (ret < 0) 2213 return ret; 2214 2215 pipe_config->limited_color_range = 2216 intel_dp_limited_color_range(pipe_config, conn_state); 2217 2218 if (pipe_config->dsc_params.compression_enable) 2219 output_bpp = pipe_config->dsc_params.compressed_bpp; 2220 else 2221 output_bpp = intel_dp_output_bpp(pipe_config, pipe_config->pipe_bpp); 2222 2223 intel_link_compute_m_n(output_bpp, 2224 pipe_config->lane_count, 2225 adjusted_mode->crtc_clock, 2226 pipe_config->port_clock, 2227 &pipe_config->dp_m_n, 2228 constant_n); 2229 2230 if (intel_connector->panel.downclock_mode != NULL && 2231 dev_priv->drrs.type == SEAMLESS_DRRS_SUPPORT) { 2232 pipe_config->has_drrs = true; 2233 intel_link_compute_m_n(output_bpp, 2234 pipe_config->lane_count, 2235 intel_connector->panel.downclock_mode->clock, 2236 pipe_config->port_clock, 2237 &pipe_config->dp_m2_n2, 2238 constant_n); 2239 } 2240 2241 if (!HAS_DDI(dev_priv)) 2242 intel_dp_set_clock(encoder, pipe_config); 2243 2244 intel_psr_compute_config(intel_dp, pipe_config); 2245 2246 return 0; 2247 } 2248 2249 void intel_dp_set_link_params(struct intel_dp *intel_dp, 2250 int link_rate, u8 lane_count, 2251 bool link_mst) 2252 { 2253 intel_dp->link_trained = false; 2254 intel_dp->link_rate = link_rate; 2255 intel_dp->lane_count = lane_count; 2256 intel_dp->link_mst = link_mst; 2257 } 2258 2259 static void intel_dp_prepare(struct intel_encoder *encoder, 2260 const struct intel_crtc_state *pipe_config) 2261 { 2262 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 2263 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 2264 enum port port = encoder->port; 2265 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 2266 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; 2267 2268 intel_dp_set_link_params(intel_dp, pipe_config->port_clock, 2269 pipe_config->lane_count, 2270 intel_crtc_has_type(pipe_config, 2271 INTEL_OUTPUT_DP_MST)); 2272 2273 /* 2274 * There are four kinds of DP registers: 2275 * 2276 * IBX PCH 2277 * SNB CPU 2278 * IVB CPU 2279 * CPT PCH 2280 * 2281 * IBX PCH and CPU are the same for almost everything, 2282 * except that the CPU DP PLL is configured in this 2283 * register 2284 * 2285 * CPT PCH is quite different, having many bits moved 2286 * to the TRANS_DP_CTL register instead. That 2287 * configuration happens (oddly) in ironlake_pch_enable 2288 */ 2289 2290 /* Preserve the BIOS-computed detected bit. This is 2291 * supposed to be read-only. 2292 */ 2293 intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; 2294 2295 /* Handle DP bits in common between all three register formats */ 2296 intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; 2297 intel_dp->DP |= DP_PORT_WIDTH(pipe_config->lane_count); 2298 2299 /* Split out the IBX/CPU vs CPT settings */ 2300 2301 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { 2302 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 2303 intel_dp->DP |= DP_SYNC_HS_HIGH; 2304 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 2305 intel_dp->DP |= DP_SYNC_VS_HIGH; 2306 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 2307 2308 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 2309 intel_dp->DP |= DP_ENHANCED_FRAMING; 2310 2311 intel_dp->DP |= DP_PIPE_SEL_IVB(crtc->pipe); 2312 } else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { 2313 u32 trans_dp; 2314 2315 intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; 2316 2317 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 2318 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 2319 trans_dp |= TRANS_DP_ENH_FRAMING; 2320 else 2321 trans_dp &= ~TRANS_DP_ENH_FRAMING; 2322 I915_WRITE(TRANS_DP_CTL(crtc->pipe), trans_dp); 2323 } else { 2324 if (IS_G4X(dev_priv) && pipe_config->limited_color_range) 2325 intel_dp->DP |= DP_COLOR_RANGE_16_235; 2326 2327 if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) 2328 intel_dp->DP |= DP_SYNC_HS_HIGH; 2329 if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) 2330 intel_dp->DP |= DP_SYNC_VS_HIGH; 2331 intel_dp->DP |= DP_LINK_TRAIN_OFF; 2332 2333 if (drm_dp_enhanced_frame_cap(intel_dp->dpcd)) 2334 intel_dp->DP |= DP_ENHANCED_FRAMING; 2335 2336 if (IS_CHERRYVIEW(dev_priv)) 2337 intel_dp->DP |= DP_PIPE_SEL_CHV(crtc->pipe); 2338 else 2339 intel_dp->DP |= DP_PIPE_SEL(crtc->pipe); 2340 } 2341 } 2342 2343 #define IDLE_ON_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) 2344 #define IDLE_ON_VALUE (PP_ON | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) 2345 2346 #define IDLE_OFF_MASK (PP_ON | PP_SEQUENCE_MASK | 0 | 0) 2347 #define IDLE_OFF_VALUE (0 | PP_SEQUENCE_NONE | 0 | 0) 2348 2349 #define IDLE_CYCLE_MASK (PP_ON | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) 2350 #define IDLE_CYCLE_VALUE (0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) 2351 2352 static void intel_pps_verify_state(struct intel_dp *intel_dp); 2353 2354 static void wait_panel_status(struct intel_dp *intel_dp, 2355 u32 mask, 2356 u32 value) 2357 { 2358 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2359 i915_reg_t pp_stat_reg, pp_ctrl_reg; 2360 2361 lockdep_assert_held(&dev_priv->pps_mutex); 2362 2363 intel_pps_verify_state(intel_dp); 2364 2365 pp_stat_reg = _pp_stat_reg(intel_dp); 2366 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2367 2368 DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", 2369 mask, value, 2370 I915_READ(pp_stat_reg), 2371 I915_READ(pp_ctrl_reg)); 2372 2373 if (intel_wait_for_register(&dev_priv->uncore, 2374 pp_stat_reg, mask, value, 2375 5000)) 2376 DRM_ERROR("Panel status timeout: status %08x control %08x\n", 2377 I915_READ(pp_stat_reg), 2378 I915_READ(pp_ctrl_reg)); 2379 2380 DRM_DEBUG_KMS("Wait complete\n"); 2381 } 2382 2383 static void wait_panel_on(struct intel_dp *intel_dp) 2384 { 2385 DRM_DEBUG_KMS("Wait for panel power on\n"); 2386 wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); 2387 } 2388 2389 static void wait_panel_off(struct intel_dp *intel_dp) 2390 { 2391 DRM_DEBUG_KMS("Wait for panel power off time\n"); 2392 wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); 2393 } 2394 2395 static void wait_panel_power_cycle(struct intel_dp *intel_dp) 2396 { 2397 ktime_t panel_power_on_time; 2398 s64 panel_power_off_duration; 2399 2400 DRM_DEBUG_KMS("Wait for panel power cycle\n"); 2401 2402 /* take the difference of currrent time and panel power off time 2403 * and then make panel wait for t11_t12 if needed. */ 2404 panel_power_on_time = ktime_get_boottime(); 2405 panel_power_off_duration = ktime_ms_delta(panel_power_on_time, intel_dp->panel_power_off_time); 2406 2407 /* When we disable the VDD override bit last we have to do the manual 2408 * wait. */ 2409 if (panel_power_off_duration < (s64)intel_dp->panel_power_cycle_delay) 2410 wait_remaining_ms_from_jiffies(jiffies, 2411 intel_dp->panel_power_cycle_delay - panel_power_off_duration); 2412 2413 wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); 2414 } 2415 2416 static void wait_backlight_on(struct intel_dp *intel_dp) 2417 { 2418 wait_remaining_ms_from_jiffies(intel_dp->last_power_on, 2419 intel_dp->backlight_on_delay); 2420 } 2421 2422 static void edp_wait_backlight_off(struct intel_dp *intel_dp) 2423 { 2424 wait_remaining_ms_from_jiffies(intel_dp->last_backlight_off, 2425 intel_dp->backlight_off_delay); 2426 } 2427 2428 /* Read the current pp_control value, unlocking the register if it 2429 * is locked 2430 */ 2431 2432 static u32 ironlake_get_pp_control(struct intel_dp *intel_dp) 2433 { 2434 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2435 u32 control; 2436 2437 lockdep_assert_held(&dev_priv->pps_mutex); 2438 2439 control = I915_READ(_pp_ctrl_reg(intel_dp)); 2440 if (WARN_ON(!HAS_DDI(dev_priv) && 2441 (control & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS)) { 2442 control &= ~PANEL_UNLOCK_MASK; 2443 control |= PANEL_UNLOCK_REGS; 2444 } 2445 return control; 2446 } 2447 2448 /* 2449 * Must be paired with edp_panel_vdd_off(). 2450 * Must hold pps_mutex around the whole on/off sequence. 2451 * Can be nested with intel_edp_panel_vdd_{on,off}() calls. 2452 */ 2453 static bool edp_panel_vdd_on(struct intel_dp *intel_dp) 2454 { 2455 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2456 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 2457 u32 pp; 2458 i915_reg_t pp_stat_reg, pp_ctrl_reg; 2459 bool need_to_disable = !intel_dp->want_panel_vdd; 2460 2461 lockdep_assert_held(&dev_priv->pps_mutex); 2462 2463 if (!intel_dp_is_edp(intel_dp)) 2464 return false; 2465 2466 cancel_delayed_work(&intel_dp->panel_vdd_work); 2467 intel_dp->want_panel_vdd = true; 2468 2469 if (edp_have_panel_vdd(intel_dp)) 2470 return need_to_disable; 2471 2472 intel_display_power_get(dev_priv, 2473 intel_aux_power_domain(intel_dig_port)); 2474 2475 DRM_DEBUG_KMS("Turning eDP port %c VDD on\n", 2476 port_name(intel_dig_port->base.port)); 2477 2478 if (!edp_have_panel_power(intel_dp)) 2479 wait_panel_power_cycle(intel_dp); 2480 2481 pp = ironlake_get_pp_control(intel_dp); 2482 pp |= EDP_FORCE_VDD; 2483 2484 pp_stat_reg = _pp_stat_reg(intel_dp); 2485 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2486 2487 I915_WRITE(pp_ctrl_reg, pp); 2488 POSTING_READ(pp_ctrl_reg); 2489 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 2490 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 2491 /* 2492 * If the panel wasn't on, delay before accessing aux channel 2493 */ 2494 if (!edp_have_panel_power(intel_dp)) { 2495 DRM_DEBUG_KMS("eDP port %c panel power wasn't enabled\n", 2496 port_name(intel_dig_port->base.port)); 2497 msleep(intel_dp->panel_power_up_delay); 2498 } 2499 2500 return need_to_disable; 2501 } 2502 2503 /* 2504 * Must be paired with intel_edp_panel_vdd_off() or 2505 * intel_edp_panel_off(). 2506 * Nested calls to these functions are not allowed since 2507 * we drop the lock. Caller must use some higher level 2508 * locking to prevent nested calls from other threads. 2509 */ 2510 void intel_edp_panel_vdd_on(struct intel_dp *intel_dp) 2511 { 2512 intel_wakeref_t wakeref; 2513 bool vdd; 2514 2515 if (!intel_dp_is_edp(intel_dp)) 2516 return; 2517 2518 vdd = false; 2519 with_pps_lock(intel_dp, wakeref) 2520 vdd = edp_panel_vdd_on(intel_dp); 2521 I915_STATE_WARN(!vdd, "eDP port %c VDD already requested on\n", 2522 port_name(dp_to_dig_port(intel_dp)->base.port)); 2523 } 2524 2525 static void edp_panel_vdd_off_sync(struct intel_dp *intel_dp) 2526 { 2527 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2528 struct intel_digital_port *intel_dig_port = 2529 dp_to_dig_port(intel_dp); 2530 u32 pp; 2531 i915_reg_t pp_stat_reg, pp_ctrl_reg; 2532 2533 lockdep_assert_held(&dev_priv->pps_mutex); 2534 2535 WARN_ON(intel_dp->want_panel_vdd); 2536 2537 if (!edp_have_panel_vdd(intel_dp)) 2538 return; 2539 2540 DRM_DEBUG_KMS("Turning eDP port %c VDD off\n", 2541 port_name(intel_dig_port->base.port)); 2542 2543 pp = ironlake_get_pp_control(intel_dp); 2544 pp &= ~EDP_FORCE_VDD; 2545 2546 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2547 pp_stat_reg = _pp_stat_reg(intel_dp); 2548 2549 I915_WRITE(pp_ctrl_reg, pp); 2550 POSTING_READ(pp_ctrl_reg); 2551 2552 /* Make sure sequencer is idle before allowing subsequent activity */ 2553 DRM_DEBUG_KMS("PP_STATUS: 0x%08x PP_CONTROL: 0x%08x\n", 2554 I915_READ(pp_stat_reg), I915_READ(pp_ctrl_reg)); 2555 2556 if ((pp & PANEL_POWER_ON) == 0) 2557 intel_dp->panel_power_off_time = ktime_get_boottime(); 2558 2559 intel_display_power_put_unchecked(dev_priv, 2560 intel_aux_power_domain(intel_dig_port)); 2561 } 2562 2563 static void edp_panel_vdd_work(struct work_struct *__work) 2564 { 2565 struct intel_dp *intel_dp = 2566 container_of(to_delayed_work(__work), 2567 struct intel_dp, panel_vdd_work); 2568 intel_wakeref_t wakeref; 2569 2570 with_pps_lock(intel_dp, wakeref) { 2571 if (!intel_dp->want_panel_vdd) 2572 edp_panel_vdd_off_sync(intel_dp); 2573 } 2574 } 2575 2576 static void edp_panel_vdd_schedule_off(struct intel_dp *intel_dp) 2577 { 2578 unsigned long delay; 2579 2580 /* 2581 * Queue the timer to fire a long time from now (relative to the power 2582 * down delay) to keep the panel power up across a sequence of 2583 * operations. 2584 */ 2585 delay = msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5); 2586 schedule_delayed_work(&intel_dp->panel_vdd_work, delay); 2587 } 2588 2589 /* 2590 * Must be paired with edp_panel_vdd_on(). 2591 * Must hold pps_mutex around the whole on/off sequence. 2592 * Can be nested with intel_edp_panel_vdd_{on,off}() calls. 2593 */ 2594 static void edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) 2595 { 2596 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2597 2598 lockdep_assert_held(&dev_priv->pps_mutex); 2599 2600 if (!intel_dp_is_edp(intel_dp)) 2601 return; 2602 2603 I915_STATE_WARN(!intel_dp->want_panel_vdd, "eDP port %c VDD not forced on", 2604 port_name(dp_to_dig_port(intel_dp)->base.port)); 2605 2606 intel_dp->want_panel_vdd = false; 2607 2608 if (sync) 2609 edp_panel_vdd_off_sync(intel_dp); 2610 else 2611 edp_panel_vdd_schedule_off(intel_dp); 2612 } 2613 2614 static void edp_panel_on(struct intel_dp *intel_dp) 2615 { 2616 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2617 u32 pp; 2618 i915_reg_t pp_ctrl_reg; 2619 2620 lockdep_assert_held(&dev_priv->pps_mutex); 2621 2622 if (!intel_dp_is_edp(intel_dp)) 2623 return; 2624 2625 DRM_DEBUG_KMS("Turn eDP port %c panel power on\n", 2626 port_name(dp_to_dig_port(intel_dp)->base.port)); 2627 2628 if (WARN(edp_have_panel_power(intel_dp), 2629 "eDP port %c panel power already on\n", 2630 port_name(dp_to_dig_port(intel_dp)->base.port))) 2631 return; 2632 2633 wait_panel_power_cycle(intel_dp); 2634 2635 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2636 pp = ironlake_get_pp_control(intel_dp); 2637 if (IS_GEN(dev_priv, 5)) { 2638 /* ILK workaround: disable reset around power sequence */ 2639 pp &= ~PANEL_POWER_RESET; 2640 I915_WRITE(pp_ctrl_reg, pp); 2641 POSTING_READ(pp_ctrl_reg); 2642 } 2643 2644 pp |= PANEL_POWER_ON; 2645 if (!IS_GEN(dev_priv, 5)) 2646 pp |= PANEL_POWER_RESET; 2647 2648 I915_WRITE(pp_ctrl_reg, pp); 2649 POSTING_READ(pp_ctrl_reg); 2650 2651 wait_panel_on(intel_dp); 2652 intel_dp->last_power_on = jiffies; 2653 2654 if (IS_GEN(dev_priv, 5)) { 2655 pp |= PANEL_POWER_RESET; /* restore panel reset bit */ 2656 I915_WRITE(pp_ctrl_reg, pp); 2657 POSTING_READ(pp_ctrl_reg); 2658 } 2659 } 2660 2661 void intel_edp_panel_on(struct intel_dp *intel_dp) 2662 { 2663 intel_wakeref_t wakeref; 2664 2665 if (!intel_dp_is_edp(intel_dp)) 2666 return; 2667 2668 with_pps_lock(intel_dp, wakeref) 2669 edp_panel_on(intel_dp); 2670 } 2671 2672 2673 static void edp_panel_off(struct intel_dp *intel_dp) 2674 { 2675 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2676 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2677 u32 pp; 2678 i915_reg_t pp_ctrl_reg; 2679 2680 lockdep_assert_held(&dev_priv->pps_mutex); 2681 2682 if (!intel_dp_is_edp(intel_dp)) 2683 return; 2684 2685 DRM_DEBUG_KMS("Turn eDP port %c panel power off\n", 2686 port_name(dig_port->base.port)); 2687 2688 WARN(!intel_dp->want_panel_vdd, "Need eDP port %c VDD to turn off panel\n", 2689 port_name(dig_port->base.port)); 2690 2691 pp = ironlake_get_pp_control(intel_dp); 2692 /* We need to switch off panel power _and_ force vdd, for otherwise some 2693 * panels get very unhappy and cease to work. */ 2694 pp &= ~(PANEL_POWER_ON | PANEL_POWER_RESET | EDP_FORCE_VDD | 2695 EDP_BLC_ENABLE); 2696 2697 pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2698 2699 intel_dp->want_panel_vdd = false; 2700 2701 I915_WRITE(pp_ctrl_reg, pp); 2702 POSTING_READ(pp_ctrl_reg); 2703 2704 wait_panel_off(intel_dp); 2705 intel_dp->panel_power_off_time = ktime_get_boottime(); 2706 2707 /* We got a reference when we enabled the VDD. */ 2708 intel_display_power_put_unchecked(dev_priv, intel_aux_power_domain(dig_port)); 2709 } 2710 2711 void intel_edp_panel_off(struct intel_dp *intel_dp) 2712 { 2713 intel_wakeref_t wakeref; 2714 2715 if (!intel_dp_is_edp(intel_dp)) 2716 return; 2717 2718 with_pps_lock(intel_dp, wakeref) 2719 edp_panel_off(intel_dp); 2720 } 2721 2722 /* Enable backlight in the panel power control. */ 2723 static void _intel_edp_backlight_on(struct intel_dp *intel_dp) 2724 { 2725 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2726 intel_wakeref_t wakeref; 2727 2728 /* 2729 * If we enable the backlight right away following a panel power 2730 * on, we may see slight flicker as the panel syncs with the eDP 2731 * link. So delay a bit to make sure the image is solid before 2732 * allowing it to appear. 2733 */ 2734 wait_backlight_on(intel_dp); 2735 2736 with_pps_lock(intel_dp, wakeref) { 2737 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2738 u32 pp; 2739 2740 pp = ironlake_get_pp_control(intel_dp); 2741 pp |= EDP_BLC_ENABLE; 2742 2743 I915_WRITE(pp_ctrl_reg, pp); 2744 POSTING_READ(pp_ctrl_reg); 2745 } 2746 } 2747 2748 /* Enable backlight PWM and backlight PP control. */ 2749 void intel_edp_backlight_on(const struct intel_crtc_state *crtc_state, 2750 const struct drm_connector_state *conn_state) 2751 { 2752 struct intel_dp *intel_dp = enc_to_intel_dp(conn_state->best_encoder); 2753 2754 if (!intel_dp_is_edp(intel_dp)) 2755 return; 2756 2757 DRM_DEBUG_KMS("\n"); 2758 2759 intel_panel_enable_backlight(crtc_state, conn_state); 2760 _intel_edp_backlight_on(intel_dp); 2761 } 2762 2763 /* Disable backlight in the panel power control. */ 2764 static void _intel_edp_backlight_off(struct intel_dp *intel_dp) 2765 { 2766 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 2767 intel_wakeref_t wakeref; 2768 2769 if (!intel_dp_is_edp(intel_dp)) 2770 return; 2771 2772 with_pps_lock(intel_dp, wakeref) { 2773 i915_reg_t pp_ctrl_reg = _pp_ctrl_reg(intel_dp); 2774 u32 pp; 2775 2776 pp = ironlake_get_pp_control(intel_dp); 2777 pp &= ~EDP_BLC_ENABLE; 2778 2779 I915_WRITE(pp_ctrl_reg, pp); 2780 POSTING_READ(pp_ctrl_reg); 2781 } 2782 2783 intel_dp->last_backlight_off = jiffies; 2784 edp_wait_backlight_off(intel_dp); 2785 } 2786 2787 /* Disable backlight PP control and backlight PWM. */ 2788 void intel_edp_backlight_off(const struct drm_connector_state *old_conn_state) 2789 { 2790 struct intel_dp *intel_dp = enc_to_intel_dp(old_conn_state->best_encoder); 2791 2792 if (!intel_dp_is_edp(intel_dp)) 2793 return; 2794 2795 DRM_DEBUG_KMS("\n"); 2796 2797 _intel_edp_backlight_off(intel_dp); 2798 intel_panel_disable_backlight(old_conn_state); 2799 } 2800 2801 /* 2802 * Hook for controlling the panel power control backlight through the bl_power 2803 * sysfs attribute. Take care to handle multiple calls. 2804 */ 2805 static void intel_edp_backlight_power(struct intel_connector *connector, 2806 bool enable) 2807 { 2808 struct intel_dp *intel_dp = intel_attached_dp(&connector->base); 2809 intel_wakeref_t wakeref; 2810 bool is_enabled; 2811 2812 is_enabled = false; 2813 with_pps_lock(intel_dp, wakeref) 2814 is_enabled = ironlake_get_pp_control(intel_dp) & EDP_BLC_ENABLE; 2815 if (is_enabled == enable) 2816 return; 2817 2818 DRM_DEBUG_KMS("panel power control backlight %s\n", 2819 enable ? "enable" : "disable"); 2820 2821 if (enable) 2822 _intel_edp_backlight_on(intel_dp); 2823 else 2824 _intel_edp_backlight_off(intel_dp); 2825 } 2826 2827 static void assert_dp_port(struct intel_dp *intel_dp, bool state) 2828 { 2829 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 2830 struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); 2831 bool cur_state = I915_READ(intel_dp->output_reg) & DP_PORT_EN; 2832 2833 I915_STATE_WARN(cur_state != state, 2834 "DP port %c state assertion failure (expected %s, current %s)\n", 2835 port_name(dig_port->base.port), 2836 onoff(state), onoff(cur_state)); 2837 } 2838 #define assert_dp_port_disabled(d) assert_dp_port((d), false) 2839 2840 static void assert_edp_pll(struct drm_i915_private *dev_priv, bool state) 2841 { 2842 bool cur_state = I915_READ(DP_A) & DP_PLL_ENABLE; 2843 2844 I915_STATE_WARN(cur_state != state, 2845 "eDP PLL state assertion failure (expected %s, current %s)\n", 2846 onoff(state), onoff(cur_state)); 2847 } 2848 #define assert_edp_pll_enabled(d) assert_edp_pll((d), true) 2849 #define assert_edp_pll_disabled(d) assert_edp_pll((d), false) 2850 2851 static void ironlake_edp_pll_on(struct intel_dp *intel_dp, 2852 const struct intel_crtc_state *pipe_config) 2853 { 2854 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 2855 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2856 2857 assert_pipe_disabled(dev_priv, crtc->pipe); 2858 assert_dp_port_disabled(intel_dp); 2859 assert_edp_pll_disabled(dev_priv); 2860 2861 DRM_DEBUG_KMS("enabling eDP PLL for clock %d\n", 2862 pipe_config->port_clock); 2863 2864 intel_dp->DP &= ~DP_PLL_FREQ_MASK; 2865 2866 if (pipe_config->port_clock == 162000) 2867 intel_dp->DP |= DP_PLL_FREQ_162MHZ; 2868 else 2869 intel_dp->DP |= DP_PLL_FREQ_270MHZ; 2870 2871 I915_WRITE(DP_A, intel_dp->DP); 2872 POSTING_READ(DP_A); 2873 udelay(500); 2874 2875 /* 2876 * [DevILK] Work around required when enabling DP PLL 2877 * while a pipe is enabled going to FDI: 2878 * 1. Wait for the start of vertical blank on the enabled pipe going to FDI 2879 * 2. Program DP PLL enable 2880 */ 2881 if (IS_GEN(dev_priv, 5)) 2882 intel_wait_for_vblank_if_active(dev_priv, !crtc->pipe); 2883 2884 intel_dp->DP |= DP_PLL_ENABLE; 2885 2886 I915_WRITE(DP_A, intel_dp->DP); 2887 POSTING_READ(DP_A); 2888 udelay(200); 2889 } 2890 2891 static void ironlake_edp_pll_off(struct intel_dp *intel_dp, 2892 const struct intel_crtc_state *old_crtc_state) 2893 { 2894 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 2895 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); 2896 2897 assert_pipe_disabled(dev_priv, crtc->pipe); 2898 assert_dp_port_disabled(intel_dp); 2899 assert_edp_pll_enabled(dev_priv); 2900 2901 DRM_DEBUG_KMS("disabling eDP PLL\n"); 2902 2903 intel_dp->DP &= ~DP_PLL_ENABLE; 2904 2905 I915_WRITE(DP_A, intel_dp->DP); 2906 POSTING_READ(DP_A); 2907 udelay(200); 2908 } 2909 2910 static bool downstream_hpd_needs_d0(struct intel_dp *intel_dp) 2911 { 2912 /* 2913 * DPCD 1.2+ should support BRANCH_DEVICE_CTRL, and thus 2914 * be capable of signalling downstream hpd with a long pulse. 2915 * Whether or not that means D3 is safe to use is not clear, 2916 * but let's assume so until proven otherwise. 2917 * 2918 * FIXME should really check all downstream ports... 2919 */ 2920 return intel_dp->dpcd[DP_DPCD_REV] == 0x11 && 2921 intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT && 2922 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD; 2923 } 2924 2925 void intel_dp_sink_set_decompression_state(struct intel_dp *intel_dp, 2926 const struct intel_crtc_state *crtc_state, 2927 bool enable) 2928 { 2929 int ret; 2930 2931 if (!crtc_state->dsc_params.compression_enable) 2932 return; 2933 2934 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_DSC_ENABLE, 2935 enable ? DP_DECOMPRESSION_EN : 0); 2936 if (ret < 0) 2937 DRM_DEBUG_KMS("Failed to %s sink decompression state\n", 2938 enable ? "enable" : "disable"); 2939 } 2940 2941 /* If the sink supports it, try to set the power state appropriately */ 2942 void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) 2943 { 2944 int ret, i; 2945 2946 /* Should have a valid DPCD by this point */ 2947 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 2948 return; 2949 2950 if (mode != DRM_MODE_DPMS_ON) { 2951 if (downstream_hpd_needs_d0(intel_dp)) 2952 return; 2953 2954 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 2955 DP_SET_POWER_D3); 2956 } else { 2957 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); 2958 2959 /* 2960 * When turning on, we need to retry for 1ms to give the sink 2961 * time to wake up. 2962 */ 2963 for (i = 0; i < 3; i++) { 2964 ret = drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER, 2965 DP_SET_POWER_D0); 2966 if (ret == 1) 2967 break; 2968 msleep(1); 2969 } 2970 2971 if (ret == 1 && lspcon->active) 2972 lspcon_wait_pcon_mode(lspcon); 2973 } 2974 2975 if (ret != 1) 2976 DRM_DEBUG_KMS("failed to %s sink power state\n", 2977 mode == DRM_MODE_DPMS_ON ? "enable" : "disable"); 2978 } 2979 2980 static bool cpt_dp_port_selected(struct drm_i915_private *dev_priv, 2981 enum port port, enum pipe *pipe) 2982 { 2983 enum pipe p; 2984 2985 for_each_pipe(dev_priv, p) { 2986 u32 val = I915_READ(TRANS_DP_CTL(p)); 2987 2988 if ((val & TRANS_DP_PORT_SEL_MASK) == TRANS_DP_PORT_SEL(port)) { 2989 *pipe = p; 2990 return true; 2991 } 2992 } 2993 2994 DRM_DEBUG_KMS("No pipe for DP port %c found\n", port_name(port)); 2995 2996 /* must initialize pipe to something for the asserts */ 2997 *pipe = PIPE_A; 2998 2999 return false; 3000 } 3001 3002 bool intel_dp_port_enabled(struct drm_i915_private *dev_priv, 3003 i915_reg_t dp_reg, enum port port, 3004 enum pipe *pipe) 3005 { 3006 bool ret; 3007 u32 val; 3008 3009 val = I915_READ(dp_reg); 3010 3011 ret = val & DP_PORT_EN; 3012 3013 /* asserts want to know the pipe even if the port is disabled */ 3014 if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) 3015 *pipe = (val & DP_PIPE_SEL_MASK_IVB) >> DP_PIPE_SEL_SHIFT_IVB; 3016 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) 3017 ret &= cpt_dp_port_selected(dev_priv, port, pipe); 3018 else if (IS_CHERRYVIEW(dev_priv)) 3019 *pipe = (val & DP_PIPE_SEL_MASK_CHV) >> DP_PIPE_SEL_SHIFT_CHV; 3020 else 3021 *pipe = (val & DP_PIPE_SEL_MASK) >> DP_PIPE_SEL_SHIFT; 3022 3023 return ret; 3024 } 3025 3026 static bool intel_dp_get_hw_state(struct intel_encoder *encoder, 3027 enum pipe *pipe) 3028 { 3029 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3030 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3031 intel_wakeref_t wakeref; 3032 bool ret; 3033 3034 wakeref = intel_display_power_get_if_enabled(dev_priv, 3035 encoder->power_domain); 3036 if (!wakeref) 3037 return false; 3038 3039 ret = intel_dp_port_enabled(dev_priv, intel_dp->output_reg, 3040 encoder->port, pipe); 3041 3042 intel_display_power_put(dev_priv, encoder->power_domain, wakeref); 3043 3044 return ret; 3045 } 3046 3047 static void intel_dp_get_config(struct intel_encoder *encoder, 3048 struct intel_crtc_state *pipe_config) 3049 { 3050 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3051 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3052 u32 tmp, flags = 0; 3053 enum port port = encoder->port; 3054 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 3055 3056 if (encoder->type == INTEL_OUTPUT_EDP) 3057 pipe_config->output_types |= BIT(INTEL_OUTPUT_EDP); 3058 else 3059 pipe_config->output_types |= BIT(INTEL_OUTPUT_DP); 3060 3061 tmp = I915_READ(intel_dp->output_reg); 3062 3063 pipe_config->has_audio = tmp & DP_AUDIO_OUTPUT_ENABLE && port != PORT_A; 3064 3065 if (HAS_PCH_CPT(dev_priv) && port != PORT_A) { 3066 u32 trans_dp = I915_READ(TRANS_DP_CTL(crtc->pipe)); 3067 3068 if (trans_dp & TRANS_DP_HSYNC_ACTIVE_HIGH) 3069 flags |= DRM_MODE_FLAG_PHSYNC; 3070 else 3071 flags |= DRM_MODE_FLAG_NHSYNC; 3072 3073 if (trans_dp & TRANS_DP_VSYNC_ACTIVE_HIGH) 3074 flags |= DRM_MODE_FLAG_PVSYNC; 3075 else 3076 flags |= DRM_MODE_FLAG_NVSYNC; 3077 } else { 3078 if (tmp & DP_SYNC_HS_HIGH) 3079 flags |= DRM_MODE_FLAG_PHSYNC; 3080 else 3081 flags |= DRM_MODE_FLAG_NHSYNC; 3082 3083 if (tmp & DP_SYNC_VS_HIGH) 3084 flags |= DRM_MODE_FLAG_PVSYNC; 3085 else 3086 flags |= DRM_MODE_FLAG_NVSYNC; 3087 } 3088 3089 pipe_config->base.adjusted_mode.flags |= flags; 3090 3091 if (IS_G4X(dev_priv) && tmp & DP_COLOR_RANGE_16_235) 3092 pipe_config->limited_color_range = true; 3093 3094 pipe_config->lane_count = 3095 ((tmp & DP_PORT_WIDTH_MASK) >> DP_PORT_WIDTH_SHIFT) + 1; 3096 3097 intel_dp_get_m_n(crtc, pipe_config); 3098 3099 if (port == PORT_A) { 3100 if ((I915_READ(DP_A) & DP_PLL_FREQ_MASK) == DP_PLL_FREQ_162MHZ) 3101 pipe_config->port_clock = 162000; 3102 else 3103 pipe_config->port_clock = 270000; 3104 } 3105 3106 pipe_config->base.adjusted_mode.crtc_clock = 3107 intel_dotclock_calculate(pipe_config->port_clock, 3108 &pipe_config->dp_m_n); 3109 3110 if (intel_dp_is_edp(intel_dp) && dev_priv->vbt.edp.bpp && 3111 pipe_config->pipe_bpp > dev_priv->vbt.edp.bpp) { 3112 /* 3113 * This is a big fat ugly hack. 3114 * 3115 * Some machines in UEFI boot mode provide us a VBT that has 18 3116 * bpp and 1.62 GHz link bandwidth for eDP, which for reasons 3117 * unknown we fail to light up. Yet the same BIOS boots up with 3118 * 24 bpp and 2.7 GHz link. Use the same bpp as the BIOS uses as 3119 * max, not what it tells us to use. 3120 * 3121 * Note: This will still be broken if the eDP panel is not lit 3122 * up by the BIOS, and thus we can't get the mode at module 3123 * load. 3124 */ 3125 DRM_DEBUG_KMS("pipe has %d bpp for eDP panel, overriding BIOS-provided max %d bpp\n", 3126 pipe_config->pipe_bpp, dev_priv->vbt.edp.bpp); 3127 dev_priv->vbt.edp.bpp = pipe_config->pipe_bpp; 3128 } 3129 } 3130 3131 static void intel_disable_dp(struct intel_encoder *encoder, 3132 const struct intel_crtc_state *old_crtc_state, 3133 const struct drm_connector_state *old_conn_state) 3134 { 3135 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3136 3137 intel_dp->link_trained = false; 3138 3139 if (old_crtc_state->has_audio) 3140 intel_audio_codec_disable(encoder, 3141 old_crtc_state, old_conn_state); 3142 3143 /* Make sure the panel is off before trying to change the mode. But also 3144 * ensure that we have vdd while we switch off the panel. */ 3145 intel_edp_panel_vdd_on(intel_dp); 3146 intel_edp_backlight_off(old_conn_state); 3147 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_OFF); 3148 intel_edp_panel_off(intel_dp); 3149 } 3150 3151 static void g4x_disable_dp(struct intel_encoder *encoder, 3152 const struct intel_crtc_state *old_crtc_state, 3153 const struct drm_connector_state *old_conn_state) 3154 { 3155 intel_disable_dp(encoder, old_crtc_state, old_conn_state); 3156 } 3157 3158 static void vlv_disable_dp(struct intel_encoder *encoder, 3159 const struct intel_crtc_state *old_crtc_state, 3160 const struct drm_connector_state *old_conn_state) 3161 { 3162 intel_disable_dp(encoder, old_crtc_state, old_conn_state); 3163 } 3164 3165 static void g4x_post_disable_dp(struct intel_encoder *encoder, 3166 const struct intel_crtc_state *old_crtc_state, 3167 const struct drm_connector_state *old_conn_state) 3168 { 3169 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3170 enum port port = encoder->port; 3171 3172 /* 3173 * Bspec does not list a specific disable sequence for g4x DP. 3174 * Follow the ilk+ sequence (disable pipe before the port) for 3175 * g4x DP as it does not suffer from underruns like the normal 3176 * g4x modeset sequence (disable pipe after the port). 3177 */ 3178 intel_dp_link_down(encoder, old_crtc_state); 3179 3180 /* Only ilk+ has port A */ 3181 if (port == PORT_A) 3182 ironlake_edp_pll_off(intel_dp, old_crtc_state); 3183 } 3184 3185 static void vlv_post_disable_dp(struct intel_encoder *encoder, 3186 const struct intel_crtc_state *old_crtc_state, 3187 const struct drm_connector_state *old_conn_state) 3188 { 3189 intel_dp_link_down(encoder, old_crtc_state); 3190 } 3191 3192 static void chv_post_disable_dp(struct intel_encoder *encoder, 3193 const struct intel_crtc_state *old_crtc_state, 3194 const struct drm_connector_state *old_conn_state) 3195 { 3196 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3197 3198 intel_dp_link_down(encoder, old_crtc_state); 3199 3200 vlv_dpio_get(dev_priv); 3201 3202 /* Assert data lane reset */ 3203 chv_data_lane_soft_reset(encoder, old_crtc_state, true); 3204 3205 vlv_dpio_put(dev_priv); 3206 } 3207 3208 static void 3209 _intel_dp_set_link_train(struct intel_dp *intel_dp, 3210 u32 *DP, 3211 u8 dp_train_pat) 3212 { 3213 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3214 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3215 enum port port = intel_dig_port->base.port; 3216 u8 train_pat_mask = drm_dp_training_pattern_mask(intel_dp->dpcd); 3217 3218 if (dp_train_pat & train_pat_mask) 3219 DRM_DEBUG_KMS("Using DP training pattern TPS%d\n", 3220 dp_train_pat & train_pat_mask); 3221 3222 if (HAS_DDI(dev_priv)) { 3223 u32 temp = I915_READ(DP_TP_CTL(port)); 3224 3225 if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) 3226 temp |= DP_TP_CTL_SCRAMBLE_DISABLE; 3227 else 3228 temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; 3229 3230 temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3231 switch (dp_train_pat & train_pat_mask) { 3232 case DP_TRAINING_PATTERN_DISABLE: 3233 temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; 3234 3235 break; 3236 case DP_TRAINING_PATTERN_1: 3237 temp |= DP_TP_CTL_LINK_TRAIN_PAT1; 3238 break; 3239 case DP_TRAINING_PATTERN_2: 3240 temp |= DP_TP_CTL_LINK_TRAIN_PAT2; 3241 break; 3242 case DP_TRAINING_PATTERN_3: 3243 temp |= DP_TP_CTL_LINK_TRAIN_PAT3; 3244 break; 3245 case DP_TRAINING_PATTERN_4: 3246 temp |= DP_TP_CTL_LINK_TRAIN_PAT4; 3247 break; 3248 } 3249 I915_WRITE(DP_TP_CTL(port), temp); 3250 3251 } else if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || 3252 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { 3253 *DP &= ~DP_LINK_TRAIN_MASK_CPT; 3254 3255 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 3256 case DP_TRAINING_PATTERN_DISABLE: 3257 *DP |= DP_LINK_TRAIN_OFF_CPT; 3258 break; 3259 case DP_TRAINING_PATTERN_1: 3260 *DP |= DP_LINK_TRAIN_PAT_1_CPT; 3261 break; 3262 case DP_TRAINING_PATTERN_2: 3263 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 3264 break; 3265 case DP_TRAINING_PATTERN_3: 3266 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); 3267 *DP |= DP_LINK_TRAIN_PAT_2_CPT; 3268 break; 3269 } 3270 3271 } else { 3272 *DP &= ~DP_LINK_TRAIN_MASK; 3273 3274 switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { 3275 case DP_TRAINING_PATTERN_DISABLE: 3276 *DP |= DP_LINK_TRAIN_OFF; 3277 break; 3278 case DP_TRAINING_PATTERN_1: 3279 *DP |= DP_LINK_TRAIN_PAT_1; 3280 break; 3281 case DP_TRAINING_PATTERN_2: 3282 *DP |= DP_LINK_TRAIN_PAT_2; 3283 break; 3284 case DP_TRAINING_PATTERN_3: 3285 DRM_DEBUG_KMS("TPS3 not supported, using TPS2 instead\n"); 3286 *DP |= DP_LINK_TRAIN_PAT_2; 3287 break; 3288 } 3289 } 3290 } 3291 3292 static void intel_dp_enable_port(struct intel_dp *intel_dp, 3293 const struct intel_crtc_state *old_crtc_state) 3294 { 3295 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3296 3297 /* enable with pattern 1 (as per spec) */ 3298 3299 intel_dp_program_link_training_pattern(intel_dp, DP_TRAINING_PATTERN_1); 3300 3301 /* 3302 * Magic for VLV/CHV. We _must_ first set up the register 3303 * without actually enabling the port, and then do another 3304 * write to enable the port. Otherwise link training will 3305 * fail when the power sequencer is freshly used for this port. 3306 */ 3307 intel_dp->DP |= DP_PORT_EN; 3308 if (old_crtc_state->has_audio) 3309 intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; 3310 3311 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 3312 POSTING_READ(intel_dp->output_reg); 3313 } 3314 3315 static void intel_enable_dp(struct intel_encoder *encoder, 3316 const struct intel_crtc_state *pipe_config, 3317 const struct drm_connector_state *conn_state) 3318 { 3319 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3320 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3321 struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); 3322 u32 dp_reg = I915_READ(intel_dp->output_reg); 3323 enum pipe pipe = crtc->pipe; 3324 intel_wakeref_t wakeref; 3325 3326 if (WARN_ON(dp_reg & DP_PORT_EN)) 3327 return; 3328 3329 with_pps_lock(intel_dp, wakeref) { 3330 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3331 vlv_init_panel_power_sequencer(encoder, pipe_config); 3332 3333 intel_dp_enable_port(intel_dp, pipe_config); 3334 3335 edp_panel_vdd_on(intel_dp); 3336 edp_panel_on(intel_dp); 3337 edp_panel_vdd_off(intel_dp, true); 3338 } 3339 3340 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 3341 unsigned int lane_mask = 0x0; 3342 3343 if (IS_CHERRYVIEW(dev_priv)) 3344 lane_mask = intel_dp_unused_lane_mask(pipe_config->lane_count); 3345 3346 vlv_wait_port_ready(dev_priv, dp_to_dig_port(intel_dp), 3347 lane_mask); 3348 } 3349 3350 intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); 3351 intel_dp_start_link_train(intel_dp); 3352 intel_dp_stop_link_train(intel_dp); 3353 3354 if (pipe_config->has_audio) { 3355 DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", 3356 pipe_name(pipe)); 3357 intel_audio_codec_enable(encoder, pipe_config, conn_state); 3358 } 3359 } 3360 3361 static void g4x_enable_dp(struct intel_encoder *encoder, 3362 const struct intel_crtc_state *pipe_config, 3363 const struct drm_connector_state *conn_state) 3364 { 3365 intel_enable_dp(encoder, pipe_config, conn_state); 3366 intel_edp_backlight_on(pipe_config, conn_state); 3367 } 3368 3369 static void vlv_enable_dp(struct intel_encoder *encoder, 3370 const struct intel_crtc_state *pipe_config, 3371 const struct drm_connector_state *conn_state) 3372 { 3373 intel_edp_backlight_on(pipe_config, conn_state); 3374 } 3375 3376 static void g4x_pre_enable_dp(struct intel_encoder *encoder, 3377 const struct intel_crtc_state *pipe_config, 3378 const struct drm_connector_state *conn_state) 3379 { 3380 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3381 enum port port = encoder->port; 3382 3383 intel_dp_prepare(encoder, pipe_config); 3384 3385 /* Only ilk+ has port A */ 3386 if (port == PORT_A) 3387 ironlake_edp_pll_on(intel_dp, pipe_config); 3388 } 3389 3390 static void vlv_detach_power_sequencer(struct intel_dp *intel_dp) 3391 { 3392 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3393 struct drm_i915_private *dev_priv = to_i915(intel_dig_port->base.base.dev); 3394 enum pipe pipe = intel_dp->pps_pipe; 3395 i915_reg_t pp_on_reg = PP_ON_DELAYS(pipe); 3396 3397 WARN_ON(intel_dp->active_pipe != INVALID_PIPE); 3398 3399 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) 3400 return; 3401 3402 edp_panel_vdd_off_sync(intel_dp); 3403 3404 /* 3405 * VLV seems to get confused when multiple power sequencers 3406 * have the same port selected (even if only one has power/vdd 3407 * enabled). The failure manifests as vlv_wait_port_ready() failing 3408 * CHV on the other hand doesn't seem to mind having the same port 3409 * selected in multiple power sequencers, but let's clear the 3410 * port select always when logically disconnecting a power sequencer 3411 * from a port. 3412 */ 3413 DRM_DEBUG_KMS("detaching pipe %c power sequencer from port %c\n", 3414 pipe_name(pipe), port_name(intel_dig_port->base.port)); 3415 I915_WRITE(pp_on_reg, 0); 3416 POSTING_READ(pp_on_reg); 3417 3418 intel_dp->pps_pipe = INVALID_PIPE; 3419 } 3420 3421 static void vlv_steal_power_sequencer(struct drm_i915_private *dev_priv, 3422 enum pipe pipe) 3423 { 3424 struct intel_encoder *encoder; 3425 3426 lockdep_assert_held(&dev_priv->pps_mutex); 3427 3428 for_each_intel_dp(&dev_priv->drm, encoder) { 3429 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3430 enum port port = encoder->port; 3431 3432 WARN(intel_dp->active_pipe == pipe, 3433 "stealing pipe %c power sequencer from active (e)DP port %c\n", 3434 pipe_name(pipe), port_name(port)); 3435 3436 if (intel_dp->pps_pipe != pipe) 3437 continue; 3438 3439 DRM_DEBUG_KMS("stealing pipe %c power sequencer from port %c\n", 3440 pipe_name(pipe), port_name(port)); 3441 3442 /* make sure vdd is off before we steal it */ 3443 vlv_detach_power_sequencer(intel_dp); 3444 } 3445 } 3446 3447 static void vlv_init_panel_power_sequencer(struct intel_encoder *encoder, 3448 const struct intel_crtc_state *crtc_state) 3449 { 3450 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3451 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3452 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); 3453 3454 lockdep_assert_held(&dev_priv->pps_mutex); 3455 3456 WARN_ON(intel_dp->active_pipe != INVALID_PIPE); 3457 3458 if (intel_dp->pps_pipe != INVALID_PIPE && 3459 intel_dp->pps_pipe != crtc->pipe) { 3460 /* 3461 * If another power sequencer was being used on this 3462 * port previously make sure to turn off vdd there while 3463 * we still have control of it. 3464 */ 3465 vlv_detach_power_sequencer(intel_dp); 3466 } 3467 3468 /* 3469 * We may be stealing the power 3470 * sequencer from another port. 3471 */ 3472 vlv_steal_power_sequencer(dev_priv, crtc->pipe); 3473 3474 intel_dp->active_pipe = crtc->pipe; 3475 3476 if (!intel_dp_is_edp(intel_dp)) 3477 return; 3478 3479 /* now it's all ours */ 3480 intel_dp->pps_pipe = crtc->pipe; 3481 3482 DRM_DEBUG_KMS("initializing pipe %c power sequencer for port %c\n", 3483 pipe_name(intel_dp->pps_pipe), port_name(encoder->port)); 3484 3485 /* init power sequencer on this pipe and port */ 3486 intel_dp_init_panel_power_sequencer(intel_dp); 3487 intel_dp_init_panel_power_sequencer_registers(intel_dp, true); 3488 } 3489 3490 static void vlv_pre_enable_dp(struct intel_encoder *encoder, 3491 const struct intel_crtc_state *pipe_config, 3492 const struct drm_connector_state *conn_state) 3493 { 3494 vlv_phy_pre_encoder_enable(encoder, pipe_config); 3495 3496 intel_enable_dp(encoder, pipe_config, conn_state); 3497 } 3498 3499 static void vlv_dp_pre_pll_enable(struct intel_encoder *encoder, 3500 const struct intel_crtc_state *pipe_config, 3501 const struct drm_connector_state *conn_state) 3502 { 3503 intel_dp_prepare(encoder, pipe_config); 3504 3505 vlv_phy_pre_pll_enable(encoder, pipe_config); 3506 } 3507 3508 static void chv_pre_enable_dp(struct intel_encoder *encoder, 3509 const struct intel_crtc_state *pipe_config, 3510 const struct drm_connector_state *conn_state) 3511 { 3512 chv_phy_pre_encoder_enable(encoder, pipe_config); 3513 3514 intel_enable_dp(encoder, pipe_config, conn_state); 3515 3516 /* Second common lane will stay alive on its own now */ 3517 chv_phy_release_cl2_override(encoder); 3518 } 3519 3520 static void chv_dp_pre_pll_enable(struct intel_encoder *encoder, 3521 const struct intel_crtc_state *pipe_config, 3522 const struct drm_connector_state *conn_state) 3523 { 3524 intel_dp_prepare(encoder, pipe_config); 3525 3526 chv_phy_pre_pll_enable(encoder, pipe_config); 3527 } 3528 3529 static void chv_dp_post_pll_disable(struct intel_encoder *encoder, 3530 const struct intel_crtc_state *old_crtc_state, 3531 const struct drm_connector_state *old_conn_state) 3532 { 3533 chv_phy_post_pll_disable(encoder, old_crtc_state); 3534 } 3535 3536 /* 3537 * Fetch AUX CH registers 0x202 - 0x207 which contain 3538 * link status information 3539 */ 3540 bool 3541 intel_dp_get_link_status(struct intel_dp *intel_dp, u8 link_status[DP_LINK_STATUS_SIZE]) 3542 { 3543 return drm_dp_dpcd_read(&intel_dp->aux, DP_LANE0_1_STATUS, link_status, 3544 DP_LINK_STATUS_SIZE) == DP_LINK_STATUS_SIZE; 3545 } 3546 3547 /* These are source-specific values. */ 3548 u8 3549 intel_dp_voltage_max(struct intel_dp *intel_dp) 3550 { 3551 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3552 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3553 enum port port = encoder->port; 3554 3555 if (HAS_DDI(dev_priv)) 3556 return intel_ddi_dp_voltage_max(encoder); 3557 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 3558 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 3559 else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) 3560 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 3561 else if (HAS_PCH_CPT(dev_priv) && port != PORT_A) 3562 return DP_TRAIN_VOLTAGE_SWING_LEVEL_3; 3563 else 3564 return DP_TRAIN_VOLTAGE_SWING_LEVEL_2; 3565 } 3566 3567 u8 3568 intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, u8 voltage_swing) 3569 { 3570 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3571 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3572 enum port port = encoder->port; 3573 3574 if (HAS_DDI(dev_priv)) { 3575 return intel_ddi_dp_pre_emphasis_max(encoder, voltage_swing); 3576 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 3577 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 3578 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3579 return DP_TRAIN_PRE_EMPH_LEVEL_3; 3580 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3581 return DP_TRAIN_PRE_EMPH_LEVEL_2; 3582 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3583 return DP_TRAIN_PRE_EMPH_LEVEL_1; 3584 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3585 default: 3586 return DP_TRAIN_PRE_EMPH_LEVEL_0; 3587 } 3588 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { 3589 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 3590 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3591 return DP_TRAIN_PRE_EMPH_LEVEL_2; 3592 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3593 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3594 return DP_TRAIN_PRE_EMPH_LEVEL_1; 3595 default: 3596 return DP_TRAIN_PRE_EMPH_LEVEL_0; 3597 } 3598 } else { 3599 switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { 3600 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3601 return DP_TRAIN_PRE_EMPH_LEVEL_2; 3602 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3603 return DP_TRAIN_PRE_EMPH_LEVEL_2; 3604 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3605 return DP_TRAIN_PRE_EMPH_LEVEL_1; 3606 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3607 default: 3608 return DP_TRAIN_PRE_EMPH_LEVEL_0; 3609 } 3610 } 3611 } 3612 3613 static u32 vlv_signal_levels(struct intel_dp *intel_dp) 3614 { 3615 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3616 unsigned long demph_reg_value, preemph_reg_value, 3617 uniqtranscale_reg_value; 3618 u8 train_set = intel_dp->train_set[0]; 3619 3620 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 3621 case DP_TRAIN_PRE_EMPH_LEVEL_0: 3622 preemph_reg_value = 0x0004000; 3623 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3624 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3625 demph_reg_value = 0x2B405555; 3626 uniqtranscale_reg_value = 0x552AB83A; 3627 break; 3628 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3629 demph_reg_value = 0x2B404040; 3630 uniqtranscale_reg_value = 0x5548B83A; 3631 break; 3632 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3633 demph_reg_value = 0x2B245555; 3634 uniqtranscale_reg_value = 0x5560B83A; 3635 break; 3636 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3637 demph_reg_value = 0x2B405555; 3638 uniqtranscale_reg_value = 0x5598DA3A; 3639 break; 3640 default: 3641 return 0; 3642 } 3643 break; 3644 case DP_TRAIN_PRE_EMPH_LEVEL_1: 3645 preemph_reg_value = 0x0002000; 3646 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3647 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3648 demph_reg_value = 0x2B404040; 3649 uniqtranscale_reg_value = 0x5552B83A; 3650 break; 3651 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3652 demph_reg_value = 0x2B404848; 3653 uniqtranscale_reg_value = 0x5580B83A; 3654 break; 3655 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3656 demph_reg_value = 0x2B404040; 3657 uniqtranscale_reg_value = 0x55ADDA3A; 3658 break; 3659 default: 3660 return 0; 3661 } 3662 break; 3663 case DP_TRAIN_PRE_EMPH_LEVEL_2: 3664 preemph_reg_value = 0x0000000; 3665 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3666 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3667 demph_reg_value = 0x2B305555; 3668 uniqtranscale_reg_value = 0x5570B83A; 3669 break; 3670 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3671 demph_reg_value = 0x2B2B4040; 3672 uniqtranscale_reg_value = 0x55ADDA3A; 3673 break; 3674 default: 3675 return 0; 3676 } 3677 break; 3678 case DP_TRAIN_PRE_EMPH_LEVEL_3: 3679 preemph_reg_value = 0x0006000; 3680 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3681 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3682 demph_reg_value = 0x1B405555; 3683 uniqtranscale_reg_value = 0x55ADDA3A; 3684 break; 3685 default: 3686 return 0; 3687 } 3688 break; 3689 default: 3690 return 0; 3691 } 3692 3693 vlv_set_phy_signal_level(encoder, demph_reg_value, preemph_reg_value, 3694 uniqtranscale_reg_value, 0); 3695 3696 return 0; 3697 } 3698 3699 static u32 chv_signal_levels(struct intel_dp *intel_dp) 3700 { 3701 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 3702 u32 deemph_reg_value, margin_reg_value; 3703 bool uniq_trans_scale = false; 3704 u8 train_set = intel_dp->train_set[0]; 3705 3706 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 3707 case DP_TRAIN_PRE_EMPH_LEVEL_0: 3708 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3709 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3710 deemph_reg_value = 128; 3711 margin_reg_value = 52; 3712 break; 3713 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3714 deemph_reg_value = 128; 3715 margin_reg_value = 77; 3716 break; 3717 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3718 deemph_reg_value = 128; 3719 margin_reg_value = 102; 3720 break; 3721 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3722 deemph_reg_value = 128; 3723 margin_reg_value = 154; 3724 uniq_trans_scale = true; 3725 break; 3726 default: 3727 return 0; 3728 } 3729 break; 3730 case DP_TRAIN_PRE_EMPH_LEVEL_1: 3731 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3732 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3733 deemph_reg_value = 85; 3734 margin_reg_value = 78; 3735 break; 3736 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3737 deemph_reg_value = 85; 3738 margin_reg_value = 116; 3739 break; 3740 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3741 deemph_reg_value = 85; 3742 margin_reg_value = 154; 3743 break; 3744 default: 3745 return 0; 3746 } 3747 break; 3748 case DP_TRAIN_PRE_EMPH_LEVEL_2: 3749 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3750 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3751 deemph_reg_value = 64; 3752 margin_reg_value = 104; 3753 break; 3754 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3755 deemph_reg_value = 64; 3756 margin_reg_value = 154; 3757 break; 3758 default: 3759 return 0; 3760 } 3761 break; 3762 case DP_TRAIN_PRE_EMPH_LEVEL_3: 3763 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3764 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3765 deemph_reg_value = 43; 3766 margin_reg_value = 154; 3767 break; 3768 default: 3769 return 0; 3770 } 3771 break; 3772 default: 3773 return 0; 3774 } 3775 3776 chv_set_phy_signal_level(encoder, deemph_reg_value, 3777 margin_reg_value, uniq_trans_scale); 3778 3779 return 0; 3780 } 3781 3782 static u32 3783 g4x_signal_levels(u8 train_set) 3784 { 3785 u32 signal_levels = 0; 3786 3787 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { 3788 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0: 3789 default: 3790 signal_levels |= DP_VOLTAGE_0_4; 3791 break; 3792 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1: 3793 signal_levels |= DP_VOLTAGE_0_6; 3794 break; 3795 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2: 3796 signal_levels |= DP_VOLTAGE_0_8; 3797 break; 3798 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3: 3799 signal_levels |= DP_VOLTAGE_1_2; 3800 break; 3801 } 3802 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { 3803 case DP_TRAIN_PRE_EMPH_LEVEL_0: 3804 default: 3805 signal_levels |= DP_PRE_EMPHASIS_0; 3806 break; 3807 case DP_TRAIN_PRE_EMPH_LEVEL_1: 3808 signal_levels |= DP_PRE_EMPHASIS_3_5; 3809 break; 3810 case DP_TRAIN_PRE_EMPH_LEVEL_2: 3811 signal_levels |= DP_PRE_EMPHASIS_6; 3812 break; 3813 case DP_TRAIN_PRE_EMPH_LEVEL_3: 3814 signal_levels |= DP_PRE_EMPHASIS_9_5; 3815 break; 3816 } 3817 return signal_levels; 3818 } 3819 3820 /* SNB CPU eDP voltage swing and pre-emphasis control */ 3821 static u32 3822 snb_cpu_edp_signal_levels(u8 train_set) 3823 { 3824 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 3825 DP_TRAIN_PRE_EMPHASIS_MASK); 3826 switch (signal_levels) { 3827 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3828 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3829 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 3830 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3831 return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; 3832 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 3833 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_2: 3834 return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; 3835 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3836 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3837 return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; 3838 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3839 case DP_TRAIN_VOLTAGE_SWING_LEVEL_3 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3840 return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; 3841 default: 3842 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 3843 "0x%x\n", signal_levels); 3844 return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; 3845 } 3846 } 3847 3848 /* IVB CPU eDP voltage swing and pre-emphasis control */ 3849 static u32 3850 ivb_cpu_edp_signal_levels(u8 train_set) 3851 { 3852 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | 3853 DP_TRAIN_PRE_EMPHASIS_MASK); 3854 switch (signal_levels) { 3855 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3856 return EDP_LINK_TRAIN_400MV_0DB_IVB; 3857 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3858 return EDP_LINK_TRAIN_400MV_3_5DB_IVB; 3859 case DP_TRAIN_VOLTAGE_SWING_LEVEL_0 | DP_TRAIN_PRE_EMPH_LEVEL_2: 3860 return EDP_LINK_TRAIN_400MV_6DB_IVB; 3861 3862 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3863 return EDP_LINK_TRAIN_600MV_0DB_IVB; 3864 case DP_TRAIN_VOLTAGE_SWING_LEVEL_1 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3865 return EDP_LINK_TRAIN_600MV_3_5DB_IVB; 3866 3867 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_0: 3868 return EDP_LINK_TRAIN_800MV_0DB_IVB; 3869 case DP_TRAIN_VOLTAGE_SWING_LEVEL_2 | DP_TRAIN_PRE_EMPH_LEVEL_1: 3870 return EDP_LINK_TRAIN_800MV_3_5DB_IVB; 3871 3872 default: 3873 DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" 3874 "0x%x\n", signal_levels); 3875 return EDP_LINK_TRAIN_500MV_0DB_IVB; 3876 } 3877 } 3878 3879 void 3880 intel_dp_set_signal_levels(struct intel_dp *intel_dp) 3881 { 3882 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3883 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3884 enum port port = intel_dig_port->base.port; 3885 u32 signal_levels, mask = 0; 3886 u8 train_set = intel_dp->train_set[0]; 3887 3888 if (IS_GEN9_LP(dev_priv) || INTEL_GEN(dev_priv) >= 10) { 3889 signal_levels = bxt_signal_levels(intel_dp); 3890 } else if (HAS_DDI(dev_priv)) { 3891 signal_levels = ddi_signal_levels(intel_dp); 3892 mask = DDI_BUF_EMP_MASK; 3893 } else if (IS_CHERRYVIEW(dev_priv)) { 3894 signal_levels = chv_signal_levels(intel_dp); 3895 } else if (IS_VALLEYVIEW(dev_priv)) { 3896 signal_levels = vlv_signal_levels(intel_dp); 3897 } else if (IS_IVYBRIDGE(dev_priv) && port == PORT_A) { 3898 signal_levels = ivb_cpu_edp_signal_levels(train_set); 3899 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_IVB; 3900 } else if (IS_GEN(dev_priv, 6) && port == PORT_A) { 3901 signal_levels = snb_cpu_edp_signal_levels(train_set); 3902 mask = EDP_LINK_TRAIN_VOL_EMP_MASK_SNB; 3903 } else { 3904 signal_levels = g4x_signal_levels(train_set); 3905 mask = DP_VOLTAGE_MASK | DP_PRE_EMPHASIS_MASK; 3906 } 3907 3908 if (mask) 3909 DRM_DEBUG_KMS("Using signal levels %08x\n", signal_levels); 3910 3911 DRM_DEBUG_KMS("Using vswing level %d\n", 3912 train_set & DP_TRAIN_VOLTAGE_SWING_MASK); 3913 DRM_DEBUG_KMS("Using pre-emphasis level %d\n", 3914 (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) >> 3915 DP_TRAIN_PRE_EMPHASIS_SHIFT); 3916 3917 intel_dp->DP = (intel_dp->DP & ~mask) | signal_levels; 3918 3919 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 3920 POSTING_READ(intel_dp->output_reg); 3921 } 3922 3923 void 3924 intel_dp_program_link_training_pattern(struct intel_dp *intel_dp, 3925 u8 dp_train_pat) 3926 { 3927 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3928 struct drm_i915_private *dev_priv = 3929 to_i915(intel_dig_port->base.base.dev); 3930 3931 _intel_dp_set_link_train(intel_dp, &intel_dp->DP, dp_train_pat); 3932 3933 I915_WRITE(intel_dp->output_reg, intel_dp->DP); 3934 POSTING_READ(intel_dp->output_reg); 3935 } 3936 3937 void intel_dp_set_idle_link_train(struct intel_dp *intel_dp) 3938 { 3939 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 3940 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 3941 enum port port = intel_dig_port->base.port; 3942 u32 val; 3943 3944 if (!HAS_DDI(dev_priv)) 3945 return; 3946 3947 val = I915_READ(DP_TP_CTL(port)); 3948 val &= ~DP_TP_CTL_LINK_TRAIN_MASK; 3949 val |= DP_TP_CTL_LINK_TRAIN_IDLE; 3950 I915_WRITE(DP_TP_CTL(port), val); 3951 3952 /* 3953 * On PORT_A we can have only eDP in SST mode. There the only reason 3954 * we need to set idle transmission mode is to work around a HW issue 3955 * where we enable the pipe while not in idle link-training mode. 3956 * In this case there is requirement to wait for a minimum number of 3957 * idle patterns to be sent. 3958 */ 3959 if (port == PORT_A) 3960 return; 3961 3962 if (intel_wait_for_register(&dev_priv->uncore, DP_TP_STATUS(port), 3963 DP_TP_STATUS_IDLE_DONE, 3964 DP_TP_STATUS_IDLE_DONE, 3965 1)) 3966 DRM_ERROR("Timed out waiting for DP idle patterns\n"); 3967 } 3968 3969 static void 3970 intel_dp_link_down(struct intel_encoder *encoder, 3971 const struct intel_crtc_state *old_crtc_state) 3972 { 3973 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 3974 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 3975 struct intel_crtc *crtc = to_intel_crtc(old_crtc_state->base.crtc); 3976 enum port port = encoder->port; 3977 u32 DP = intel_dp->DP; 3978 3979 if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) 3980 return; 3981 3982 DRM_DEBUG_KMS("\n"); 3983 3984 if ((IS_IVYBRIDGE(dev_priv) && port == PORT_A) || 3985 (HAS_PCH_CPT(dev_priv) && port != PORT_A)) { 3986 DP &= ~DP_LINK_TRAIN_MASK_CPT; 3987 DP |= DP_LINK_TRAIN_PAT_IDLE_CPT; 3988 } else { 3989 DP &= ~DP_LINK_TRAIN_MASK; 3990 DP |= DP_LINK_TRAIN_PAT_IDLE; 3991 } 3992 I915_WRITE(intel_dp->output_reg, DP); 3993 POSTING_READ(intel_dp->output_reg); 3994 3995 DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); 3996 I915_WRITE(intel_dp->output_reg, DP); 3997 POSTING_READ(intel_dp->output_reg); 3998 3999 /* 4000 * HW workaround for IBX, we need to move the port 4001 * to transcoder A after disabling it to allow the 4002 * matching HDMI port to be enabled on transcoder A. 4003 */ 4004 if (HAS_PCH_IBX(dev_priv) && crtc->pipe == PIPE_B && port != PORT_A) { 4005 /* 4006 * We get CPU/PCH FIFO underruns on the other pipe when 4007 * doing the workaround. Sweep them under the rug. 4008 */ 4009 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, false); 4010 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, false); 4011 4012 /* always enable with pattern 1 (as per spec) */ 4013 DP &= ~(DP_PIPE_SEL_MASK | DP_LINK_TRAIN_MASK); 4014 DP |= DP_PORT_EN | DP_PIPE_SEL(PIPE_A) | 4015 DP_LINK_TRAIN_PAT_1; 4016 I915_WRITE(intel_dp->output_reg, DP); 4017 POSTING_READ(intel_dp->output_reg); 4018 4019 DP &= ~DP_PORT_EN; 4020 I915_WRITE(intel_dp->output_reg, DP); 4021 POSTING_READ(intel_dp->output_reg); 4022 4023 intel_wait_for_vblank_if_active(dev_priv, PIPE_A); 4024 intel_set_cpu_fifo_underrun_reporting(dev_priv, PIPE_A, true); 4025 intel_set_pch_fifo_underrun_reporting(dev_priv, PIPE_A, true); 4026 } 4027 4028 msleep(intel_dp->panel_power_down_delay); 4029 4030 intel_dp->DP = DP; 4031 4032 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 4033 intel_wakeref_t wakeref; 4034 4035 with_pps_lock(intel_dp, wakeref) 4036 intel_dp->active_pipe = INVALID_PIPE; 4037 } 4038 } 4039 4040 static void 4041 intel_dp_extended_receiver_capabilities(struct intel_dp *intel_dp) 4042 { 4043 u8 dpcd_ext[6]; 4044 4045 /* 4046 * Prior to DP1.3 the bit represented by 4047 * DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT was reserved. 4048 * if it is set DP_DPCD_REV at 0000h could be at a value less than 4049 * the true capability of the panel. The only way to check is to 4050 * then compare 0000h and 2200h. 4051 */ 4052 if (!(intel_dp->dpcd[DP_TRAINING_AUX_RD_INTERVAL] & 4053 DP_EXTENDED_RECEIVER_CAP_FIELD_PRESENT)) 4054 return; 4055 4056 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DP13_DPCD_REV, 4057 &dpcd_ext, sizeof(dpcd_ext)) != sizeof(dpcd_ext)) { 4058 DRM_ERROR("DPCD failed read at extended capabilities\n"); 4059 return; 4060 } 4061 4062 if (intel_dp->dpcd[DP_DPCD_REV] > dpcd_ext[DP_DPCD_REV]) { 4063 DRM_DEBUG_KMS("DPCD extended DPCD rev less than base DPCD rev\n"); 4064 return; 4065 } 4066 4067 if (!memcmp(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext))) 4068 return; 4069 4070 DRM_DEBUG_KMS("Base DPCD: %*ph\n", 4071 (int)sizeof(intel_dp->dpcd), intel_dp->dpcd); 4072 4073 memcpy(intel_dp->dpcd, dpcd_ext, sizeof(dpcd_ext)); 4074 } 4075 4076 bool 4077 intel_dp_read_dpcd(struct intel_dp *intel_dp) 4078 { 4079 if (drm_dp_dpcd_read(&intel_dp->aux, 0x000, intel_dp->dpcd, 4080 sizeof(intel_dp->dpcd)) < 0) 4081 return false; /* aux transfer failed */ 4082 4083 intel_dp_extended_receiver_capabilities(intel_dp); 4084 4085 DRM_DEBUG_KMS("DPCD: %*ph\n", (int) sizeof(intel_dp->dpcd), intel_dp->dpcd); 4086 4087 return intel_dp->dpcd[DP_DPCD_REV] != 0; 4088 } 4089 4090 bool intel_dp_get_colorimetry_status(struct intel_dp *intel_dp) 4091 { 4092 u8 dprx = 0; 4093 4094 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_DPRX_FEATURE_ENUMERATION_LIST, 4095 &dprx) != 1) 4096 return false; 4097 return dprx & DP_VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED; 4098 } 4099 4100 static void intel_dp_get_dsc_sink_cap(struct intel_dp *intel_dp) 4101 { 4102 /* 4103 * Clear the cached register set to avoid using stale values 4104 * for the sinks that do not support DSC. 4105 */ 4106 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); 4107 4108 /* Clear fec_capable to avoid using stale values */ 4109 intel_dp->fec_capable = 0; 4110 4111 /* Cache the DSC DPCD if eDP or DP rev >= 1.4 */ 4112 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x14 || 4113 intel_dp->edp_dpcd[0] >= DP_EDP_14) { 4114 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DSC_SUPPORT, 4115 intel_dp->dsc_dpcd, 4116 sizeof(intel_dp->dsc_dpcd)) < 0) 4117 DRM_ERROR("Failed to read DPCD register 0x%x\n", 4118 DP_DSC_SUPPORT); 4119 4120 DRM_DEBUG_KMS("DSC DPCD: %*ph\n", 4121 (int)sizeof(intel_dp->dsc_dpcd), 4122 intel_dp->dsc_dpcd); 4123 4124 /* FEC is supported only on DP 1.4 */ 4125 if (!intel_dp_is_edp(intel_dp) && 4126 drm_dp_dpcd_readb(&intel_dp->aux, DP_FEC_CAPABILITY, 4127 &intel_dp->fec_capable) < 0) 4128 DRM_ERROR("Failed to read FEC DPCD register\n"); 4129 4130 DRM_DEBUG_KMS("FEC CAPABILITY: %x\n", intel_dp->fec_capable); 4131 } 4132 } 4133 4134 static bool 4135 intel_edp_init_dpcd(struct intel_dp *intel_dp) 4136 { 4137 struct drm_i915_private *dev_priv = 4138 to_i915(dp_to_dig_port(intel_dp)->base.base.dev); 4139 4140 /* this function is meant to be called only once */ 4141 WARN_ON(intel_dp->dpcd[DP_DPCD_REV] != 0); 4142 4143 if (!intel_dp_read_dpcd(intel_dp)) 4144 return false; 4145 4146 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 4147 drm_dp_is_branch(intel_dp->dpcd)); 4148 4149 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) 4150 dev_priv->no_aux_handshake = intel_dp->dpcd[DP_MAX_DOWNSPREAD] & 4151 DP_NO_AUX_HANDSHAKE_LINK_TRAINING; 4152 4153 /* 4154 * Read the eDP display control registers. 4155 * 4156 * Do this independent of DP_DPCD_DISPLAY_CONTROL_CAPABLE bit in 4157 * DP_EDP_CONFIGURATION_CAP, because some buggy displays do not have it 4158 * set, but require eDP 1.4+ detection (e.g. for supported link rates 4159 * method). The display control registers should read zero if they're 4160 * not supported anyway. 4161 */ 4162 if (drm_dp_dpcd_read(&intel_dp->aux, DP_EDP_DPCD_REV, 4163 intel_dp->edp_dpcd, sizeof(intel_dp->edp_dpcd)) == 4164 sizeof(intel_dp->edp_dpcd)) 4165 DRM_DEBUG_KMS("eDP DPCD: %*ph\n", (int) sizeof(intel_dp->edp_dpcd), 4166 intel_dp->edp_dpcd); 4167 4168 /* 4169 * This has to be called after intel_dp->edp_dpcd is filled, PSR checks 4170 * for SET_POWER_CAPABLE bit in intel_dp->edp_dpcd[1] 4171 */ 4172 intel_psr_init_dpcd(intel_dp); 4173 4174 /* Read the eDP 1.4+ supported link rates. */ 4175 if (intel_dp->edp_dpcd[0] >= DP_EDP_14) { 4176 __le16 sink_rates[DP_MAX_SUPPORTED_RATES]; 4177 int i; 4178 4179 drm_dp_dpcd_read(&intel_dp->aux, DP_SUPPORTED_LINK_RATES, 4180 sink_rates, sizeof(sink_rates)); 4181 4182 for (i = 0; i < ARRAY_SIZE(sink_rates); i++) { 4183 int val = le16_to_cpu(sink_rates[i]); 4184 4185 if (val == 0) 4186 break; 4187 4188 /* Value read multiplied by 200kHz gives the per-lane 4189 * link rate in kHz. The source rates are, however, 4190 * stored in terms of LS_Clk kHz. The full conversion 4191 * back to symbols is 4192 * (val * 200kHz)*(8/10 ch. encoding)*(1/8 bit to Byte) 4193 */ 4194 intel_dp->sink_rates[i] = (val * 200) / 10; 4195 } 4196 intel_dp->num_sink_rates = i; 4197 } 4198 4199 /* 4200 * Use DP_LINK_RATE_SET if DP_SUPPORTED_LINK_RATES are available, 4201 * default to DP_MAX_LINK_RATE and DP_LINK_BW_SET otherwise. 4202 */ 4203 if (intel_dp->num_sink_rates) 4204 intel_dp->use_rate_select = true; 4205 else 4206 intel_dp_set_sink_rates(intel_dp); 4207 4208 intel_dp_set_common_rates(intel_dp); 4209 4210 /* Read the eDP DSC DPCD registers */ 4211 if (INTEL_GEN(dev_priv) >= 10 || IS_GEMINILAKE(dev_priv)) 4212 intel_dp_get_dsc_sink_cap(intel_dp); 4213 4214 return true; 4215 } 4216 4217 4218 static bool 4219 intel_dp_get_dpcd(struct intel_dp *intel_dp) 4220 { 4221 if (!intel_dp_read_dpcd(intel_dp)) 4222 return false; 4223 4224 /* 4225 * Don't clobber cached eDP rates. Also skip re-reading 4226 * the OUI/ID since we know it won't change. 4227 */ 4228 if (!intel_dp_is_edp(intel_dp)) { 4229 drm_dp_read_desc(&intel_dp->aux, &intel_dp->desc, 4230 drm_dp_is_branch(intel_dp->dpcd)); 4231 4232 intel_dp_set_sink_rates(intel_dp); 4233 intel_dp_set_common_rates(intel_dp); 4234 } 4235 4236 /* 4237 * Some eDP panels do not set a valid value for sink count, that is why 4238 * it don't care about read it here and in intel_edp_init_dpcd(). 4239 */ 4240 if (!intel_dp_is_edp(intel_dp) && 4241 !drm_dp_has_quirk(&intel_dp->desc, DP_DPCD_QUIRK_NO_SINK_COUNT)) { 4242 u8 count; 4243 ssize_t r; 4244 4245 r = drm_dp_dpcd_readb(&intel_dp->aux, DP_SINK_COUNT, &count); 4246 if (r < 1) 4247 return false; 4248 4249 /* 4250 * Sink count can change between short pulse hpd hence 4251 * a member variable in intel_dp will track any changes 4252 * between short pulse interrupts. 4253 */ 4254 intel_dp->sink_count = DP_GET_SINK_COUNT(count); 4255 4256 /* 4257 * SINK_COUNT == 0 and DOWNSTREAM_PORT_PRESENT == 1 implies that 4258 * a dongle is present but no display. Unless we require to know 4259 * if a dongle is present or not, we don't need to update 4260 * downstream port information. So, an early return here saves 4261 * time from performing other operations which are not required. 4262 */ 4263 if (!intel_dp->sink_count) 4264 return false; 4265 } 4266 4267 if (!drm_dp_is_branch(intel_dp->dpcd)) 4268 return true; /* native DP sink */ 4269 4270 if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) 4271 return true; /* no per-port downstream info */ 4272 4273 if (drm_dp_dpcd_read(&intel_dp->aux, DP_DOWNSTREAM_PORT_0, 4274 intel_dp->downstream_ports, 4275 DP_MAX_DOWNSTREAM_PORTS) < 0) 4276 return false; /* downstream port status fetch failed */ 4277 4278 return true; 4279 } 4280 4281 static bool 4282 intel_dp_sink_can_mst(struct intel_dp *intel_dp) 4283 { 4284 u8 mstm_cap; 4285 4286 if (intel_dp->dpcd[DP_DPCD_REV] < 0x12) 4287 return false; 4288 4289 if (drm_dp_dpcd_readb(&intel_dp->aux, DP_MSTM_CAP, &mstm_cap) != 1) 4290 return false; 4291 4292 return mstm_cap & DP_MST_CAP; 4293 } 4294 4295 static bool 4296 intel_dp_can_mst(struct intel_dp *intel_dp) 4297 { 4298 return i915_modparams.enable_dp_mst && 4299 intel_dp->can_mst && 4300 intel_dp_sink_can_mst(intel_dp); 4301 } 4302 4303 static void 4304 intel_dp_configure_mst(struct intel_dp *intel_dp) 4305 { 4306 struct intel_encoder *encoder = 4307 &dp_to_dig_port(intel_dp)->base; 4308 bool sink_can_mst = intel_dp_sink_can_mst(intel_dp); 4309 4310 DRM_DEBUG_KMS("MST support? port %c: %s, sink: %s, modparam: %s\n", 4311 port_name(encoder->port), yesno(intel_dp->can_mst), 4312 yesno(sink_can_mst), yesno(i915_modparams.enable_dp_mst)); 4313 4314 if (!intel_dp->can_mst) 4315 return; 4316 4317 intel_dp->is_mst = sink_can_mst && 4318 i915_modparams.enable_dp_mst; 4319 4320 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 4321 intel_dp->is_mst); 4322 } 4323 4324 static bool 4325 intel_dp_get_sink_irq_esi(struct intel_dp *intel_dp, u8 *sink_irq_vector) 4326 { 4327 return drm_dp_dpcd_read(&intel_dp->aux, DP_SINK_COUNT_ESI, 4328 sink_irq_vector, DP_DPRX_ESI_LEN) == 4329 DP_DPRX_ESI_LEN; 4330 } 4331 4332 u16 intel_dp_dsc_get_output_bpp(int link_clock, u8 lane_count, 4333 int mode_clock, int mode_hdisplay) 4334 { 4335 u16 bits_per_pixel, max_bpp_small_joiner_ram; 4336 int i; 4337 4338 /* 4339 * Available Link Bandwidth(Kbits/sec) = (NumberOfLanes)* 4340 * (LinkSymbolClock)* 8 * ((100-FECOverhead)/100)*(TimeSlotsPerMTP) 4341 * FECOverhead = 2.4%, for SST -> TimeSlotsPerMTP is 1, 4342 * for MST -> TimeSlotsPerMTP has to be calculated 4343 */ 4344 bits_per_pixel = (link_clock * lane_count * 8 * 4345 DP_DSC_FEC_OVERHEAD_FACTOR) / 4346 mode_clock; 4347 4348 /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ 4349 max_bpp_small_joiner_ram = DP_DSC_MAX_SMALL_JOINER_RAM_BUFFER / 4350 mode_hdisplay; 4351 4352 /* 4353 * Greatest allowed DSC BPP = MIN (output BPP from avaialble Link BW 4354 * check, output bpp from small joiner RAM check) 4355 */ 4356 bits_per_pixel = min(bits_per_pixel, max_bpp_small_joiner_ram); 4357 4358 /* Error out if the max bpp is less than smallest allowed valid bpp */ 4359 if (bits_per_pixel < valid_dsc_bpp[0]) { 4360 DRM_DEBUG_KMS("Unsupported BPP %d\n", bits_per_pixel); 4361 return 0; 4362 } 4363 4364 /* Find the nearest match in the array of known BPPs from VESA */ 4365 for (i = 0; i < ARRAY_SIZE(valid_dsc_bpp) - 1; i++) { 4366 if (bits_per_pixel < valid_dsc_bpp[i + 1]) 4367 break; 4368 } 4369 bits_per_pixel = valid_dsc_bpp[i]; 4370 4371 /* 4372 * Compressed BPP in U6.4 format so multiply by 16, for Gen 11, 4373 * fractional part is 0 4374 */ 4375 return bits_per_pixel << 4; 4376 } 4377 4378 u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, 4379 int mode_clock, 4380 int mode_hdisplay) 4381 { 4382 u8 min_slice_count, i; 4383 int max_slice_width; 4384 4385 if (mode_clock <= DP_DSC_PEAK_PIXEL_RATE) 4386 min_slice_count = DIV_ROUND_UP(mode_clock, 4387 DP_DSC_MAX_ENC_THROUGHPUT_0); 4388 else 4389 min_slice_count = DIV_ROUND_UP(mode_clock, 4390 DP_DSC_MAX_ENC_THROUGHPUT_1); 4391 4392 max_slice_width = drm_dp_dsc_sink_max_slice_width(intel_dp->dsc_dpcd); 4393 if (max_slice_width < DP_DSC_MIN_SLICE_WIDTH_VALUE) { 4394 DRM_DEBUG_KMS("Unsupported slice width %d by DP DSC Sink device\n", 4395 max_slice_width); 4396 return 0; 4397 } 4398 /* Also take into account max slice width */ 4399 min_slice_count = min_t(u8, min_slice_count, 4400 DIV_ROUND_UP(mode_hdisplay, 4401 max_slice_width)); 4402 4403 /* Find the closest match to the valid slice count values */ 4404 for (i = 0; i < ARRAY_SIZE(valid_dsc_slicecount); i++) { 4405 if (valid_dsc_slicecount[i] > 4406 drm_dp_dsc_sink_max_slice_count(intel_dp->dsc_dpcd, 4407 false)) 4408 break; 4409 if (min_slice_count <= valid_dsc_slicecount[i]) 4410 return valid_dsc_slicecount[i]; 4411 } 4412 4413 DRM_DEBUG_KMS("Unsupported Slice Count %d\n", min_slice_count); 4414 return 0; 4415 } 4416 4417 static void 4418 intel_pixel_encoding_setup_vsc(struct intel_dp *intel_dp, 4419 const struct intel_crtc_state *crtc_state) 4420 { 4421 struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp); 4422 struct dp_sdp vsc_sdp = {}; 4423 4424 /* Prepare VSC Header for SU as per DP 1.4a spec, Table 2-119 */ 4425 vsc_sdp.sdp_header.HB0 = 0; 4426 vsc_sdp.sdp_header.HB1 = 0x7; 4427 4428 /* 4429 * VSC SDP supporting 3D stereo, PSR2, and Pixel Encoding/ 4430 * Colorimetry Format indication. 4431 */ 4432 vsc_sdp.sdp_header.HB2 = 0x5; 4433 4434 /* 4435 * VSC SDP supporting 3D stereo, + PSR2, + Pixel Encoding/ 4436 * Colorimetry Format indication (HB2 = 05h). 4437 */ 4438 vsc_sdp.sdp_header.HB3 = 0x13; 4439 4440 /* 4441 * YCbCr 420 = 3h DB16[7:4] ITU-R BT.601 = 0h, ITU-R BT.709 = 1h 4442 * DB16[3:0] DP 1.4a spec, Table 2-120 4443 */ 4444 vsc_sdp.db[16] = 0x3 << 4; /* 0x3 << 4 , YCbCr 420*/ 4445 /* RGB->YCBCR color conversion uses the BT.709 color space. */ 4446 vsc_sdp.db[16] |= 0x1; /* 0x1, ITU-R BT.709 */ 4447 4448 /* 4449 * For pixel encoding formats YCbCr444, YCbCr422, YCbCr420, and Y Only, 4450 * the following Component Bit Depth values are defined: 4451 * 001b = 8bpc. 4452 * 010b = 10bpc. 4453 * 011b = 12bpc. 4454 * 100b = 16bpc. 4455 */ 4456 switch (crtc_state->pipe_bpp) { 4457 case 24: /* 8bpc */ 4458 vsc_sdp.db[17] = 0x1; 4459 break; 4460 case 30: /* 10bpc */ 4461 vsc_sdp.db[17] = 0x2; 4462 break; 4463 case 36: /* 12bpc */ 4464 vsc_sdp.db[17] = 0x3; 4465 break; 4466 case 48: /* 16bpc */ 4467 vsc_sdp.db[17] = 0x4; 4468 break; 4469 default: 4470 MISSING_CASE(crtc_state->pipe_bpp); 4471 break; 4472 } 4473 4474 /* 4475 * Dynamic Range (Bit 7) 4476 * 0 = VESA range, 1 = CTA range. 4477 * all YCbCr are always limited range 4478 */ 4479 vsc_sdp.db[17] |= 0x80; 4480 4481 /* 4482 * Content Type (Bits 2:0) 4483 * 000b = Not defined. 4484 * 001b = Graphics. 4485 * 010b = Photo. 4486 * 011b = Video. 4487 * 100b = Game 4488 * All other values are RESERVED. 4489 * Note: See CTA-861-G for the definition and expected 4490 * processing by a stream sink for the above contect types. 4491 */ 4492 vsc_sdp.db[18] = 0; 4493 4494 intel_dig_port->write_infoframe(&intel_dig_port->base, 4495 crtc_state, DP_SDP_VSC, &vsc_sdp, sizeof(vsc_sdp)); 4496 } 4497 4498 void intel_dp_ycbcr_420_enable(struct intel_dp *intel_dp, 4499 const struct intel_crtc_state *crtc_state) 4500 { 4501 if (crtc_state->output_format != INTEL_OUTPUT_FORMAT_YCBCR420) 4502 return; 4503 4504 intel_pixel_encoding_setup_vsc(intel_dp, crtc_state); 4505 } 4506 4507 static u8 intel_dp_autotest_link_training(struct intel_dp *intel_dp) 4508 { 4509 int status = 0; 4510 int test_link_rate; 4511 u8 test_lane_count, test_link_bw; 4512 /* (DP CTS 1.2) 4513 * 4.3.1.11 4514 */ 4515 /* Read the TEST_LANE_COUNT and TEST_LINK_RTAE fields (DP CTS 3.1.4) */ 4516 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LANE_COUNT, 4517 &test_lane_count); 4518 4519 if (status <= 0) { 4520 DRM_DEBUG_KMS("Lane count read failed\n"); 4521 return DP_TEST_NAK; 4522 } 4523 test_lane_count &= DP_MAX_LANE_COUNT_MASK; 4524 4525 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_LINK_RATE, 4526 &test_link_bw); 4527 if (status <= 0) { 4528 DRM_DEBUG_KMS("Link Rate read failed\n"); 4529 return DP_TEST_NAK; 4530 } 4531 test_link_rate = drm_dp_bw_code_to_link_rate(test_link_bw); 4532 4533 /* Validate the requested link rate and lane count */ 4534 if (!intel_dp_link_params_valid(intel_dp, test_link_rate, 4535 test_lane_count)) 4536 return DP_TEST_NAK; 4537 4538 intel_dp->compliance.test_lane_count = test_lane_count; 4539 intel_dp->compliance.test_link_rate = test_link_rate; 4540 4541 return DP_TEST_ACK; 4542 } 4543 4544 static u8 intel_dp_autotest_video_pattern(struct intel_dp *intel_dp) 4545 { 4546 u8 test_pattern; 4547 u8 test_misc; 4548 __be16 h_width, v_height; 4549 int status = 0; 4550 4551 /* Read the TEST_PATTERN (DP CTS 3.1.5) */ 4552 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_PATTERN, 4553 &test_pattern); 4554 if (status <= 0) { 4555 DRM_DEBUG_KMS("Test pattern read failed\n"); 4556 return DP_TEST_NAK; 4557 } 4558 if (test_pattern != DP_COLOR_RAMP) 4559 return DP_TEST_NAK; 4560 4561 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_H_WIDTH_HI, 4562 &h_width, 2); 4563 if (status <= 0) { 4564 DRM_DEBUG_KMS("H Width read failed\n"); 4565 return DP_TEST_NAK; 4566 } 4567 4568 status = drm_dp_dpcd_read(&intel_dp->aux, DP_TEST_V_HEIGHT_HI, 4569 &v_height, 2); 4570 if (status <= 0) { 4571 DRM_DEBUG_KMS("V Height read failed\n"); 4572 return DP_TEST_NAK; 4573 } 4574 4575 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_MISC0, 4576 &test_misc); 4577 if (status <= 0) { 4578 DRM_DEBUG_KMS("TEST MISC read failed\n"); 4579 return DP_TEST_NAK; 4580 } 4581 if ((test_misc & DP_TEST_COLOR_FORMAT_MASK) != DP_COLOR_FORMAT_RGB) 4582 return DP_TEST_NAK; 4583 if (test_misc & DP_TEST_DYNAMIC_RANGE_CEA) 4584 return DP_TEST_NAK; 4585 switch (test_misc & DP_TEST_BIT_DEPTH_MASK) { 4586 case DP_TEST_BIT_DEPTH_6: 4587 intel_dp->compliance.test_data.bpc = 6; 4588 break; 4589 case DP_TEST_BIT_DEPTH_8: 4590 intel_dp->compliance.test_data.bpc = 8; 4591 break; 4592 default: 4593 return DP_TEST_NAK; 4594 } 4595 4596 intel_dp->compliance.test_data.video_pattern = test_pattern; 4597 intel_dp->compliance.test_data.hdisplay = be16_to_cpu(h_width); 4598 intel_dp->compliance.test_data.vdisplay = be16_to_cpu(v_height); 4599 /* Set test active flag here so userspace doesn't interrupt things */ 4600 intel_dp->compliance.test_active = 1; 4601 4602 return DP_TEST_ACK; 4603 } 4604 4605 static u8 intel_dp_autotest_edid(struct intel_dp *intel_dp) 4606 { 4607 u8 test_result = DP_TEST_ACK; 4608 struct intel_connector *intel_connector = intel_dp->attached_connector; 4609 struct drm_connector *connector = &intel_connector->base; 4610 4611 if (intel_connector->detect_edid == NULL || 4612 connector->edid_corrupt || 4613 intel_dp->aux.i2c_defer_count > 6) { 4614 /* Check EDID read for NACKs, DEFERs and corruption 4615 * (DP CTS 1.2 Core r1.1) 4616 * 4.2.2.4 : Failed EDID read, I2C_NAK 4617 * 4.2.2.5 : Failed EDID read, I2C_DEFER 4618 * 4.2.2.6 : EDID corruption detected 4619 * Use failsafe mode for all cases 4620 */ 4621 if (intel_dp->aux.i2c_nack_count > 0 || 4622 intel_dp->aux.i2c_defer_count > 0) 4623 DRM_DEBUG_KMS("EDID read had %d NACKs, %d DEFERs\n", 4624 intel_dp->aux.i2c_nack_count, 4625 intel_dp->aux.i2c_defer_count); 4626 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_FAILSAFE; 4627 } else { 4628 struct edid *block = intel_connector->detect_edid; 4629 4630 /* We have to write the checksum 4631 * of the last block read 4632 */ 4633 block += intel_connector->detect_edid->extensions; 4634 4635 if (drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_EDID_CHECKSUM, 4636 block->checksum) <= 0) 4637 DRM_DEBUG_KMS("Failed to write EDID checksum\n"); 4638 4639 test_result = DP_TEST_ACK | DP_TEST_EDID_CHECKSUM_WRITE; 4640 intel_dp->compliance.test_data.edid = INTEL_DP_RESOLUTION_PREFERRED; 4641 } 4642 4643 /* Set test active flag here so userspace doesn't interrupt things */ 4644 intel_dp->compliance.test_active = 1; 4645 4646 return test_result; 4647 } 4648 4649 static u8 intel_dp_autotest_phy_pattern(struct intel_dp *intel_dp) 4650 { 4651 u8 test_result = DP_TEST_NAK; 4652 return test_result; 4653 } 4654 4655 static void intel_dp_handle_test_request(struct intel_dp *intel_dp) 4656 { 4657 u8 response = DP_TEST_NAK; 4658 u8 request = 0; 4659 int status; 4660 4661 status = drm_dp_dpcd_readb(&intel_dp->aux, DP_TEST_REQUEST, &request); 4662 if (status <= 0) { 4663 DRM_DEBUG_KMS("Could not read test request from sink\n"); 4664 goto update_status; 4665 } 4666 4667 switch (request) { 4668 case DP_TEST_LINK_TRAINING: 4669 DRM_DEBUG_KMS("LINK_TRAINING test requested\n"); 4670 response = intel_dp_autotest_link_training(intel_dp); 4671 break; 4672 case DP_TEST_LINK_VIDEO_PATTERN: 4673 DRM_DEBUG_KMS("TEST_PATTERN test requested\n"); 4674 response = intel_dp_autotest_video_pattern(intel_dp); 4675 break; 4676 case DP_TEST_LINK_EDID_READ: 4677 DRM_DEBUG_KMS("EDID test requested\n"); 4678 response = intel_dp_autotest_edid(intel_dp); 4679 break; 4680 case DP_TEST_LINK_PHY_TEST_PATTERN: 4681 DRM_DEBUG_KMS("PHY_PATTERN test requested\n"); 4682 response = intel_dp_autotest_phy_pattern(intel_dp); 4683 break; 4684 default: 4685 DRM_DEBUG_KMS("Invalid test request '%02x'\n", request); 4686 break; 4687 } 4688 4689 if (response & DP_TEST_ACK) 4690 intel_dp->compliance.test_type = request; 4691 4692 update_status: 4693 status = drm_dp_dpcd_writeb(&intel_dp->aux, DP_TEST_RESPONSE, response); 4694 if (status <= 0) 4695 DRM_DEBUG_KMS("Could not write test response to sink\n"); 4696 } 4697 4698 static int 4699 intel_dp_check_mst_status(struct intel_dp *intel_dp) 4700 { 4701 bool bret; 4702 4703 if (intel_dp->is_mst) { 4704 u8 esi[DP_DPRX_ESI_LEN] = { 0 }; 4705 int ret = 0; 4706 int retry; 4707 bool handled; 4708 4709 WARN_ON_ONCE(intel_dp->active_mst_links < 0); 4710 bret = intel_dp_get_sink_irq_esi(intel_dp, esi); 4711 go_again: 4712 if (bret == true) { 4713 4714 /* check link status - esi[10] = 0x200c */ 4715 if (intel_dp->active_mst_links > 0 && 4716 !drm_dp_channel_eq_ok(&esi[10], intel_dp->lane_count)) { 4717 DRM_DEBUG_KMS("channel EQ not ok, retraining\n"); 4718 intel_dp_start_link_train(intel_dp); 4719 intel_dp_stop_link_train(intel_dp); 4720 } 4721 4722 DRM_DEBUG_KMS("got esi %3ph\n", esi); 4723 ret = drm_dp_mst_hpd_irq(&intel_dp->mst_mgr, esi, &handled); 4724 4725 if (handled) { 4726 for (retry = 0; retry < 3; retry++) { 4727 int wret; 4728 wret = drm_dp_dpcd_write(&intel_dp->aux, 4729 DP_SINK_COUNT_ESI+1, 4730 &esi[1], 3); 4731 if (wret == 3) { 4732 break; 4733 } 4734 } 4735 4736 bret = intel_dp_get_sink_irq_esi(intel_dp, esi); 4737 if (bret == true) { 4738 DRM_DEBUG_KMS("got esi2 %3ph\n", esi); 4739 goto go_again; 4740 } 4741 } else 4742 ret = 0; 4743 4744 return ret; 4745 } else { 4746 DRM_DEBUG_KMS("failed to get ESI - device may have failed\n"); 4747 intel_dp->is_mst = false; 4748 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 4749 intel_dp->is_mst); 4750 } 4751 } 4752 return -EINVAL; 4753 } 4754 4755 static bool 4756 intel_dp_needs_link_retrain(struct intel_dp *intel_dp) 4757 { 4758 u8 link_status[DP_LINK_STATUS_SIZE]; 4759 4760 if (!intel_dp->link_trained) 4761 return false; 4762 4763 /* 4764 * While PSR source HW is enabled, it will control main-link sending 4765 * frames, enabling and disabling it so trying to do a retrain will fail 4766 * as the link would or not be on or it could mix training patterns 4767 * and frame data at the same time causing retrain to fail. 4768 * Also when exiting PSR, HW will retrain the link anyways fixing 4769 * any link status error. 4770 */ 4771 if (intel_psr_enabled(intel_dp)) 4772 return false; 4773 4774 if (!intel_dp_get_link_status(intel_dp, link_status)) 4775 return false; 4776 4777 /* 4778 * Validate the cached values of intel_dp->link_rate and 4779 * intel_dp->lane_count before attempting to retrain. 4780 */ 4781 if (!intel_dp_link_params_valid(intel_dp, intel_dp->link_rate, 4782 intel_dp->lane_count)) 4783 return false; 4784 4785 /* Retrain if Channel EQ or CR not ok */ 4786 return !drm_dp_channel_eq_ok(link_status, intel_dp->lane_count); 4787 } 4788 4789 int intel_dp_retrain_link(struct intel_encoder *encoder, 4790 struct drm_modeset_acquire_ctx *ctx) 4791 { 4792 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 4793 struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); 4794 struct intel_connector *connector = intel_dp->attached_connector; 4795 struct drm_connector_state *conn_state; 4796 struct intel_crtc_state *crtc_state; 4797 struct intel_crtc *crtc; 4798 int ret; 4799 4800 /* FIXME handle the MST connectors as well */ 4801 4802 if (!connector || connector->base.status != connector_status_connected) 4803 return 0; 4804 4805 ret = drm_modeset_lock(&dev_priv->drm.mode_config.connection_mutex, 4806 ctx); 4807 if (ret) 4808 return ret; 4809 4810 conn_state = connector->base.state; 4811 4812 crtc = to_intel_crtc(conn_state->crtc); 4813 if (!crtc) 4814 return 0; 4815 4816 ret = drm_modeset_lock(&crtc->base.mutex, ctx); 4817 if (ret) 4818 return ret; 4819 4820 crtc_state = to_intel_crtc_state(crtc->base.state); 4821 4822 WARN_ON(!intel_crtc_has_dp_encoder(crtc_state)); 4823 4824 if (!crtc_state->base.active) 4825 return 0; 4826 4827 if (conn_state->commit && 4828 !try_wait_for_completion(&conn_state->commit->hw_done)) 4829 return 0; 4830 4831 if (!intel_dp_needs_link_retrain(intel_dp)) 4832 return 0; 4833 4834 /* Suppress underruns caused by re-training */ 4835 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, false); 4836 if (crtc_state->has_pch_encoder) 4837 intel_set_pch_fifo_underrun_reporting(dev_priv, 4838 intel_crtc_pch_transcoder(crtc), false); 4839 4840 intel_dp_start_link_train(intel_dp); 4841 intel_dp_stop_link_train(intel_dp); 4842 4843 /* Keep underrun reporting disabled until things are stable */ 4844 intel_wait_for_vblank(dev_priv, crtc->pipe); 4845 4846 intel_set_cpu_fifo_underrun_reporting(dev_priv, crtc->pipe, true); 4847 if (crtc_state->has_pch_encoder) 4848 intel_set_pch_fifo_underrun_reporting(dev_priv, 4849 intel_crtc_pch_transcoder(crtc), true); 4850 4851 return 0; 4852 } 4853 4854 /* 4855 * If display is now connected check links status, 4856 * there has been known issues of link loss triggering 4857 * long pulse. 4858 * 4859 * Some sinks (eg. ASUS PB287Q) seem to perform some 4860 * weird HPD ping pong during modesets. So we can apparently 4861 * end up with HPD going low during a modeset, and then 4862 * going back up soon after. And once that happens we must 4863 * retrain the link to get a picture. That's in case no 4864 * userspace component reacted to intermittent HPD dip. 4865 */ 4866 static enum intel_hotplug_state 4867 intel_dp_hotplug(struct intel_encoder *encoder, 4868 struct intel_connector *connector, 4869 bool irq_received) 4870 { 4871 struct drm_modeset_acquire_ctx ctx; 4872 enum intel_hotplug_state state; 4873 int ret; 4874 4875 state = intel_encoder_hotplug(encoder, connector, irq_received); 4876 4877 drm_modeset_acquire_init(&ctx, 0); 4878 4879 for (;;) { 4880 ret = intel_dp_retrain_link(encoder, &ctx); 4881 4882 if (ret == -EDEADLK) { 4883 drm_modeset_backoff(&ctx); 4884 continue; 4885 } 4886 4887 break; 4888 } 4889 4890 drm_modeset_drop_locks(&ctx); 4891 drm_modeset_acquire_fini(&ctx); 4892 WARN(ret, "Acquiring modeset locks failed with %i\n", ret); 4893 4894 /* 4895 * Keeping it consistent with intel_ddi_hotplug() and 4896 * intel_hdmi_hotplug(). 4897 */ 4898 if (state == INTEL_HOTPLUG_UNCHANGED && irq_received) 4899 state = INTEL_HOTPLUG_RETRY; 4900 4901 return state; 4902 } 4903 4904 static void intel_dp_check_service_irq(struct intel_dp *intel_dp) 4905 { 4906 u8 val; 4907 4908 if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) 4909 return; 4910 4911 if (drm_dp_dpcd_readb(&intel_dp->aux, 4912 DP_DEVICE_SERVICE_IRQ_VECTOR, &val) != 1 || !val) 4913 return; 4914 4915 drm_dp_dpcd_writeb(&intel_dp->aux, DP_DEVICE_SERVICE_IRQ_VECTOR, val); 4916 4917 if (val & DP_AUTOMATED_TEST_REQUEST) 4918 intel_dp_handle_test_request(intel_dp); 4919 4920 if (val & DP_CP_IRQ) 4921 intel_hdcp_handle_cp_irq(intel_dp->attached_connector); 4922 4923 if (val & DP_SINK_SPECIFIC_IRQ) 4924 DRM_DEBUG_DRIVER("Sink specific irq unhandled\n"); 4925 } 4926 4927 /* 4928 * According to DP spec 4929 * 5.1.2: 4930 * 1. Read DPCD 4931 * 2. Configure link according to Receiver Capabilities 4932 * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 4933 * 4. Check link status on receipt of hot-plug interrupt 4934 * 4935 * intel_dp_short_pulse - handles short pulse interrupts 4936 * when full detection is not required. 4937 * Returns %true if short pulse is handled and full detection 4938 * is NOT required and %false otherwise. 4939 */ 4940 static bool 4941 intel_dp_short_pulse(struct intel_dp *intel_dp) 4942 { 4943 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 4944 u8 old_sink_count = intel_dp->sink_count; 4945 bool ret; 4946 4947 /* 4948 * Clearing compliance test variables to allow capturing 4949 * of values for next automated test request. 4950 */ 4951 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); 4952 4953 /* 4954 * Now read the DPCD to see if it's actually running 4955 * If the current value of sink count doesn't match with 4956 * the value that was stored earlier or dpcd read failed 4957 * we need to do full detection 4958 */ 4959 ret = intel_dp_get_dpcd(intel_dp); 4960 4961 if ((old_sink_count != intel_dp->sink_count) || !ret) { 4962 /* No need to proceed if we are going to do full detect */ 4963 return false; 4964 } 4965 4966 intel_dp_check_service_irq(intel_dp); 4967 4968 /* Handle CEC interrupts, if any */ 4969 drm_dp_cec_irq(&intel_dp->aux); 4970 4971 /* defer to the hotplug work for link retraining if needed */ 4972 if (intel_dp_needs_link_retrain(intel_dp)) 4973 return false; 4974 4975 intel_psr_short_pulse(intel_dp); 4976 4977 if (intel_dp->compliance.test_type == DP_TEST_LINK_TRAINING) { 4978 DRM_DEBUG_KMS("Link Training Compliance Test requested\n"); 4979 /* Send a Hotplug Uevent to userspace to start modeset */ 4980 drm_kms_helper_hotplug_event(&dev_priv->drm); 4981 } 4982 4983 return true; 4984 } 4985 4986 /* XXX this is probably wrong for multiple downstream ports */ 4987 static enum drm_connector_status 4988 intel_dp_detect_dpcd(struct intel_dp *intel_dp) 4989 { 4990 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); 4991 u8 *dpcd = intel_dp->dpcd; 4992 u8 type; 4993 4994 if (WARN_ON(intel_dp_is_edp(intel_dp))) 4995 return connector_status_connected; 4996 4997 if (lspcon->active) 4998 lspcon_resume(lspcon); 4999 5000 if (!intel_dp_get_dpcd(intel_dp)) 5001 return connector_status_disconnected; 5002 5003 /* if there's no downstream port, we're done */ 5004 if (!drm_dp_is_branch(dpcd)) 5005 return connector_status_connected; 5006 5007 /* If we're HPD-aware, SINK_COUNT changes dynamically */ 5008 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && 5009 intel_dp->downstream_ports[0] & DP_DS_PORT_HPD) { 5010 5011 return intel_dp->sink_count ? 5012 connector_status_connected : connector_status_disconnected; 5013 } 5014 5015 if (intel_dp_can_mst(intel_dp)) 5016 return connector_status_connected; 5017 5018 /* If no HPD, poke DDC gently */ 5019 if (drm_probe_ddc(&intel_dp->aux.ddc)) 5020 return connector_status_connected; 5021 5022 /* Well we tried, say unknown for unreliable port types */ 5023 if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) { 5024 type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; 5025 if (type == DP_DS_PORT_TYPE_VGA || 5026 type == DP_DS_PORT_TYPE_NON_EDID) 5027 return connector_status_unknown; 5028 } else { 5029 type = intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & 5030 DP_DWN_STRM_PORT_TYPE_MASK; 5031 if (type == DP_DWN_STRM_PORT_TYPE_ANALOG || 5032 type == DP_DWN_STRM_PORT_TYPE_OTHER) 5033 return connector_status_unknown; 5034 } 5035 5036 /* Anything else is out of spec, warn and ignore */ 5037 DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); 5038 return connector_status_disconnected; 5039 } 5040 5041 static enum drm_connector_status 5042 edp_detect(struct intel_dp *intel_dp) 5043 { 5044 return connector_status_connected; 5045 } 5046 5047 static bool ibx_digital_port_connected(struct intel_encoder *encoder) 5048 { 5049 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5050 u32 bit; 5051 5052 switch (encoder->hpd_pin) { 5053 case HPD_PORT_B: 5054 bit = SDE_PORTB_HOTPLUG; 5055 break; 5056 case HPD_PORT_C: 5057 bit = SDE_PORTC_HOTPLUG; 5058 break; 5059 case HPD_PORT_D: 5060 bit = SDE_PORTD_HOTPLUG; 5061 break; 5062 default: 5063 MISSING_CASE(encoder->hpd_pin); 5064 return false; 5065 } 5066 5067 return I915_READ(SDEISR) & bit; 5068 } 5069 5070 static bool cpt_digital_port_connected(struct intel_encoder *encoder) 5071 { 5072 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5073 u32 bit; 5074 5075 switch (encoder->hpd_pin) { 5076 case HPD_PORT_B: 5077 bit = SDE_PORTB_HOTPLUG_CPT; 5078 break; 5079 case HPD_PORT_C: 5080 bit = SDE_PORTC_HOTPLUG_CPT; 5081 break; 5082 case HPD_PORT_D: 5083 bit = SDE_PORTD_HOTPLUG_CPT; 5084 break; 5085 default: 5086 MISSING_CASE(encoder->hpd_pin); 5087 return false; 5088 } 5089 5090 return I915_READ(SDEISR) & bit; 5091 } 5092 5093 static bool spt_digital_port_connected(struct intel_encoder *encoder) 5094 { 5095 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5096 u32 bit; 5097 5098 switch (encoder->hpd_pin) { 5099 case HPD_PORT_A: 5100 bit = SDE_PORTA_HOTPLUG_SPT; 5101 break; 5102 case HPD_PORT_E: 5103 bit = SDE_PORTE_HOTPLUG_SPT; 5104 break; 5105 default: 5106 return cpt_digital_port_connected(encoder); 5107 } 5108 5109 return I915_READ(SDEISR) & bit; 5110 } 5111 5112 static bool g4x_digital_port_connected(struct intel_encoder *encoder) 5113 { 5114 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5115 u32 bit; 5116 5117 switch (encoder->hpd_pin) { 5118 case HPD_PORT_B: 5119 bit = PORTB_HOTPLUG_LIVE_STATUS_G4X; 5120 break; 5121 case HPD_PORT_C: 5122 bit = PORTC_HOTPLUG_LIVE_STATUS_G4X; 5123 break; 5124 case HPD_PORT_D: 5125 bit = PORTD_HOTPLUG_LIVE_STATUS_G4X; 5126 break; 5127 default: 5128 MISSING_CASE(encoder->hpd_pin); 5129 return false; 5130 } 5131 5132 return I915_READ(PORT_HOTPLUG_STAT) & bit; 5133 } 5134 5135 static bool gm45_digital_port_connected(struct intel_encoder *encoder) 5136 { 5137 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5138 u32 bit; 5139 5140 switch (encoder->hpd_pin) { 5141 case HPD_PORT_B: 5142 bit = PORTB_HOTPLUG_LIVE_STATUS_GM45; 5143 break; 5144 case HPD_PORT_C: 5145 bit = PORTC_HOTPLUG_LIVE_STATUS_GM45; 5146 break; 5147 case HPD_PORT_D: 5148 bit = PORTD_HOTPLUG_LIVE_STATUS_GM45; 5149 break; 5150 default: 5151 MISSING_CASE(encoder->hpd_pin); 5152 return false; 5153 } 5154 5155 return I915_READ(PORT_HOTPLUG_STAT) & bit; 5156 } 5157 5158 static bool ilk_digital_port_connected(struct intel_encoder *encoder) 5159 { 5160 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5161 5162 if (encoder->hpd_pin == HPD_PORT_A) 5163 return I915_READ(DEISR) & DE_DP_A_HOTPLUG; 5164 else 5165 return ibx_digital_port_connected(encoder); 5166 } 5167 5168 static bool snb_digital_port_connected(struct intel_encoder *encoder) 5169 { 5170 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5171 5172 if (encoder->hpd_pin == HPD_PORT_A) 5173 return I915_READ(DEISR) & DE_DP_A_HOTPLUG; 5174 else 5175 return cpt_digital_port_connected(encoder); 5176 } 5177 5178 static bool ivb_digital_port_connected(struct intel_encoder *encoder) 5179 { 5180 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5181 5182 if (encoder->hpd_pin == HPD_PORT_A) 5183 return I915_READ(DEISR) & DE_DP_A_HOTPLUG_IVB; 5184 else 5185 return cpt_digital_port_connected(encoder); 5186 } 5187 5188 static bool bdw_digital_port_connected(struct intel_encoder *encoder) 5189 { 5190 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5191 5192 if (encoder->hpd_pin == HPD_PORT_A) 5193 return I915_READ(GEN8_DE_PORT_ISR) & GEN8_PORT_DP_A_HOTPLUG; 5194 else 5195 return cpt_digital_port_connected(encoder); 5196 } 5197 5198 static bool bxt_digital_port_connected(struct intel_encoder *encoder) 5199 { 5200 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5201 u32 bit; 5202 5203 switch (encoder->hpd_pin) { 5204 case HPD_PORT_A: 5205 bit = BXT_DE_PORT_HP_DDIA; 5206 break; 5207 case HPD_PORT_B: 5208 bit = BXT_DE_PORT_HP_DDIB; 5209 break; 5210 case HPD_PORT_C: 5211 bit = BXT_DE_PORT_HP_DDIC; 5212 break; 5213 default: 5214 MISSING_CASE(encoder->hpd_pin); 5215 return false; 5216 } 5217 5218 return I915_READ(GEN8_DE_PORT_ISR) & bit; 5219 } 5220 5221 static bool icl_combo_port_connected(struct drm_i915_private *dev_priv, 5222 struct intel_digital_port *intel_dig_port) 5223 { 5224 enum port port = intel_dig_port->base.port; 5225 5226 return I915_READ(SDEISR) & SDE_DDI_HOTPLUG_ICP(port); 5227 } 5228 5229 static bool icl_digital_port_connected(struct intel_encoder *encoder) 5230 { 5231 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5232 struct intel_digital_port *dig_port = enc_to_dig_port(&encoder->base); 5233 enum phy phy = intel_port_to_phy(dev_priv, encoder->port); 5234 5235 if (intel_phy_is_combo(dev_priv, phy)) 5236 return icl_combo_port_connected(dev_priv, dig_port); 5237 else if (intel_phy_is_tc(dev_priv, phy)) 5238 return intel_tc_port_connected(dig_port); 5239 else 5240 MISSING_CASE(encoder->hpd_pin); 5241 5242 return false; 5243 } 5244 5245 /* 5246 * intel_digital_port_connected - is the specified port connected? 5247 * @encoder: intel_encoder 5248 * 5249 * In cases where there's a connector physically connected but it can't be used 5250 * by our hardware we also return false, since the rest of the driver should 5251 * pretty much treat the port as disconnected. This is relevant for type-C 5252 * (starting on ICL) where there's ownership involved. 5253 * 5254 * Return %true if port is connected, %false otherwise. 5255 */ 5256 static bool __intel_digital_port_connected(struct intel_encoder *encoder) 5257 { 5258 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5259 5260 if (HAS_GMCH(dev_priv)) { 5261 if (IS_GM45(dev_priv)) 5262 return gm45_digital_port_connected(encoder); 5263 else 5264 return g4x_digital_port_connected(encoder); 5265 } 5266 5267 if (INTEL_GEN(dev_priv) >= 11) 5268 return icl_digital_port_connected(encoder); 5269 else if (IS_GEN(dev_priv, 10) || IS_GEN9_BC(dev_priv)) 5270 return spt_digital_port_connected(encoder); 5271 else if (IS_GEN9_LP(dev_priv)) 5272 return bxt_digital_port_connected(encoder); 5273 else if (IS_GEN(dev_priv, 8)) 5274 return bdw_digital_port_connected(encoder); 5275 else if (IS_GEN(dev_priv, 7)) 5276 return ivb_digital_port_connected(encoder); 5277 else if (IS_GEN(dev_priv, 6)) 5278 return snb_digital_port_connected(encoder); 5279 else if (IS_GEN(dev_priv, 5)) 5280 return ilk_digital_port_connected(encoder); 5281 5282 MISSING_CASE(INTEL_GEN(dev_priv)); 5283 return false; 5284 } 5285 5286 bool intel_digital_port_connected(struct intel_encoder *encoder) 5287 { 5288 struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); 5289 bool is_connected = false; 5290 intel_wakeref_t wakeref; 5291 5292 with_intel_display_power(dev_priv, POWER_DOMAIN_DISPLAY_CORE, wakeref) 5293 is_connected = __intel_digital_port_connected(encoder); 5294 5295 return is_connected; 5296 } 5297 5298 static struct edid * 5299 intel_dp_get_edid(struct intel_dp *intel_dp) 5300 { 5301 struct intel_connector *intel_connector = intel_dp->attached_connector; 5302 5303 /* use cached edid if we have one */ 5304 if (intel_connector->edid) { 5305 /* invalid edid */ 5306 if (IS_ERR(intel_connector->edid)) 5307 return NULL; 5308 5309 return drm_edid_duplicate(intel_connector->edid); 5310 } else 5311 return drm_get_edid(&intel_connector->base, 5312 &intel_dp->aux.ddc); 5313 } 5314 5315 static void 5316 intel_dp_set_edid(struct intel_dp *intel_dp) 5317 { 5318 struct intel_connector *intel_connector = intel_dp->attached_connector; 5319 struct edid *edid; 5320 5321 intel_dp_unset_edid(intel_dp); 5322 edid = intel_dp_get_edid(intel_dp); 5323 intel_connector->detect_edid = edid; 5324 5325 intel_dp->has_audio = drm_detect_monitor_audio(edid); 5326 drm_dp_cec_set_edid(&intel_dp->aux, edid); 5327 } 5328 5329 static void 5330 intel_dp_unset_edid(struct intel_dp *intel_dp) 5331 { 5332 struct intel_connector *intel_connector = intel_dp->attached_connector; 5333 5334 drm_dp_cec_unset_edid(&intel_dp->aux); 5335 kfree(intel_connector->detect_edid); 5336 intel_connector->detect_edid = NULL; 5337 5338 intel_dp->has_audio = false; 5339 } 5340 5341 static int 5342 intel_dp_detect(struct drm_connector *connector, 5343 struct drm_modeset_acquire_ctx *ctx, 5344 bool force) 5345 { 5346 struct drm_i915_private *dev_priv = to_i915(connector->dev); 5347 struct intel_dp *intel_dp = intel_attached_dp(connector); 5348 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5349 struct intel_encoder *encoder = &dig_port->base; 5350 enum drm_connector_status status; 5351 5352 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 5353 connector->base.id, connector->name); 5354 WARN_ON(!drm_modeset_is_locked(&dev_priv->drm.mode_config.connection_mutex)); 5355 5356 /* Can't disconnect eDP */ 5357 if (intel_dp_is_edp(intel_dp)) 5358 status = edp_detect(intel_dp); 5359 else if (intel_digital_port_connected(encoder)) 5360 status = intel_dp_detect_dpcd(intel_dp); 5361 else 5362 status = connector_status_disconnected; 5363 5364 if (status == connector_status_disconnected) { 5365 memset(&intel_dp->compliance, 0, sizeof(intel_dp->compliance)); 5366 memset(intel_dp->dsc_dpcd, 0, sizeof(intel_dp->dsc_dpcd)); 5367 5368 if (intel_dp->is_mst) { 5369 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", 5370 intel_dp->is_mst, 5371 intel_dp->mst_mgr.mst_state); 5372 intel_dp->is_mst = false; 5373 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 5374 intel_dp->is_mst); 5375 } 5376 5377 goto out; 5378 } 5379 5380 if (intel_dp->reset_link_params) { 5381 /* Initial max link lane count */ 5382 intel_dp->max_link_lane_count = intel_dp_max_common_lane_count(intel_dp); 5383 5384 /* Initial max link rate */ 5385 intel_dp->max_link_rate = intel_dp_max_common_rate(intel_dp); 5386 5387 intel_dp->reset_link_params = false; 5388 } 5389 5390 intel_dp_print_rates(intel_dp); 5391 5392 /* Read DP Sink DSC Cap DPCD regs for DP v1.4 */ 5393 if (INTEL_GEN(dev_priv) >= 11) 5394 intel_dp_get_dsc_sink_cap(intel_dp); 5395 5396 intel_dp_configure_mst(intel_dp); 5397 5398 if (intel_dp->is_mst) { 5399 /* 5400 * If we are in MST mode then this connector 5401 * won't appear connected or have anything 5402 * with EDID on it 5403 */ 5404 status = connector_status_disconnected; 5405 goto out; 5406 } 5407 5408 /* 5409 * Some external monitors do not signal loss of link synchronization 5410 * with an IRQ_HPD, so force a link status check. 5411 */ 5412 if (!intel_dp_is_edp(intel_dp)) { 5413 int ret; 5414 5415 ret = intel_dp_retrain_link(encoder, ctx); 5416 if (ret) 5417 return ret; 5418 } 5419 5420 /* 5421 * Clearing NACK and defer counts to get their exact values 5422 * while reading EDID which are required by Compliance tests 5423 * 4.2.2.4 and 4.2.2.5 5424 */ 5425 intel_dp->aux.i2c_nack_count = 0; 5426 intel_dp->aux.i2c_defer_count = 0; 5427 5428 intel_dp_set_edid(intel_dp); 5429 if (intel_dp_is_edp(intel_dp) || 5430 to_intel_connector(connector)->detect_edid) 5431 status = connector_status_connected; 5432 5433 intel_dp_check_service_irq(intel_dp); 5434 5435 out: 5436 if (status != connector_status_connected && !intel_dp->is_mst) 5437 intel_dp_unset_edid(intel_dp); 5438 5439 return status; 5440 } 5441 5442 static void 5443 intel_dp_force(struct drm_connector *connector) 5444 { 5445 struct intel_dp *intel_dp = intel_attached_dp(connector); 5446 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 5447 struct intel_encoder *intel_encoder = &dig_port->base; 5448 struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); 5449 enum intel_display_power_domain aux_domain = 5450 intel_aux_power_domain(dig_port); 5451 intel_wakeref_t wakeref; 5452 5453 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", 5454 connector->base.id, connector->name); 5455 intel_dp_unset_edid(intel_dp); 5456 5457 if (connector->status != connector_status_connected) 5458 return; 5459 5460 wakeref = intel_display_power_get(dev_priv, aux_domain); 5461 5462 intel_dp_set_edid(intel_dp); 5463 5464 intel_display_power_put(dev_priv, aux_domain, wakeref); 5465 } 5466 5467 static int intel_dp_get_modes(struct drm_connector *connector) 5468 { 5469 struct intel_connector *intel_connector = to_intel_connector(connector); 5470 struct edid *edid; 5471 5472 edid = intel_connector->detect_edid; 5473 if (edid) { 5474 int ret = intel_connector_update_modes(connector, edid); 5475 if (ret) 5476 return ret; 5477 } 5478 5479 /* if eDP has no EDID, fall back to fixed mode */ 5480 if (intel_dp_is_edp(intel_attached_dp(connector)) && 5481 intel_connector->panel.fixed_mode) { 5482 struct drm_display_mode *mode; 5483 5484 mode = drm_mode_duplicate(connector->dev, 5485 intel_connector->panel.fixed_mode); 5486 if (mode) { 5487 drm_mode_probed_add(connector, mode); 5488 return 1; 5489 } 5490 } 5491 5492 return 0; 5493 } 5494 5495 static int 5496 intel_dp_connector_register(struct drm_connector *connector) 5497 { 5498 struct intel_dp *intel_dp = intel_attached_dp(connector); 5499 struct drm_device *dev = connector->dev; 5500 int ret; 5501 5502 ret = intel_connector_register(connector); 5503 if (ret) 5504 return ret; 5505 5506 i915_debugfs_connector_add(connector); 5507 5508 DRM_DEBUG_KMS("registering %s bus for %s\n", 5509 intel_dp->aux.name, connector->kdev->kobj.name); 5510 5511 intel_dp->aux.dev = connector->kdev; 5512 ret = drm_dp_aux_register(&intel_dp->aux); 5513 if (!ret) 5514 drm_dp_cec_register_connector(&intel_dp->aux, 5515 connector->name, dev->dev); 5516 return ret; 5517 } 5518 5519 static void 5520 intel_dp_connector_unregister(struct drm_connector *connector) 5521 { 5522 struct intel_dp *intel_dp = intel_attached_dp(connector); 5523 5524 drm_dp_cec_unregister_connector(&intel_dp->aux); 5525 drm_dp_aux_unregister(&intel_dp->aux); 5526 intel_connector_unregister(connector); 5527 } 5528 5529 void intel_dp_encoder_flush_work(struct drm_encoder *encoder) 5530 { 5531 struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder); 5532 struct intel_dp *intel_dp = &intel_dig_port->dp; 5533 5534 intel_dp_mst_encoder_cleanup(intel_dig_port); 5535 if (intel_dp_is_edp(intel_dp)) { 5536 intel_wakeref_t wakeref; 5537 5538 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 5539 /* 5540 * vdd might still be enabled do to the delayed vdd off. 5541 * Make sure vdd is actually turned off here. 5542 */ 5543 with_pps_lock(intel_dp, wakeref) 5544 edp_panel_vdd_off_sync(intel_dp); 5545 5546 if (intel_dp->edp_notifier.notifier_call) { 5547 unregister_reboot_notifier(&intel_dp->edp_notifier); 5548 intel_dp->edp_notifier.notifier_call = NULL; 5549 } 5550 } 5551 5552 intel_dp_aux_fini(intel_dp); 5553 } 5554 5555 static void intel_dp_encoder_destroy(struct drm_encoder *encoder) 5556 { 5557 intel_dp_encoder_flush_work(encoder); 5558 5559 drm_encoder_cleanup(encoder); 5560 kfree(enc_to_dig_port(encoder)); 5561 } 5562 5563 void intel_dp_encoder_suspend(struct intel_encoder *intel_encoder) 5564 { 5565 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_encoder->base); 5566 intel_wakeref_t wakeref; 5567 5568 if (!intel_dp_is_edp(intel_dp)) 5569 return; 5570 5571 /* 5572 * vdd might still be enabled do to the delayed vdd off. 5573 * Make sure vdd is actually turned off here. 5574 */ 5575 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 5576 with_pps_lock(intel_dp, wakeref) 5577 edp_panel_vdd_off_sync(intel_dp); 5578 } 5579 5580 static void intel_dp_hdcp_wait_for_cp_irq(struct intel_hdcp *hdcp, int timeout) 5581 { 5582 long ret; 5583 5584 #define C (hdcp->cp_irq_count_cached != atomic_read(&hdcp->cp_irq_count)) 5585 ret = wait_event_interruptible_timeout(hdcp->cp_irq_queue, C, 5586 msecs_to_jiffies(timeout)); 5587 5588 if (!ret) 5589 DRM_DEBUG_KMS("Timedout at waiting for CP_IRQ\n"); 5590 } 5591 5592 static 5593 int intel_dp_hdcp_write_an_aksv(struct intel_digital_port *intel_dig_port, 5594 u8 *an) 5595 { 5596 struct intel_dp *intel_dp = enc_to_intel_dp(&intel_dig_port->base.base); 5597 static const struct drm_dp_aux_msg msg = { 5598 .request = DP_AUX_NATIVE_WRITE, 5599 .address = DP_AUX_HDCP_AKSV, 5600 .size = DRM_HDCP_KSV_LEN, 5601 }; 5602 u8 txbuf[HEADER_SIZE + DRM_HDCP_KSV_LEN] = {}, rxbuf[2], reply = 0; 5603 ssize_t dpcd_ret; 5604 int ret; 5605 5606 /* Output An first, that's easy */ 5607 dpcd_ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, DP_AUX_HDCP_AN, 5608 an, DRM_HDCP_AN_LEN); 5609 if (dpcd_ret != DRM_HDCP_AN_LEN) { 5610 DRM_DEBUG_KMS("Failed to write An over DP/AUX (%zd)\n", 5611 dpcd_ret); 5612 return dpcd_ret >= 0 ? -EIO : dpcd_ret; 5613 } 5614 5615 /* 5616 * Since Aksv is Oh-So-Secret, we can't access it in software. So in 5617 * order to get it on the wire, we need to create the AUX header as if 5618 * we were writing the data, and then tickle the hardware to output the 5619 * data once the header is sent out. 5620 */ 5621 intel_dp_aux_header(txbuf, &msg); 5622 5623 ret = intel_dp_aux_xfer(intel_dp, txbuf, HEADER_SIZE + msg.size, 5624 rxbuf, sizeof(rxbuf), 5625 DP_AUX_CH_CTL_AUX_AKSV_SELECT); 5626 if (ret < 0) { 5627 DRM_DEBUG_KMS("Write Aksv over DP/AUX failed (%d)\n", ret); 5628 return ret; 5629 } else if (ret == 0) { 5630 DRM_DEBUG_KMS("Aksv write over DP/AUX was empty\n"); 5631 return -EIO; 5632 } 5633 5634 reply = (rxbuf[0] >> 4) & DP_AUX_NATIVE_REPLY_MASK; 5635 if (reply != DP_AUX_NATIVE_REPLY_ACK) { 5636 DRM_DEBUG_KMS("Aksv write: no DP_AUX_NATIVE_REPLY_ACK %x\n", 5637 reply); 5638 return -EIO; 5639 } 5640 return 0; 5641 } 5642 5643 static int intel_dp_hdcp_read_bksv(struct intel_digital_port *intel_dig_port, 5644 u8 *bksv) 5645 { 5646 ssize_t ret; 5647 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BKSV, bksv, 5648 DRM_HDCP_KSV_LEN); 5649 if (ret != DRM_HDCP_KSV_LEN) { 5650 DRM_DEBUG_KMS("Read Bksv from DP/AUX failed (%zd)\n", ret); 5651 return ret >= 0 ? -EIO : ret; 5652 } 5653 return 0; 5654 } 5655 5656 static int intel_dp_hdcp_read_bstatus(struct intel_digital_port *intel_dig_port, 5657 u8 *bstatus) 5658 { 5659 ssize_t ret; 5660 /* 5661 * For some reason the HDMI and DP HDCP specs call this register 5662 * definition by different names. In the HDMI spec, it's called BSTATUS, 5663 * but in DP it's called BINFO. 5664 */ 5665 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BINFO, 5666 bstatus, DRM_HDCP_BSTATUS_LEN); 5667 if (ret != DRM_HDCP_BSTATUS_LEN) { 5668 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret); 5669 return ret >= 0 ? -EIO : ret; 5670 } 5671 return 0; 5672 } 5673 5674 static 5675 int intel_dp_hdcp_read_bcaps(struct intel_digital_port *intel_dig_port, 5676 u8 *bcaps) 5677 { 5678 ssize_t ret; 5679 5680 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BCAPS, 5681 bcaps, 1); 5682 if (ret != 1) { 5683 DRM_DEBUG_KMS("Read bcaps from DP/AUX failed (%zd)\n", ret); 5684 return ret >= 0 ? -EIO : ret; 5685 } 5686 5687 return 0; 5688 } 5689 5690 static 5691 int intel_dp_hdcp_repeater_present(struct intel_digital_port *intel_dig_port, 5692 bool *repeater_present) 5693 { 5694 ssize_t ret; 5695 u8 bcaps; 5696 5697 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); 5698 if (ret) 5699 return ret; 5700 5701 *repeater_present = bcaps & DP_BCAPS_REPEATER_PRESENT; 5702 return 0; 5703 } 5704 5705 static 5706 int intel_dp_hdcp_read_ri_prime(struct intel_digital_port *intel_dig_port, 5707 u8 *ri_prime) 5708 { 5709 ssize_t ret; 5710 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_RI_PRIME, 5711 ri_prime, DRM_HDCP_RI_LEN); 5712 if (ret != DRM_HDCP_RI_LEN) { 5713 DRM_DEBUG_KMS("Read Ri' from DP/AUX failed (%zd)\n", ret); 5714 return ret >= 0 ? -EIO : ret; 5715 } 5716 return 0; 5717 } 5718 5719 static 5720 int intel_dp_hdcp_read_ksv_ready(struct intel_digital_port *intel_dig_port, 5721 bool *ksv_ready) 5722 { 5723 ssize_t ret; 5724 u8 bstatus; 5725 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, 5726 &bstatus, 1); 5727 if (ret != 1) { 5728 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret); 5729 return ret >= 0 ? -EIO : ret; 5730 } 5731 *ksv_ready = bstatus & DP_BSTATUS_READY; 5732 return 0; 5733 } 5734 5735 static 5736 int intel_dp_hdcp_read_ksv_fifo(struct intel_digital_port *intel_dig_port, 5737 int num_downstream, u8 *ksv_fifo) 5738 { 5739 ssize_t ret; 5740 int i; 5741 5742 /* KSV list is read via 15 byte window (3 entries @ 5 bytes each) */ 5743 for (i = 0; i < num_downstream; i += 3) { 5744 size_t len = min(num_downstream - i, 3) * DRM_HDCP_KSV_LEN; 5745 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, 5746 DP_AUX_HDCP_KSV_FIFO, 5747 ksv_fifo + i * DRM_HDCP_KSV_LEN, 5748 len); 5749 if (ret != len) { 5750 DRM_DEBUG_KMS("Read ksv[%d] from DP/AUX failed (%zd)\n", 5751 i, ret); 5752 return ret >= 0 ? -EIO : ret; 5753 } 5754 } 5755 return 0; 5756 } 5757 5758 static 5759 int intel_dp_hdcp_read_v_prime_part(struct intel_digital_port *intel_dig_port, 5760 int i, u32 *part) 5761 { 5762 ssize_t ret; 5763 5764 if (i >= DRM_HDCP_V_PRIME_NUM_PARTS) 5765 return -EINVAL; 5766 5767 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, 5768 DP_AUX_HDCP_V_PRIME(i), part, 5769 DRM_HDCP_V_PRIME_PART_LEN); 5770 if (ret != DRM_HDCP_V_PRIME_PART_LEN) { 5771 DRM_DEBUG_KMS("Read v'[%d] from DP/AUX failed (%zd)\n", i, ret); 5772 return ret >= 0 ? -EIO : ret; 5773 } 5774 return 0; 5775 } 5776 5777 static 5778 int intel_dp_hdcp_toggle_signalling(struct intel_digital_port *intel_dig_port, 5779 bool enable) 5780 { 5781 /* Not used for single stream DisplayPort setups */ 5782 return 0; 5783 } 5784 5785 static 5786 bool intel_dp_hdcp_check_link(struct intel_digital_port *intel_dig_port) 5787 { 5788 ssize_t ret; 5789 u8 bstatus; 5790 5791 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, DP_AUX_HDCP_BSTATUS, 5792 &bstatus, 1); 5793 if (ret != 1) { 5794 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret); 5795 return false; 5796 } 5797 5798 return !(bstatus & (DP_BSTATUS_LINK_FAILURE | DP_BSTATUS_REAUTH_REQ)); 5799 } 5800 5801 static 5802 int intel_dp_hdcp_capable(struct intel_digital_port *intel_dig_port, 5803 bool *hdcp_capable) 5804 { 5805 ssize_t ret; 5806 u8 bcaps; 5807 5808 ret = intel_dp_hdcp_read_bcaps(intel_dig_port, &bcaps); 5809 if (ret) 5810 return ret; 5811 5812 *hdcp_capable = bcaps & DP_BCAPS_HDCP_CAPABLE; 5813 return 0; 5814 } 5815 5816 struct hdcp2_dp_errata_stream_type { 5817 u8 msg_id; 5818 u8 stream_type; 5819 } __packed; 5820 5821 static struct hdcp2_dp_msg_data { 5822 u8 msg_id; 5823 u32 offset; 5824 bool msg_detectable; 5825 u32 timeout; 5826 u32 timeout2; /* Added for non_paired situation */ 5827 } hdcp2_msg_data[] = { 5828 {HDCP_2_2_AKE_INIT, DP_HDCP_2_2_AKE_INIT_OFFSET, false, 0, 0}, 5829 {HDCP_2_2_AKE_SEND_CERT, DP_HDCP_2_2_AKE_SEND_CERT_OFFSET, 5830 false, HDCP_2_2_CERT_TIMEOUT_MS, 0}, 5831 {HDCP_2_2_AKE_NO_STORED_KM, DP_HDCP_2_2_AKE_NO_STORED_KM_OFFSET, 5832 false, 0, 0}, 5833 {HDCP_2_2_AKE_STORED_KM, DP_HDCP_2_2_AKE_STORED_KM_OFFSET, 5834 false, 0, 0}, 5835 {HDCP_2_2_AKE_SEND_HPRIME, DP_HDCP_2_2_AKE_SEND_HPRIME_OFFSET, 5836 true, HDCP_2_2_HPRIME_PAIRED_TIMEOUT_MS, 5837 HDCP_2_2_HPRIME_NO_PAIRED_TIMEOUT_MS}, 5838 {HDCP_2_2_AKE_SEND_PAIRING_INFO, 5839 DP_HDCP_2_2_AKE_SEND_PAIRING_INFO_OFFSET, true, 5840 HDCP_2_2_PAIRING_TIMEOUT_MS, 0}, 5841 {HDCP_2_2_LC_INIT, DP_HDCP_2_2_LC_INIT_OFFSET, false, 0, 0}, 5842 {HDCP_2_2_LC_SEND_LPRIME, DP_HDCP_2_2_LC_SEND_LPRIME_OFFSET, 5843 false, HDCP_2_2_DP_LPRIME_TIMEOUT_MS, 0}, 5844 {HDCP_2_2_SKE_SEND_EKS, DP_HDCP_2_2_SKE_SEND_EKS_OFFSET, false, 5845 0, 0}, 5846 {HDCP_2_2_REP_SEND_RECVID_LIST, 5847 DP_HDCP_2_2_REP_SEND_RECVID_LIST_OFFSET, true, 5848 HDCP_2_2_RECVID_LIST_TIMEOUT_MS, 0}, 5849 {HDCP_2_2_REP_SEND_ACK, DP_HDCP_2_2_REP_SEND_ACK_OFFSET, false, 5850 0, 0}, 5851 {HDCP_2_2_REP_STREAM_MANAGE, 5852 DP_HDCP_2_2_REP_STREAM_MANAGE_OFFSET, false, 5853 0, 0}, 5854 {HDCP_2_2_REP_STREAM_READY, DP_HDCP_2_2_REP_STREAM_READY_OFFSET, 5855 false, HDCP_2_2_STREAM_READY_TIMEOUT_MS, 0}, 5856 /* local define to shovel this through the write_2_2 interface */ 5857 #define HDCP_2_2_ERRATA_DP_STREAM_TYPE 50 5858 {HDCP_2_2_ERRATA_DP_STREAM_TYPE, 5859 DP_HDCP_2_2_REG_STREAM_TYPE_OFFSET, false, 5860 0, 0}, 5861 }; 5862 5863 static inline 5864 int intel_dp_hdcp2_read_rx_status(struct intel_digital_port *intel_dig_port, 5865 u8 *rx_status) 5866 { 5867 ssize_t ret; 5868 5869 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, 5870 DP_HDCP_2_2_REG_RXSTATUS_OFFSET, rx_status, 5871 HDCP_2_2_DP_RXSTATUS_LEN); 5872 if (ret != HDCP_2_2_DP_RXSTATUS_LEN) { 5873 DRM_DEBUG_KMS("Read bstatus from DP/AUX failed (%zd)\n", ret); 5874 return ret >= 0 ? -EIO : ret; 5875 } 5876 5877 return 0; 5878 } 5879 5880 static 5881 int hdcp2_detect_msg_availability(struct intel_digital_port *intel_dig_port, 5882 u8 msg_id, bool *msg_ready) 5883 { 5884 u8 rx_status; 5885 int ret; 5886 5887 *msg_ready = false; 5888 ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); 5889 if (ret < 0) 5890 return ret; 5891 5892 switch (msg_id) { 5893 case HDCP_2_2_AKE_SEND_HPRIME: 5894 if (HDCP_2_2_DP_RXSTATUS_H_PRIME(rx_status)) 5895 *msg_ready = true; 5896 break; 5897 case HDCP_2_2_AKE_SEND_PAIRING_INFO: 5898 if (HDCP_2_2_DP_RXSTATUS_PAIRING(rx_status)) 5899 *msg_ready = true; 5900 break; 5901 case HDCP_2_2_REP_SEND_RECVID_LIST: 5902 if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) 5903 *msg_ready = true; 5904 break; 5905 default: 5906 DRM_ERROR("Unidentified msg_id: %d\n", msg_id); 5907 return -EINVAL; 5908 } 5909 5910 return 0; 5911 } 5912 5913 static ssize_t 5914 intel_dp_hdcp2_wait_for_msg(struct intel_digital_port *intel_dig_port, 5915 struct hdcp2_dp_msg_data *hdcp2_msg_data) 5916 { 5917 struct intel_dp *dp = &intel_dig_port->dp; 5918 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; 5919 u8 msg_id = hdcp2_msg_data->msg_id; 5920 int ret, timeout; 5921 bool msg_ready = false; 5922 5923 if (msg_id == HDCP_2_2_AKE_SEND_HPRIME && !hdcp->is_paired) 5924 timeout = hdcp2_msg_data->timeout2; 5925 else 5926 timeout = hdcp2_msg_data->timeout; 5927 5928 /* 5929 * There is no way to detect the CERT, LPRIME and STREAM_READY 5930 * availability. So Wait for timeout and read the msg. 5931 */ 5932 if (!hdcp2_msg_data->msg_detectable) { 5933 mdelay(timeout); 5934 ret = 0; 5935 } else { 5936 /* 5937 * As we want to check the msg availability at timeout, Ignoring 5938 * the timeout at wait for CP_IRQ. 5939 */ 5940 intel_dp_hdcp_wait_for_cp_irq(hdcp, timeout); 5941 ret = hdcp2_detect_msg_availability(intel_dig_port, 5942 msg_id, &msg_ready); 5943 if (!msg_ready) 5944 ret = -ETIMEDOUT; 5945 } 5946 5947 if (ret) 5948 DRM_DEBUG_KMS("msg_id %d, ret %d, timeout(mSec): %d\n", 5949 hdcp2_msg_data->msg_id, ret, timeout); 5950 5951 return ret; 5952 } 5953 5954 static struct hdcp2_dp_msg_data *get_hdcp2_dp_msg_data(u8 msg_id) 5955 { 5956 int i; 5957 5958 for (i = 0; i < ARRAY_SIZE(hdcp2_msg_data); i++) 5959 if (hdcp2_msg_data[i].msg_id == msg_id) 5960 return &hdcp2_msg_data[i]; 5961 5962 return NULL; 5963 } 5964 5965 static 5966 int intel_dp_hdcp2_write_msg(struct intel_digital_port *intel_dig_port, 5967 void *buf, size_t size) 5968 { 5969 struct intel_dp *dp = &intel_dig_port->dp; 5970 struct intel_hdcp *hdcp = &dp->attached_connector->hdcp; 5971 unsigned int offset; 5972 u8 *byte = buf; 5973 ssize_t ret, bytes_to_write, len; 5974 struct hdcp2_dp_msg_data *hdcp2_msg_data; 5975 5976 hdcp2_msg_data = get_hdcp2_dp_msg_data(*byte); 5977 if (!hdcp2_msg_data) 5978 return -EINVAL; 5979 5980 offset = hdcp2_msg_data->offset; 5981 5982 /* No msg_id in DP HDCP2.2 msgs */ 5983 bytes_to_write = size - 1; 5984 byte++; 5985 5986 hdcp->cp_irq_count_cached = atomic_read(&hdcp->cp_irq_count); 5987 5988 while (bytes_to_write) { 5989 len = bytes_to_write > DP_AUX_MAX_PAYLOAD_BYTES ? 5990 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_write; 5991 5992 ret = drm_dp_dpcd_write(&intel_dig_port->dp.aux, 5993 offset, (void *)byte, len); 5994 if (ret < 0) 5995 return ret; 5996 5997 bytes_to_write -= ret; 5998 byte += ret; 5999 offset += ret; 6000 } 6001 6002 return size; 6003 } 6004 6005 static 6006 ssize_t get_receiver_id_list_size(struct intel_digital_port *intel_dig_port) 6007 { 6008 u8 rx_info[HDCP_2_2_RXINFO_LEN]; 6009 u32 dev_cnt; 6010 ssize_t ret; 6011 6012 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, 6013 DP_HDCP_2_2_REG_RXINFO_OFFSET, 6014 (void *)rx_info, HDCP_2_2_RXINFO_LEN); 6015 if (ret != HDCP_2_2_RXINFO_LEN) 6016 return ret >= 0 ? -EIO : ret; 6017 6018 dev_cnt = (HDCP_2_2_DEV_COUNT_HI(rx_info[0]) << 4 | 6019 HDCP_2_2_DEV_COUNT_LO(rx_info[1])); 6020 6021 if (dev_cnt > HDCP_2_2_MAX_DEVICE_COUNT) 6022 dev_cnt = HDCP_2_2_MAX_DEVICE_COUNT; 6023 6024 ret = sizeof(struct hdcp2_rep_send_receiverid_list) - 6025 HDCP_2_2_RECEIVER_IDS_MAX_LEN + 6026 (dev_cnt * HDCP_2_2_RECEIVER_ID_LEN); 6027 6028 return ret; 6029 } 6030 6031 static 6032 int intel_dp_hdcp2_read_msg(struct intel_digital_port *intel_dig_port, 6033 u8 msg_id, void *buf, size_t size) 6034 { 6035 unsigned int offset; 6036 u8 *byte = buf; 6037 ssize_t ret, bytes_to_recv, len; 6038 struct hdcp2_dp_msg_data *hdcp2_msg_data; 6039 6040 hdcp2_msg_data = get_hdcp2_dp_msg_data(msg_id); 6041 if (!hdcp2_msg_data) 6042 return -EINVAL; 6043 offset = hdcp2_msg_data->offset; 6044 6045 ret = intel_dp_hdcp2_wait_for_msg(intel_dig_port, hdcp2_msg_data); 6046 if (ret < 0) 6047 return ret; 6048 6049 if (msg_id == HDCP_2_2_REP_SEND_RECVID_LIST) { 6050 ret = get_receiver_id_list_size(intel_dig_port); 6051 if (ret < 0) 6052 return ret; 6053 6054 size = ret; 6055 } 6056 bytes_to_recv = size - 1; 6057 6058 /* DP adaptation msgs has no msg_id */ 6059 byte++; 6060 6061 while (bytes_to_recv) { 6062 len = bytes_to_recv > DP_AUX_MAX_PAYLOAD_BYTES ? 6063 DP_AUX_MAX_PAYLOAD_BYTES : bytes_to_recv; 6064 6065 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, offset, 6066 (void *)byte, len); 6067 if (ret < 0) { 6068 DRM_DEBUG_KMS("msg_id %d, ret %zd\n", msg_id, ret); 6069 return ret; 6070 } 6071 6072 bytes_to_recv -= ret; 6073 byte += ret; 6074 offset += ret; 6075 } 6076 byte = buf; 6077 *byte = msg_id; 6078 6079 return size; 6080 } 6081 6082 static 6083 int intel_dp_hdcp2_config_stream_type(struct intel_digital_port *intel_dig_port, 6084 bool is_repeater, u8 content_type) 6085 { 6086 struct hdcp2_dp_errata_stream_type stream_type_msg; 6087 6088 if (is_repeater) 6089 return 0; 6090 6091 /* 6092 * Errata for DP: As Stream type is used for encryption, Receiver 6093 * should be communicated with stream type for the decryption of the 6094 * content. 6095 * Repeater will be communicated with stream type as a part of it's 6096 * auth later in time. 6097 */ 6098 stream_type_msg.msg_id = HDCP_2_2_ERRATA_DP_STREAM_TYPE; 6099 stream_type_msg.stream_type = content_type; 6100 6101 return intel_dp_hdcp2_write_msg(intel_dig_port, &stream_type_msg, 6102 sizeof(stream_type_msg)); 6103 } 6104 6105 static 6106 int intel_dp_hdcp2_check_link(struct intel_digital_port *intel_dig_port) 6107 { 6108 u8 rx_status; 6109 int ret; 6110 6111 ret = intel_dp_hdcp2_read_rx_status(intel_dig_port, &rx_status); 6112 if (ret) 6113 return ret; 6114 6115 if (HDCP_2_2_DP_RXSTATUS_REAUTH_REQ(rx_status)) 6116 ret = HDCP_REAUTH_REQUEST; 6117 else if (HDCP_2_2_DP_RXSTATUS_LINK_FAILED(rx_status)) 6118 ret = HDCP_LINK_INTEGRITY_FAILURE; 6119 else if (HDCP_2_2_DP_RXSTATUS_READY(rx_status)) 6120 ret = HDCP_TOPOLOGY_CHANGE; 6121 6122 return ret; 6123 } 6124 6125 static 6126 int intel_dp_hdcp2_capable(struct intel_digital_port *intel_dig_port, 6127 bool *capable) 6128 { 6129 u8 rx_caps[3]; 6130 int ret; 6131 6132 *capable = false; 6133 ret = drm_dp_dpcd_read(&intel_dig_port->dp.aux, 6134 DP_HDCP_2_2_REG_RX_CAPS_OFFSET, 6135 rx_caps, HDCP_2_2_RXCAPS_LEN); 6136 if (ret != HDCP_2_2_RXCAPS_LEN) 6137 return ret >= 0 ? -EIO : ret; 6138 6139 if (rx_caps[0] == HDCP_2_2_RX_CAPS_VERSION_VAL && 6140 HDCP_2_2_DP_HDCP_CAPABLE(rx_caps[2])) 6141 *capable = true; 6142 6143 return 0; 6144 } 6145 6146 static const struct intel_hdcp_shim intel_dp_hdcp_shim = { 6147 .write_an_aksv = intel_dp_hdcp_write_an_aksv, 6148 .read_bksv = intel_dp_hdcp_read_bksv, 6149 .read_bstatus = intel_dp_hdcp_read_bstatus, 6150 .repeater_present = intel_dp_hdcp_repeater_present, 6151 .read_ri_prime = intel_dp_hdcp_read_ri_prime, 6152 .read_ksv_ready = intel_dp_hdcp_read_ksv_ready, 6153 .read_ksv_fifo = intel_dp_hdcp_read_ksv_fifo, 6154 .read_v_prime_part = intel_dp_hdcp_read_v_prime_part, 6155 .toggle_signalling = intel_dp_hdcp_toggle_signalling, 6156 .check_link = intel_dp_hdcp_check_link, 6157 .hdcp_capable = intel_dp_hdcp_capable, 6158 .write_2_2_msg = intel_dp_hdcp2_write_msg, 6159 .read_2_2_msg = intel_dp_hdcp2_read_msg, 6160 .config_stream_type = intel_dp_hdcp2_config_stream_type, 6161 .check_2_2_link = intel_dp_hdcp2_check_link, 6162 .hdcp_2_2_capable = intel_dp_hdcp2_capable, 6163 .protocol = HDCP_PROTOCOL_DP, 6164 }; 6165 6166 static void intel_edp_panel_vdd_sanitize(struct intel_dp *intel_dp) 6167 { 6168 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 6169 struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); 6170 6171 lockdep_assert_held(&dev_priv->pps_mutex); 6172 6173 if (!edp_have_panel_vdd(intel_dp)) 6174 return; 6175 6176 /* 6177 * The VDD bit needs a power domain reference, so if the bit is 6178 * already enabled when we boot or resume, grab this reference and 6179 * schedule a vdd off, so we don't hold on to the reference 6180 * indefinitely. 6181 */ 6182 DRM_DEBUG_KMS("VDD left on by BIOS, adjusting state tracking\n"); 6183 intel_display_power_get(dev_priv, intel_aux_power_domain(dig_port)); 6184 6185 edp_panel_vdd_schedule_off(intel_dp); 6186 } 6187 6188 static enum pipe vlv_active_pipe(struct intel_dp *intel_dp) 6189 { 6190 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 6191 struct intel_encoder *encoder = &dp_to_dig_port(intel_dp)->base; 6192 enum pipe pipe; 6193 6194 if (intel_dp_port_enabled(dev_priv, intel_dp->output_reg, 6195 encoder->port, &pipe)) 6196 return pipe; 6197 6198 return INVALID_PIPE; 6199 } 6200 6201 void intel_dp_encoder_reset(struct drm_encoder *encoder) 6202 { 6203 struct drm_i915_private *dev_priv = to_i915(encoder->dev); 6204 struct intel_dp *intel_dp = enc_to_intel_dp(encoder); 6205 struct intel_lspcon *lspcon = dp_to_lspcon(intel_dp); 6206 intel_wakeref_t wakeref; 6207 6208 if (!HAS_DDI(dev_priv)) 6209 intel_dp->DP = I915_READ(intel_dp->output_reg); 6210 6211 if (lspcon->active) 6212 lspcon_resume(lspcon); 6213 6214 intel_dp->reset_link_params = true; 6215 6216 if (!IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv) && 6217 !intel_dp_is_edp(intel_dp)) 6218 return; 6219 6220 with_pps_lock(intel_dp, wakeref) { 6221 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6222 intel_dp->active_pipe = vlv_active_pipe(intel_dp); 6223 6224 if (intel_dp_is_edp(intel_dp)) { 6225 /* 6226 * Reinit the power sequencer, in case BIOS did 6227 * something nasty with it. 6228 */ 6229 intel_dp_pps_init(intel_dp); 6230 intel_edp_panel_vdd_sanitize(intel_dp); 6231 } 6232 } 6233 } 6234 6235 static const struct drm_connector_funcs intel_dp_connector_funcs = { 6236 .force = intel_dp_force, 6237 .fill_modes = drm_helper_probe_single_connector_modes, 6238 .atomic_get_property = intel_digital_connector_atomic_get_property, 6239 .atomic_set_property = intel_digital_connector_atomic_set_property, 6240 .late_register = intel_dp_connector_register, 6241 .early_unregister = intel_dp_connector_unregister, 6242 .destroy = intel_connector_destroy, 6243 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, 6244 .atomic_duplicate_state = intel_digital_connector_duplicate_state, 6245 }; 6246 6247 static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { 6248 .detect_ctx = intel_dp_detect, 6249 .get_modes = intel_dp_get_modes, 6250 .mode_valid = intel_dp_mode_valid, 6251 .atomic_check = intel_digital_connector_atomic_check, 6252 }; 6253 6254 static const struct drm_encoder_funcs intel_dp_enc_funcs = { 6255 .reset = intel_dp_encoder_reset, 6256 .destroy = intel_dp_encoder_destroy, 6257 }; 6258 6259 enum irqreturn 6260 intel_dp_hpd_pulse(struct intel_digital_port *intel_dig_port, bool long_hpd) 6261 { 6262 struct intel_dp *intel_dp = &intel_dig_port->dp; 6263 6264 if (long_hpd && intel_dig_port->base.type == INTEL_OUTPUT_EDP) { 6265 /* 6266 * vdd off can generate a long pulse on eDP which 6267 * would require vdd on to handle it, and thus we 6268 * would end up in an endless cycle of 6269 * "vdd off -> long hpd -> vdd on -> detect -> vdd off -> ..." 6270 */ 6271 DRM_DEBUG_KMS("ignoring long hpd on eDP port %c\n", 6272 port_name(intel_dig_port->base.port)); 6273 return IRQ_HANDLED; 6274 } 6275 6276 DRM_DEBUG_KMS("got hpd irq on port %c - %s\n", 6277 port_name(intel_dig_port->base.port), 6278 long_hpd ? "long" : "short"); 6279 6280 if (long_hpd) { 6281 intel_dp->reset_link_params = true; 6282 return IRQ_NONE; 6283 } 6284 6285 if (intel_dp->is_mst) { 6286 if (intel_dp_check_mst_status(intel_dp) == -EINVAL) { 6287 /* 6288 * If we were in MST mode, and device is not 6289 * there, get out of MST mode 6290 */ 6291 DRM_DEBUG_KMS("MST device may have disappeared %d vs %d\n", 6292 intel_dp->is_mst, intel_dp->mst_mgr.mst_state); 6293 intel_dp->is_mst = false; 6294 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 6295 intel_dp->is_mst); 6296 6297 return IRQ_NONE; 6298 } 6299 } 6300 6301 if (!intel_dp->is_mst) { 6302 bool handled; 6303 6304 handled = intel_dp_short_pulse(intel_dp); 6305 6306 if (!handled) 6307 return IRQ_NONE; 6308 } 6309 6310 return IRQ_HANDLED; 6311 } 6312 6313 /* check the VBT to see whether the eDP is on another port */ 6314 bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port) 6315 { 6316 /* 6317 * eDP not supported on g4x. so bail out early just 6318 * for a bit extra safety in case the VBT is bonkers. 6319 */ 6320 if (INTEL_GEN(dev_priv) < 5) 6321 return false; 6322 6323 if (INTEL_GEN(dev_priv) < 9 && port == PORT_A) 6324 return true; 6325 6326 return intel_bios_is_port_edp(dev_priv, port); 6327 } 6328 6329 static void 6330 intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) 6331 { 6332 struct drm_i915_private *dev_priv = to_i915(connector->dev); 6333 enum port port = dp_to_dig_port(intel_dp)->base.port; 6334 6335 if (!IS_G4X(dev_priv) && port != PORT_A) 6336 intel_attach_force_audio_property(connector); 6337 6338 intel_attach_broadcast_rgb_property(connector); 6339 if (HAS_GMCH(dev_priv)) 6340 drm_connector_attach_max_bpc_property(connector, 6, 10); 6341 else if (INTEL_GEN(dev_priv) >= 5) 6342 drm_connector_attach_max_bpc_property(connector, 6, 12); 6343 6344 if (intel_dp_is_edp(intel_dp)) { 6345 u32 allowed_scalers; 6346 6347 allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT) | BIT(DRM_MODE_SCALE_FULLSCREEN); 6348 if (!HAS_GMCH(dev_priv)) 6349 allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); 6350 6351 drm_connector_attach_scaling_mode_property(connector, allowed_scalers); 6352 6353 connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; 6354 6355 } 6356 } 6357 6358 static void intel_dp_init_panel_power_timestamps(struct intel_dp *intel_dp) 6359 { 6360 intel_dp->panel_power_off_time = ktime_get_boottime(); 6361 intel_dp->last_power_on = jiffies; 6362 intel_dp->last_backlight_off = jiffies; 6363 } 6364 6365 static void 6366 intel_pps_readout_hw_state(struct intel_dp *intel_dp, struct edp_power_seq *seq) 6367 { 6368 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 6369 u32 pp_on, pp_off, pp_ctl; 6370 struct pps_registers regs; 6371 6372 intel_pps_get_registers(intel_dp, ®s); 6373 6374 pp_ctl = ironlake_get_pp_control(intel_dp); 6375 6376 /* Ensure PPS is unlocked */ 6377 if (!HAS_DDI(dev_priv)) 6378 I915_WRITE(regs.pp_ctrl, pp_ctl); 6379 6380 pp_on = I915_READ(regs.pp_on); 6381 pp_off = I915_READ(regs.pp_off); 6382 6383 /* Pull timing values out of registers */ 6384 seq->t1_t3 = REG_FIELD_GET(PANEL_POWER_UP_DELAY_MASK, pp_on); 6385 seq->t8 = REG_FIELD_GET(PANEL_LIGHT_ON_DELAY_MASK, pp_on); 6386 seq->t9 = REG_FIELD_GET(PANEL_LIGHT_OFF_DELAY_MASK, pp_off); 6387 seq->t10 = REG_FIELD_GET(PANEL_POWER_DOWN_DELAY_MASK, pp_off); 6388 6389 if (i915_mmio_reg_valid(regs.pp_div)) { 6390 u32 pp_div; 6391 6392 pp_div = I915_READ(regs.pp_div); 6393 6394 seq->t11_t12 = REG_FIELD_GET(PANEL_POWER_CYCLE_DELAY_MASK, pp_div) * 1000; 6395 } else { 6396 seq->t11_t12 = REG_FIELD_GET(BXT_POWER_CYCLE_DELAY_MASK, pp_ctl) * 1000; 6397 } 6398 } 6399 6400 static void 6401 intel_pps_dump_state(const char *state_name, const struct edp_power_seq *seq) 6402 { 6403 DRM_DEBUG_KMS("%s t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", 6404 state_name, 6405 seq->t1_t3, seq->t8, seq->t9, seq->t10, seq->t11_t12); 6406 } 6407 6408 static void 6409 intel_pps_verify_state(struct intel_dp *intel_dp) 6410 { 6411 struct edp_power_seq hw; 6412 struct edp_power_seq *sw = &intel_dp->pps_delays; 6413 6414 intel_pps_readout_hw_state(intel_dp, &hw); 6415 6416 if (hw.t1_t3 != sw->t1_t3 || hw.t8 != sw->t8 || hw.t9 != sw->t9 || 6417 hw.t10 != sw->t10 || hw.t11_t12 != sw->t11_t12) { 6418 DRM_ERROR("PPS state mismatch\n"); 6419 intel_pps_dump_state("sw", sw); 6420 intel_pps_dump_state("hw", &hw); 6421 } 6422 } 6423 6424 static void 6425 intel_dp_init_panel_power_sequencer(struct intel_dp *intel_dp) 6426 { 6427 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 6428 struct edp_power_seq cur, vbt, spec, 6429 *final = &intel_dp->pps_delays; 6430 6431 lockdep_assert_held(&dev_priv->pps_mutex); 6432 6433 /* already initialized? */ 6434 if (final->t11_t12 != 0) 6435 return; 6436 6437 intel_pps_readout_hw_state(intel_dp, &cur); 6438 6439 intel_pps_dump_state("cur", &cur); 6440 6441 vbt = dev_priv->vbt.edp.pps; 6442 /* On Toshiba Satellite P50-C-18C system the VBT T12 delay 6443 * of 500ms appears to be too short. Ocassionally the panel 6444 * just fails to power back on. Increasing the delay to 800ms 6445 * seems sufficient to avoid this problem. 6446 */ 6447 if (dev_priv->quirks & QUIRK_INCREASE_T12_DELAY) { 6448 vbt.t11_t12 = max_t(u16, vbt.t11_t12, 1300 * 10); 6449 DRM_DEBUG_KMS("Increasing T12 panel delay as per the quirk to %d\n", 6450 vbt.t11_t12); 6451 } 6452 /* T11_T12 delay is special and actually in units of 100ms, but zero 6453 * based in the hw (so we need to add 100 ms). But the sw vbt 6454 * table multiplies it with 1000 to make it in units of 100usec, 6455 * too. */ 6456 vbt.t11_t12 += 100 * 10; 6457 6458 /* Upper limits from eDP 1.3 spec. Note that we use the clunky units of 6459 * our hw here, which are all in 100usec. */ 6460 spec.t1_t3 = 210 * 10; 6461 spec.t8 = 50 * 10; /* no limit for t8, use t7 instead */ 6462 spec.t9 = 50 * 10; /* no limit for t9, make it symmetric with t8 */ 6463 spec.t10 = 500 * 10; 6464 /* This one is special and actually in units of 100ms, but zero 6465 * based in the hw (so we need to add 100 ms). But the sw vbt 6466 * table multiplies it with 1000 to make it in units of 100usec, 6467 * too. */ 6468 spec.t11_t12 = (510 + 100) * 10; 6469 6470 intel_pps_dump_state("vbt", &vbt); 6471 6472 /* Use the max of the register settings and vbt. If both are 6473 * unset, fall back to the spec limits. */ 6474 #define assign_final(field) final->field = (max(cur.field, vbt.field) == 0 ? \ 6475 spec.field : \ 6476 max(cur.field, vbt.field)) 6477 assign_final(t1_t3); 6478 assign_final(t8); 6479 assign_final(t9); 6480 assign_final(t10); 6481 assign_final(t11_t12); 6482 #undef assign_final 6483 6484 #define get_delay(field) (DIV_ROUND_UP(final->field, 10)) 6485 intel_dp->panel_power_up_delay = get_delay(t1_t3); 6486 intel_dp->backlight_on_delay = get_delay(t8); 6487 intel_dp->backlight_off_delay = get_delay(t9); 6488 intel_dp->panel_power_down_delay = get_delay(t10); 6489 intel_dp->panel_power_cycle_delay = get_delay(t11_t12); 6490 #undef get_delay 6491 6492 DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", 6493 intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, 6494 intel_dp->panel_power_cycle_delay); 6495 6496 DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", 6497 intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); 6498 6499 /* 6500 * We override the HW backlight delays to 1 because we do manual waits 6501 * on them. For T8, even BSpec recommends doing it. For T9, if we 6502 * don't do this, we'll end up waiting for the backlight off delay 6503 * twice: once when we do the manual sleep, and once when we disable 6504 * the panel and wait for the PP_STATUS bit to become zero. 6505 */ 6506 final->t8 = 1; 6507 final->t9 = 1; 6508 6509 /* 6510 * HW has only a 100msec granularity for t11_t12 so round it up 6511 * accordingly. 6512 */ 6513 final->t11_t12 = roundup(final->t11_t12, 100 * 10); 6514 } 6515 6516 static void 6517 intel_dp_init_panel_power_sequencer_registers(struct intel_dp *intel_dp, 6518 bool force_disable_vdd) 6519 { 6520 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 6521 u32 pp_on, pp_off, port_sel = 0; 6522 int div = dev_priv->rawclk_freq / 1000; 6523 struct pps_registers regs; 6524 enum port port = dp_to_dig_port(intel_dp)->base.port; 6525 const struct edp_power_seq *seq = &intel_dp->pps_delays; 6526 6527 lockdep_assert_held(&dev_priv->pps_mutex); 6528 6529 intel_pps_get_registers(intel_dp, ®s); 6530 6531 /* 6532 * On some VLV machines the BIOS can leave the VDD 6533 * enabled even on power sequencers which aren't 6534 * hooked up to any port. This would mess up the 6535 * power domain tracking the first time we pick 6536 * one of these power sequencers for use since 6537 * edp_panel_vdd_on() would notice that the VDD was 6538 * already on and therefore wouldn't grab the power 6539 * domain reference. Disable VDD first to avoid this. 6540 * This also avoids spuriously turning the VDD on as 6541 * soon as the new power sequencer gets initialized. 6542 */ 6543 if (force_disable_vdd) { 6544 u32 pp = ironlake_get_pp_control(intel_dp); 6545 6546 WARN(pp & PANEL_POWER_ON, "Panel power already on\n"); 6547 6548 if (pp & EDP_FORCE_VDD) 6549 DRM_DEBUG_KMS("VDD already on, disabling first\n"); 6550 6551 pp &= ~EDP_FORCE_VDD; 6552 6553 I915_WRITE(regs.pp_ctrl, pp); 6554 } 6555 6556 pp_on = REG_FIELD_PREP(PANEL_POWER_UP_DELAY_MASK, seq->t1_t3) | 6557 REG_FIELD_PREP(PANEL_LIGHT_ON_DELAY_MASK, seq->t8); 6558 pp_off = REG_FIELD_PREP(PANEL_LIGHT_OFF_DELAY_MASK, seq->t9) | 6559 REG_FIELD_PREP(PANEL_POWER_DOWN_DELAY_MASK, seq->t10); 6560 6561 /* Haswell doesn't have any port selection bits for the panel 6562 * power sequencer any more. */ 6563 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 6564 port_sel = PANEL_PORT_SELECT_VLV(port); 6565 } else if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) { 6566 switch (port) { 6567 case PORT_A: 6568 port_sel = PANEL_PORT_SELECT_DPA; 6569 break; 6570 case PORT_C: 6571 port_sel = PANEL_PORT_SELECT_DPC; 6572 break; 6573 case PORT_D: 6574 port_sel = PANEL_PORT_SELECT_DPD; 6575 break; 6576 default: 6577 MISSING_CASE(port); 6578 break; 6579 } 6580 } 6581 6582 pp_on |= port_sel; 6583 6584 I915_WRITE(regs.pp_on, pp_on); 6585 I915_WRITE(regs.pp_off, pp_off); 6586 6587 /* 6588 * Compute the divisor for the pp clock, simply match the Bspec formula. 6589 */ 6590 if (i915_mmio_reg_valid(regs.pp_div)) { 6591 I915_WRITE(regs.pp_div, 6592 REG_FIELD_PREP(PP_REFERENCE_DIVIDER_MASK, (100 * div) / 2 - 1) | 6593 REG_FIELD_PREP(PANEL_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000))); 6594 } else { 6595 u32 pp_ctl; 6596 6597 pp_ctl = I915_READ(regs.pp_ctrl); 6598 pp_ctl &= ~BXT_POWER_CYCLE_DELAY_MASK; 6599 pp_ctl |= REG_FIELD_PREP(BXT_POWER_CYCLE_DELAY_MASK, DIV_ROUND_UP(seq->t11_t12, 1000)); 6600 I915_WRITE(regs.pp_ctrl, pp_ctl); 6601 } 6602 6603 DRM_DEBUG_KMS("panel power sequencer register settings: PP_ON %#x, PP_OFF %#x, PP_DIV %#x\n", 6604 I915_READ(regs.pp_on), 6605 I915_READ(regs.pp_off), 6606 i915_mmio_reg_valid(regs.pp_div) ? 6607 I915_READ(regs.pp_div) : 6608 (I915_READ(regs.pp_ctrl) & BXT_POWER_CYCLE_DELAY_MASK)); 6609 } 6610 6611 static void intel_dp_pps_init(struct intel_dp *intel_dp) 6612 { 6613 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 6614 6615 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 6616 vlv_initial_power_sequencer_setup(intel_dp); 6617 } else { 6618 intel_dp_init_panel_power_sequencer(intel_dp); 6619 intel_dp_init_panel_power_sequencer_registers(intel_dp, false); 6620 } 6621 } 6622 6623 /** 6624 * intel_dp_set_drrs_state - program registers for RR switch to take effect 6625 * @dev_priv: i915 device 6626 * @crtc_state: a pointer to the active intel_crtc_state 6627 * @refresh_rate: RR to be programmed 6628 * 6629 * This function gets called when refresh rate (RR) has to be changed from 6630 * one frequency to another. Switches can be between high and low RR 6631 * supported by the panel or to any other RR based on media playback (in 6632 * this case, RR value needs to be passed from user space). 6633 * 6634 * The caller of this function needs to take a lock on dev_priv->drrs. 6635 */ 6636 static void intel_dp_set_drrs_state(struct drm_i915_private *dev_priv, 6637 const struct intel_crtc_state *crtc_state, 6638 int refresh_rate) 6639 { 6640 struct intel_dp *intel_dp = dev_priv->drrs.dp; 6641 struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); 6642 enum drrs_refresh_rate_type index = DRRS_HIGH_RR; 6643 6644 if (refresh_rate <= 0) { 6645 DRM_DEBUG_KMS("Refresh rate should be positive non-zero.\n"); 6646 return; 6647 } 6648 6649 if (intel_dp == NULL) { 6650 DRM_DEBUG_KMS("DRRS not supported.\n"); 6651 return; 6652 } 6653 6654 if (!intel_crtc) { 6655 DRM_DEBUG_KMS("DRRS: intel_crtc not initialized\n"); 6656 return; 6657 } 6658 6659 if (dev_priv->drrs.type < SEAMLESS_DRRS_SUPPORT) { 6660 DRM_DEBUG_KMS("Only Seamless DRRS supported.\n"); 6661 return; 6662 } 6663 6664 if (intel_dp->attached_connector->panel.downclock_mode->vrefresh == 6665 refresh_rate) 6666 index = DRRS_LOW_RR; 6667 6668 if (index == dev_priv->drrs.refresh_rate_type) { 6669 DRM_DEBUG_KMS( 6670 "DRRS requested for previously set RR...ignoring\n"); 6671 return; 6672 } 6673 6674 if (!crtc_state->base.active) { 6675 DRM_DEBUG_KMS("eDP encoder disabled. CRTC not Active\n"); 6676 return; 6677 } 6678 6679 if (INTEL_GEN(dev_priv) >= 8 && !IS_CHERRYVIEW(dev_priv)) { 6680 switch (index) { 6681 case DRRS_HIGH_RR: 6682 intel_dp_set_m_n(crtc_state, M1_N1); 6683 break; 6684 case DRRS_LOW_RR: 6685 intel_dp_set_m_n(crtc_state, M2_N2); 6686 break; 6687 case DRRS_MAX_RR: 6688 default: 6689 DRM_ERROR("Unsupported refreshrate type\n"); 6690 } 6691 } else if (INTEL_GEN(dev_priv) > 6) { 6692 i915_reg_t reg = PIPECONF(crtc_state->cpu_transcoder); 6693 u32 val; 6694 6695 val = I915_READ(reg); 6696 if (index > DRRS_HIGH_RR) { 6697 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6698 val |= PIPECONF_EDP_RR_MODE_SWITCH_VLV; 6699 else 6700 val |= PIPECONF_EDP_RR_MODE_SWITCH; 6701 } else { 6702 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 6703 val &= ~PIPECONF_EDP_RR_MODE_SWITCH_VLV; 6704 else 6705 val &= ~PIPECONF_EDP_RR_MODE_SWITCH; 6706 } 6707 I915_WRITE(reg, val); 6708 } 6709 6710 dev_priv->drrs.refresh_rate_type = index; 6711 6712 DRM_DEBUG_KMS("eDP Refresh Rate set to : %dHz\n", refresh_rate); 6713 } 6714 6715 /** 6716 * intel_edp_drrs_enable - init drrs struct if supported 6717 * @intel_dp: DP struct 6718 * @crtc_state: A pointer to the active crtc state. 6719 * 6720 * Initializes frontbuffer_bits and drrs.dp 6721 */ 6722 void intel_edp_drrs_enable(struct intel_dp *intel_dp, 6723 const struct intel_crtc_state *crtc_state) 6724 { 6725 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 6726 6727 if (!crtc_state->has_drrs) { 6728 DRM_DEBUG_KMS("Panel doesn't support DRRS\n"); 6729 return; 6730 } 6731 6732 if (dev_priv->psr.enabled) { 6733 DRM_DEBUG_KMS("PSR enabled. Not enabling DRRS.\n"); 6734 return; 6735 } 6736 6737 mutex_lock(&dev_priv->drrs.mutex); 6738 if (dev_priv->drrs.dp) { 6739 DRM_DEBUG_KMS("DRRS already enabled\n"); 6740 goto unlock; 6741 } 6742 6743 dev_priv->drrs.busy_frontbuffer_bits = 0; 6744 6745 dev_priv->drrs.dp = intel_dp; 6746 6747 unlock: 6748 mutex_unlock(&dev_priv->drrs.mutex); 6749 } 6750 6751 /** 6752 * intel_edp_drrs_disable - Disable DRRS 6753 * @intel_dp: DP struct 6754 * @old_crtc_state: Pointer to old crtc_state. 6755 * 6756 */ 6757 void intel_edp_drrs_disable(struct intel_dp *intel_dp, 6758 const struct intel_crtc_state *old_crtc_state) 6759 { 6760 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 6761 6762 if (!old_crtc_state->has_drrs) 6763 return; 6764 6765 mutex_lock(&dev_priv->drrs.mutex); 6766 if (!dev_priv->drrs.dp) { 6767 mutex_unlock(&dev_priv->drrs.mutex); 6768 return; 6769 } 6770 6771 if (dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 6772 intel_dp_set_drrs_state(dev_priv, old_crtc_state, 6773 intel_dp->attached_connector->panel.fixed_mode->vrefresh); 6774 6775 dev_priv->drrs.dp = NULL; 6776 mutex_unlock(&dev_priv->drrs.mutex); 6777 6778 cancel_delayed_work_sync(&dev_priv->drrs.work); 6779 } 6780 6781 static void intel_edp_drrs_downclock_work(struct work_struct *work) 6782 { 6783 struct drm_i915_private *dev_priv = 6784 container_of(work, typeof(*dev_priv), drrs.work.work); 6785 struct intel_dp *intel_dp; 6786 6787 mutex_lock(&dev_priv->drrs.mutex); 6788 6789 intel_dp = dev_priv->drrs.dp; 6790 6791 if (!intel_dp) 6792 goto unlock; 6793 6794 /* 6795 * The delayed work can race with an invalidate hence we need to 6796 * recheck. 6797 */ 6798 6799 if (dev_priv->drrs.busy_frontbuffer_bits) 6800 goto unlock; 6801 6802 if (dev_priv->drrs.refresh_rate_type != DRRS_LOW_RR) { 6803 struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc; 6804 6805 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, 6806 intel_dp->attached_connector->panel.downclock_mode->vrefresh); 6807 } 6808 6809 unlock: 6810 mutex_unlock(&dev_priv->drrs.mutex); 6811 } 6812 6813 /** 6814 * intel_edp_drrs_invalidate - Disable Idleness DRRS 6815 * @dev_priv: i915 device 6816 * @frontbuffer_bits: frontbuffer plane tracking bits 6817 * 6818 * This function gets called everytime rendering on the given planes start. 6819 * Hence DRRS needs to be Upclocked, i.e. (LOW_RR -> HIGH_RR). 6820 * 6821 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 6822 */ 6823 void intel_edp_drrs_invalidate(struct drm_i915_private *dev_priv, 6824 unsigned int frontbuffer_bits) 6825 { 6826 struct drm_crtc *crtc; 6827 enum pipe pipe; 6828 6829 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) 6830 return; 6831 6832 cancel_delayed_work(&dev_priv->drrs.work); 6833 6834 mutex_lock(&dev_priv->drrs.mutex); 6835 if (!dev_priv->drrs.dp) { 6836 mutex_unlock(&dev_priv->drrs.mutex); 6837 return; 6838 } 6839 6840 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; 6841 pipe = to_intel_crtc(crtc)->pipe; 6842 6843 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 6844 dev_priv->drrs.busy_frontbuffer_bits |= frontbuffer_bits; 6845 6846 /* invalidate means busy screen hence upclock */ 6847 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 6848 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, 6849 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); 6850 6851 mutex_unlock(&dev_priv->drrs.mutex); 6852 } 6853 6854 /** 6855 * intel_edp_drrs_flush - Restart Idleness DRRS 6856 * @dev_priv: i915 device 6857 * @frontbuffer_bits: frontbuffer plane tracking bits 6858 * 6859 * This function gets called every time rendering on the given planes has 6860 * completed or flip on a crtc is completed. So DRRS should be upclocked 6861 * (LOW_RR -> HIGH_RR). And also Idleness detection should be started again, 6862 * if no other planes are dirty. 6863 * 6864 * Dirty frontbuffers relevant to DRRS are tracked in busy_frontbuffer_bits. 6865 */ 6866 void intel_edp_drrs_flush(struct drm_i915_private *dev_priv, 6867 unsigned int frontbuffer_bits) 6868 { 6869 struct drm_crtc *crtc; 6870 enum pipe pipe; 6871 6872 if (dev_priv->drrs.type == DRRS_NOT_SUPPORTED) 6873 return; 6874 6875 cancel_delayed_work(&dev_priv->drrs.work); 6876 6877 mutex_lock(&dev_priv->drrs.mutex); 6878 if (!dev_priv->drrs.dp) { 6879 mutex_unlock(&dev_priv->drrs.mutex); 6880 return; 6881 } 6882 6883 crtc = dp_to_dig_port(dev_priv->drrs.dp)->base.base.crtc; 6884 pipe = to_intel_crtc(crtc)->pipe; 6885 6886 frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe); 6887 dev_priv->drrs.busy_frontbuffer_bits &= ~frontbuffer_bits; 6888 6889 /* flush means busy screen hence upclock */ 6890 if (frontbuffer_bits && dev_priv->drrs.refresh_rate_type == DRRS_LOW_RR) 6891 intel_dp_set_drrs_state(dev_priv, to_intel_crtc(crtc)->config, 6892 dev_priv->drrs.dp->attached_connector->panel.fixed_mode->vrefresh); 6893 6894 /* 6895 * flush also means no more activity hence schedule downclock, if all 6896 * other fbs are quiescent too 6897 */ 6898 if (!dev_priv->drrs.busy_frontbuffer_bits) 6899 schedule_delayed_work(&dev_priv->drrs.work, 6900 msecs_to_jiffies(1000)); 6901 mutex_unlock(&dev_priv->drrs.mutex); 6902 } 6903 6904 /** 6905 * DOC: Display Refresh Rate Switching (DRRS) 6906 * 6907 * Display Refresh Rate Switching (DRRS) is a power conservation feature 6908 * which enables swtching between low and high refresh rates, 6909 * dynamically, based on the usage scenario. This feature is applicable 6910 * for internal panels. 6911 * 6912 * Indication that the panel supports DRRS is given by the panel EDID, which 6913 * would list multiple refresh rates for one resolution. 6914 * 6915 * DRRS is of 2 types - static and seamless. 6916 * Static DRRS involves changing refresh rate (RR) by doing a full modeset 6917 * (may appear as a blink on screen) and is used in dock-undock scenario. 6918 * Seamless DRRS involves changing RR without any visual effect to the user 6919 * and can be used during normal system usage. This is done by programming 6920 * certain registers. 6921 * 6922 * Support for static/seamless DRRS may be indicated in the VBT based on 6923 * inputs from the panel spec. 6924 * 6925 * DRRS saves power by switching to low RR based on usage scenarios. 6926 * 6927 * The implementation is based on frontbuffer tracking implementation. When 6928 * there is a disturbance on the screen triggered by user activity or a periodic 6929 * system activity, DRRS is disabled (RR is changed to high RR). When there is 6930 * no movement on screen, after a timeout of 1 second, a switch to low RR is 6931 * made. 6932 * 6933 * For integration with frontbuffer tracking code, intel_edp_drrs_invalidate() 6934 * and intel_edp_drrs_flush() are called. 6935 * 6936 * DRRS can be further extended to support other internal panels and also 6937 * the scenario of video playback wherein RR is set based on the rate 6938 * requested by userspace. 6939 */ 6940 6941 /** 6942 * intel_dp_drrs_init - Init basic DRRS work and mutex. 6943 * @connector: eDP connector 6944 * @fixed_mode: preferred mode of panel 6945 * 6946 * This function is called only once at driver load to initialize basic 6947 * DRRS stuff. 6948 * 6949 * Returns: 6950 * Downclock mode if panel supports it, else return NULL. 6951 * DRRS support is determined by the presence of downclock mode (apart 6952 * from VBT setting). 6953 */ 6954 static struct drm_display_mode * 6955 intel_dp_drrs_init(struct intel_connector *connector, 6956 struct drm_display_mode *fixed_mode) 6957 { 6958 struct drm_i915_private *dev_priv = to_i915(connector->base.dev); 6959 struct drm_display_mode *downclock_mode = NULL; 6960 6961 INIT_DELAYED_WORK(&dev_priv->drrs.work, intel_edp_drrs_downclock_work); 6962 mutex_init(&dev_priv->drrs.mutex); 6963 6964 if (INTEL_GEN(dev_priv) <= 6) { 6965 DRM_DEBUG_KMS("DRRS supported for Gen7 and above\n"); 6966 return NULL; 6967 } 6968 6969 if (dev_priv->vbt.drrs_type != SEAMLESS_DRRS_SUPPORT) { 6970 DRM_DEBUG_KMS("VBT doesn't support DRRS\n"); 6971 return NULL; 6972 } 6973 6974 downclock_mode = intel_panel_edid_downclock_mode(connector, fixed_mode); 6975 if (!downclock_mode) { 6976 DRM_DEBUG_KMS("Downclock mode is not found. DRRS not supported\n"); 6977 return NULL; 6978 } 6979 6980 dev_priv->drrs.type = dev_priv->vbt.drrs_type; 6981 6982 dev_priv->drrs.refresh_rate_type = DRRS_HIGH_RR; 6983 DRM_DEBUG_KMS("seamless DRRS supported for eDP panel.\n"); 6984 return downclock_mode; 6985 } 6986 6987 static bool intel_edp_init_connector(struct intel_dp *intel_dp, 6988 struct intel_connector *intel_connector) 6989 { 6990 struct drm_i915_private *dev_priv = dp_to_i915(intel_dp); 6991 struct drm_device *dev = &dev_priv->drm; 6992 struct drm_connector *connector = &intel_connector->base; 6993 struct drm_display_mode *fixed_mode = NULL; 6994 struct drm_display_mode *downclock_mode = NULL; 6995 bool has_dpcd; 6996 enum pipe pipe = INVALID_PIPE; 6997 intel_wakeref_t wakeref; 6998 struct edid *edid; 6999 7000 if (!intel_dp_is_edp(intel_dp)) 7001 return true; 7002 7003 INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, edp_panel_vdd_work); 7004 7005 /* 7006 * On IBX/CPT we may get here with LVDS already registered. Since the 7007 * driver uses the only internal power sequencer available for both 7008 * eDP and LVDS bail out early in this case to prevent interfering 7009 * with an already powered-on LVDS power sequencer. 7010 */ 7011 if (intel_get_lvds_encoder(dev_priv)) { 7012 WARN_ON(!(HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv))); 7013 DRM_INFO("LVDS was detected, not registering eDP\n"); 7014 7015 return false; 7016 } 7017 7018 with_pps_lock(intel_dp, wakeref) { 7019 intel_dp_init_panel_power_timestamps(intel_dp); 7020 intel_dp_pps_init(intel_dp); 7021 intel_edp_panel_vdd_sanitize(intel_dp); 7022 } 7023 7024 /* Cache DPCD and EDID for edp. */ 7025 has_dpcd = intel_edp_init_dpcd(intel_dp); 7026 7027 if (!has_dpcd) { 7028 /* if this fails, presume the device is a ghost */ 7029 DRM_INFO("failed to retrieve link info, disabling eDP\n"); 7030 goto out_vdd_off; 7031 } 7032 7033 mutex_lock(&dev->mode_config.mutex); 7034 edid = drm_get_edid(connector, &intel_dp->aux.ddc); 7035 if (edid) { 7036 if (drm_add_edid_modes(connector, edid)) { 7037 drm_connector_update_edid_property(connector, 7038 edid); 7039 } else { 7040 kfree(edid); 7041 edid = ERR_PTR(-EINVAL); 7042 } 7043 } else { 7044 edid = ERR_PTR(-ENOENT); 7045 } 7046 intel_connector->edid = edid; 7047 7048 fixed_mode = intel_panel_edid_fixed_mode(intel_connector); 7049 if (fixed_mode) 7050 downclock_mode = intel_dp_drrs_init(intel_connector, fixed_mode); 7051 7052 /* fallback to VBT if available for eDP */ 7053 if (!fixed_mode) 7054 fixed_mode = intel_panel_vbt_fixed_mode(intel_connector); 7055 mutex_unlock(&dev->mode_config.mutex); 7056 7057 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { 7058 intel_dp->edp_notifier.notifier_call = edp_notify_handler; 7059 register_reboot_notifier(&intel_dp->edp_notifier); 7060 7061 /* 7062 * Figure out the current pipe for the initial backlight setup. 7063 * If the current pipe isn't valid, try the PPS pipe, and if that 7064 * fails just assume pipe A. 7065 */ 7066 pipe = vlv_active_pipe(intel_dp); 7067 7068 if (pipe != PIPE_A && pipe != PIPE_B) 7069 pipe = intel_dp->pps_pipe; 7070 7071 if (pipe != PIPE_A && pipe != PIPE_B) 7072 pipe = PIPE_A; 7073 7074 DRM_DEBUG_KMS("using pipe %c for initial backlight setup\n", 7075 pipe_name(pipe)); 7076 } 7077 7078 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); 7079 intel_connector->panel.backlight.power = intel_edp_backlight_power; 7080 intel_panel_setup_backlight(connector, pipe); 7081 7082 if (fixed_mode) 7083 drm_connector_init_panel_orientation_property( 7084 connector, fixed_mode->hdisplay, fixed_mode->vdisplay); 7085 7086 return true; 7087 7088 out_vdd_off: 7089 cancel_delayed_work_sync(&intel_dp->panel_vdd_work); 7090 /* 7091 * vdd might still be enabled do to the delayed vdd off. 7092 * Make sure vdd is actually turned off here. 7093 */ 7094 with_pps_lock(intel_dp, wakeref) 7095 edp_panel_vdd_off_sync(intel_dp); 7096 7097 return false; 7098 } 7099 7100 static void intel_dp_modeset_retry_work_fn(struct work_struct *work) 7101 { 7102 struct intel_connector *intel_connector; 7103 struct drm_connector *connector; 7104 7105 intel_connector = container_of(work, typeof(*intel_connector), 7106 modeset_retry_work); 7107 connector = &intel_connector->base; 7108 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", connector->base.id, 7109 connector->name); 7110 7111 /* Grab the locks before changing connector property*/ 7112 mutex_lock(&connector->dev->mode_config.mutex); 7113 /* Set connector link status to BAD and send a Uevent to notify 7114 * userspace to do a modeset. 7115 */ 7116 drm_connector_set_link_status_property(connector, 7117 DRM_MODE_LINK_STATUS_BAD); 7118 mutex_unlock(&connector->dev->mode_config.mutex); 7119 /* Send Hotplug uevent so userspace can reprobe */ 7120 drm_kms_helper_hotplug_event(connector->dev); 7121 } 7122 7123 bool 7124 intel_dp_init_connector(struct intel_digital_port *intel_dig_port, 7125 struct intel_connector *intel_connector) 7126 { 7127 struct drm_connector *connector = &intel_connector->base; 7128 struct intel_dp *intel_dp = &intel_dig_port->dp; 7129 struct intel_encoder *intel_encoder = &intel_dig_port->base; 7130 struct drm_device *dev = intel_encoder->base.dev; 7131 struct drm_i915_private *dev_priv = to_i915(dev); 7132 enum port port = intel_encoder->port; 7133 enum phy phy = intel_port_to_phy(dev_priv, port); 7134 int type; 7135 7136 /* Initialize the work for modeset in case of link train failure */ 7137 INIT_WORK(&intel_connector->modeset_retry_work, 7138 intel_dp_modeset_retry_work_fn); 7139 7140 if (WARN(intel_dig_port->max_lanes < 1, 7141 "Not enough lanes (%d) for DP on port %c\n", 7142 intel_dig_port->max_lanes, port_name(port))) 7143 return false; 7144 7145 intel_dp_set_source_rates(intel_dp); 7146 7147 intel_dp->reset_link_params = true; 7148 intel_dp->pps_pipe = INVALID_PIPE; 7149 intel_dp->active_pipe = INVALID_PIPE; 7150 7151 /* Preserve the current hw state. */ 7152 intel_dp->DP = I915_READ(intel_dp->output_reg); 7153 intel_dp->attached_connector = intel_connector; 7154 7155 if (intel_dp_is_port_edp(dev_priv, port)) { 7156 /* 7157 * Currently we don't support eDP on TypeC ports, although in 7158 * theory it could work on TypeC legacy ports. 7159 */ 7160 WARN_ON(intel_phy_is_tc(dev_priv, phy)); 7161 type = DRM_MODE_CONNECTOR_eDP; 7162 } else { 7163 type = DRM_MODE_CONNECTOR_DisplayPort; 7164 } 7165 7166 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) 7167 intel_dp->active_pipe = vlv_active_pipe(intel_dp); 7168 7169 /* 7170 * For eDP we always set the encoder type to INTEL_OUTPUT_EDP, but 7171 * for DP the encoder type can be set by the caller to 7172 * INTEL_OUTPUT_UNKNOWN for DDI, so don't rewrite it. 7173 */ 7174 if (type == DRM_MODE_CONNECTOR_eDP) 7175 intel_encoder->type = INTEL_OUTPUT_EDP; 7176 7177 /* eDP only on port B and/or C on vlv/chv */ 7178 if (WARN_ON((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) && 7179 intel_dp_is_edp(intel_dp) && 7180 port != PORT_B && port != PORT_C)) 7181 return false; 7182 7183 DRM_DEBUG_KMS("Adding %s connector on port %c\n", 7184 type == DRM_MODE_CONNECTOR_eDP ? "eDP" : "DP", 7185 port_name(port)); 7186 7187 drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); 7188 drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); 7189 7190 if (!HAS_GMCH(dev_priv)) 7191 connector->interlace_allowed = true; 7192 connector->doublescan_allowed = 0; 7193 7194 if (INTEL_GEN(dev_priv) >= 11) 7195 connector->ycbcr_420_allowed = true; 7196 7197 intel_encoder->hpd_pin = intel_hpd_pin_default(dev_priv, port); 7198 7199 intel_dp_aux_init(intel_dp); 7200 7201 intel_connector_attach_encoder(intel_connector, intel_encoder); 7202 7203 if (HAS_DDI(dev_priv)) 7204 intel_connector->get_hw_state = intel_ddi_connector_get_hw_state; 7205 else 7206 intel_connector->get_hw_state = intel_connector_get_hw_state; 7207 7208 /* init MST on ports that can support it */ 7209 if (HAS_DP_MST(dev_priv) && !intel_dp_is_edp(intel_dp) && 7210 (port == PORT_B || port == PORT_C || 7211 port == PORT_D || port == PORT_F)) 7212 intel_dp_mst_encoder_init(intel_dig_port, 7213 intel_connector->base.base.id); 7214 7215 if (!intel_edp_init_connector(intel_dp, intel_connector)) { 7216 intel_dp_aux_fini(intel_dp); 7217 intel_dp_mst_encoder_cleanup(intel_dig_port); 7218 goto fail; 7219 } 7220 7221 intel_dp_add_properties(intel_dp, connector); 7222 7223 if (is_hdcp_supported(dev_priv, port) && !intel_dp_is_edp(intel_dp)) { 7224 int ret = intel_hdcp_init(intel_connector, &intel_dp_hdcp_shim); 7225 if (ret) 7226 DRM_DEBUG_KMS("HDCP init failed, skipping.\n"); 7227 } 7228 7229 /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written 7230 * 0xd. Failure to do so will result in spurious interrupts being 7231 * generated on the port when a cable is not attached. 7232 */ 7233 if (IS_G45(dev_priv)) { 7234 u32 temp = I915_READ(PEG_BAND_GAP_DATA); 7235 I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); 7236 } 7237 7238 return true; 7239 7240 fail: 7241 drm_connector_cleanup(connector); 7242 7243 return false; 7244 } 7245 7246 bool intel_dp_init(struct drm_i915_private *dev_priv, 7247 i915_reg_t output_reg, 7248 enum port port) 7249 { 7250 struct intel_digital_port *intel_dig_port; 7251 struct intel_encoder *intel_encoder; 7252 struct drm_encoder *encoder; 7253 struct intel_connector *intel_connector; 7254 7255 intel_dig_port = kzalloc(sizeof(*intel_dig_port), GFP_KERNEL); 7256 if (!intel_dig_port) 7257 return false; 7258 7259 intel_connector = intel_connector_alloc(); 7260 if (!intel_connector) 7261 goto err_connector_alloc; 7262 7263 intel_encoder = &intel_dig_port->base; 7264 encoder = &intel_encoder->base; 7265 7266 if (drm_encoder_init(&dev_priv->drm, &intel_encoder->base, 7267 &intel_dp_enc_funcs, DRM_MODE_ENCODER_TMDS, 7268 "DP %c", port_name(port))) 7269 goto err_encoder_init; 7270 7271 intel_encoder->hotplug = intel_dp_hotplug; 7272 intel_encoder->compute_config = intel_dp_compute_config; 7273 intel_encoder->get_hw_state = intel_dp_get_hw_state; 7274 intel_encoder->get_config = intel_dp_get_config; 7275 intel_encoder->update_pipe = intel_panel_update_backlight; 7276 intel_encoder->suspend = intel_dp_encoder_suspend; 7277 if (IS_CHERRYVIEW(dev_priv)) { 7278 intel_encoder->pre_pll_enable = chv_dp_pre_pll_enable; 7279 intel_encoder->pre_enable = chv_pre_enable_dp; 7280 intel_encoder->enable = vlv_enable_dp; 7281 intel_encoder->disable = vlv_disable_dp; 7282 intel_encoder->post_disable = chv_post_disable_dp; 7283 intel_encoder->post_pll_disable = chv_dp_post_pll_disable; 7284 } else if (IS_VALLEYVIEW(dev_priv)) { 7285 intel_encoder->pre_pll_enable = vlv_dp_pre_pll_enable; 7286 intel_encoder->pre_enable = vlv_pre_enable_dp; 7287 intel_encoder->enable = vlv_enable_dp; 7288 intel_encoder->disable = vlv_disable_dp; 7289 intel_encoder->post_disable = vlv_post_disable_dp; 7290 } else { 7291 intel_encoder->pre_enable = g4x_pre_enable_dp; 7292 intel_encoder->enable = g4x_enable_dp; 7293 intel_encoder->disable = g4x_disable_dp; 7294 intel_encoder->post_disable = g4x_post_disable_dp; 7295 } 7296 7297 intel_dig_port->dp.output_reg = output_reg; 7298 intel_dig_port->max_lanes = 4; 7299 7300 intel_encoder->type = INTEL_OUTPUT_DP; 7301 intel_encoder->power_domain = intel_port_to_power_domain(port); 7302 if (IS_CHERRYVIEW(dev_priv)) { 7303 if (port == PORT_D) 7304 intel_encoder->crtc_mask = 1 << 2; 7305 else 7306 intel_encoder->crtc_mask = (1 << 0) | (1 << 1); 7307 } else { 7308 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); 7309 } 7310 intel_encoder->cloneable = 0; 7311 intel_encoder->port = port; 7312 7313 intel_dig_port->hpd_pulse = intel_dp_hpd_pulse; 7314 7315 if (port != PORT_A) 7316 intel_infoframe_init(intel_dig_port); 7317 7318 intel_dig_port->aux_ch = intel_bios_port_aux_ch(dev_priv, port); 7319 if (!intel_dp_init_connector(intel_dig_port, intel_connector)) 7320 goto err_init_connector; 7321 7322 return true; 7323 7324 err_init_connector: 7325 drm_encoder_cleanup(encoder); 7326 err_encoder_init: 7327 kfree(intel_connector); 7328 err_connector_alloc: 7329 kfree(intel_dig_port); 7330 return false; 7331 } 7332 7333 void intel_dp_mst_suspend(struct drm_i915_private *dev_priv) 7334 { 7335 struct intel_encoder *encoder; 7336 7337 for_each_intel_encoder(&dev_priv->drm, encoder) { 7338 struct intel_dp *intel_dp; 7339 7340 if (encoder->type != INTEL_OUTPUT_DDI) 7341 continue; 7342 7343 intel_dp = enc_to_intel_dp(&encoder->base); 7344 7345 if (!intel_dp->can_mst) 7346 continue; 7347 7348 if (intel_dp->is_mst) 7349 drm_dp_mst_topology_mgr_suspend(&intel_dp->mst_mgr); 7350 } 7351 } 7352 7353 void intel_dp_mst_resume(struct drm_i915_private *dev_priv) 7354 { 7355 struct intel_encoder *encoder; 7356 7357 for_each_intel_encoder(&dev_priv->drm, encoder) { 7358 struct intel_dp *intel_dp; 7359 int ret; 7360 7361 if (encoder->type != INTEL_OUTPUT_DDI) 7362 continue; 7363 7364 intel_dp = enc_to_intel_dp(&encoder->base); 7365 7366 if (!intel_dp->can_mst) 7367 continue; 7368 7369 ret = drm_dp_mst_topology_mgr_resume(&intel_dp->mst_mgr); 7370 if (ret) { 7371 intel_dp->is_mst = false; 7372 drm_dp_mst_topology_mgr_set_mst(&intel_dp->mst_mgr, 7373 false); 7374 } 7375 } 7376 } 7377