1 /* SPDX-License-Identifier: MIT */ 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #ifndef __INTEL_DMC_REGS_H__ 7 #define __INTEL_DMC_REGS_H__ 8 9 #include "i915_reg_defs.h" 10 11 #define DMC_PROGRAM(addr, i) _MMIO((addr) + (i) * 4) 12 #define DMC_SSP_BASE_ADDR_GEN9 0x00002FC0 13 #define DMC_HTP_ADDR_SKL 0x00500034 14 #define DMC_SSP_BASE _MMIO(0x8F074) 15 #define DMC_HTP_SKL _MMIO(0x8F004) 16 #define DMC_LAST_WRITE _MMIO(0x8F034) 17 #define DMC_LAST_WRITE_VALUE 0xc003b400 18 #define DMC_MMIO_START_RANGE 0x80000 19 #define DMC_MMIO_END_RANGE 0x8FFFF 20 #define SKL_DMC_DC3_DC5_COUNT _MMIO(0x80030) 21 #define SKL_DMC_DC5_DC6_COUNT _MMIO(0x8002C) 22 #define BXT_DMC_DC3_DC5_COUNT _MMIO(0x80038) 23 #define TGL_DMC_DEBUG_DC5_COUNT _MMIO(0x101084) 24 #define TGL_DMC_DEBUG_DC6_COUNT _MMIO(0x101088) 25 #define DG1_DMC_DEBUG_DC5_COUNT _MMIO(0x134154) 26 27 #define TGL_DMC_DEBUG3 _MMIO(0x101090) 28 #define DG1_DMC_DEBUG3 _MMIO(0x13415c) 29 30 #endif /* __INTEL_DMC_REGS_H__ */ 31