132f9402dSAnusha Srivatsa /* SPDX-License-Identifier: MIT */ 232f9402dSAnusha Srivatsa /* 332f9402dSAnusha Srivatsa * Copyright © 2019 Intel Corporation 432f9402dSAnusha Srivatsa */ 532f9402dSAnusha Srivatsa 632f9402dSAnusha Srivatsa #ifndef __INTEL_DMC_H__ 732f9402dSAnusha Srivatsa #define __INTEL_DMC_H__ 832f9402dSAnusha Srivatsa 9ce2fce25SMatt Roper #include "i915_reg_defs.h" 103ed131e5SAnusha Srivatsa #include "intel_wakeref.h" 113ed131e5SAnusha Srivatsa #include <linux/workqueue.h> 123ed131e5SAnusha Srivatsa 135efde05fSJani Nikula struct drm_i915_error_state_buf; 1432f9402dSAnusha Srivatsa struct drm_i915_private; 1532f9402dSAnusha Srivatsa 16451e05e2SAnusha Srivatsa enum { 17451e05e2SAnusha Srivatsa DMC_FW_MAIN = 0, 183d5928a1SAnusha Srivatsa DMC_FW_PIPEA, 192ef140bdSAnusha Srivatsa DMC_FW_PIPEB, 20f2787d87SAnusha Srivatsa DMC_FW_PIPEC, 21f2787d87SAnusha Srivatsa DMC_FW_PIPED, 22451e05e2SAnusha Srivatsa DMC_FW_MAX 23451e05e2SAnusha Srivatsa }; 24451e05e2SAnusha Srivatsa 253ed131e5SAnusha Srivatsa struct intel_dmc { 263ed131e5SAnusha Srivatsa struct work_struct work; 273ed131e5SAnusha Srivatsa const char *fw_path; 283ed131e5SAnusha Srivatsa u32 required_version; 293ed131e5SAnusha Srivatsa u32 max_fw_size; /* bytes */ 303ed131e5SAnusha Srivatsa u32 version; 31451e05e2SAnusha Srivatsa struct dmc_fw_info { 323ed131e5SAnusha Srivatsa u32 mmio_count; 333ed131e5SAnusha Srivatsa i915_reg_t mmioaddr[20]; 343ed131e5SAnusha Srivatsa u32 mmiodata[20]; 353d5928a1SAnusha Srivatsa u32 dmc_offset; 363d5928a1SAnusha Srivatsa u32 start_mmioaddr; 37451e05e2SAnusha Srivatsa u32 dmc_fw_size; /*dwords */ 38451e05e2SAnusha Srivatsa u32 *payload; 393d5928a1SAnusha Srivatsa bool present; 40451e05e2SAnusha Srivatsa } dmc_info[DMC_FW_MAX]; 41451e05e2SAnusha Srivatsa 423ed131e5SAnusha Srivatsa u32 dc_state; 433ed131e5SAnusha Srivatsa u32 target_dc_state; 443ed131e5SAnusha Srivatsa u32 allowed_dc_mask; 453ed131e5SAnusha Srivatsa intel_wakeref_t wakeref; 463ed131e5SAnusha Srivatsa }; 473ed131e5SAnusha Srivatsa 4832f9402dSAnusha Srivatsa void intel_dmc_ucode_init(struct drm_i915_private *i915); 4932f9402dSAnusha Srivatsa void intel_dmc_load_program(struct drm_i915_private *i915); 50*fa6a4cdeSImre Deak void intel_dmc_disable_program(struct drm_i915_private *i915); 5132f9402dSAnusha Srivatsa void intel_dmc_ucode_fini(struct drm_i915_private *i915); 5232f9402dSAnusha Srivatsa void intel_dmc_ucode_suspend(struct drm_i915_private *i915); 5332f9402dSAnusha Srivatsa void intel_dmc_ucode_resume(struct drm_i915_private *i915); 5403256487SAnusha Srivatsa bool intel_dmc_has_payload(struct drm_i915_private *i915); 55f0147745SJani Nikula void intel_dmc_debugfs_register(struct drm_i915_private *i915); 565efde05fSJani Nikula void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m, 575efde05fSJani Nikula struct drm_i915_private *i915); 5832f9402dSAnusha Srivatsa 59790daf74SJani Nikula void assert_dmc_loaded(struct drm_i915_private *i915); 60790daf74SJani Nikula 6132f9402dSAnusha Srivatsa #endif /* __INTEL_DMC_H__ */ 62