132f9402dSAnusha Srivatsa /* SPDX-License-Identifier: MIT */ 232f9402dSAnusha Srivatsa /* 332f9402dSAnusha Srivatsa * Copyright © 2019 Intel Corporation 432f9402dSAnusha Srivatsa */ 532f9402dSAnusha Srivatsa 632f9402dSAnusha Srivatsa #ifndef __INTEL_DMC_H__ 732f9402dSAnusha Srivatsa #define __INTEL_DMC_H__ 832f9402dSAnusha Srivatsa 9ce2fce25SMatt Roper #include "i915_reg_defs.h" 103ed131e5SAnusha Srivatsa #include "intel_wakeref.h" 113ed131e5SAnusha Srivatsa #include <linux/workqueue.h> 123ed131e5SAnusha Srivatsa 135efde05fSJani Nikula struct drm_i915_error_state_buf; 1432f9402dSAnusha Srivatsa struct drm_i915_private; 1532f9402dSAnusha Srivatsa 163af2ff08SImre Deak enum pipe; 173af2ff08SImre Deak 18e4ef6503SJani Nikula enum intel_dmc_id { 19451e05e2SAnusha Srivatsa DMC_FW_MAIN = 0, 203d5928a1SAnusha Srivatsa DMC_FW_PIPEA, 212ef140bdSAnusha Srivatsa DMC_FW_PIPEB, 22f2787d87SAnusha Srivatsa DMC_FW_PIPEC, 23f2787d87SAnusha Srivatsa DMC_FW_PIPED, 24451e05e2SAnusha Srivatsa DMC_FW_MAX 25451e05e2SAnusha Srivatsa }; 26451e05e2SAnusha Srivatsa 273ed131e5SAnusha Srivatsa struct intel_dmc { 283ed131e5SAnusha Srivatsa struct work_struct work; 293ed131e5SAnusha Srivatsa const char *fw_path; 303ed131e5SAnusha Srivatsa u32 max_fw_size; /* bytes */ 313ed131e5SAnusha Srivatsa u32 version; 32451e05e2SAnusha Srivatsa struct dmc_fw_info { 333ed131e5SAnusha Srivatsa u32 mmio_count; 343ed131e5SAnusha Srivatsa i915_reg_t mmioaddr[20]; 353ed131e5SAnusha Srivatsa u32 mmiodata[20]; 363d5928a1SAnusha Srivatsa u32 dmc_offset; 373d5928a1SAnusha Srivatsa u32 start_mmioaddr; 38451e05e2SAnusha Srivatsa u32 dmc_fw_size; /*dwords */ 39451e05e2SAnusha Srivatsa u32 *payload; 403d5928a1SAnusha Srivatsa bool present; 41451e05e2SAnusha Srivatsa } dmc_info[DMC_FW_MAX]; 42451e05e2SAnusha Srivatsa 433ed131e5SAnusha Srivatsa u32 dc_state; 443ed131e5SAnusha Srivatsa u32 target_dc_state; 453ed131e5SAnusha Srivatsa u32 allowed_dc_mask; 463ed131e5SAnusha Srivatsa intel_wakeref_t wakeref; 473ed131e5SAnusha Srivatsa }; 483ed131e5SAnusha Srivatsa 49*ac7215c4SJani Nikula void intel_dmc_init(struct drm_i915_private *i915); 5032f9402dSAnusha Srivatsa void intel_dmc_load_program(struct drm_i915_private *i915); 51fa6a4cdeSImre Deak void intel_dmc_disable_program(struct drm_i915_private *i915); 523af2ff08SImre Deak void intel_dmc_enable_pipe(struct drm_i915_private *i915, enum pipe pipe); 533af2ff08SImre Deak void intel_dmc_disable_pipe(struct drm_i915_private *i915, enum pipe pipe); 54*ac7215c4SJani Nikula void intel_dmc_fini(struct drm_i915_private *i915); 55*ac7215c4SJani Nikula void intel_dmc_suspend(struct drm_i915_private *i915); 56*ac7215c4SJani Nikula void intel_dmc_resume(struct drm_i915_private *i915); 5703256487SAnusha Srivatsa bool intel_dmc_has_payload(struct drm_i915_private *i915); 58f0147745SJani Nikula void intel_dmc_debugfs_register(struct drm_i915_private *i915); 595efde05fSJani Nikula void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m, 605efde05fSJani Nikula struct drm_i915_private *i915); 6132f9402dSAnusha Srivatsa 62790daf74SJani Nikula void assert_dmc_loaded(struct drm_i915_private *i915); 63790daf74SJani Nikula 6432f9402dSAnusha Srivatsa #endif /* __INTEL_DMC_H__ */ 65