132f9402dSAnusha Srivatsa /* SPDX-License-Identifier: MIT */ 232f9402dSAnusha Srivatsa /* 332f9402dSAnusha Srivatsa * Copyright © 2019 Intel Corporation 432f9402dSAnusha Srivatsa */ 532f9402dSAnusha Srivatsa 632f9402dSAnusha Srivatsa #ifndef __INTEL_DMC_H__ 732f9402dSAnusha Srivatsa #define __INTEL_DMC_H__ 832f9402dSAnusha Srivatsa 9ce2fce25SMatt Roper #include "i915_reg_defs.h" 103ed131e5SAnusha Srivatsa #include "intel_wakeref.h" 113ed131e5SAnusha Srivatsa #include <linux/workqueue.h> 123ed131e5SAnusha Srivatsa 13*5efde05fSJani Nikula struct drm_i915_error_state_buf; 1432f9402dSAnusha Srivatsa struct drm_i915_private; 1532f9402dSAnusha Srivatsa 1632f9402dSAnusha Srivatsa #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 1732f9402dSAnusha Srivatsa #define DMC_VERSION_MAJOR(version) ((version) >> 16) 1832f9402dSAnusha Srivatsa #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 1932f9402dSAnusha Srivatsa 20451e05e2SAnusha Srivatsa enum { 21451e05e2SAnusha Srivatsa DMC_FW_MAIN = 0, 223d5928a1SAnusha Srivatsa DMC_FW_PIPEA, 232ef140bdSAnusha Srivatsa DMC_FW_PIPEB, 24f2787d87SAnusha Srivatsa DMC_FW_PIPEC, 25f2787d87SAnusha Srivatsa DMC_FW_PIPED, 26451e05e2SAnusha Srivatsa DMC_FW_MAX 27451e05e2SAnusha Srivatsa }; 28451e05e2SAnusha Srivatsa 293ed131e5SAnusha Srivatsa struct intel_dmc { 303ed131e5SAnusha Srivatsa struct work_struct work; 313ed131e5SAnusha Srivatsa const char *fw_path; 323ed131e5SAnusha Srivatsa u32 required_version; 333ed131e5SAnusha Srivatsa u32 max_fw_size; /* bytes */ 343ed131e5SAnusha Srivatsa u32 version; 35451e05e2SAnusha Srivatsa struct dmc_fw_info { 363ed131e5SAnusha Srivatsa u32 mmio_count; 373ed131e5SAnusha Srivatsa i915_reg_t mmioaddr[20]; 383ed131e5SAnusha Srivatsa u32 mmiodata[20]; 393d5928a1SAnusha Srivatsa u32 dmc_offset; 403d5928a1SAnusha Srivatsa u32 start_mmioaddr; 41451e05e2SAnusha Srivatsa u32 dmc_fw_size; /*dwords */ 42451e05e2SAnusha Srivatsa u32 *payload; 433d5928a1SAnusha Srivatsa bool present; 44451e05e2SAnusha Srivatsa } dmc_info[DMC_FW_MAX]; 45451e05e2SAnusha Srivatsa 463ed131e5SAnusha Srivatsa u32 dc_state; 473ed131e5SAnusha Srivatsa u32 target_dc_state; 483ed131e5SAnusha Srivatsa u32 allowed_dc_mask; 493ed131e5SAnusha Srivatsa intel_wakeref_t wakeref; 503ed131e5SAnusha Srivatsa }; 513ed131e5SAnusha Srivatsa 5232f9402dSAnusha Srivatsa void intel_dmc_ucode_init(struct drm_i915_private *i915); 5332f9402dSAnusha Srivatsa void intel_dmc_load_program(struct drm_i915_private *i915); 5432f9402dSAnusha Srivatsa void intel_dmc_ucode_fini(struct drm_i915_private *i915); 5532f9402dSAnusha Srivatsa void intel_dmc_ucode_suspend(struct drm_i915_private *i915); 5632f9402dSAnusha Srivatsa void intel_dmc_ucode_resume(struct drm_i915_private *i915); 5703256487SAnusha Srivatsa bool intel_dmc_has_payload(struct drm_i915_private *i915); 58f0147745SJani Nikula void intel_dmc_debugfs_register(struct drm_i915_private *i915); 59*5efde05fSJani Nikula void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m, 60*5efde05fSJani Nikula struct drm_i915_private *i915); 6132f9402dSAnusha Srivatsa 62790daf74SJani Nikula void assert_dmc_loaded(struct drm_i915_private *i915); 63790daf74SJani Nikula 6432f9402dSAnusha Srivatsa #endif /* __INTEL_DMC_H__ */ 65