1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/firmware.h> 26 27 #include "i915_drv.h" 28 #include "i915_reg.h" 29 #include "intel_de.h" 30 #include "intel_dmc.h" 31 32 /** 33 * DOC: DMC Firmware Support 34 * 35 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 36 * engine to save and restore the state of display engine when it enter into 37 * low-power state and comes back to normal. 38 */ 39 40 #define DMC_PATH(platform, major, minor) \ 41 "i915/" \ 42 __stringify(platform) "_dmc_ver" \ 43 __stringify(major) "_" \ 44 __stringify(minor) ".bin" 45 46 #define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 47 48 #define ADLP_DMC_PATH DMC_PATH(adlp, 2, 10) 49 #define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 10) 50 MODULE_FIRMWARE(ADLP_DMC_PATH); 51 52 #define ADLS_DMC_PATH DMC_PATH(adls, 2, 01) 53 #define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1) 54 MODULE_FIRMWARE(ADLS_DMC_PATH); 55 56 #define DG1_DMC_PATH DMC_PATH(dg1, 2, 02) 57 #define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) 58 MODULE_FIRMWARE(DG1_DMC_PATH); 59 60 #define RKL_DMC_PATH DMC_PATH(rkl, 2, 03) 61 #define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 3) 62 MODULE_FIRMWARE(RKL_DMC_PATH); 63 64 #define TGL_DMC_PATH DMC_PATH(tgl, 2, 12) 65 #define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 12) 66 MODULE_FIRMWARE(TGL_DMC_PATH); 67 68 #define ICL_DMC_PATH DMC_PATH(icl, 1, 09) 69 #define ICL_DMC_VERSION_REQUIRED DMC_VERSION(1, 9) 70 #define ICL_DMC_MAX_FW_SIZE 0x6000 71 MODULE_FIRMWARE(ICL_DMC_PATH); 72 73 #define GLK_DMC_PATH DMC_PATH(glk, 1, 04) 74 #define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) 75 #define GLK_DMC_MAX_FW_SIZE 0x4000 76 MODULE_FIRMWARE(GLK_DMC_PATH); 77 78 #define KBL_DMC_PATH DMC_PATH(kbl, 1, 04) 79 #define KBL_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) 80 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 81 MODULE_FIRMWARE(KBL_DMC_PATH); 82 83 #define SKL_DMC_PATH DMC_PATH(skl, 1, 27) 84 #define SKL_DMC_VERSION_REQUIRED DMC_VERSION(1, 27) 85 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 86 MODULE_FIRMWARE(SKL_DMC_PATH); 87 88 #define BXT_DMC_PATH DMC_PATH(bxt, 1, 07) 89 #define BXT_DMC_VERSION_REQUIRED DMC_VERSION(1, 7) 90 #define BXT_DMC_MAX_FW_SIZE 0x3000 91 MODULE_FIRMWARE(BXT_DMC_PATH); 92 93 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 94 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 95 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 96 #define DMC_V1_MAX_MMIO_COUNT 8 97 #define DMC_V3_MAX_MMIO_COUNT 20 98 #define DMC_V1_MMIO_START_RANGE 0x80000 99 100 struct intel_css_header { 101 /* 0x09 for DMC */ 102 u32 module_type; 103 104 /* Includes the DMC specific header in dwords */ 105 u32 header_len; 106 107 /* always value would be 0x10000 */ 108 u32 header_ver; 109 110 /* Not used */ 111 u32 module_id; 112 113 /* Not used */ 114 u32 module_vendor; 115 116 /* in YYYYMMDD format */ 117 u32 date; 118 119 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 120 u32 size; 121 122 /* Not used */ 123 u32 key_size; 124 125 /* Not used */ 126 u32 modulus_size; 127 128 /* Not used */ 129 u32 exponent_size; 130 131 /* Not used */ 132 u32 reserved1[12]; 133 134 /* Major Minor */ 135 u32 version; 136 137 /* Not used */ 138 u32 reserved2[8]; 139 140 /* Not used */ 141 u32 kernel_header_info; 142 } __packed; 143 144 struct intel_fw_info { 145 u8 reserved1; 146 147 /* reserved on package_header version 1, must be 0 on version 2 */ 148 u8 dmc_id; 149 150 /* Stepping (A, B, C, ..., *). * is a wildcard */ 151 char stepping; 152 153 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 154 char substepping; 155 156 u32 offset; 157 u32 reserved2; 158 } __packed; 159 160 struct intel_package_header { 161 /* DMC container header length in dwords */ 162 u8 header_len; 163 164 /* 0x01, 0x02 */ 165 u8 header_ver; 166 167 u8 reserved[10]; 168 169 /* Number of valid entries in the FWInfo array below */ 170 u32 num_entries; 171 } __packed; 172 173 struct intel_dmc_header_base { 174 /* always value would be 0x40403E3E */ 175 u32 signature; 176 177 /* DMC binary header length */ 178 u8 header_len; 179 180 /* 0x01 */ 181 u8 header_ver; 182 183 /* Reserved */ 184 u16 dmcc_ver; 185 186 /* Major, Minor */ 187 u32 project; 188 189 /* Firmware program size (excluding header) in dwords */ 190 u32 fw_size; 191 192 /* Major Minor version */ 193 u32 fw_version; 194 } __packed; 195 196 struct intel_dmc_header_v1 { 197 struct intel_dmc_header_base base; 198 199 /* Number of valid MMIO cycles present. */ 200 u32 mmio_count; 201 202 /* MMIO address */ 203 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 204 205 /* MMIO data */ 206 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 207 208 /* FW filename */ 209 char dfile[32]; 210 211 u32 reserved1[2]; 212 } __packed; 213 214 struct intel_dmc_header_v3 { 215 struct intel_dmc_header_base base; 216 217 /* DMC RAM start MMIO address */ 218 u32 start_mmioaddr; 219 220 u32 reserved[9]; 221 222 /* FW filename */ 223 char dfile[32]; 224 225 /* Number of valid MMIO cycles present. */ 226 u32 mmio_count; 227 228 /* MMIO address */ 229 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 230 231 /* MMIO data */ 232 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 233 } __packed; 234 235 struct stepping_info { 236 char stepping; 237 char substepping; 238 }; 239 240 bool intel_dmc_has_payload(struct drm_i915_private *i915) 241 { 242 return i915->dmc.dmc_info[DMC_FW_MAIN].payload; 243 } 244 245 static const struct stepping_info * 246 intel_get_stepping_info(struct drm_i915_private *i915, 247 struct stepping_info *si) 248 { 249 const char *step_name = intel_step_name(RUNTIME_INFO(i915)->step.display_step); 250 251 si->stepping = step_name[0]; 252 si->substepping = step_name[1]; 253 return si; 254 } 255 256 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) 257 { 258 u32 val, mask; 259 260 mask = DC_STATE_DEBUG_MASK_MEMORY_UP; 261 262 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 263 mask |= DC_STATE_DEBUG_MASK_CORES; 264 265 /* The below bit doesn't need to be cleared ever afterwards */ 266 val = intel_de_read(dev_priv, DC_STATE_DEBUG); 267 if ((val & mask) != mask) { 268 val |= mask; 269 intel_de_write(dev_priv, DC_STATE_DEBUG, val); 270 intel_de_posting_read(dev_priv, DC_STATE_DEBUG); 271 } 272 } 273 274 /** 275 * intel_dmc_load_program() - write the firmware from memory to register. 276 * @dev_priv: i915 drm device. 277 * 278 * DMC firmware is read from a .bin file and kept in internal memory one time. 279 * Everytime display comes back from low power state this function is called to 280 * copy the firmware from internal memory to registers. 281 */ 282 void intel_dmc_load_program(struct drm_i915_private *dev_priv) 283 { 284 struct intel_dmc *dmc = &dev_priv->dmc; 285 u32 id, i; 286 287 if (!HAS_DMC(dev_priv)) { 288 drm_err(&dev_priv->drm, 289 "No DMC support available for this platform\n"); 290 return; 291 } 292 293 if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) { 294 drm_err(&dev_priv->drm, 295 "Tried to program CSR with empty payload\n"); 296 return; 297 } 298 299 assert_rpm_wakelock_held(&dev_priv->runtime_pm); 300 301 preempt_disable(); 302 303 for (id = 0; id < DMC_FW_MAX; id++) { 304 for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) { 305 intel_uncore_write_fw(&dev_priv->uncore, 306 DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i), 307 dmc->dmc_info[id].payload[i]); 308 } 309 } 310 311 preempt_enable(); 312 313 for (id = 0; id < DMC_FW_MAX; id++) { 314 for (i = 0; i < dmc->dmc_info[id].mmio_count; i++) { 315 intel_de_write(dev_priv, dmc->dmc_info[id].mmioaddr[i], 316 dmc->dmc_info[id].mmiodata[i]); 317 } 318 } 319 320 dev_priv->dmc.dc_state = 0; 321 322 gen9_set_dc_state_debugmask(dev_priv); 323 } 324 325 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 326 const struct stepping_info *si) 327 { 328 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 329 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 330 /* 331 * If we don't find a more specific one from above two checks, we 332 * then check for the generic one to be sure to work even with 333 * "broken firmware" 334 */ 335 (si->stepping == '*' && si->substepping == fw_info->substepping) || 336 (fw_info->stepping == '*' && fw_info->substepping == '*')) 337 return true; 338 339 return false; 340 } 341 342 /* 343 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 344 * already sanitized. 345 */ 346 static void dmc_set_fw_offset(struct intel_dmc *dmc, 347 const struct intel_fw_info *fw_info, 348 unsigned int num_entries, 349 const struct stepping_info *si, 350 u8 package_ver) 351 { 352 unsigned int i, id; 353 354 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 355 356 for (i = 0; i < num_entries; i++) { 357 id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 358 359 if (id >= DMC_FW_MAX) { 360 drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", id); 361 continue; 362 } 363 364 /* More specific versions come first, so we don't even have to 365 * check for the stepping since we already found a previous FW 366 * for this id. 367 */ 368 if (dmc->dmc_info[id].present) 369 continue; 370 371 if (fw_info_matches_stepping(&fw_info[i], si)) { 372 dmc->dmc_info[id].present = true; 373 dmc->dmc_info[id].dmc_offset = fw_info[i].offset; 374 } 375 } 376 } 377 378 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 379 const struct intel_dmc_header_base *dmc_header, 380 size_t rem_size, u8 dmc_id) 381 { 382 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 383 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 384 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 385 const u32 *mmioaddr, *mmiodata; 386 u32 mmio_count, mmio_count_max, start_mmioaddr; 387 u8 *payload; 388 389 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 390 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 391 392 /* 393 * Check if we can access common fields, we will checkc again below 394 * after we have read the version 395 */ 396 if (rem_size < sizeof(struct intel_dmc_header_base)) 397 goto error_truncated; 398 399 /* Cope with small differences between v1 and v3 */ 400 if (dmc_header->header_ver == 3) { 401 const struct intel_dmc_header_v3 *v3 = 402 (const struct intel_dmc_header_v3 *)dmc_header; 403 404 if (rem_size < sizeof(struct intel_dmc_header_v3)) 405 goto error_truncated; 406 407 mmioaddr = v3->mmioaddr; 408 mmiodata = v3->mmiodata; 409 mmio_count = v3->mmio_count; 410 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 411 /* header_len is in dwords */ 412 header_len_bytes = dmc_header->header_len * 4; 413 start_mmioaddr = v3->start_mmioaddr; 414 dmc_header_size = sizeof(*v3); 415 } else if (dmc_header->header_ver == 1) { 416 const struct intel_dmc_header_v1 *v1 = 417 (const struct intel_dmc_header_v1 *)dmc_header; 418 419 if (rem_size < sizeof(struct intel_dmc_header_v1)) 420 goto error_truncated; 421 422 mmioaddr = v1->mmioaddr; 423 mmiodata = v1->mmiodata; 424 mmio_count = v1->mmio_count; 425 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 426 header_len_bytes = dmc_header->header_len; 427 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 428 dmc_header_size = sizeof(*v1); 429 } else { 430 drm_err(&i915->drm, "Unknown DMC fw header version: %u\n", 431 dmc_header->header_ver); 432 return 0; 433 } 434 435 if (header_len_bytes != dmc_header_size) { 436 drm_err(&i915->drm, "DMC firmware has wrong dmc header length " 437 "(%u bytes)\n", header_len_bytes); 438 return 0; 439 } 440 441 /* Cache the dmc header info. */ 442 if (mmio_count > mmio_count_max) { 443 drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 444 return 0; 445 } 446 447 for (i = 0; i < mmio_count; i++) { 448 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 449 dmc_info->mmiodata[i] = mmiodata[i]; 450 } 451 dmc_info->mmio_count = mmio_count; 452 dmc_info->start_mmioaddr = start_mmioaddr; 453 454 rem_size -= header_len_bytes; 455 456 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 457 payload_size = dmc_header->fw_size * 4; 458 if (rem_size < payload_size) 459 goto error_truncated; 460 461 if (payload_size > dmc->max_fw_size) { 462 drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size); 463 return 0; 464 } 465 dmc_info->dmc_fw_size = dmc_header->fw_size; 466 467 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 468 if (!dmc_info->payload) 469 return 0; 470 471 payload = (u8 *)(dmc_header) + header_len_bytes; 472 memcpy(dmc_info->payload, payload, payload_size); 473 474 return header_len_bytes + payload_size; 475 476 error_truncated: 477 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 478 return 0; 479 } 480 481 static u32 482 parse_dmc_fw_package(struct intel_dmc *dmc, 483 const struct intel_package_header *package_header, 484 const struct stepping_info *si, 485 size_t rem_size) 486 { 487 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 488 u32 package_size = sizeof(struct intel_package_header); 489 u32 num_entries, max_entries; 490 const struct intel_fw_info *fw_info; 491 492 if (rem_size < package_size) 493 goto error_truncated; 494 495 if (package_header->header_ver == 1) { 496 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 497 } else if (package_header->header_ver == 2) { 498 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 499 } else { 500 drm_err(&i915->drm, "DMC firmware has unknown header version %u\n", 501 package_header->header_ver); 502 return 0; 503 } 504 505 /* 506 * We should always have space for max_entries, 507 * even if not all are used 508 */ 509 package_size += max_entries * sizeof(struct intel_fw_info); 510 if (rem_size < package_size) 511 goto error_truncated; 512 513 if (package_header->header_len * 4 != package_size) { 514 drm_err(&i915->drm, "DMC firmware has wrong package header length " 515 "(%u bytes)\n", package_size); 516 return 0; 517 } 518 519 num_entries = package_header->num_entries; 520 if (WARN_ON(package_header->num_entries > max_entries)) 521 num_entries = max_entries; 522 523 fw_info = (const struct intel_fw_info *) 524 ((u8 *)package_header + sizeof(*package_header)); 525 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 526 package_header->header_ver); 527 528 /* dmc_offset is in dwords */ 529 return package_size; 530 531 error_truncated: 532 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 533 return 0; 534 } 535 536 /* Return number of bytes parsed or 0 on error */ 537 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 538 struct intel_css_header *css_header, 539 size_t rem_size) 540 { 541 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 542 543 if (rem_size < sizeof(struct intel_css_header)) { 544 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 545 return 0; 546 } 547 548 if (sizeof(struct intel_css_header) != 549 (css_header->header_len * 4)) { 550 drm_err(&i915->drm, "DMC firmware has wrong CSS header length " 551 "(%u bytes)\n", 552 (css_header->header_len * 4)); 553 return 0; 554 } 555 556 if (dmc->required_version && 557 css_header->version != dmc->required_version) { 558 drm_info(&i915->drm, "Refusing to load DMC firmware v%u.%u," 559 " please use v%u.%u\n", 560 DMC_VERSION_MAJOR(css_header->version), 561 DMC_VERSION_MINOR(css_header->version), 562 DMC_VERSION_MAJOR(dmc->required_version), 563 DMC_VERSION_MINOR(dmc->required_version)); 564 return 0; 565 } 566 567 dmc->version = css_header->version; 568 569 return sizeof(struct intel_css_header); 570 } 571 572 static void parse_dmc_fw(struct drm_i915_private *dev_priv, 573 const struct firmware *fw) 574 { 575 struct intel_css_header *css_header; 576 struct intel_package_header *package_header; 577 struct intel_dmc_header_base *dmc_header; 578 struct intel_dmc *dmc = &dev_priv->dmc; 579 struct stepping_info display_info = { '*', '*'}; 580 const struct stepping_info *si = intel_get_stepping_info(dev_priv, &display_info); 581 u32 readcount = 0; 582 u32 r, offset; 583 int id; 584 585 if (!fw) 586 return; 587 588 /* Extract CSS Header information */ 589 css_header = (struct intel_css_header *)fw->data; 590 r = parse_dmc_fw_css(dmc, css_header, fw->size); 591 if (!r) 592 return; 593 594 readcount += r; 595 596 /* Extract Package Header information */ 597 package_header = (struct intel_package_header *)&fw->data[readcount]; 598 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); 599 if (!r) 600 return; 601 602 readcount += r; 603 604 for (id = 0; id < DMC_FW_MAX; id++) { 605 if (!dev_priv->dmc.dmc_info[id].present) 606 continue; 607 608 offset = readcount + dmc->dmc_info[id].dmc_offset * 4; 609 if (fw->size - offset < 0) { 610 drm_err(&dev_priv->drm, "Reading beyond the fw_size\n"); 611 continue; 612 } 613 614 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 615 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, id); 616 } 617 } 618 619 static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv) 620 { 621 drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref); 622 dev_priv->dmc.wakeref = 623 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 624 } 625 626 static void intel_dmc_runtime_pm_put(struct drm_i915_private *dev_priv) 627 { 628 intel_wakeref_t wakeref __maybe_unused = 629 fetch_and_zero(&dev_priv->dmc.wakeref); 630 631 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 632 } 633 634 static void dmc_load_work_fn(struct work_struct *work) 635 { 636 struct drm_i915_private *dev_priv; 637 struct intel_dmc *dmc; 638 const struct firmware *fw = NULL; 639 640 dev_priv = container_of(work, typeof(*dev_priv), dmc.work); 641 dmc = &dev_priv->dmc; 642 643 request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev); 644 parse_dmc_fw(dev_priv, fw); 645 646 if (intel_dmc_has_payload(dev_priv)) { 647 intel_dmc_load_program(dev_priv); 648 intel_dmc_runtime_pm_put(dev_priv); 649 650 drm_info(&dev_priv->drm, 651 "Finished loading DMC firmware %s (v%u.%u)\n", 652 dev_priv->dmc.fw_path, DMC_VERSION_MAJOR(dmc->version), 653 DMC_VERSION_MINOR(dmc->version)); 654 } else { 655 drm_notice(&dev_priv->drm, 656 "Failed to load DMC firmware %s." 657 " Disabling runtime power management.\n", 658 dmc->fw_path); 659 drm_notice(&dev_priv->drm, "DMC firmware homepage: %s", 660 INTEL_UC_FIRMWARE_URL); 661 } 662 663 release_firmware(fw); 664 } 665 666 /** 667 * intel_dmc_ucode_init() - initialize the firmware loading. 668 * @dev_priv: i915 drm device. 669 * 670 * This function is called at the time of loading the display driver to read 671 * firmware from a .bin file and copied into a internal memory. 672 */ 673 void intel_dmc_ucode_init(struct drm_i915_private *dev_priv) 674 { 675 struct intel_dmc *dmc = &dev_priv->dmc; 676 677 INIT_WORK(&dev_priv->dmc.work, dmc_load_work_fn); 678 679 if (!HAS_DMC(dev_priv)) 680 return; 681 682 /* 683 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 684 * runtime-suspend. 685 * 686 * On error, we return with the rpm wakeref held to prevent runtime 687 * suspend as runtime suspend *requires* a working DMC for whatever 688 * reason. 689 */ 690 intel_dmc_runtime_pm_get(dev_priv); 691 692 if (IS_ALDERLAKE_P(dev_priv)) { 693 dmc->fw_path = ADLP_DMC_PATH; 694 dmc->required_version = ADLP_DMC_VERSION_REQUIRED; 695 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE; 696 } else if (IS_ALDERLAKE_S(dev_priv)) { 697 dmc->fw_path = ADLS_DMC_PATH; 698 dmc->required_version = ADLS_DMC_VERSION_REQUIRED; 699 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE; 700 } else if (IS_DG1(dev_priv)) { 701 dmc->fw_path = DG1_DMC_PATH; 702 dmc->required_version = DG1_DMC_VERSION_REQUIRED; 703 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE; 704 } else if (IS_ROCKETLAKE(dev_priv)) { 705 dmc->fw_path = RKL_DMC_PATH; 706 dmc->required_version = RKL_DMC_VERSION_REQUIRED; 707 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE; 708 } else if (DISPLAY_VER(dev_priv) >= 12) { 709 dmc->fw_path = TGL_DMC_PATH; 710 dmc->required_version = TGL_DMC_VERSION_REQUIRED; 711 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE; 712 } else if (DISPLAY_VER(dev_priv) == 11) { 713 dmc->fw_path = ICL_DMC_PATH; 714 dmc->required_version = ICL_DMC_VERSION_REQUIRED; 715 dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE; 716 } else if (IS_GEMINILAKE(dev_priv)) { 717 dmc->fw_path = GLK_DMC_PATH; 718 dmc->required_version = GLK_DMC_VERSION_REQUIRED; 719 dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE; 720 } else if (IS_KABYLAKE(dev_priv) || 721 IS_COFFEELAKE(dev_priv) || 722 IS_COMETLAKE(dev_priv)) { 723 dmc->fw_path = KBL_DMC_PATH; 724 dmc->required_version = KBL_DMC_VERSION_REQUIRED; 725 dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE; 726 } else if (IS_SKYLAKE(dev_priv)) { 727 dmc->fw_path = SKL_DMC_PATH; 728 dmc->required_version = SKL_DMC_VERSION_REQUIRED; 729 dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE; 730 } else if (IS_BROXTON(dev_priv)) { 731 dmc->fw_path = BXT_DMC_PATH; 732 dmc->required_version = BXT_DMC_VERSION_REQUIRED; 733 dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE; 734 } 735 736 if (dev_priv->params.dmc_firmware_path) { 737 if (strlen(dev_priv->params.dmc_firmware_path) == 0) { 738 dmc->fw_path = NULL; 739 drm_info(&dev_priv->drm, 740 "Disabling DMC firmware and runtime PM\n"); 741 return; 742 } 743 744 dmc->fw_path = dev_priv->params.dmc_firmware_path; 745 /* Bypass version check for firmware override. */ 746 dmc->required_version = 0; 747 } 748 749 if (!dmc->fw_path) { 750 drm_dbg_kms(&dev_priv->drm, 751 "No known DMC firmware for platform, disabling runtime PM\n"); 752 return; 753 } 754 755 drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path); 756 schedule_work(&dev_priv->dmc.work); 757 } 758 759 /** 760 * intel_dmc_ucode_suspend() - prepare DMC firmware before system suspend 761 * @dev_priv: i915 drm device 762 * 763 * Prepare the DMC firmware before entering system suspend. This includes 764 * flushing pending work items and releasing any resources acquired during 765 * init. 766 */ 767 void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv) 768 { 769 if (!HAS_DMC(dev_priv)) 770 return; 771 772 flush_work(&dev_priv->dmc.work); 773 774 /* Drop the reference held in case DMC isn't loaded. */ 775 if (!intel_dmc_has_payload(dev_priv)) 776 intel_dmc_runtime_pm_put(dev_priv); 777 } 778 779 /** 780 * intel_dmc_ucode_resume() - init DMC firmware during system resume 781 * @dev_priv: i915 drm device 782 * 783 * Reinitialize the DMC firmware during system resume, reacquiring any 784 * resources released in intel_dmc_ucode_suspend(). 785 */ 786 void intel_dmc_ucode_resume(struct drm_i915_private *dev_priv) 787 { 788 if (!HAS_DMC(dev_priv)) 789 return; 790 791 /* 792 * Reacquire the reference to keep RPM disabled in case DMC isn't 793 * loaded. 794 */ 795 if (!intel_dmc_has_payload(dev_priv)) 796 intel_dmc_runtime_pm_get(dev_priv); 797 } 798 799 /** 800 * intel_dmc_ucode_fini() - unload the DMC firmware. 801 * @dev_priv: i915 drm device. 802 * 803 * Firmmware unloading includes freeing the internal memory and reset the 804 * firmware loading status. 805 */ 806 void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv) 807 { 808 if (!HAS_DMC(dev_priv)) 809 return; 810 811 intel_dmc_ucode_suspend(dev_priv); 812 drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref); 813 814 kfree(dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload); 815 } 816