1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/firmware.h> 26 27 #include "i915_drv.h" 28 #include "i915_reg.h" 29 #include "intel_de.h" 30 #include "intel_dmc.h" 31 32 /** 33 * DOC: DMC Firmware Support 34 * 35 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 36 * engine to save and restore the state of display engine when it enter into 37 * low-power state and comes back to normal. 38 */ 39 40 #define DMC_PATH(platform, major, minor) \ 41 "i915/" \ 42 __stringify(platform) "_dmc_ver" \ 43 __stringify(major) "_" \ 44 __stringify(minor) ".bin" 45 46 #define GEN12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 47 48 #define ADLP_DMC_PATH DMC_PATH(adlp, 2, 10) 49 #define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 10) 50 MODULE_FIRMWARE(ADLP_DMC_PATH); 51 52 #define ADLS_DMC_PATH DMC_PATH(adls, 2, 01) 53 #define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1) 54 MODULE_FIRMWARE(ADLS_DMC_PATH); 55 56 #define DG1_DMC_PATH DMC_PATH(dg1, 2, 02) 57 #define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) 58 MODULE_FIRMWARE(DG1_DMC_PATH); 59 60 #define RKL_DMC_PATH DMC_PATH(rkl, 2, 02) 61 #define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) 62 MODULE_FIRMWARE(RKL_DMC_PATH); 63 64 #define TGL_DMC_PATH DMC_PATH(tgl, 2, 08) 65 #define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 8) 66 MODULE_FIRMWARE(TGL_DMC_PATH); 67 68 #define ICL_DMC_PATH DMC_PATH(icl, 1, 09) 69 #define ICL_DMC_VERSION_REQUIRED DMC_VERSION(1, 9) 70 #define ICL_DMC_MAX_FW_SIZE 0x6000 71 MODULE_FIRMWARE(ICL_DMC_PATH); 72 73 #define CNL_DMC_PATH DMC_PATH(cnl, 1, 07) 74 #define CNL_DMC_VERSION_REQUIRED DMC_VERSION(1, 7) 75 #define CNL_DMC_MAX_FW_SIZE GLK_DMC_MAX_FW_SIZE 76 MODULE_FIRMWARE(CNL_DMC_PATH); 77 78 #define GLK_DMC_PATH DMC_PATH(glk, 1, 04) 79 #define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) 80 #define GLK_DMC_MAX_FW_SIZE 0x4000 81 MODULE_FIRMWARE(GLK_DMC_PATH); 82 83 #define KBL_DMC_PATH DMC_PATH(kbl, 1, 04) 84 #define KBL_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) 85 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 86 MODULE_FIRMWARE(KBL_DMC_PATH); 87 88 #define SKL_DMC_PATH DMC_PATH(skl, 1, 27) 89 #define SKL_DMC_VERSION_REQUIRED DMC_VERSION(1, 27) 90 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 91 MODULE_FIRMWARE(SKL_DMC_PATH); 92 93 #define BXT_DMC_PATH DMC_PATH(bxt, 1, 07) 94 #define BXT_DMC_VERSION_REQUIRED DMC_VERSION(1, 7) 95 #define BXT_DMC_MAX_FW_SIZE 0x3000 96 MODULE_FIRMWARE(BXT_DMC_PATH); 97 98 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 99 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 100 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 101 #define DMC_V1_MAX_MMIO_COUNT 8 102 #define DMC_V3_MAX_MMIO_COUNT 20 103 #define DMC_V1_MMIO_START_RANGE 0x80000 104 105 struct intel_css_header { 106 /* 0x09 for DMC */ 107 u32 module_type; 108 109 /* Includes the DMC specific header in dwords */ 110 u32 header_len; 111 112 /* always value would be 0x10000 */ 113 u32 header_ver; 114 115 /* Not used */ 116 u32 module_id; 117 118 /* Not used */ 119 u32 module_vendor; 120 121 /* in YYYYMMDD format */ 122 u32 date; 123 124 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 125 u32 size; 126 127 /* Not used */ 128 u32 key_size; 129 130 /* Not used */ 131 u32 modulus_size; 132 133 /* Not used */ 134 u32 exponent_size; 135 136 /* Not used */ 137 u32 reserved1[12]; 138 139 /* Major Minor */ 140 u32 version; 141 142 /* Not used */ 143 u32 reserved2[8]; 144 145 /* Not used */ 146 u32 kernel_header_info; 147 } __packed; 148 149 struct intel_fw_info { 150 u8 reserved1; 151 152 /* reserved on package_header version 1, must be 0 on version 2 */ 153 u8 dmc_id; 154 155 /* Stepping (A, B, C, ..., *). * is a wildcard */ 156 char stepping; 157 158 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 159 char substepping; 160 161 u32 offset; 162 u32 reserved2; 163 } __packed; 164 165 struct intel_package_header { 166 /* DMC container header length in dwords */ 167 u8 header_len; 168 169 /* 0x01, 0x02 */ 170 u8 header_ver; 171 172 u8 reserved[10]; 173 174 /* Number of valid entries in the FWInfo array below */ 175 u32 num_entries; 176 } __packed; 177 178 struct intel_dmc_header_base { 179 /* always value would be 0x40403E3E */ 180 u32 signature; 181 182 /* DMC binary header length */ 183 u8 header_len; 184 185 /* 0x01 */ 186 u8 header_ver; 187 188 /* Reserved */ 189 u16 dmcc_ver; 190 191 /* Major, Minor */ 192 u32 project; 193 194 /* Firmware program size (excluding header) in dwords */ 195 u32 fw_size; 196 197 /* Major Minor version */ 198 u32 fw_version; 199 } __packed; 200 201 struct intel_dmc_header_v1 { 202 struct intel_dmc_header_base base; 203 204 /* Number of valid MMIO cycles present. */ 205 u32 mmio_count; 206 207 /* MMIO address */ 208 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 209 210 /* MMIO data */ 211 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 212 213 /* FW filename */ 214 char dfile[32]; 215 216 u32 reserved1[2]; 217 } __packed; 218 219 struct intel_dmc_header_v3 { 220 struct intel_dmc_header_base base; 221 222 /* DMC RAM start MMIO address */ 223 u32 start_mmioaddr; 224 225 u32 reserved[9]; 226 227 /* FW filename */ 228 char dfile[32]; 229 230 /* Number of valid MMIO cycles present. */ 231 u32 mmio_count; 232 233 /* MMIO address */ 234 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 235 236 /* MMIO data */ 237 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 238 } __packed; 239 240 struct stepping_info { 241 char stepping; 242 char substepping; 243 }; 244 245 bool intel_dmc_has_payload(struct drm_i915_private *i915) 246 { 247 return i915->dmc.dmc_info[DMC_FW_MAIN].payload; 248 } 249 250 static const struct stepping_info skl_stepping_info[] = { 251 {'A', '0'}, {'B', '0'}, {'C', '0'}, 252 {'D', '0'}, {'E', '0'}, {'F', '0'}, 253 {'G', '0'}, {'H', '0'}, {'I', '0'}, 254 {'J', '0'}, {'K', '0'} 255 }; 256 257 static const struct stepping_info bxt_stepping_info[] = { 258 {'A', '0'}, {'A', '1'}, {'A', '2'}, 259 {'B', '0'}, {'B', '1'}, {'B', '2'} 260 }; 261 262 static const struct stepping_info icl_stepping_info[] = { 263 {'A', '0'}, {'A', '1'}, {'A', '2'}, 264 {'B', '0'}, {'B', '2'}, 265 {'C', '0'} 266 }; 267 268 static const struct stepping_info no_stepping_info = { '*', '*' }; 269 270 static const struct stepping_info * 271 intel_get_stepping_info(struct drm_i915_private *dev_priv) 272 { 273 const struct stepping_info *si; 274 unsigned int size; 275 276 if (IS_ICELAKE(dev_priv)) { 277 size = ARRAY_SIZE(icl_stepping_info); 278 si = icl_stepping_info; 279 } else if (IS_SKYLAKE(dev_priv)) { 280 size = ARRAY_SIZE(skl_stepping_info); 281 si = skl_stepping_info; 282 } else if (IS_BROXTON(dev_priv)) { 283 size = ARRAY_SIZE(bxt_stepping_info); 284 si = bxt_stepping_info; 285 } else { 286 size = 0; 287 si = NULL; 288 } 289 290 if (INTEL_REVID(dev_priv) < size) 291 return si + INTEL_REVID(dev_priv); 292 293 return &no_stepping_info; 294 } 295 296 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) 297 { 298 u32 val, mask; 299 300 mask = DC_STATE_DEBUG_MASK_MEMORY_UP; 301 302 if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv)) 303 mask |= DC_STATE_DEBUG_MASK_CORES; 304 305 /* The below bit doesn't need to be cleared ever afterwards */ 306 val = intel_de_read(dev_priv, DC_STATE_DEBUG); 307 if ((val & mask) != mask) { 308 val |= mask; 309 intel_de_write(dev_priv, DC_STATE_DEBUG, val); 310 intel_de_posting_read(dev_priv, DC_STATE_DEBUG); 311 } 312 } 313 314 /** 315 * intel_dmc_load_program() - write the firmware from memory to register. 316 * @dev_priv: i915 drm device. 317 * 318 * DMC firmware is read from a .bin file and kept in internal memory one time. 319 * Everytime display comes back from low power state this function is called to 320 * copy the firmware from internal memory to registers. 321 */ 322 void intel_dmc_load_program(struct drm_i915_private *dev_priv) 323 { 324 struct intel_dmc *dmc = &dev_priv->dmc; 325 u32 id, i; 326 327 if (!HAS_DMC(dev_priv)) { 328 drm_err(&dev_priv->drm, 329 "No DMC support available for this platform\n"); 330 return; 331 } 332 333 if (!dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload) { 334 drm_err(&dev_priv->drm, 335 "Tried to program CSR with empty payload\n"); 336 return; 337 } 338 339 assert_rpm_wakelock_held(&dev_priv->runtime_pm); 340 341 preempt_disable(); 342 343 for (id = 0; id < DMC_FW_MAX; id++) { 344 for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) { 345 intel_uncore_write_fw(&dev_priv->uncore, 346 DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i), 347 dmc->dmc_info[id].payload[i]); 348 } 349 } 350 351 preempt_enable(); 352 353 for (id = 0; id < DMC_FW_MAX; id++) { 354 for (i = 0; i < dmc->dmc_info[id].mmio_count; i++) { 355 intel_de_write(dev_priv, dmc->dmc_info[id].mmioaddr[i], 356 dmc->dmc_info[id].mmiodata[i]); 357 } 358 } 359 360 dev_priv->dmc.dc_state = 0; 361 362 gen9_set_dc_state_debugmask(dev_priv); 363 } 364 365 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 366 const struct stepping_info *si) 367 { 368 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 369 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 370 /* 371 * If we don't find a more specific one from above two checks, we 372 * then check for the generic one to be sure to work even with 373 * "broken firmware" 374 */ 375 (si->stepping == '*' && si->substepping == fw_info->substepping) || 376 (fw_info->stepping == '*' && fw_info->substepping == '*')) 377 return true; 378 379 return false; 380 } 381 382 /* 383 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 384 * already sanitized. 385 */ 386 static void dmc_set_fw_offset(struct intel_dmc *dmc, 387 const struct intel_fw_info *fw_info, 388 unsigned int num_entries, 389 const struct stepping_info *si, 390 u8 package_ver) 391 { 392 unsigned int i, id; 393 394 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 395 396 for (i = 0; i < num_entries; i++) { 397 id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 398 399 if (id >= DMC_FW_MAX) { 400 drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", id); 401 continue; 402 } 403 404 /* More specific versions come first, so we don't even have to 405 * check for the stepping since we already found a previous FW 406 * for this id. 407 */ 408 if (dmc->dmc_info[id].present) 409 continue; 410 411 if (fw_info_matches_stepping(&fw_info[i], si)) { 412 dmc->dmc_info[id].present = true; 413 dmc->dmc_info[id].dmc_offset = fw_info[i].offset; 414 } 415 } 416 } 417 418 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 419 const struct intel_dmc_header_base *dmc_header, 420 size_t rem_size, u8 dmc_id) 421 { 422 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 423 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 424 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 425 const u32 *mmioaddr, *mmiodata; 426 u32 mmio_count, mmio_count_max, start_mmioaddr; 427 u8 *payload; 428 429 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 430 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 431 432 /* 433 * Check if we can access common fields, we will checkc again below 434 * after we have read the version 435 */ 436 if (rem_size < sizeof(struct intel_dmc_header_base)) 437 goto error_truncated; 438 439 /* Cope with small differences between v1 and v3 */ 440 if (dmc_header->header_ver == 3) { 441 const struct intel_dmc_header_v3 *v3 = 442 (const struct intel_dmc_header_v3 *)dmc_header; 443 444 if (rem_size < sizeof(struct intel_dmc_header_v3)) 445 goto error_truncated; 446 447 mmioaddr = v3->mmioaddr; 448 mmiodata = v3->mmiodata; 449 mmio_count = v3->mmio_count; 450 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 451 /* header_len is in dwords */ 452 header_len_bytes = dmc_header->header_len * 4; 453 start_mmioaddr = v3->start_mmioaddr; 454 dmc_header_size = sizeof(*v3); 455 } else if (dmc_header->header_ver == 1) { 456 const struct intel_dmc_header_v1 *v1 = 457 (const struct intel_dmc_header_v1 *)dmc_header; 458 459 if (rem_size < sizeof(struct intel_dmc_header_v1)) 460 goto error_truncated; 461 462 mmioaddr = v1->mmioaddr; 463 mmiodata = v1->mmiodata; 464 mmio_count = v1->mmio_count; 465 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 466 header_len_bytes = dmc_header->header_len; 467 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 468 dmc_header_size = sizeof(*v1); 469 } else { 470 drm_err(&i915->drm, "Unknown DMC fw header version: %u\n", 471 dmc_header->header_ver); 472 return 0; 473 } 474 475 if (header_len_bytes != dmc_header_size) { 476 drm_err(&i915->drm, "DMC firmware has wrong dmc header length " 477 "(%u bytes)\n", header_len_bytes); 478 return 0; 479 } 480 481 /* Cache the dmc header info. */ 482 if (mmio_count > mmio_count_max) { 483 drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 484 return 0; 485 } 486 487 for (i = 0; i < mmio_count; i++) { 488 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 489 dmc_info->mmiodata[i] = mmiodata[i]; 490 } 491 dmc_info->mmio_count = mmio_count; 492 dmc_info->start_mmioaddr = start_mmioaddr; 493 494 rem_size -= header_len_bytes; 495 496 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 497 payload_size = dmc_header->fw_size * 4; 498 if (rem_size < payload_size) 499 goto error_truncated; 500 501 if (payload_size > dmc->max_fw_size) { 502 drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size); 503 return 0; 504 } 505 dmc_info->dmc_fw_size = dmc_header->fw_size; 506 507 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 508 if (!dmc_info->payload) 509 return 0; 510 511 payload = (u8 *)(dmc_header) + header_len_bytes; 512 memcpy(dmc_info->payload, payload, payload_size); 513 514 return header_len_bytes + payload_size; 515 516 error_truncated: 517 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 518 return 0; 519 } 520 521 static u32 522 parse_dmc_fw_package(struct intel_dmc *dmc, 523 const struct intel_package_header *package_header, 524 const struct stepping_info *si, 525 size_t rem_size) 526 { 527 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 528 u32 package_size = sizeof(struct intel_package_header); 529 u32 num_entries, max_entries; 530 const struct intel_fw_info *fw_info; 531 532 if (rem_size < package_size) 533 goto error_truncated; 534 535 if (package_header->header_ver == 1) { 536 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 537 } else if (package_header->header_ver == 2) { 538 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 539 } else { 540 drm_err(&i915->drm, "DMC firmware has unknown header version %u\n", 541 package_header->header_ver); 542 return 0; 543 } 544 545 /* 546 * We should always have space for max_entries, 547 * even if not all are used 548 */ 549 package_size += max_entries * sizeof(struct intel_fw_info); 550 if (rem_size < package_size) 551 goto error_truncated; 552 553 if (package_header->header_len * 4 != package_size) { 554 drm_err(&i915->drm, "DMC firmware has wrong package header length " 555 "(%u bytes)\n", package_size); 556 return 0; 557 } 558 559 num_entries = package_header->num_entries; 560 if (WARN_ON(package_header->num_entries > max_entries)) 561 num_entries = max_entries; 562 563 fw_info = (const struct intel_fw_info *) 564 ((u8 *)package_header + sizeof(*package_header)); 565 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 566 package_header->header_ver); 567 568 /* dmc_offset is in dwords */ 569 return package_size; 570 571 error_truncated: 572 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 573 return 0; 574 } 575 576 /* Return number of bytes parsed or 0 on error */ 577 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 578 struct intel_css_header *css_header, 579 size_t rem_size) 580 { 581 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 582 583 if (rem_size < sizeof(struct intel_css_header)) { 584 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 585 return 0; 586 } 587 588 if (sizeof(struct intel_css_header) != 589 (css_header->header_len * 4)) { 590 drm_err(&i915->drm, "DMC firmware has wrong CSS header length " 591 "(%u bytes)\n", 592 (css_header->header_len * 4)); 593 return 0; 594 } 595 596 if (dmc->required_version && 597 css_header->version != dmc->required_version) { 598 drm_info(&i915->drm, "Refusing to load DMC firmware v%u.%u," 599 " please use v%u.%u\n", 600 DMC_VERSION_MAJOR(css_header->version), 601 DMC_VERSION_MINOR(css_header->version), 602 DMC_VERSION_MAJOR(dmc->required_version), 603 DMC_VERSION_MINOR(dmc->required_version)); 604 return 0; 605 } 606 607 dmc->version = css_header->version; 608 609 return sizeof(struct intel_css_header); 610 } 611 612 static void parse_dmc_fw(struct drm_i915_private *dev_priv, 613 const struct firmware *fw) 614 { 615 struct intel_css_header *css_header; 616 struct intel_package_header *package_header; 617 struct intel_dmc_header_base *dmc_header; 618 struct intel_dmc *dmc = &dev_priv->dmc; 619 const struct stepping_info *si = intel_get_stepping_info(dev_priv); 620 u32 readcount = 0; 621 u32 r, offset; 622 int id; 623 624 if (!fw) 625 return; 626 627 /* Extract CSS Header information */ 628 css_header = (struct intel_css_header *)fw->data; 629 r = parse_dmc_fw_css(dmc, css_header, fw->size); 630 if (!r) 631 return; 632 633 readcount += r; 634 635 /* Extract Package Header information */ 636 package_header = (struct intel_package_header *)&fw->data[readcount]; 637 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); 638 if (!r) 639 return; 640 641 readcount += r; 642 643 for (id = 0; id < DMC_FW_MAX; id++) { 644 if (!dev_priv->dmc.dmc_info[id].present) 645 continue; 646 647 offset = readcount + dmc->dmc_info[id].dmc_offset * 4; 648 if (fw->size - offset < 0) { 649 drm_err(&dev_priv->drm, "Reading beyond the fw_size\n"); 650 continue; 651 } 652 653 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 654 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, id); 655 } 656 } 657 658 static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv) 659 { 660 drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref); 661 dev_priv->dmc.wakeref = 662 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 663 } 664 665 static void intel_dmc_runtime_pm_put(struct drm_i915_private *dev_priv) 666 { 667 intel_wakeref_t wakeref __maybe_unused = 668 fetch_and_zero(&dev_priv->dmc.wakeref); 669 670 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 671 } 672 673 static void dmc_load_work_fn(struct work_struct *work) 674 { 675 struct drm_i915_private *dev_priv; 676 struct intel_dmc *dmc; 677 const struct firmware *fw = NULL; 678 679 dev_priv = container_of(work, typeof(*dev_priv), dmc.work); 680 dmc = &dev_priv->dmc; 681 682 request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev); 683 parse_dmc_fw(dev_priv, fw); 684 685 if (intel_dmc_has_payload(dev_priv)) { 686 intel_dmc_load_program(dev_priv); 687 intel_dmc_runtime_pm_put(dev_priv); 688 689 drm_info(&dev_priv->drm, 690 "Finished loading DMC firmware %s (v%u.%u)\n", 691 dev_priv->dmc.fw_path, DMC_VERSION_MAJOR(dmc->version), 692 DMC_VERSION_MINOR(dmc->version)); 693 } else { 694 drm_notice(&dev_priv->drm, 695 "Failed to load DMC firmware %s." 696 " Disabling runtime power management.\n", 697 dmc->fw_path); 698 drm_notice(&dev_priv->drm, "DMC firmware homepage: %s", 699 INTEL_UC_FIRMWARE_URL); 700 } 701 702 release_firmware(fw); 703 } 704 705 /** 706 * intel_dmc_ucode_init() - initialize the firmware loading. 707 * @dev_priv: i915 drm device. 708 * 709 * This function is called at the time of loading the display driver to read 710 * firmware from a .bin file and copied into a internal memory. 711 */ 712 void intel_dmc_ucode_init(struct drm_i915_private *dev_priv) 713 { 714 struct intel_dmc *dmc = &dev_priv->dmc; 715 716 INIT_WORK(&dev_priv->dmc.work, dmc_load_work_fn); 717 718 if (!HAS_DMC(dev_priv)) 719 return; 720 721 /* 722 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 723 * runtime-suspend. 724 * 725 * On error, we return with the rpm wakeref held to prevent runtime 726 * suspend as runtime suspend *requires* a working DMC for whatever 727 * reason. 728 */ 729 intel_dmc_runtime_pm_get(dev_priv); 730 731 if (IS_ALDERLAKE_P(dev_priv)) { 732 dmc->fw_path = ADLP_DMC_PATH; 733 dmc->required_version = ADLP_DMC_VERSION_REQUIRED; 734 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE; 735 } else if (IS_ALDERLAKE_S(dev_priv)) { 736 dmc->fw_path = ADLS_DMC_PATH; 737 dmc->required_version = ADLS_DMC_VERSION_REQUIRED; 738 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE; 739 } else if (IS_DG1(dev_priv)) { 740 dmc->fw_path = DG1_DMC_PATH; 741 dmc->required_version = DG1_DMC_VERSION_REQUIRED; 742 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE; 743 } else if (IS_ROCKETLAKE(dev_priv)) { 744 dmc->fw_path = RKL_DMC_PATH; 745 dmc->required_version = RKL_DMC_VERSION_REQUIRED; 746 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE; 747 } else if (DISPLAY_VER(dev_priv) >= 12) { 748 dmc->fw_path = TGL_DMC_PATH; 749 dmc->required_version = TGL_DMC_VERSION_REQUIRED; 750 dmc->max_fw_size = GEN12_DMC_MAX_FW_SIZE; 751 } else if (DISPLAY_VER(dev_priv) == 11) { 752 dmc->fw_path = ICL_DMC_PATH; 753 dmc->required_version = ICL_DMC_VERSION_REQUIRED; 754 dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE; 755 } else if (IS_CANNONLAKE(dev_priv)) { 756 dmc->fw_path = CNL_DMC_PATH; 757 dmc->required_version = CNL_DMC_VERSION_REQUIRED; 758 dmc->max_fw_size = CNL_DMC_MAX_FW_SIZE; 759 } else if (IS_GEMINILAKE(dev_priv)) { 760 dmc->fw_path = GLK_DMC_PATH; 761 dmc->required_version = GLK_DMC_VERSION_REQUIRED; 762 dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE; 763 } else if (IS_KABYLAKE(dev_priv) || 764 IS_COFFEELAKE(dev_priv) || 765 IS_COMETLAKE(dev_priv)) { 766 dmc->fw_path = KBL_DMC_PATH; 767 dmc->required_version = KBL_DMC_VERSION_REQUIRED; 768 dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE; 769 } else if (IS_SKYLAKE(dev_priv)) { 770 dmc->fw_path = SKL_DMC_PATH; 771 dmc->required_version = SKL_DMC_VERSION_REQUIRED; 772 dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE; 773 } else if (IS_BROXTON(dev_priv)) { 774 dmc->fw_path = BXT_DMC_PATH; 775 dmc->required_version = BXT_DMC_VERSION_REQUIRED; 776 dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE; 777 } 778 779 if (dev_priv->params.dmc_firmware_path) { 780 if (strlen(dev_priv->params.dmc_firmware_path) == 0) { 781 dmc->fw_path = NULL; 782 drm_info(&dev_priv->drm, 783 "Disabling DMC firmware and runtime PM\n"); 784 return; 785 } 786 787 dmc->fw_path = dev_priv->params.dmc_firmware_path; 788 /* Bypass version check for firmware override. */ 789 dmc->required_version = 0; 790 } 791 792 if (!dmc->fw_path) { 793 drm_dbg_kms(&dev_priv->drm, 794 "No known DMC firmware for platform, disabling runtime PM\n"); 795 return; 796 } 797 798 drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path); 799 schedule_work(&dev_priv->dmc.work); 800 } 801 802 /** 803 * intel_dmc_ucode_suspend() - prepare DMC firmware before system suspend 804 * @dev_priv: i915 drm device 805 * 806 * Prepare the DMC firmware before entering system suspend. This includes 807 * flushing pending work items and releasing any resources acquired during 808 * init. 809 */ 810 void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv) 811 { 812 if (!HAS_DMC(dev_priv)) 813 return; 814 815 flush_work(&dev_priv->dmc.work); 816 817 /* Drop the reference held in case DMC isn't loaded. */ 818 if (!intel_dmc_has_payload(dev_priv)) 819 intel_dmc_runtime_pm_put(dev_priv); 820 } 821 822 /** 823 * intel_dmc_ucode_resume() - init DMC firmware during system resume 824 * @dev_priv: i915 drm device 825 * 826 * Reinitialize the DMC firmware during system resume, reacquiring any 827 * resources released in intel_dmc_ucode_suspend(). 828 */ 829 void intel_dmc_ucode_resume(struct drm_i915_private *dev_priv) 830 { 831 if (!HAS_DMC(dev_priv)) 832 return; 833 834 /* 835 * Reacquire the reference to keep RPM disabled in case DMC isn't 836 * loaded. 837 */ 838 if (!intel_dmc_has_payload(dev_priv)) 839 intel_dmc_runtime_pm_get(dev_priv); 840 } 841 842 /** 843 * intel_dmc_ucode_fini() - unload the DMC firmware. 844 * @dev_priv: i915 drm device. 845 * 846 * Firmmware unloading includes freeing the internal memory and reset the 847 * firmware loading status. 848 */ 849 void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv) 850 { 851 if (!HAS_DMC(dev_priv)) 852 return; 853 854 intel_dmc_ucode_suspend(dev_priv); 855 drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref); 856 857 kfree(dev_priv->dmc.dmc_info[DMC_FW_MAIN].payload); 858 } 859