1 /* 2 * Copyright © 2014 Intel Corporation 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice (including the next 12 * paragraph) shall be included in all copies or substantial portions of the 13 * Software. 14 * 15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING 20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS 21 * IN THE SOFTWARE. 22 * 23 */ 24 25 #include <linux/firmware.h> 26 27 #include "i915_drv.h" 28 #include "i915_reg.h" 29 #include "intel_de.h" 30 #include "intel_dmc.h" 31 #include "intel_dmc_regs.h" 32 33 /** 34 * DOC: DMC Firmware Support 35 * 36 * From gen9 onwards we have newly added DMC (Display microcontroller) in display 37 * engine to save and restore the state of display engine when it enter into 38 * low-power state and comes back to normal. 39 */ 40 41 #define DMC_VERSION(major, minor) ((major) << 16 | (minor)) 42 #define DMC_VERSION_MAJOR(version) ((version) >> 16) 43 #define DMC_VERSION_MINOR(version) ((version) & 0xffff) 44 45 #define DMC_PATH(platform, major, minor) \ 46 "i915/" \ 47 __stringify(platform) "_dmc_ver" \ 48 __stringify(major) "_" \ 49 __stringify(minor) ".bin" 50 51 #define DISPLAY_VER13_DMC_MAX_FW_SIZE 0x20000 52 53 #define DISPLAY_VER12_DMC_MAX_FW_SIZE ICL_DMC_MAX_FW_SIZE 54 55 #define ADLP_DMC_PATH DMC_PATH(adlp, 2, 16) 56 #define ADLP_DMC_VERSION_REQUIRED DMC_VERSION(2, 16) 57 MODULE_FIRMWARE(ADLP_DMC_PATH); 58 59 #define ADLS_DMC_PATH DMC_PATH(adls, 2, 01) 60 #define ADLS_DMC_VERSION_REQUIRED DMC_VERSION(2, 1) 61 MODULE_FIRMWARE(ADLS_DMC_PATH); 62 63 #define DG1_DMC_PATH DMC_PATH(dg1, 2, 02) 64 #define DG1_DMC_VERSION_REQUIRED DMC_VERSION(2, 2) 65 MODULE_FIRMWARE(DG1_DMC_PATH); 66 67 #define RKL_DMC_PATH DMC_PATH(rkl, 2, 03) 68 #define RKL_DMC_VERSION_REQUIRED DMC_VERSION(2, 3) 69 MODULE_FIRMWARE(RKL_DMC_PATH); 70 71 #define TGL_DMC_PATH DMC_PATH(tgl, 2, 12) 72 #define TGL_DMC_VERSION_REQUIRED DMC_VERSION(2, 12) 73 MODULE_FIRMWARE(TGL_DMC_PATH); 74 75 #define ICL_DMC_PATH DMC_PATH(icl, 1, 09) 76 #define ICL_DMC_VERSION_REQUIRED DMC_VERSION(1, 9) 77 #define ICL_DMC_MAX_FW_SIZE 0x6000 78 MODULE_FIRMWARE(ICL_DMC_PATH); 79 80 #define GLK_DMC_PATH DMC_PATH(glk, 1, 04) 81 #define GLK_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) 82 #define GLK_DMC_MAX_FW_SIZE 0x4000 83 MODULE_FIRMWARE(GLK_DMC_PATH); 84 85 #define KBL_DMC_PATH DMC_PATH(kbl, 1, 04) 86 #define KBL_DMC_VERSION_REQUIRED DMC_VERSION(1, 4) 87 #define KBL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 88 MODULE_FIRMWARE(KBL_DMC_PATH); 89 90 #define SKL_DMC_PATH DMC_PATH(skl, 1, 27) 91 #define SKL_DMC_VERSION_REQUIRED DMC_VERSION(1, 27) 92 #define SKL_DMC_MAX_FW_SIZE BXT_DMC_MAX_FW_SIZE 93 MODULE_FIRMWARE(SKL_DMC_PATH); 94 95 #define BXT_DMC_PATH DMC_PATH(bxt, 1, 07) 96 #define BXT_DMC_VERSION_REQUIRED DMC_VERSION(1, 7) 97 #define BXT_DMC_MAX_FW_SIZE 0x3000 98 MODULE_FIRMWARE(BXT_DMC_PATH); 99 100 #define DMC_DEFAULT_FW_OFFSET 0xFFFFFFFF 101 #define PACKAGE_MAX_FW_INFO_ENTRIES 20 102 #define PACKAGE_V2_MAX_FW_INFO_ENTRIES 32 103 #define DMC_V1_MAX_MMIO_COUNT 8 104 #define DMC_V3_MAX_MMIO_COUNT 20 105 #define DMC_V1_MMIO_START_RANGE 0x80000 106 107 struct intel_css_header { 108 /* 0x09 for DMC */ 109 u32 module_type; 110 111 /* Includes the DMC specific header in dwords */ 112 u32 header_len; 113 114 /* always value would be 0x10000 */ 115 u32 header_ver; 116 117 /* Not used */ 118 u32 module_id; 119 120 /* Not used */ 121 u32 module_vendor; 122 123 /* in YYYYMMDD format */ 124 u32 date; 125 126 /* Size in dwords (CSS_Headerlen + PackageHeaderLen + dmc FWsLen)/4 */ 127 u32 size; 128 129 /* Not used */ 130 u32 key_size; 131 132 /* Not used */ 133 u32 modulus_size; 134 135 /* Not used */ 136 u32 exponent_size; 137 138 /* Not used */ 139 u32 reserved1[12]; 140 141 /* Major Minor */ 142 u32 version; 143 144 /* Not used */ 145 u32 reserved2[8]; 146 147 /* Not used */ 148 u32 kernel_header_info; 149 } __packed; 150 151 struct intel_fw_info { 152 u8 reserved1; 153 154 /* reserved on package_header version 1, must be 0 on version 2 */ 155 u8 dmc_id; 156 157 /* Stepping (A, B, C, ..., *). * is a wildcard */ 158 char stepping; 159 160 /* Sub-stepping (0, 1, ..., *). * is a wildcard */ 161 char substepping; 162 163 u32 offset; 164 u32 reserved2; 165 } __packed; 166 167 struct intel_package_header { 168 /* DMC container header length in dwords */ 169 u8 header_len; 170 171 /* 0x01, 0x02 */ 172 u8 header_ver; 173 174 u8 reserved[10]; 175 176 /* Number of valid entries in the FWInfo array below */ 177 u32 num_entries; 178 } __packed; 179 180 struct intel_dmc_header_base { 181 /* always value would be 0x40403E3E */ 182 u32 signature; 183 184 /* DMC binary header length */ 185 u8 header_len; 186 187 /* 0x01 */ 188 u8 header_ver; 189 190 /* Reserved */ 191 u16 dmcc_ver; 192 193 /* Major, Minor */ 194 u32 project; 195 196 /* Firmware program size (excluding header) in dwords */ 197 u32 fw_size; 198 199 /* Major Minor version */ 200 u32 fw_version; 201 } __packed; 202 203 struct intel_dmc_header_v1 { 204 struct intel_dmc_header_base base; 205 206 /* Number of valid MMIO cycles present. */ 207 u32 mmio_count; 208 209 /* MMIO address */ 210 u32 mmioaddr[DMC_V1_MAX_MMIO_COUNT]; 211 212 /* MMIO data */ 213 u32 mmiodata[DMC_V1_MAX_MMIO_COUNT]; 214 215 /* FW filename */ 216 char dfile[32]; 217 218 u32 reserved1[2]; 219 } __packed; 220 221 struct intel_dmc_header_v3 { 222 struct intel_dmc_header_base base; 223 224 /* DMC RAM start MMIO address */ 225 u32 start_mmioaddr; 226 227 u32 reserved[9]; 228 229 /* FW filename */ 230 char dfile[32]; 231 232 /* Number of valid MMIO cycles present. */ 233 u32 mmio_count; 234 235 /* MMIO address */ 236 u32 mmioaddr[DMC_V3_MAX_MMIO_COUNT]; 237 238 /* MMIO data */ 239 u32 mmiodata[DMC_V3_MAX_MMIO_COUNT]; 240 } __packed; 241 242 struct stepping_info { 243 char stepping; 244 char substepping; 245 }; 246 247 bool intel_dmc_has_payload(struct drm_i915_private *i915) 248 { 249 return i915->dmc.dmc_info[DMC_FW_MAIN].payload; 250 } 251 252 static const struct stepping_info * 253 intel_get_stepping_info(struct drm_i915_private *i915, 254 struct stepping_info *si) 255 { 256 const char *step_name = intel_step_name(RUNTIME_INFO(i915)->step.display_step); 257 258 si->stepping = step_name[0]; 259 si->substepping = step_name[1]; 260 return si; 261 } 262 263 static void gen9_set_dc_state_debugmask(struct drm_i915_private *dev_priv) 264 { 265 /* The below bit doesn't need to be cleared ever afterwards */ 266 intel_de_rmw(dev_priv, DC_STATE_DEBUG, 0, 267 DC_STATE_DEBUG_MASK_CORES | DC_STATE_DEBUG_MASK_MEMORY_UP); 268 intel_de_posting_read(dev_priv, DC_STATE_DEBUG); 269 } 270 271 /** 272 * intel_dmc_load_program() - write the firmware from memory to register. 273 * @dev_priv: i915 drm device. 274 * 275 * DMC firmware is read from a .bin file and kept in internal memory one time. 276 * Everytime display comes back from low power state this function is called to 277 * copy the firmware from internal memory to registers. 278 */ 279 void intel_dmc_load_program(struct drm_i915_private *dev_priv) 280 { 281 struct intel_dmc *dmc = &dev_priv->dmc; 282 u32 id, i; 283 284 if (!intel_dmc_has_payload(dev_priv)) 285 return; 286 287 assert_rpm_wakelock_held(&dev_priv->runtime_pm); 288 289 preempt_disable(); 290 291 for (id = 0; id < DMC_FW_MAX; id++) { 292 for (i = 0; i < dmc->dmc_info[id].dmc_fw_size; i++) { 293 intel_uncore_write_fw(&dev_priv->uncore, 294 DMC_PROGRAM(dmc->dmc_info[id].start_mmioaddr, i), 295 dmc->dmc_info[id].payload[i]); 296 } 297 } 298 299 preempt_enable(); 300 301 for (id = 0; id < DMC_FW_MAX; id++) { 302 for (i = 0; i < dmc->dmc_info[id].mmio_count; i++) { 303 intel_de_write(dev_priv, dmc->dmc_info[id].mmioaddr[i], 304 dmc->dmc_info[id].mmiodata[i]); 305 } 306 } 307 308 dev_priv->dmc.dc_state = 0; 309 310 gen9_set_dc_state_debugmask(dev_priv); 311 } 312 313 void assert_dmc_loaded(struct drm_i915_private *i915) 314 { 315 drm_WARN_ONCE(&i915->drm, 316 !intel_de_read(i915, DMC_PROGRAM(i915->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)), 317 "DMC program storage start is NULL\n"); 318 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_SSP_BASE), 319 "DMC SSP Base Not fine\n"); 320 drm_WARN_ONCE(&i915->drm, !intel_de_read(i915, DMC_HTP_SKL), 321 "DMC HTP Not fine\n"); 322 } 323 324 static bool fw_info_matches_stepping(const struct intel_fw_info *fw_info, 325 const struct stepping_info *si) 326 { 327 if ((fw_info->substepping == '*' && si->stepping == fw_info->stepping) || 328 (si->stepping == fw_info->stepping && si->substepping == fw_info->substepping) || 329 /* 330 * If we don't find a more specific one from above two checks, we 331 * then check for the generic one to be sure to work even with 332 * "broken firmware" 333 */ 334 (si->stepping == '*' && si->substepping == fw_info->substepping) || 335 (fw_info->stepping == '*' && fw_info->substepping == '*')) 336 return true; 337 338 return false; 339 } 340 341 /* 342 * Search fw_info table for dmc_offset to find firmware binary: num_entries is 343 * already sanitized. 344 */ 345 static void dmc_set_fw_offset(struct intel_dmc *dmc, 346 const struct intel_fw_info *fw_info, 347 unsigned int num_entries, 348 const struct stepping_info *si, 349 u8 package_ver) 350 { 351 unsigned int i, id; 352 353 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 354 355 for (i = 0; i < num_entries; i++) { 356 id = package_ver <= 1 ? DMC_FW_MAIN : fw_info[i].dmc_id; 357 358 if (id >= DMC_FW_MAX) { 359 drm_dbg(&i915->drm, "Unsupported firmware id: %u\n", id); 360 continue; 361 } 362 363 /* More specific versions come first, so we don't even have to 364 * check for the stepping since we already found a previous FW 365 * for this id. 366 */ 367 if (dmc->dmc_info[id].present) 368 continue; 369 370 if (fw_info_matches_stepping(&fw_info[i], si)) { 371 dmc->dmc_info[id].present = true; 372 dmc->dmc_info[id].dmc_offset = fw_info[i].offset; 373 } 374 } 375 } 376 377 static u32 parse_dmc_fw_header(struct intel_dmc *dmc, 378 const struct intel_dmc_header_base *dmc_header, 379 size_t rem_size, u8 dmc_id) 380 { 381 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 382 struct dmc_fw_info *dmc_info = &dmc->dmc_info[dmc_id]; 383 unsigned int header_len_bytes, dmc_header_size, payload_size, i; 384 const u32 *mmioaddr, *mmiodata; 385 u32 mmio_count, mmio_count_max, start_mmioaddr; 386 u8 *payload; 387 388 BUILD_BUG_ON(ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V3_MAX_MMIO_COUNT || 389 ARRAY_SIZE(dmc_info->mmioaddr) < DMC_V1_MAX_MMIO_COUNT); 390 391 /* 392 * Check if we can access common fields, we will checkc again below 393 * after we have read the version 394 */ 395 if (rem_size < sizeof(struct intel_dmc_header_base)) 396 goto error_truncated; 397 398 /* Cope with small differences between v1 and v3 */ 399 if (dmc_header->header_ver == 3) { 400 const struct intel_dmc_header_v3 *v3 = 401 (const struct intel_dmc_header_v3 *)dmc_header; 402 403 if (rem_size < sizeof(struct intel_dmc_header_v3)) 404 goto error_truncated; 405 406 mmioaddr = v3->mmioaddr; 407 mmiodata = v3->mmiodata; 408 mmio_count = v3->mmio_count; 409 mmio_count_max = DMC_V3_MAX_MMIO_COUNT; 410 /* header_len is in dwords */ 411 header_len_bytes = dmc_header->header_len * 4; 412 start_mmioaddr = v3->start_mmioaddr; 413 dmc_header_size = sizeof(*v3); 414 } else if (dmc_header->header_ver == 1) { 415 const struct intel_dmc_header_v1 *v1 = 416 (const struct intel_dmc_header_v1 *)dmc_header; 417 418 if (rem_size < sizeof(struct intel_dmc_header_v1)) 419 goto error_truncated; 420 421 mmioaddr = v1->mmioaddr; 422 mmiodata = v1->mmiodata; 423 mmio_count = v1->mmio_count; 424 mmio_count_max = DMC_V1_MAX_MMIO_COUNT; 425 header_len_bytes = dmc_header->header_len; 426 start_mmioaddr = DMC_V1_MMIO_START_RANGE; 427 dmc_header_size = sizeof(*v1); 428 } else { 429 drm_err(&i915->drm, "Unknown DMC fw header version: %u\n", 430 dmc_header->header_ver); 431 return 0; 432 } 433 434 if (header_len_bytes != dmc_header_size) { 435 drm_err(&i915->drm, "DMC firmware has wrong dmc header length " 436 "(%u bytes)\n", header_len_bytes); 437 return 0; 438 } 439 440 /* Cache the dmc header info. */ 441 if (mmio_count > mmio_count_max) { 442 drm_err(&i915->drm, "DMC firmware has wrong mmio count %u\n", mmio_count); 443 return 0; 444 } 445 446 for (i = 0; i < mmio_count; i++) { 447 dmc_info->mmioaddr[i] = _MMIO(mmioaddr[i]); 448 dmc_info->mmiodata[i] = mmiodata[i]; 449 } 450 dmc_info->mmio_count = mmio_count; 451 dmc_info->start_mmioaddr = start_mmioaddr; 452 453 rem_size -= header_len_bytes; 454 455 /* fw_size is in dwords, so multiplied by 4 to convert into bytes. */ 456 payload_size = dmc_header->fw_size * 4; 457 if (rem_size < payload_size) 458 goto error_truncated; 459 460 if (payload_size > dmc->max_fw_size) { 461 drm_err(&i915->drm, "DMC FW too big (%u bytes)\n", payload_size); 462 return 0; 463 } 464 dmc_info->dmc_fw_size = dmc_header->fw_size; 465 466 dmc_info->payload = kmalloc(payload_size, GFP_KERNEL); 467 if (!dmc_info->payload) 468 return 0; 469 470 payload = (u8 *)(dmc_header) + header_len_bytes; 471 memcpy(dmc_info->payload, payload, payload_size); 472 473 return header_len_bytes + payload_size; 474 475 error_truncated: 476 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 477 return 0; 478 } 479 480 static u32 481 parse_dmc_fw_package(struct intel_dmc *dmc, 482 const struct intel_package_header *package_header, 483 const struct stepping_info *si, 484 size_t rem_size) 485 { 486 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 487 u32 package_size = sizeof(struct intel_package_header); 488 u32 num_entries, max_entries; 489 const struct intel_fw_info *fw_info; 490 491 if (rem_size < package_size) 492 goto error_truncated; 493 494 if (package_header->header_ver == 1) { 495 max_entries = PACKAGE_MAX_FW_INFO_ENTRIES; 496 } else if (package_header->header_ver == 2) { 497 max_entries = PACKAGE_V2_MAX_FW_INFO_ENTRIES; 498 } else { 499 drm_err(&i915->drm, "DMC firmware has unknown header version %u\n", 500 package_header->header_ver); 501 return 0; 502 } 503 504 /* 505 * We should always have space for max_entries, 506 * even if not all are used 507 */ 508 package_size += max_entries * sizeof(struct intel_fw_info); 509 if (rem_size < package_size) 510 goto error_truncated; 511 512 if (package_header->header_len * 4 != package_size) { 513 drm_err(&i915->drm, "DMC firmware has wrong package header length " 514 "(%u bytes)\n", package_size); 515 return 0; 516 } 517 518 num_entries = package_header->num_entries; 519 if (WARN_ON(package_header->num_entries > max_entries)) 520 num_entries = max_entries; 521 522 fw_info = (const struct intel_fw_info *) 523 ((u8 *)package_header + sizeof(*package_header)); 524 dmc_set_fw_offset(dmc, fw_info, num_entries, si, 525 package_header->header_ver); 526 527 /* dmc_offset is in dwords */ 528 return package_size; 529 530 error_truncated: 531 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 532 return 0; 533 } 534 535 /* Return number of bytes parsed or 0 on error */ 536 static u32 parse_dmc_fw_css(struct intel_dmc *dmc, 537 struct intel_css_header *css_header, 538 size_t rem_size) 539 { 540 struct drm_i915_private *i915 = container_of(dmc, typeof(*i915), dmc); 541 542 if (rem_size < sizeof(struct intel_css_header)) { 543 drm_err(&i915->drm, "Truncated DMC firmware, refusing.\n"); 544 return 0; 545 } 546 547 if (sizeof(struct intel_css_header) != 548 (css_header->header_len * 4)) { 549 drm_err(&i915->drm, "DMC firmware has wrong CSS header length " 550 "(%u bytes)\n", 551 (css_header->header_len * 4)); 552 return 0; 553 } 554 555 if (dmc->required_version && 556 css_header->version != dmc->required_version) { 557 drm_info(&i915->drm, "Refusing to load DMC firmware v%u.%u," 558 " please use v%u.%u\n", 559 DMC_VERSION_MAJOR(css_header->version), 560 DMC_VERSION_MINOR(css_header->version), 561 DMC_VERSION_MAJOR(dmc->required_version), 562 DMC_VERSION_MINOR(dmc->required_version)); 563 return 0; 564 } 565 566 dmc->version = css_header->version; 567 568 return sizeof(struct intel_css_header); 569 } 570 571 static void parse_dmc_fw(struct drm_i915_private *dev_priv, 572 const struct firmware *fw) 573 { 574 struct intel_css_header *css_header; 575 struct intel_package_header *package_header; 576 struct intel_dmc_header_base *dmc_header; 577 struct intel_dmc *dmc = &dev_priv->dmc; 578 struct stepping_info display_info = { '*', '*'}; 579 const struct stepping_info *si = intel_get_stepping_info(dev_priv, &display_info); 580 u32 readcount = 0; 581 u32 r, offset; 582 int id; 583 584 if (!fw) 585 return; 586 587 /* Extract CSS Header information */ 588 css_header = (struct intel_css_header *)fw->data; 589 r = parse_dmc_fw_css(dmc, css_header, fw->size); 590 if (!r) 591 return; 592 593 readcount += r; 594 595 /* Extract Package Header information */ 596 package_header = (struct intel_package_header *)&fw->data[readcount]; 597 r = parse_dmc_fw_package(dmc, package_header, si, fw->size - readcount); 598 if (!r) 599 return; 600 601 readcount += r; 602 603 for (id = 0; id < DMC_FW_MAX; id++) { 604 if (!dev_priv->dmc.dmc_info[id].present) 605 continue; 606 607 offset = readcount + dmc->dmc_info[id].dmc_offset * 4; 608 if (offset > fw->size) { 609 drm_err(&dev_priv->drm, "Reading beyond the fw_size\n"); 610 continue; 611 } 612 613 dmc_header = (struct intel_dmc_header_base *)&fw->data[offset]; 614 parse_dmc_fw_header(dmc, dmc_header, fw->size - offset, id); 615 } 616 } 617 618 static void intel_dmc_runtime_pm_get(struct drm_i915_private *dev_priv) 619 { 620 drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref); 621 dev_priv->dmc.wakeref = 622 intel_display_power_get(dev_priv, POWER_DOMAIN_INIT); 623 } 624 625 static void intel_dmc_runtime_pm_put(struct drm_i915_private *dev_priv) 626 { 627 intel_wakeref_t wakeref __maybe_unused = 628 fetch_and_zero(&dev_priv->dmc.wakeref); 629 630 intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref); 631 } 632 633 static void dmc_load_work_fn(struct work_struct *work) 634 { 635 struct drm_i915_private *dev_priv; 636 struct intel_dmc *dmc; 637 const struct firmware *fw = NULL; 638 639 dev_priv = container_of(work, typeof(*dev_priv), dmc.work); 640 dmc = &dev_priv->dmc; 641 642 request_firmware(&fw, dev_priv->dmc.fw_path, dev_priv->drm.dev); 643 parse_dmc_fw(dev_priv, fw); 644 645 if (intel_dmc_has_payload(dev_priv)) { 646 intel_dmc_load_program(dev_priv); 647 intel_dmc_runtime_pm_put(dev_priv); 648 649 drm_info(&dev_priv->drm, 650 "Finished loading DMC firmware %s (v%u.%u)\n", 651 dev_priv->dmc.fw_path, DMC_VERSION_MAJOR(dmc->version), 652 DMC_VERSION_MINOR(dmc->version)); 653 } else { 654 drm_notice(&dev_priv->drm, 655 "Failed to load DMC firmware %s." 656 " Disabling runtime power management.\n", 657 dmc->fw_path); 658 drm_notice(&dev_priv->drm, "DMC firmware homepage: %s", 659 INTEL_UC_FIRMWARE_URL); 660 } 661 662 release_firmware(fw); 663 } 664 665 /** 666 * intel_dmc_ucode_init() - initialize the firmware loading. 667 * @dev_priv: i915 drm device. 668 * 669 * This function is called at the time of loading the display driver to read 670 * firmware from a .bin file and copied into a internal memory. 671 */ 672 void intel_dmc_ucode_init(struct drm_i915_private *dev_priv) 673 { 674 struct intel_dmc *dmc = &dev_priv->dmc; 675 676 INIT_WORK(&dev_priv->dmc.work, dmc_load_work_fn); 677 678 if (!HAS_DMC(dev_priv)) 679 return; 680 681 /* 682 * Obtain a runtime pm reference, until DMC is loaded, to avoid entering 683 * runtime-suspend. 684 * 685 * On error, we return with the rpm wakeref held to prevent runtime 686 * suspend as runtime suspend *requires* a working DMC for whatever 687 * reason. 688 */ 689 intel_dmc_runtime_pm_get(dev_priv); 690 691 if (IS_ALDERLAKE_P(dev_priv)) { 692 dmc->fw_path = ADLP_DMC_PATH; 693 dmc->required_version = ADLP_DMC_VERSION_REQUIRED; 694 dmc->max_fw_size = DISPLAY_VER13_DMC_MAX_FW_SIZE; 695 } else if (IS_ALDERLAKE_S(dev_priv)) { 696 dmc->fw_path = ADLS_DMC_PATH; 697 dmc->required_version = ADLS_DMC_VERSION_REQUIRED; 698 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 699 } else if (IS_DG1(dev_priv)) { 700 dmc->fw_path = DG1_DMC_PATH; 701 dmc->required_version = DG1_DMC_VERSION_REQUIRED; 702 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 703 } else if (IS_ROCKETLAKE(dev_priv)) { 704 dmc->fw_path = RKL_DMC_PATH; 705 dmc->required_version = RKL_DMC_VERSION_REQUIRED; 706 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 707 } else if (IS_TIGERLAKE(dev_priv)) { 708 dmc->fw_path = TGL_DMC_PATH; 709 dmc->required_version = TGL_DMC_VERSION_REQUIRED; 710 dmc->max_fw_size = DISPLAY_VER12_DMC_MAX_FW_SIZE; 711 } else if (DISPLAY_VER(dev_priv) == 11) { 712 dmc->fw_path = ICL_DMC_PATH; 713 dmc->required_version = ICL_DMC_VERSION_REQUIRED; 714 dmc->max_fw_size = ICL_DMC_MAX_FW_SIZE; 715 } else if (IS_GEMINILAKE(dev_priv)) { 716 dmc->fw_path = GLK_DMC_PATH; 717 dmc->required_version = GLK_DMC_VERSION_REQUIRED; 718 dmc->max_fw_size = GLK_DMC_MAX_FW_SIZE; 719 } else if (IS_KABYLAKE(dev_priv) || 720 IS_COFFEELAKE(dev_priv) || 721 IS_COMETLAKE(dev_priv)) { 722 dmc->fw_path = KBL_DMC_PATH; 723 dmc->required_version = KBL_DMC_VERSION_REQUIRED; 724 dmc->max_fw_size = KBL_DMC_MAX_FW_SIZE; 725 } else if (IS_SKYLAKE(dev_priv)) { 726 dmc->fw_path = SKL_DMC_PATH; 727 dmc->required_version = SKL_DMC_VERSION_REQUIRED; 728 dmc->max_fw_size = SKL_DMC_MAX_FW_SIZE; 729 } else if (IS_BROXTON(dev_priv)) { 730 dmc->fw_path = BXT_DMC_PATH; 731 dmc->required_version = BXT_DMC_VERSION_REQUIRED; 732 dmc->max_fw_size = BXT_DMC_MAX_FW_SIZE; 733 } 734 735 if (dev_priv->params.dmc_firmware_path) { 736 if (strlen(dev_priv->params.dmc_firmware_path) == 0) { 737 dmc->fw_path = NULL; 738 drm_info(&dev_priv->drm, 739 "Disabling DMC firmware and runtime PM\n"); 740 return; 741 } 742 743 dmc->fw_path = dev_priv->params.dmc_firmware_path; 744 /* Bypass version check for firmware override. */ 745 dmc->required_version = 0; 746 } 747 748 if (!dmc->fw_path) { 749 drm_dbg_kms(&dev_priv->drm, 750 "No known DMC firmware for platform, disabling runtime PM\n"); 751 return; 752 } 753 754 drm_dbg_kms(&dev_priv->drm, "Loading %s\n", dmc->fw_path); 755 schedule_work(&dev_priv->dmc.work); 756 } 757 758 /** 759 * intel_dmc_ucode_suspend() - prepare DMC firmware before system suspend 760 * @dev_priv: i915 drm device 761 * 762 * Prepare the DMC firmware before entering system suspend. This includes 763 * flushing pending work items and releasing any resources acquired during 764 * init. 765 */ 766 void intel_dmc_ucode_suspend(struct drm_i915_private *dev_priv) 767 { 768 if (!HAS_DMC(dev_priv)) 769 return; 770 771 flush_work(&dev_priv->dmc.work); 772 773 /* Drop the reference held in case DMC isn't loaded. */ 774 if (!intel_dmc_has_payload(dev_priv)) 775 intel_dmc_runtime_pm_put(dev_priv); 776 } 777 778 /** 779 * intel_dmc_ucode_resume() - init DMC firmware during system resume 780 * @dev_priv: i915 drm device 781 * 782 * Reinitialize the DMC firmware during system resume, reacquiring any 783 * resources released in intel_dmc_ucode_suspend(). 784 */ 785 void intel_dmc_ucode_resume(struct drm_i915_private *dev_priv) 786 { 787 if (!HAS_DMC(dev_priv)) 788 return; 789 790 /* 791 * Reacquire the reference to keep RPM disabled in case DMC isn't 792 * loaded. 793 */ 794 if (!intel_dmc_has_payload(dev_priv)) 795 intel_dmc_runtime_pm_get(dev_priv); 796 } 797 798 /** 799 * intel_dmc_ucode_fini() - unload the DMC firmware. 800 * @dev_priv: i915 drm device. 801 * 802 * Firmmware unloading includes freeing the internal memory and reset the 803 * firmware loading status. 804 */ 805 void intel_dmc_ucode_fini(struct drm_i915_private *dev_priv) 806 { 807 int id; 808 809 if (!HAS_DMC(dev_priv)) 810 return; 811 812 intel_dmc_ucode_suspend(dev_priv); 813 drm_WARN_ON(&dev_priv->drm, dev_priv->dmc.wakeref); 814 815 for (id = 0; id < DMC_FW_MAX; id++) 816 kfree(dev_priv->dmc.dmc_info[id].payload); 817 } 818 819 void intel_dmc_print_error_state(struct drm_i915_error_state_buf *m, 820 struct drm_i915_private *i915) 821 { 822 struct intel_dmc *dmc = &i915->dmc; 823 824 if (!HAS_DMC(i915)) 825 return; 826 827 i915_error_printf(m, "DMC loaded: %s\n", 828 str_yes_no(intel_dmc_has_payload(i915))); 829 i915_error_printf(m, "DMC fw version: %d.%d\n", 830 DMC_VERSION_MAJOR(dmc->version), 831 DMC_VERSION_MINOR(dmc->version)); 832 } 833 834 static int intel_dmc_debugfs_status_show(struct seq_file *m, void *unused) 835 { 836 struct drm_i915_private *i915 = m->private; 837 intel_wakeref_t wakeref; 838 struct intel_dmc *dmc; 839 i915_reg_t dc5_reg, dc6_reg = INVALID_MMIO_REG; 840 841 if (!HAS_DMC(i915)) 842 return -ENODEV; 843 844 dmc = &i915->dmc; 845 846 wakeref = intel_runtime_pm_get(&i915->runtime_pm); 847 848 seq_printf(m, "fw loaded: %s\n", 849 str_yes_no(intel_dmc_has_payload(i915))); 850 seq_printf(m, "path: %s\n", dmc->fw_path); 851 seq_printf(m, "Pipe A fw support: %s\n", 852 str_yes_no(GRAPHICS_VER(i915) >= 12)); 853 seq_printf(m, "Pipe A fw loaded: %s\n", 854 str_yes_no(dmc->dmc_info[DMC_FW_PIPEA].payload)); 855 seq_printf(m, "Pipe B fw support: %s\n", 856 str_yes_no(IS_ALDERLAKE_P(i915))); 857 seq_printf(m, "Pipe B fw loaded: %s\n", 858 str_yes_no(dmc->dmc_info[DMC_FW_PIPEB].payload)); 859 860 if (!intel_dmc_has_payload(i915)) 861 goto out; 862 863 seq_printf(m, "version: %d.%d\n", DMC_VERSION_MAJOR(dmc->version), 864 DMC_VERSION_MINOR(dmc->version)); 865 866 if (DISPLAY_VER(i915) >= 12) { 867 if (IS_DGFX(i915)) { 868 dc5_reg = DG1_DMC_DEBUG_DC5_COUNT; 869 } else { 870 dc5_reg = TGL_DMC_DEBUG_DC5_COUNT; 871 dc6_reg = TGL_DMC_DEBUG_DC6_COUNT; 872 } 873 874 /* 875 * NOTE: DMC_DEBUG3 is a general purpose reg. 876 * According to B.Specs:49196 DMC f/w reuses DC5/6 counter 877 * reg for DC3CO debugging and validation, 878 * but TGL DMC f/w is using DMC_DEBUG3 reg for DC3CO counter. 879 */ 880 seq_printf(m, "DC3CO count: %d\n", 881 intel_de_read(i915, IS_DGFX(i915) ? 882 DG1_DMC_DEBUG3 : TGL_DMC_DEBUG3)); 883 } else { 884 dc5_reg = IS_BROXTON(i915) ? BXT_DMC_DC3_DC5_COUNT : 885 SKL_DMC_DC3_DC5_COUNT; 886 if (!IS_GEMINILAKE(i915) && !IS_BROXTON(i915)) 887 dc6_reg = SKL_DMC_DC5_DC6_COUNT; 888 } 889 890 seq_printf(m, "DC3 -> DC5 count: %d\n", intel_de_read(i915, dc5_reg)); 891 if (i915_mmio_reg_valid(dc6_reg)) 892 seq_printf(m, "DC5 -> DC6 count: %d\n", 893 intel_de_read(i915, dc6_reg)); 894 895 out: 896 seq_printf(m, "program base: 0x%08x\n", 897 intel_de_read(i915, DMC_PROGRAM(dmc->dmc_info[DMC_FW_MAIN].start_mmioaddr, 0))); 898 seq_printf(m, "ssp base: 0x%08x\n", 899 intel_de_read(i915, DMC_SSP_BASE)); 900 seq_printf(m, "htp: 0x%08x\n", intel_de_read(i915, DMC_HTP_SKL)); 901 902 intel_runtime_pm_put(&i915->runtime_pm, wakeref); 903 904 return 0; 905 } 906 907 DEFINE_SHOW_ATTRIBUTE(intel_dmc_debugfs_status); 908 909 void intel_dmc_debugfs_register(struct drm_i915_private *i915) 910 { 911 struct drm_minor *minor = i915->drm.primary; 912 913 debugfs_create_file("i915_dmc_info", 0444, minor->debugfs_root, 914 i915, &intel_dmc_debugfs_status_fops); 915 } 916